2 * SD Association Host Standard Specification v2.0 controller emulation
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Mitsyanko Igor <i.mitsyanko@samsung.com>
6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
9 * by Alexey Merkulov and Vladimir Monakhov.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
27 #include "sysemu/block-backend.h"
28 #include "sysemu/blockdev.h"
29 #include "sysemu/dma.h"
30 #include "qemu/timer.h"
31 #include "qemu/bitops.h"
32 #include "sdhci-internal.h"
34 /* host controller debug messages */
39 #define DPRINT_L1(fmt, args...) \
42 fprintf(stderr, "QEMU SDHC: " fmt, ## args); \
45 #define DPRINT_L2(fmt, args...) \
47 if (SDHC_DEBUG > 1) { \
48 fprintf(stderr, "QEMU SDHC: " fmt, ## args); \
51 #define ERRPRINT(fmt, args...) \
54 fprintf(stderr, "QEMU SDHC ERROR: " fmt, ## args); \
58 /* Default SD/MMC host controller features information, which will be
59 * presented in CAPABILITIES register of generic SD host controller at reset.
60 * If not stated otherwise:
61 * 0 - not supported, 1 - supported, other - prohibited.
63 #define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */
64 #define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */
65 #define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */
66 #define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */
67 #define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */
68 #define SDHC_CAPAB_SDMA 1ul /* SDMA support */
69 #define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */
70 #define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */
71 #define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */
72 /* Maximum host controller R/W buffers size
73 * Possible values: 512, 1024, 2048 bytes */
74 #define SDHC_CAPAB_MAXBLOCKLENGTH 512ul
75 /* Maximum clock frequency for SDclock in MHz
76 * value in range 10-63 MHz, 0 - not defined */
77 #define SDHC_CAPAB_BASECLKFREQ 52ul
78 #define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */
79 /* Timeout clock frequency 1-63, 0 - not defined */
80 #define SDHC_CAPAB_TOCLKFREQ 52ul
82 /* Now check all parameters and calculate CAPABILITIES REGISTER value */
83 #if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \
84 SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \
85 SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\
87 #error Capabilities features can have value 0 or 1 only!
90 #if SDHC_CAPAB_MAXBLOCKLENGTH == 512
91 #define MAX_BLOCK_LENGTH 0ul
92 #elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024
93 #define MAX_BLOCK_LENGTH 1ul
94 #elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048
95 #define MAX_BLOCK_LENGTH 2ul
97 #error Max host controller block size can have value 512, 1024 or 2048 only!
100 #if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \
101 SDHC_CAPAB_BASECLKFREQ > 63
102 #error SDclock frequency can have value in range 0, 10-63 only!
105 #if SDHC_CAPAB_TOCLKFREQ > 63
106 #error Timeout clock frequency can have value in range 0-63 only!
109 #define SDHC_CAPAB_REG_DEFAULT \
110 ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \
111 (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \
112 (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \
113 (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \
114 (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \
115 (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \
116 (SDHC_CAPAB_TOCLKFREQ))
118 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
120 static uint8_t sdhci_slotint(SDHCIState
*s
)
122 return (s
->norintsts
& s
->norintsigen
) || (s
->errintsts
& s
->errintsigen
) ||
123 ((s
->norintsts
& SDHC_NIS_INSERT
) && (s
->wakcon
& SDHC_WKUP_ON_INS
)) ||
124 ((s
->norintsts
& SDHC_NIS_REMOVE
) && (s
->wakcon
& SDHC_WKUP_ON_RMV
));
127 static inline void sdhci_update_irq(SDHCIState
*s
)
129 qemu_set_irq(s
->irq
, sdhci_slotint(s
));
132 static void sdhci_raise_insertion_irq(void *opaque
)
134 SDHCIState
*s
= (SDHCIState
*)opaque
;
136 if (s
->norintsts
& SDHC_NIS_REMOVE
) {
137 timer_mod(s
->insert_timer
,
138 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_INSERTION_DELAY
);
140 s
->prnsts
= 0x1ff0000;
141 if (s
->norintstsen
& SDHC_NISEN_INSERT
) {
142 s
->norintsts
|= SDHC_NIS_INSERT
;
148 static void sdhci_insert_eject_cb(void *opaque
, int irq
, int level
)
150 SDHCIState
*s
= (SDHCIState
*)opaque
;
151 DPRINT_L1("Card state changed: %s!\n", level
? "insert" : "eject");
153 if ((s
->norintsts
& SDHC_NIS_REMOVE
) && level
) {
154 /* Give target some time to notice card ejection */
155 timer_mod(s
->insert_timer
,
156 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_INSERTION_DELAY
);
159 s
->prnsts
= 0x1ff0000;
160 if (s
->norintstsen
& SDHC_NISEN_INSERT
) {
161 s
->norintsts
|= SDHC_NIS_INSERT
;
164 s
->prnsts
= 0x1fa0000;
165 s
->pwrcon
&= ~SDHC_POWER_ON
;
166 s
->clkcon
&= ~SDHC_CLOCK_SDCLK_EN
;
167 if (s
->norintstsen
& SDHC_NISEN_REMOVE
) {
168 s
->norintsts
|= SDHC_NIS_REMOVE
;
175 static void sdhci_card_readonly_cb(void *opaque
, int irq
, int level
)
177 SDHCIState
*s
= (SDHCIState
*)opaque
;
180 s
->prnsts
&= ~SDHC_WRITE_PROTECT
;
183 s
->prnsts
|= SDHC_WRITE_PROTECT
;
187 static void sdhci_reset(SDHCIState
*s
)
189 timer_del(s
->insert_timer
);
190 timer_del(s
->transfer_timer
);
191 /* Set all registers to 0. Capabilities registers are not cleared
192 * and assumed to always preserve their value, given to them during
194 memset(&s
->sdmasysad
, 0, (uintptr_t)&s
->capareg
- (uintptr_t)&s
->sdmasysad
);
196 sd_set_cb(s
->card
, s
->ro_cb
, s
->eject_cb
);
198 s
->stopped_state
= sdhc_not_stopped
;
201 static void sdhci_data_transfer(void *opaque
);
203 static void sdhci_send_command(SDHCIState
*s
)
206 uint8_t response
[16];
211 request
.cmd
= s
->cmdreg
>> 8;
212 request
.arg
= s
->argument
;
213 DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request
.cmd
, request
.arg
);
214 rlen
= sd_do_command(s
->card
, &request
, response
);
216 if (s
->cmdreg
& SDHC_CMD_RESPONSE
) {
218 s
->rspreg
[0] = (response
[0] << 24) | (response
[1] << 16) |
219 (response
[2] << 8) | response
[3];
220 s
->rspreg
[1] = s
->rspreg
[2] = s
->rspreg
[3] = 0;
221 DPRINT_L1("Response: RSPREG[31..0]=0x%08x\n", s
->rspreg
[0]);
222 } else if (rlen
== 16) {
223 s
->rspreg
[0] = (response
[11] << 24) | (response
[12] << 16) |
224 (response
[13] << 8) | response
[14];
225 s
->rspreg
[1] = (response
[7] << 24) | (response
[8] << 16) |
226 (response
[9] << 8) | response
[10];
227 s
->rspreg
[2] = (response
[3] << 24) | (response
[4] << 16) |
228 (response
[5] << 8) | response
[6];
229 s
->rspreg
[3] = (response
[0] << 16) | (response
[1] << 8) |
231 DPRINT_L1("Response received:\n RSPREG[127..96]=0x%08x, RSPREG[95.."
232 "64]=0x%08x,\n RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x\n",
233 s
->rspreg
[3], s
->rspreg
[2], s
->rspreg
[1], s
->rspreg
[0]);
235 ERRPRINT("Timeout waiting for command response\n");
236 if (s
->errintstsen
& SDHC_EISEN_CMDTIMEOUT
) {
237 s
->errintsts
|= SDHC_EIS_CMDTIMEOUT
;
238 s
->norintsts
|= SDHC_NIS_ERR
;
242 if ((s
->norintstsen
& SDHC_NISEN_TRSCMP
) &&
243 (s
->cmdreg
& SDHC_CMD_RESPONSE
) == SDHC_CMD_RSP_WITH_BUSY
) {
244 s
->norintsts
|= SDHC_NIS_TRSCMP
;
246 } else if (rlen
!= 0 && (s
->errintstsen
& SDHC_EISEN_CMDIDX
)) {
247 s
->errintsts
|= SDHC_EIS_CMDIDX
;
248 s
->norintsts
|= SDHC_NIS_ERR
;
251 if (s
->norintstsen
& SDHC_NISEN_CMDCMP
) {
252 s
->norintsts
|= SDHC_NIS_CMDCMP
;
257 if (s
->blksize
&& (s
->cmdreg
& SDHC_CMD_DATA_PRESENT
)) {
259 sdhci_data_transfer(s
);
263 static void sdhci_end_transfer(SDHCIState
*s
)
265 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
266 if ((s
->trnmod
& SDHC_TRNS_ACMD12
) != 0) {
268 uint8_t response
[16];
272 DPRINT_L1("Automatically issue CMD%d %08x\n", request
.cmd
, request
.arg
);
273 sd_do_command(s
->card
, &request
, response
);
274 /* Auto CMD12 response goes to the upper Response register */
275 s
->rspreg
[3] = (response
[0] << 24) | (response
[1] << 16) |
276 (response
[2] << 8) | response
[3];
279 s
->prnsts
&= ~(SDHC_DOING_READ
| SDHC_DOING_WRITE
|
280 SDHC_DAT_LINE_ACTIVE
| SDHC_DATA_INHIBIT
|
281 SDHC_SPACE_AVAILABLE
| SDHC_DATA_AVAILABLE
);
283 if (s
->norintstsen
& SDHC_NISEN_TRSCMP
) {
284 s
->norintsts
|= SDHC_NIS_TRSCMP
;
291 * Programmed i/o data transfer
294 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */
295 static void sdhci_read_block_from_card(SDHCIState
*s
)
299 if ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
300 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0)) {
304 for (index
= 0; index
< (s
->blksize
& 0x0fff); index
++) {
305 s
->fifo_buffer
[index
] = sd_read_data(s
->card
);
308 /* New data now available for READ through Buffer Port Register */
309 s
->prnsts
|= SDHC_DATA_AVAILABLE
;
310 if (s
->norintstsen
& SDHC_NISEN_RBUFRDY
) {
311 s
->norintsts
|= SDHC_NIS_RBUFRDY
;
314 /* Clear DAT line active status if that was the last block */
315 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
316 ((s
->trnmod
& SDHC_TRNS_MULTI
) && s
->blkcnt
== 1)) {
317 s
->prnsts
&= ~SDHC_DAT_LINE_ACTIVE
;
320 /* If stop at block gap request was set and it's not the last block of
321 * data - generate Block Event interrupt */
322 if (s
->stopped_state
== sdhc_gap_read
&& (s
->trnmod
& SDHC_TRNS_MULTI
) &&
324 s
->prnsts
&= ~SDHC_DAT_LINE_ACTIVE
;
325 if (s
->norintstsen
& SDHC_EISEN_BLKGAP
) {
326 s
->norintsts
|= SDHC_EIS_BLKGAP
;
333 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */
334 static uint32_t sdhci_read_dataport(SDHCIState
*s
, unsigned size
)
339 /* first check that a valid data exists in host controller input buffer */
340 if ((s
->prnsts
& SDHC_DATA_AVAILABLE
) == 0) {
341 ERRPRINT("Trying to read from empty buffer\n");
345 for (i
= 0; i
< size
; i
++) {
346 value
|= s
->fifo_buffer
[s
->data_count
] << i
* 8;
348 /* check if we've read all valid data (blksize bytes) from buffer */
349 if ((s
->data_count
) >= (s
->blksize
& 0x0fff)) {
350 DPRINT_L2("All %u bytes of data have been read from input buffer\n",
352 s
->prnsts
&= ~SDHC_DATA_AVAILABLE
; /* no more data in a buffer */
353 s
->data_count
= 0; /* next buff read must start at position [0] */
355 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
359 /* if that was the last block of data */
360 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
361 ((s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0)) ||
362 /* stop at gap request */
363 (s
->stopped_state
== sdhc_gap_read
&&
364 !(s
->prnsts
& SDHC_DAT_LINE_ACTIVE
))) {
365 sdhci_end_transfer(s
);
366 } else { /* if there are more data, read next block from card */
367 sdhci_read_block_from_card(s
);
376 /* Write data from host controller FIFO to card */
377 static void sdhci_write_block_to_card(SDHCIState
*s
)
381 if (s
->prnsts
& SDHC_SPACE_AVAILABLE
) {
382 if (s
->norintstsen
& SDHC_NISEN_WBUFRDY
) {
383 s
->norintsts
|= SDHC_NIS_WBUFRDY
;
389 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
390 if (s
->blkcnt
== 0) {
397 for (index
= 0; index
< (s
->blksize
& 0x0fff); index
++) {
398 sd_write_data(s
->card
, s
->fifo_buffer
[index
]);
401 /* Next data can be written through BUFFER DATORT register */
402 s
->prnsts
|= SDHC_SPACE_AVAILABLE
;
404 /* Finish transfer if that was the last block of data */
405 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
406 ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
407 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0))) {
408 sdhci_end_transfer(s
);
409 } else if (s
->norintstsen
& SDHC_NISEN_WBUFRDY
) {
410 s
->norintsts
|= SDHC_NIS_WBUFRDY
;
413 /* Generate Block Gap Event if requested and if not the last block */
414 if (s
->stopped_state
== sdhc_gap_write
&& (s
->trnmod
& SDHC_TRNS_MULTI
) &&
416 s
->prnsts
&= ~SDHC_DOING_WRITE
;
417 if (s
->norintstsen
& SDHC_EISEN_BLKGAP
) {
418 s
->norintsts
|= SDHC_EIS_BLKGAP
;
420 sdhci_end_transfer(s
);
426 /* Write @size bytes of @value data to host controller @s Buffer Data Port
428 static void sdhci_write_dataport(SDHCIState
*s
, uint32_t value
, unsigned size
)
432 /* Check that there is free space left in a buffer */
433 if (!(s
->prnsts
& SDHC_SPACE_AVAILABLE
)) {
434 ERRPRINT("Can't write to data buffer: buffer full\n");
438 for (i
= 0; i
< size
; i
++) {
439 s
->fifo_buffer
[s
->data_count
] = value
& 0xFF;
442 if (s
->data_count
>= (s
->blksize
& 0x0fff)) {
443 DPRINT_L2("write buffer filled with %u bytes of data\n",
446 s
->prnsts
&= ~SDHC_SPACE_AVAILABLE
;
447 if (s
->prnsts
& SDHC_DOING_WRITE
) {
448 sdhci_write_block_to_card(s
);
455 * Single DMA data transfer
458 /* Multi block SDMA transfer */
459 static void sdhci_sdma_transfer_multi_blocks(SDHCIState
*s
)
461 bool page_aligned
= false;
462 unsigned int n
, begin
;
463 const uint16_t block_size
= s
->blksize
& 0x0fff;
464 uint32_t boundary_chk
= 1 << (((s
->blksize
& 0xf000) >> 12) + 12);
465 uint32_t boundary_count
= boundary_chk
- (s
->sdmasysad
% boundary_chk
);
467 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
468 * possible stop at page boundary if initial address is not page aligned,
469 * allow them to work properly */
470 if ((s
->sdmasysad
% boundary_chk
) == 0) {
474 if (s
->trnmod
& SDHC_TRNS_READ
) {
475 s
->prnsts
|= SDHC_DOING_READ
| SDHC_DATA_INHIBIT
|
476 SDHC_DAT_LINE_ACTIVE
;
478 if (s
->data_count
== 0) {
479 for (n
= 0; n
< block_size
; n
++) {
480 s
->fifo_buffer
[n
] = sd_read_data(s
->card
);
483 begin
= s
->data_count
;
484 if (((boundary_count
+ begin
) < block_size
) && page_aligned
) {
485 s
->data_count
= boundary_count
+ begin
;
488 s
->data_count
= block_size
;
489 boundary_count
-= block_size
- begin
;
490 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
494 dma_memory_write(&address_space_memory
, s
->sdmasysad
,
495 &s
->fifo_buffer
[begin
], s
->data_count
- begin
);
496 s
->sdmasysad
+= s
->data_count
- begin
;
497 if (s
->data_count
== block_size
) {
500 if (page_aligned
&& boundary_count
== 0) {
505 s
->prnsts
|= SDHC_DOING_WRITE
| SDHC_DATA_INHIBIT
|
506 SDHC_DAT_LINE_ACTIVE
;
508 begin
= s
->data_count
;
509 if (((boundary_count
+ begin
) < block_size
) && page_aligned
) {
510 s
->data_count
= boundary_count
+ begin
;
513 s
->data_count
= block_size
;
514 boundary_count
-= block_size
- begin
;
516 dma_memory_read(&address_space_memory
, s
->sdmasysad
,
517 &s
->fifo_buffer
[begin
], s
->data_count
);
518 s
->sdmasysad
+= s
->data_count
- begin
;
519 if (s
->data_count
== block_size
) {
520 for (n
= 0; n
< block_size
; n
++) {
521 sd_write_data(s
->card
, s
->fifo_buffer
[n
]);
524 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
528 if (page_aligned
&& boundary_count
== 0) {
534 if (s
->blkcnt
== 0) {
535 sdhci_end_transfer(s
);
537 if (s
->norintstsen
& SDHC_NISEN_DMA
) {
538 s
->norintsts
|= SDHC_NIS_DMA
;
544 /* single block SDMA transfer */
546 static void sdhci_sdma_transfer_single_block(SDHCIState
*s
)
549 uint32_t datacnt
= s
->blksize
& 0x0fff;
551 if (s
->trnmod
& SDHC_TRNS_READ
) {
552 for (n
= 0; n
< datacnt
; n
++) {
553 s
->fifo_buffer
[n
] = sd_read_data(s
->card
);
555 dma_memory_write(&address_space_memory
, s
->sdmasysad
, s
->fifo_buffer
,
558 dma_memory_read(&address_space_memory
, s
->sdmasysad
, s
->fifo_buffer
,
560 for (n
= 0; n
< datacnt
; n
++) {
561 sd_write_data(s
->card
, s
->fifo_buffer
[n
]);
565 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
569 sdhci_end_transfer(s
);
572 typedef struct ADMADescr
{
579 static void get_adma_description(SDHCIState
*s
, ADMADescr
*dscr
)
583 hwaddr entry_addr
= (hwaddr
)s
->admasysaddr
;
584 switch (SDHC_DMA_TYPE(s
->hostctl
)) {
585 case SDHC_CTRL_ADMA2_32
:
586 dma_memory_read(&address_space_memory
, entry_addr
, (uint8_t *)&adma2
,
588 adma2
= le64_to_cpu(adma2
);
589 /* The spec does not specify endianness of descriptor table.
590 * We currently assume that it is LE.
592 dscr
->addr
= (hwaddr
)extract64(adma2
, 32, 32) & ~0x3ull
;
593 dscr
->length
= (uint16_t)extract64(adma2
, 16, 16);
594 dscr
->attr
= (uint8_t)extract64(adma2
, 0, 7);
597 case SDHC_CTRL_ADMA1_32
:
598 dma_memory_read(&address_space_memory
, entry_addr
, (uint8_t *)&adma1
,
600 adma1
= le32_to_cpu(adma1
);
601 dscr
->addr
= (hwaddr
)(adma1
& 0xFFFFF000);
602 dscr
->attr
= (uint8_t)extract32(adma1
, 0, 7);
604 if ((dscr
->attr
& SDHC_ADMA_ATTR_ACT_MASK
) == SDHC_ADMA_ATTR_SET_LEN
) {
605 dscr
->length
= (uint16_t)extract32(adma1
, 12, 16);
610 case SDHC_CTRL_ADMA2_64
:
611 dma_memory_read(&address_space_memory
, entry_addr
,
612 (uint8_t *)(&dscr
->attr
), 1);
613 dma_memory_read(&address_space_memory
, entry_addr
+ 2,
614 (uint8_t *)(&dscr
->length
), 2);
615 dscr
->length
= le16_to_cpu(dscr
->length
);
616 dma_memory_read(&address_space_memory
, entry_addr
+ 4,
617 (uint8_t *)(&dscr
->addr
), 8);
618 dscr
->attr
= le64_to_cpu(dscr
->attr
);
619 dscr
->attr
&= 0xfffffff8;
625 /* Advanced DMA data transfer */
627 static void sdhci_do_adma(SDHCIState
*s
)
629 unsigned int n
, begin
, length
;
630 const uint16_t block_size
= s
->blksize
& 0x0fff;
634 for (i
= 0; i
< SDHC_ADMA_DESCS_PER_DELAY
; ++i
) {
635 s
->admaerr
&= ~SDHC_ADMAERR_LENGTH_MISMATCH
;
637 get_adma_description(s
, &dscr
);
638 DPRINT_L2("ADMA loop: addr=" TARGET_FMT_plx
", len=%d, attr=%x\n",
639 dscr
.addr
, dscr
.length
, dscr
.attr
);
641 if ((dscr
.attr
& SDHC_ADMA_ATTR_VALID
) == 0) {
642 /* Indicate that error occurred in ST_FDS state */
643 s
->admaerr
&= ~SDHC_ADMAERR_STATE_MASK
;
644 s
->admaerr
|= SDHC_ADMAERR_STATE_ST_FDS
;
646 /* Generate ADMA error interrupt */
647 if (s
->errintstsen
& SDHC_EISEN_ADMAERR
) {
648 s
->errintsts
|= SDHC_EIS_ADMAERR
;
649 s
->norintsts
|= SDHC_NIS_ERR
;
656 length
= dscr
.length
? dscr
.length
: 65536;
658 switch (dscr
.attr
& SDHC_ADMA_ATTR_ACT_MASK
) {
659 case SDHC_ADMA_ATTR_ACT_TRAN
: /* data transfer */
661 if (s
->trnmod
& SDHC_TRNS_READ
) {
663 if (s
->data_count
== 0) {
664 for (n
= 0; n
< block_size
; n
++) {
665 s
->fifo_buffer
[n
] = sd_read_data(s
->card
);
668 begin
= s
->data_count
;
669 if ((length
+ begin
) < block_size
) {
670 s
->data_count
= length
+ begin
;
673 s
->data_count
= block_size
;
674 length
-= block_size
- begin
;
676 dma_memory_write(&address_space_memory
, dscr
.addr
,
677 &s
->fifo_buffer
[begin
],
678 s
->data_count
- begin
);
679 dscr
.addr
+= s
->data_count
- begin
;
680 if (s
->data_count
== block_size
) {
682 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
684 if (s
->blkcnt
== 0) {
692 begin
= s
->data_count
;
693 if ((length
+ begin
) < block_size
) {
694 s
->data_count
= length
+ begin
;
697 s
->data_count
= block_size
;
698 length
-= block_size
- begin
;
700 dma_memory_read(&address_space_memory
, dscr
.addr
,
701 &s
->fifo_buffer
[begin
],
702 s
->data_count
- begin
);
703 dscr
.addr
+= s
->data_count
- begin
;
704 if (s
->data_count
== block_size
) {
705 for (n
= 0; n
< block_size
; n
++) {
706 sd_write_data(s
->card
, s
->fifo_buffer
[n
]);
709 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
711 if (s
->blkcnt
== 0) {
718 s
->admasysaddr
+= dscr
.incr
;
720 case SDHC_ADMA_ATTR_ACT_LINK
: /* link to next descriptor table */
721 s
->admasysaddr
= dscr
.addr
;
722 DPRINT_L1("ADMA link: admasysaddr=0x%" PRIx64
"\n",
726 s
->admasysaddr
+= dscr
.incr
;
730 if (dscr
.attr
& SDHC_ADMA_ATTR_INT
) {
731 DPRINT_L1("ADMA interrupt: admasysaddr=0x%" PRIx64
"\n",
733 if (s
->norintstsen
& SDHC_NISEN_DMA
) {
734 s
->norintsts
|= SDHC_NIS_DMA
;
740 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */
741 if (((s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) &&
742 (s
->blkcnt
== 0)) || (dscr
.attr
& SDHC_ADMA_ATTR_END
)) {
743 DPRINT_L2("ADMA transfer completed\n");
744 if (length
|| ((dscr
.attr
& SDHC_ADMA_ATTR_END
) &&
745 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) &&
747 ERRPRINT("SD/MMC host ADMA length mismatch\n");
748 s
->admaerr
|= SDHC_ADMAERR_LENGTH_MISMATCH
|
749 SDHC_ADMAERR_STATE_ST_TFR
;
750 if (s
->errintstsen
& SDHC_EISEN_ADMAERR
) {
751 ERRPRINT("Set ADMA error flag\n");
752 s
->errintsts
|= SDHC_EIS_ADMAERR
;
753 s
->norintsts
|= SDHC_NIS_ERR
;
758 sdhci_end_transfer(s
);
764 /* we have unfinished business - reschedule to continue ADMA */
765 timer_mod(s
->transfer_timer
,
766 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_TRANSFER_DELAY
);
769 /* Perform data transfer according to controller configuration */
771 static void sdhci_data_transfer(void *opaque
)
773 SDHCIState
*s
= (SDHCIState
*)opaque
;
775 if (s
->trnmod
& SDHC_TRNS_DMA
) {
776 switch (SDHC_DMA_TYPE(s
->hostctl
)) {
778 if ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
779 (!(s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) || s
->blkcnt
== 0)) {
783 if ((s
->blkcnt
== 1) || !(s
->trnmod
& SDHC_TRNS_MULTI
)) {
784 sdhci_sdma_transfer_single_block(s
);
786 sdhci_sdma_transfer_multi_blocks(s
);
790 case SDHC_CTRL_ADMA1_32
:
791 if (!(s
->capareg
& SDHC_CAN_DO_ADMA1
)) {
792 ERRPRINT("ADMA1 not supported\n");
798 case SDHC_CTRL_ADMA2_32
:
799 if (!(s
->capareg
& SDHC_CAN_DO_ADMA2
)) {
800 ERRPRINT("ADMA2 not supported\n");
806 case SDHC_CTRL_ADMA2_64
:
807 if (!(s
->capareg
& SDHC_CAN_DO_ADMA2
) ||
808 !(s
->capareg
& SDHC_64_BIT_BUS_SUPPORT
)) {
809 ERRPRINT("64 bit ADMA not supported\n");
816 ERRPRINT("Unsupported DMA type\n");
820 if ((s
->trnmod
& SDHC_TRNS_READ
) && sd_data_ready(s
->card
)) {
821 s
->prnsts
|= SDHC_DOING_READ
| SDHC_DATA_INHIBIT
|
822 SDHC_DAT_LINE_ACTIVE
;
823 sdhci_read_block_from_card(s
);
825 s
->prnsts
|= SDHC_DOING_WRITE
| SDHC_DAT_LINE_ACTIVE
|
826 SDHC_SPACE_AVAILABLE
| SDHC_DATA_INHIBIT
;
827 sdhci_write_block_to_card(s
);
832 static bool sdhci_can_issue_command(SDHCIState
*s
)
834 if (!SDHC_CLOCK_IS_ON(s
->clkcon
) || !(s
->pwrcon
& SDHC_POWER_ON
) ||
835 (((s
->prnsts
& SDHC_DATA_INHIBIT
) || s
->stopped_state
) &&
836 ((s
->cmdreg
& SDHC_CMD_DATA_PRESENT
) ||
837 ((s
->cmdreg
& SDHC_CMD_RESPONSE
) == SDHC_CMD_RSP_WITH_BUSY
&&
838 !(SDHC_COMMAND_TYPE(s
->cmdreg
) == SDHC_CMD_ABORT
))))) {
845 /* The Buffer Data Port register must be accessed in sequential and
846 * continuous manner */
848 sdhci_buff_access_is_sequential(SDHCIState
*s
, unsigned byte_num
)
850 if ((s
->data_count
& 0x3) != byte_num
) {
851 ERRPRINT("Non-sequential access to Buffer Data Port register"
858 static uint64_t sdhci_read(void *opaque
, hwaddr offset
, unsigned size
)
860 SDHCIState
*s
= (SDHCIState
*)opaque
;
863 switch (offset
& ~0x3) {
868 ret
= s
->blksize
| (s
->blkcnt
<< 16);
874 ret
= s
->trnmod
| (s
->cmdreg
<< 16);
876 case SDHC_RSPREG0
... SDHC_RSPREG3
:
877 ret
= s
->rspreg
[((offset
& ~0x3) - SDHC_RSPREG0
) >> 2];
880 if (sdhci_buff_access_is_sequential(s
, offset
- SDHC_BDATA
)) {
881 ret
= sdhci_read_dataport(s
, size
);
882 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size
, (int)offset
,
891 ret
= s
->hostctl
| (s
->pwrcon
<< 8) | (s
->blkgap
<< 16) |
895 ret
= s
->clkcon
| (s
->timeoutcon
<< 16);
898 ret
= s
->norintsts
| (s
->errintsts
<< 16);
900 case SDHC_NORINTSTSEN
:
901 ret
= s
->norintstsen
| (s
->errintstsen
<< 16);
903 case SDHC_NORINTSIGEN
:
904 ret
= s
->norintsigen
| (s
->errintsigen
<< 16);
906 case SDHC_ACMD12ERRSTS
:
907 ret
= s
->acmd12errsts
;
918 case SDHC_ADMASYSADDR
:
919 ret
= (uint32_t)s
->admasysaddr
;
921 case SDHC_ADMASYSADDR
+ 4:
922 ret
= (uint32_t)(s
->admasysaddr
>> 32);
924 case SDHC_SLOT_INT_STATUS
:
925 ret
= (SD_HOST_SPECv2_VERS
<< 16) | sdhci_slotint(s
);
928 ERRPRINT("bad %ub read: addr[0x%04x]\n", size
, (int)offset
);
932 ret
>>= (offset
& 0x3) * 8;
933 ret
&= (1ULL << (size
* 8)) - 1;
934 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size
, (int)offset
, ret
, ret
);
938 static inline void sdhci_blkgap_write(SDHCIState
*s
, uint8_t value
)
940 if ((value
& SDHC_STOP_AT_GAP_REQ
) && (s
->blkgap
& SDHC_STOP_AT_GAP_REQ
)) {
943 s
->blkgap
= value
& SDHC_STOP_AT_GAP_REQ
;
945 if ((value
& SDHC_CONTINUE_REQ
) && s
->stopped_state
&&
946 (s
->blkgap
& SDHC_STOP_AT_GAP_REQ
) == 0) {
947 if (s
->stopped_state
== sdhc_gap_read
) {
948 s
->prnsts
|= SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_READ
;
949 sdhci_read_block_from_card(s
);
951 s
->prnsts
|= SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_WRITE
;
952 sdhci_write_block_to_card(s
);
954 s
->stopped_state
= sdhc_not_stopped
;
955 } else if (!s
->stopped_state
&& (value
& SDHC_STOP_AT_GAP_REQ
)) {
956 if (s
->prnsts
& SDHC_DOING_READ
) {
957 s
->stopped_state
= sdhc_gap_read
;
958 } else if (s
->prnsts
& SDHC_DOING_WRITE
) {
959 s
->stopped_state
= sdhc_gap_write
;
964 static inline void sdhci_reset_write(SDHCIState
*s
, uint8_t value
)
971 s
->prnsts
&= ~SDHC_CMD_INHIBIT
;
972 s
->norintsts
&= ~SDHC_NIS_CMDCMP
;
974 case SDHC_RESET_DATA
:
976 s
->prnsts
&= ~(SDHC_SPACE_AVAILABLE
| SDHC_DATA_AVAILABLE
|
977 SDHC_DOING_READ
| SDHC_DOING_WRITE
|
978 SDHC_DATA_INHIBIT
| SDHC_DAT_LINE_ACTIVE
);
979 s
->blkgap
&= ~(SDHC_STOP_AT_GAP_REQ
| SDHC_CONTINUE_REQ
);
980 s
->stopped_state
= sdhc_not_stopped
;
981 s
->norintsts
&= ~(SDHC_NIS_WBUFRDY
| SDHC_NIS_RBUFRDY
|
982 SDHC_NIS_DMA
| SDHC_NIS_TRSCMP
| SDHC_NIS_BLKGAP
);
988 sdhci_write(void *opaque
, hwaddr offset
, uint64_t val
, unsigned size
)
990 SDHCIState
*s
= (SDHCIState
*)opaque
;
991 unsigned shift
= 8 * (offset
& 0x3);
992 uint32_t mask
= ~(((1ULL << (size
* 8)) - 1) << shift
);
993 uint32_t value
= val
;
996 switch (offset
& ~0x3) {
998 s
->sdmasysad
= (s
->sdmasysad
& mask
) | value
;
999 MASKED_WRITE(s
->sdmasysad
, mask
, value
);
1000 /* Writing to last byte of sdmasysad might trigger transfer */
1001 if (!(mask
& 0xFF000000) && TRANSFERRING_DATA(s
->prnsts
) && s
->blkcnt
&&
1002 s
->blksize
&& SDHC_DMA_TYPE(s
->hostctl
) == SDHC_CTRL_SDMA
) {
1003 sdhci_sdma_transfer_multi_blocks(s
);
1007 if (!TRANSFERRING_DATA(s
->prnsts
)) {
1008 MASKED_WRITE(s
->blksize
, mask
, value
);
1009 MASKED_WRITE(s
->blkcnt
, mask
>> 16, value
>> 16);
1012 /* Limit block size to the maximum buffer size */
1013 if (extract32(s
->blksize
, 0, 12) > s
->buf_maxsz
) {
1014 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Size 0x%x is larger than " \
1015 "the maximum buffer 0x%x", __func__
, s
->blksize
,
1018 s
->blksize
= deposit32(s
->blksize
, 0, 12, s
->buf_maxsz
);
1023 MASKED_WRITE(s
->argument
, mask
, value
);
1026 /* DMA can be enabled only if it is supported as indicated by
1027 * capabilities register */
1028 if (!(s
->capareg
& SDHC_CAN_DO_DMA
)) {
1029 value
&= ~SDHC_TRNS_DMA
;
1031 MASKED_WRITE(s
->trnmod
, mask
, value
);
1032 MASKED_WRITE(s
->cmdreg
, mask
>> 16, value
>> 16);
1034 /* Writing to the upper byte of CMDREG triggers SD command generation */
1035 if ((mask
& 0xFF000000) || !sdhci_can_issue_command(s
)) {
1039 sdhci_send_command(s
);
1042 if (sdhci_buff_access_is_sequential(s
, offset
- SDHC_BDATA
)) {
1043 sdhci_write_dataport(s
, value
>> shift
, size
);
1047 if (!(mask
& 0xFF0000)) {
1048 sdhci_blkgap_write(s
, value
>> 16);
1050 MASKED_WRITE(s
->hostctl
, mask
, value
);
1051 MASKED_WRITE(s
->pwrcon
, mask
>> 8, value
>> 8);
1052 MASKED_WRITE(s
->wakcon
, mask
>> 24, value
>> 24);
1053 if (!(s
->prnsts
& SDHC_CARD_PRESENT
) || ((s
->pwrcon
>> 1) & 0x7) < 5 ||
1054 !(s
->capareg
& (1 << (31 - ((s
->pwrcon
>> 1) & 0x7))))) {
1055 s
->pwrcon
&= ~SDHC_POWER_ON
;
1059 if (!(mask
& 0xFF000000)) {
1060 sdhci_reset_write(s
, value
>> 24);
1062 MASKED_WRITE(s
->clkcon
, mask
, value
);
1063 MASKED_WRITE(s
->timeoutcon
, mask
>> 16, value
>> 16);
1064 if (s
->clkcon
& SDHC_CLOCK_INT_EN
) {
1065 s
->clkcon
|= SDHC_CLOCK_INT_STABLE
;
1067 s
->clkcon
&= ~SDHC_CLOCK_INT_STABLE
;
1070 case SDHC_NORINTSTS
:
1071 if (s
->norintstsen
& SDHC_NISEN_CARDINT
) {
1072 value
&= ~SDHC_NIS_CARDINT
;
1074 s
->norintsts
&= mask
| ~value
;
1075 s
->errintsts
&= (mask
>> 16) | ~(value
>> 16);
1077 s
->norintsts
|= SDHC_NIS_ERR
;
1079 s
->norintsts
&= ~SDHC_NIS_ERR
;
1081 sdhci_update_irq(s
);
1083 case SDHC_NORINTSTSEN
:
1084 MASKED_WRITE(s
->norintstsen
, mask
, value
);
1085 MASKED_WRITE(s
->errintstsen
, mask
>> 16, value
>> 16);
1086 s
->norintsts
&= s
->norintstsen
;
1087 s
->errintsts
&= s
->errintstsen
;
1089 s
->norintsts
|= SDHC_NIS_ERR
;
1091 s
->norintsts
&= ~SDHC_NIS_ERR
;
1093 sdhci_update_irq(s
);
1095 case SDHC_NORINTSIGEN
:
1096 MASKED_WRITE(s
->norintsigen
, mask
, value
);
1097 MASKED_WRITE(s
->errintsigen
, mask
>> 16, value
>> 16);
1098 sdhci_update_irq(s
);
1101 MASKED_WRITE(s
->admaerr
, mask
, value
);
1103 case SDHC_ADMASYSADDR
:
1104 s
->admasysaddr
= (s
->admasysaddr
& (0xFFFFFFFF00000000ULL
|
1105 (uint64_t)mask
)) | (uint64_t)value
;
1107 case SDHC_ADMASYSADDR
+ 4:
1108 s
->admasysaddr
= (s
->admasysaddr
& (0x00000000FFFFFFFFULL
|
1109 ((uint64_t)mask
<< 32))) | ((uint64_t)value
<< 32);
1112 s
->acmd12errsts
|= value
;
1113 s
->errintsts
|= (value
>> 16) & s
->errintstsen
;
1114 if (s
->acmd12errsts
) {
1115 s
->errintsts
|= SDHC_EIS_CMD12ERR
;
1118 s
->norintsts
|= SDHC_NIS_ERR
;
1120 sdhci_update_irq(s
);
1123 ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n",
1124 size
, (int)offset
, value
>> shift
, value
>> shift
);
1127 DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n",
1128 size
, (int)offset
, value
>> shift
, value
>> shift
);
1131 static const MemoryRegionOps sdhci_mmio_ops
= {
1133 .write
= sdhci_write
,
1135 .min_access_size
= 1,
1136 .max_access_size
= 4,
1139 .endianness
= DEVICE_LITTLE_ENDIAN
,
1142 static inline unsigned int sdhci_get_fifolen(SDHCIState
*s
)
1144 switch (SDHC_CAPAB_BLOCKSIZE(s
->capareg
)) {
1152 hw_error("SDHC: unsupported value for maximum block size\n");
1157 static void sdhci_initfn(SDHCIState
*s
, BlockBackend
*blk
)
1159 s
->card
= sd_init(blk
, false);
1160 if (s
->card
== NULL
) {
1163 s
->eject_cb
= qemu_allocate_irq(sdhci_insert_eject_cb
, s
, 0);
1164 s
->ro_cb
= qemu_allocate_irq(sdhci_card_readonly_cb
, s
, 0);
1165 sd_set_cb(s
->card
, s
->ro_cb
, s
->eject_cb
);
1167 s
->insert_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, sdhci_raise_insertion_irq
, s
);
1168 s
->transfer_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, sdhci_data_transfer
, s
);
1171 static void sdhci_uninitfn(SDHCIState
*s
)
1173 timer_del(s
->insert_timer
);
1174 timer_free(s
->insert_timer
);
1175 timer_del(s
->transfer_timer
);
1176 timer_free(s
->transfer_timer
);
1177 qemu_free_irq(s
->eject_cb
);
1178 qemu_free_irq(s
->ro_cb
);
1180 g_free(s
->fifo_buffer
);
1181 s
->fifo_buffer
= NULL
;
1184 const VMStateDescription sdhci_vmstate
= {
1187 .minimum_version_id
= 1,
1188 .fields
= (VMStateField
[]) {
1189 VMSTATE_UINT32(sdmasysad
, SDHCIState
),
1190 VMSTATE_UINT16(blksize
, SDHCIState
),
1191 VMSTATE_UINT16(blkcnt
, SDHCIState
),
1192 VMSTATE_UINT32(argument
, SDHCIState
),
1193 VMSTATE_UINT16(trnmod
, SDHCIState
),
1194 VMSTATE_UINT16(cmdreg
, SDHCIState
),
1195 VMSTATE_UINT32_ARRAY(rspreg
, SDHCIState
, 4),
1196 VMSTATE_UINT32(prnsts
, SDHCIState
),
1197 VMSTATE_UINT8(hostctl
, SDHCIState
),
1198 VMSTATE_UINT8(pwrcon
, SDHCIState
),
1199 VMSTATE_UINT8(blkgap
, SDHCIState
),
1200 VMSTATE_UINT8(wakcon
, SDHCIState
),
1201 VMSTATE_UINT16(clkcon
, SDHCIState
),
1202 VMSTATE_UINT8(timeoutcon
, SDHCIState
),
1203 VMSTATE_UINT8(admaerr
, SDHCIState
),
1204 VMSTATE_UINT16(norintsts
, SDHCIState
),
1205 VMSTATE_UINT16(errintsts
, SDHCIState
),
1206 VMSTATE_UINT16(norintstsen
, SDHCIState
),
1207 VMSTATE_UINT16(errintstsen
, SDHCIState
),
1208 VMSTATE_UINT16(norintsigen
, SDHCIState
),
1209 VMSTATE_UINT16(errintsigen
, SDHCIState
),
1210 VMSTATE_UINT16(acmd12errsts
, SDHCIState
),
1211 VMSTATE_UINT16(data_count
, SDHCIState
),
1212 VMSTATE_UINT64(admasysaddr
, SDHCIState
),
1213 VMSTATE_UINT8(stopped_state
, SDHCIState
),
1214 VMSTATE_VBUFFER_UINT32(fifo_buffer
, SDHCIState
, 1, NULL
, 0, buf_maxsz
),
1215 VMSTATE_TIMER_PTR(insert_timer
, SDHCIState
),
1216 VMSTATE_TIMER_PTR(transfer_timer
, SDHCIState
),
1217 VMSTATE_END_OF_LIST()
1221 /* Capabilities registers provide information on supported features of this
1222 * specific host controller implementation */
1223 static Property sdhci_pci_properties
[] = {
1224 DEFINE_BLOCK_PROPERTIES(SDHCIState
, conf
),
1225 DEFINE_PROP_UINT32("capareg", SDHCIState
, capareg
,
1226 SDHC_CAPAB_REG_DEFAULT
),
1227 DEFINE_PROP_UINT32("maxcurr", SDHCIState
, maxcurr
, 0),
1228 DEFINE_PROP_END_OF_LIST(),
1231 static void sdhci_pci_realize(PCIDevice
*dev
, Error
**errp
)
1233 SDHCIState
*s
= PCI_SDHCI(dev
);
1234 dev
->config
[PCI_CLASS_PROG
] = 0x01; /* Standard Host supported DMA */
1235 dev
->config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin A */
1236 sdhci_initfn(s
, s
->conf
.blk
);
1237 s
->buf_maxsz
= sdhci_get_fifolen(s
);
1238 s
->fifo_buffer
= g_malloc0(s
->buf_maxsz
);
1239 s
->irq
= pci_allocate_irq(dev
);
1240 memory_region_init_io(&s
->iomem
, OBJECT(s
), &sdhci_mmio_ops
, s
, "sdhci",
1241 SDHC_REGISTERS_MAP_SIZE
);
1242 pci_register_bar(dev
, 0, 0, &s
->iomem
);
1245 static void sdhci_pci_exit(PCIDevice
*dev
)
1247 SDHCIState
*s
= PCI_SDHCI(dev
);
1251 static void sdhci_pci_class_init(ObjectClass
*klass
, void *data
)
1253 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1254 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1256 k
->realize
= sdhci_pci_realize
;
1257 k
->exit
= sdhci_pci_exit
;
1258 k
->vendor_id
= PCI_VENDOR_ID_REDHAT
;
1259 k
->device_id
= PCI_DEVICE_ID_REDHAT_SDHCI
;
1260 k
->class_id
= PCI_CLASS_SYSTEM_SDHCI
;
1261 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1262 dc
->vmsd
= &sdhci_vmstate
;
1263 dc
->props
= sdhci_pci_properties
;
1266 static const TypeInfo sdhci_pci_info
= {
1267 .name
= TYPE_PCI_SDHCI
,
1268 .parent
= TYPE_PCI_DEVICE
,
1269 .instance_size
= sizeof(SDHCIState
),
1270 .class_init
= sdhci_pci_class_init
,
1273 static Property sdhci_sysbus_properties
[] = {
1274 DEFINE_PROP_UINT32("capareg", SDHCIState
, capareg
,
1275 SDHC_CAPAB_REG_DEFAULT
),
1276 DEFINE_PROP_UINT32("maxcurr", SDHCIState
, maxcurr
, 0),
1277 DEFINE_PROP_END_OF_LIST(),
1280 static void sdhci_sysbus_init(Object
*obj
)
1282 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1285 /* FIXME use a qdev drive property instead of drive_get_next() */
1286 di
= drive_get_next(IF_SD
);
1287 sdhci_initfn(s
, di
? blk_by_legacy_dinfo(di
) : NULL
);
1290 static void sdhci_sysbus_finalize(Object
*obj
)
1292 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1296 static void sdhci_sysbus_realize(DeviceState
*dev
, Error
** errp
)
1298 SDHCIState
*s
= SYSBUS_SDHCI(dev
);
1299 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1301 s
->buf_maxsz
= sdhci_get_fifolen(s
);
1302 s
->fifo_buffer
= g_malloc0(s
->buf_maxsz
);
1303 sysbus_init_irq(sbd
, &s
->irq
);
1304 memory_region_init_io(&s
->iomem
, OBJECT(s
), &sdhci_mmio_ops
, s
, "sdhci",
1305 SDHC_REGISTERS_MAP_SIZE
);
1306 sysbus_init_mmio(sbd
, &s
->iomem
);
1309 static void sdhci_sysbus_class_init(ObjectClass
*klass
, void *data
)
1311 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1313 dc
->vmsd
= &sdhci_vmstate
;
1314 dc
->props
= sdhci_sysbus_properties
;
1315 dc
->realize
= sdhci_sysbus_realize
;
1316 /* Reason: instance_init() method uses drive_get_next() */
1317 dc
->cannot_instantiate_with_device_add_yet
= true;
1320 static const TypeInfo sdhci_sysbus_info
= {
1321 .name
= TYPE_SYSBUS_SDHCI
,
1322 .parent
= TYPE_SYS_BUS_DEVICE
,
1323 .instance_size
= sizeof(SDHCIState
),
1324 .instance_init
= sdhci_sysbus_init
,
1325 .instance_finalize
= sdhci_sysbus_finalize
,
1326 .class_init
= sdhci_sysbus_class_init
,
1329 static void sdhci_register_types(void)
1331 type_register_static(&sdhci_pci_info
);
1332 type_register_static(&sdhci_sysbus_info
);
1335 type_init(sdhci_register_types
)