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xilinx_spips: lqspi: Push more data to tx-fifo
[qemu.git] / target-mips / translate_init.c
blob7cf238f34b2ead4d6d0429431a0678b82ed1cdd4
1 /*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* CPU / CPU family specific config register values. */
22
23 /* Have config1, uncached coherency */
24 #define MIPS_CONFIG0 \
25 ((1 << CP0C0_M) | (0x2 << CP0C0_K0))
26
27 /* Have config2, no coprocessor2 attached, no MDMX support attached,
28 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30 #define MIPS_CONFIG1 \
31 ((1 << CP0C1_M) | \
32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
34 (0 << CP0C1_FP))
35
36 /* Have config3, no tertiary/secondary caches implemented */
37 #define MIPS_CONFIG2 \
38 ((1 << CP0C2_M))
39
40 /* No config4, no DSP ASE, no large physaddr (PABITS),
41 no external interrupt controller, no vectored interrupts,
42 no 1kb pages, no SmartMIPS ASE, no trace logic */
43 #define MIPS_CONFIG3 \
44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
46 (0 << CP0C3_SM) | (0 << CP0C3_TL))
47
48 /* MMU types, the first four entries have the same layout as the
49 CP0C0_MT field. */
50 enum mips_mmu_types {
51 MMU_TYPE_NONE,
52 MMU_TYPE_R4000,
53 MMU_TYPE_RESERVED,
54 MMU_TYPE_FMT,
55 MMU_TYPE_R3000,
56 MMU_TYPE_R6000,
57 MMU_TYPE_R8000
58 };
59
60 struct mips_def_t {
61 const char *name;
62 int32_t CP0_PRid;
63 int32_t CP0_Config0;
64 int32_t CP0_Config1;
65 int32_t CP0_Config2;
66 int32_t CP0_Config3;
67 int32_t CP0_Config6;
68 int32_t CP0_Config7;
69 target_ulong CP0_LLAddr_rw_bitmask;
70 int CP0_LLAddr_shift;
71 int32_t SYNCI_Step;
72 int32_t CCRes;
73 int32_t CP0_Status_rw_bitmask;
74 int32_t CP0_TCStatus_rw_bitmask;
75 int32_t CP0_SRSCtl;
76 int32_t CP1_fcr0;
77 int32_t SEGBITS;
78 int32_t PABITS;
79 int32_t CP0_SRSConf0_rw_bitmask;
80 int32_t CP0_SRSConf0;
81 int32_t CP0_SRSConf1_rw_bitmask;
82 int32_t CP0_SRSConf1;
83 int32_t CP0_SRSConf2_rw_bitmask;
84 int32_t CP0_SRSConf2;
85 int32_t CP0_SRSConf3_rw_bitmask;
86 int32_t CP0_SRSConf3;
87 int32_t CP0_SRSConf4_rw_bitmask;
88 int32_t CP0_SRSConf4;
89 int insn_flags;
90 enum mips_mmu_types mmu_type;
91 };
92
93 /*****************************************************************************/
94 /* MIPS CPU definitions */
95 static const mips_def_t mips_defs[] =
96 {
97 {
98 .name = "4Kc",
99 .CP0_PRid = 0x00018000,
100 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
101 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
102 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
103 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
104 (0 << CP0C1_CA),
105 .CP0_Config2 = MIPS_CONFIG2,
106 .CP0_Config3 = MIPS_CONFIG3,
107 .CP0_LLAddr_rw_bitmask = 0,
108 .CP0_LLAddr_shift = 4,
109 .SYNCI_Step = 32,
110 .CCRes = 2,
111 .CP0_Status_rw_bitmask = 0x1278FF17,
112 .SEGBITS = 32,
113 .PABITS = 32,
114 .insn_flags = CPU_MIPS32,
115 .mmu_type = MMU_TYPE_R4000,
116 },
117 {
118 .name = "4Km",
119 .CP0_PRid = 0x00018300,
120 /* Config1 implemented, fixed mapping MMU,
121 no virtual icache, uncached coherency. */
122 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
123 .CP0_Config1 = MIPS_CONFIG1 |
124 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
125 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
126 (1 << CP0C1_CA),
127 .CP0_Config2 = MIPS_CONFIG2,
128 .CP0_Config3 = MIPS_CONFIG3,
129 .CP0_LLAddr_rw_bitmask = 0,
130 .CP0_LLAddr_shift = 4,
131 .SYNCI_Step = 32,
132 .CCRes = 2,
133 .CP0_Status_rw_bitmask = 0x1258FF17,
134 .SEGBITS = 32,
135 .PABITS = 32,
136 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
137 .mmu_type = MMU_TYPE_FMT,
138 },
139 {
140 .name = "4KEcR1",
141 .CP0_PRid = 0x00018400,
142 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
143 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
144 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
145 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
146 (0 << CP0C1_CA),
147 .CP0_Config2 = MIPS_CONFIG2,
148 .CP0_Config3 = MIPS_CONFIG3,
149 .CP0_LLAddr_rw_bitmask = 0,
150 .CP0_LLAddr_shift = 4,
151 .SYNCI_Step = 32,
152 .CCRes = 2,
153 .CP0_Status_rw_bitmask = 0x1278FF17,
154 .SEGBITS = 32,
155 .PABITS = 32,
156 .insn_flags = CPU_MIPS32,
157 .mmu_type = MMU_TYPE_R4000,
158 },
159 {
160 .name = "4KEmR1",
161 .CP0_PRid = 0x00018500,
162 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
163 .CP0_Config1 = MIPS_CONFIG1 |
164 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
165 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
166 (1 << CP0C1_CA),
167 .CP0_Config2 = MIPS_CONFIG2,
168 .CP0_Config3 = MIPS_CONFIG3,
169 .CP0_LLAddr_rw_bitmask = 0,
170 .CP0_LLAddr_shift = 4,
171 .SYNCI_Step = 32,
172 .CCRes = 2,
173 .CP0_Status_rw_bitmask = 0x1258FF17,
174 .SEGBITS = 32,
175 .PABITS = 32,
176 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
177 .mmu_type = MMU_TYPE_FMT,
178 },
179 {
180 .name = "4KEc",
181 .CP0_PRid = 0x00019000,
182 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
183 (MMU_TYPE_R4000 << CP0C0_MT),
184 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
185 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
186 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
187 (0 << CP0C1_CA),
188 .CP0_Config2 = MIPS_CONFIG2,
189 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
190 .CP0_LLAddr_rw_bitmask = 0,
191 .CP0_LLAddr_shift = 4,
192 .SYNCI_Step = 32,
193 .CCRes = 2,
194 .CP0_Status_rw_bitmask = 0x1278FF17,
195 .SEGBITS = 32,
196 .PABITS = 32,
197 .insn_flags = CPU_MIPS32R2,
198 .mmu_type = MMU_TYPE_R4000,
199 },
200 {
201 .name = "4KEm",
202 .CP0_PRid = 0x00019100,
203 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
204 (MMU_TYPE_FMT << CP0C0_MT),
205 .CP0_Config1 = MIPS_CONFIG1 |
206 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
207 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
208 (1 << CP0C1_CA),
209 .CP0_Config2 = MIPS_CONFIG2,
210 .CP0_Config3 = MIPS_CONFIG3,
211 .CP0_LLAddr_rw_bitmask = 0,
212 .CP0_LLAddr_shift = 4,
213 .SYNCI_Step = 32,
214 .CCRes = 2,
215 .CP0_Status_rw_bitmask = 0x1258FF17,
216 .SEGBITS = 32,
217 .PABITS = 32,
218 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
219 .mmu_type = MMU_TYPE_FMT,
220 },
221 {
222 .name = "24Kc",
223 .CP0_PRid = 0x00019300,
224 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
225 (MMU_TYPE_R4000 << CP0C0_MT),
226 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
227 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
228 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
229 (1 << CP0C1_CA),
230 .CP0_Config2 = MIPS_CONFIG2,
231 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
232 .CP0_LLAddr_rw_bitmask = 0,
233 .CP0_LLAddr_shift = 4,
234 .SYNCI_Step = 32,
235 .CCRes = 2,
236 /* No DSP implemented. */
237 .CP0_Status_rw_bitmask = 0x1278FF1F,
238 .SEGBITS = 32,
239 .PABITS = 32,
240 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
241 .mmu_type = MMU_TYPE_R4000,
242 },
243 {
244 .name = "24Kf",
245 .CP0_PRid = 0x00019300,
246 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
247 (MMU_TYPE_R4000 << CP0C0_MT),
248 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
249 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
250 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
251 (1 << CP0C1_CA),
252 .CP0_Config2 = MIPS_CONFIG2,
253 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
254 .CP0_LLAddr_rw_bitmask = 0,
255 .CP0_LLAddr_shift = 4,
256 .SYNCI_Step = 32,
257 .CCRes = 2,
258 /* No DSP implemented. */
259 .CP0_Status_rw_bitmask = 0x3678FF1F,
260 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
261 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
262 .SEGBITS = 32,
263 .PABITS = 32,
264 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
265 .mmu_type = MMU_TYPE_R4000,
266 },
267 {
268 .name = "34Kf",
269 .CP0_PRid = 0x00019500,
270 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
271 (MMU_TYPE_R4000 << CP0C0_MT),
272 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
273 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
274 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
275 (1 << CP0C1_CA),
276 .CP0_Config2 = MIPS_CONFIG2,
277 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT),
278 .CP0_LLAddr_rw_bitmask = 0,
279 .CP0_LLAddr_shift = 0,
280 .SYNCI_Step = 32,
281 .CCRes = 2,
282 /* No DSP implemented. */
283 .CP0_Status_rw_bitmask = 0x3678FF1F,
284 /* No DSP implemented. */
285 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
286 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
287 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
288 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
289 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
290 (0xff << CP0TCSt_TASID),
291 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
292 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
293 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
294 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
295 .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
296 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
297 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
298 .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
299 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
300 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
301 .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
302 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
303 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
304 .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
305 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
306 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
307 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
308 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
309 .SEGBITS = 32,
310 .PABITS = 32,
311 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
312 .mmu_type = MMU_TYPE_R4000,
313 },
314 {
315 .name = "74Kf",
316 .CP0_PRid = 0x00019700,
317 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
318 (MMU_TYPE_R4000 << CP0C0_MT),
319 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
320 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
321 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
322 (1 << CP0C1_CA),
323 .CP0_Config2 = MIPS_CONFIG2,
324 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP),
325 .CP0_LLAddr_rw_bitmask = 0,
326 .CP0_LLAddr_shift = 4,
327 .SYNCI_Step = 32,
328 .CCRes = 2,
329 .CP0_Status_rw_bitmask = 0x3778FF1F,
330 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
331 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
332 .SEGBITS = 32,
333 .PABITS = 32,
334 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
335 .mmu_type = MMU_TYPE_R4000,
336 },
337 #if defined(TARGET_MIPS64)
338 {
339 .name = "R4000",
340 .CP0_PRid = 0x00000400,
341 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
342 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
343 /* Note: Config1 is only used internally, the R4000 has only Config0. */
344 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
345 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
346 .CP0_LLAddr_shift = 4,
347 .SYNCI_Step = 16,
348 .CCRes = 2,
349 .CP0_Status_rw_bitmask = 0x3678FFFF,
350 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
351 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
352 .SEGBITS = 40,
353 .PABITS = 36,
354 .insn_flags = CPU_MIPS3,
355 .mmu_type = MMU_TYPE_R4000,
356 },
357 {
358 .name = "VR5432",
359 .CP0_PRid = 0x00005400,
360 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
361 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
362 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
363 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
364 .CP0_LLAddr_shift = 4,
365 .SYNCI_Step = 16,
366 .CCRes = 2,
367 .CP0_Status_rw_bitmask = 0x3678FFFF,
368 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
369 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
370 .SEGBITS = 40,
371 .PABITS = 32,
372 .insn_flags = CPU_VR54XX,
373 .mmu_type = MMU_TYPE_R4000,
374 },
375 {
376 .name = "5Kc",
377 .CP0_PRid = 0x00018100,
378 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
379 (MMU_TYPE_R4000 << CP0C0_MT),
380 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
381 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
382 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
383 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
384 .CP0_Config2 = MIPS_CONFIG2,
385 .CP0_Config3 = MIPS_CONFIG3,
386 .CP0_LLAddr_rw_bitmask = 0,
387 .CP0_LLAddr_shift = 4,
388 .SYNCI_Step = 32,
389 .CCRes = 2,
390 .CP0_Status_rw_bitmask = 0x32F8FFFF,
391 .SEGBITS = 42,
392 .PABITS = 36,
393 .insn_flags = CPU_MIPS64,
394 .mmu_type = MMU_TYPE_R4000,
395 },
396 {
397 .name = "5Kf",
398 .CP0_PRid = 0x00018100,
399 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
400 (MMU_TYPE_R4000 << CP0C0_MT),
401 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
402 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
403 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
404 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
405 .CP0_Config2 = MIPS_CONFIG2,
406 .CP0_Config3 = MIPS_CONFIG3,
407 .CP0_LLAddr_rw_bitmask = 0,
408 .CP0_LLAddr_shift = 4,
409 .SYNCI_Step = 32,
410 .CCRes = 2,
411 .CP0_Status_rw_bitmask = 0x36F8FFFF,
412 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
413 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
414 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
415 .SEGBITS = 42,
416 .PABITS = 36,
417 .insn_flags = CPU_MIPS64,
418 .mmu_type = MMU_TYPE_R4000,
419 },
420 {
421 .name = "20Kc",
422 /* We emulate a later version of the 20Kc, earlier ones had a broken
423 WAIT instruction. */
424 .CP0_PRid = 0x000182a0,
425 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
426 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
427 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
428 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
429 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
430 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
431 .CP0_Config2 = MIPS_CONFIG2,
432 .CP0_Config3 = MIPS_CONFIG3,
433 .CP0_LLAddr_rw_bitmask = 0,
434 .CP0_LLAddr_shift = 0,
435 .SYNCI_Step = 32,
436 .CCRes = 1,
437 .CP0_Status_rw_bitmask = 0x36FBFFFF,
438 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
439 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
440 (1 << FCR0_D) | (1 << FCR0_S) |
441 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
442 .SEGBITS = 40,
443 .PABITS = 36,
444 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
445 .mmu_type = MMU_TYPE_R4000,
446 },
447 {
448 /* A generic CPU providing MIPS64 Release 2 features.
449 FIXME: Eventually this should be replaced by a real CPU model. */
450 .name = "MIPS64R2-generic",
451 .CP0_PRid = 0x00010000,
452 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
453 (MMU_TYPE_R4000 << CP0C0_MT),
454 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
455 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
456 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
457 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
458 .CP0_Config2 = MIPS_CONFIG2,
459 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
460 .CP0_LLAddr_rw_bitmask = 0,
461 .CP0_LLAddr_shift = 0,
462 .SYNCI_Step = 32,
463 .CCRes = 2,
464 .CP0_Status_rw_bitmask = 0x36FBFFFF,
465 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
466 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
467 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
468 .SEGBITS = 42,
469 /* The architectural limit is 59, but we have hardcoded 36 bit
470 in some places...
471 .PABITS = 59, */ /* the architectural limit */
472 .PABITS = 36,
473 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
474 .mmu_type = MMU_TYPE_R4000,
475 },
476 {
477 .name = "Loongson-2E",
478 .CP0_PRid = 0x6302,
479 /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
480 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
481 (0x1<<4) | (0x1<<1),
482 /* Note: Config1 is only used internally, Loongson-2E has only Config0. */
483 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
484 .SYNCI_Step = 16,
485 .CCRes = 2,
486 .CP0_Status_rw_bitmask = 0x35D0FFFF,
487 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
488 .SEGBITS = 40,
489 .PABITS = 40,
490 .insn_flags = CPU_LOONGSON2E,
491 .mmu_type = MMU_TYPE_R4000,
492 },
493 {
494 .name = "Loongson-2F",
495 .CP0_PRid = 0x6303,
496 /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
497 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
498 (0x1<<4) | (0x1<<1),
499 /* Note: Config1 is only used internally, Loongson-2F has only Config0. */
500 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
501 .SYNCI_Step = 16,
502 .CCRes = 2,
503 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writable*/
504 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
505 .SEGBITS = 40,
506 .PABITS = 40,
507 .insn_flags = CPU_LOONGSON2F,
508 .mmu_type = MMU_TYPE_R4000,
509 },
510 {
511 /* A generic CPU providing MIPS64 ASE DSP 2 features.
512 FIXME: Eventually this should be replaced by a real CPU model. */
513 .name = "mips64dspr2",
514 .CP0_PRid = 0x00010000,
515 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
516 (MMU_TYPE_R4000 << CP0C0_MT),
517 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
518 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
519 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
520 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
521 .CP0_Config2 = MIPS_CONFIG2,
522 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
523 .CP0_LLAddr_rw_bitmask = 0,
524 .CP0_LLAddr_shift = 0,
525 .SYNCI_Step = 32,
526 .CCRes = 2,
527 .CP0_Status_rw_bitmask = 0x37FBFFFF,
528 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
529 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
530 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
531 .SEGBITS = 42,
532 /* The architectural limit is 59, but we have hardcoded 36 bit
533 in some places...
534 .PABITS = 59, */ /* the architectural limit */
535 .PABITS = 36,
536 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
537 .mmu_type = MMU_TYPE_R4000,
538 },
539
540 #endif
541 };
542
543 static const mips_def_t *cpu_mips_find_by_name (const char *name)
544 {
545 int i;
546
547 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
548 if (strcasecmp(name, mips_defs[i].name) == 0) {
549 return &mips_defs[i];
550 }
551 }
552 return NULL;
553 }
554
555 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
556 {
557 int i;
558
559 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
560 (*cpu_fprintf)(f, "MIPS '%s'\n",
561 mips_defs[i].name);
562 }
563 }
564
565 #ifndef CONFIG_USER_ONLY
566 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
567 {
568 env->tlb->nb_tlb = 1;
569 env->tlb->map_address = &no_mmu_map_address;
570 }
571
572 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
573 {
574 env->tlb->nb_tlb = 1;
575 env->tlb->map_address = &fixed_mmu_map_address;
576 }
577
578 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
579 {
580 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
581 env->tlb->map_address = &r4k_map_address;
582 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
583 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
584 env->tlb->helper_tlbp = r4k_helper_tlbp;
585 env->tlb->helper_tlbr = r4k_helper_tlbr;
586 }
587
588 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
589 {
590 env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
591
592 switch (def->mmu_type) {
593 case MMU_TYPE_NONE:
594 no_mmu_init(env, def);
595 break;
596 case MMU_TYPE_R4000:
597 r4k_mmu_init(env, def);
598 break;
599 case MMU_TYPE_FMT:
600 fixed_mmu_init(env, def);
601 break;
602 case MMU_TYPE_R3000:
603 case MMU_TYPE_R6000:
604 case MMU_TYPE_R8000:
605 default:
606 cpu_abort(env, "MMU type not supported\n");
607 }
608 }
609 #endif /* CONFIG_USER_ONLY */
610
611 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
612 {
613 int i;
614
615 for (i = 0; i < MIPS_FPU_MAX; i++)
616 env->fpus[i].fcr0 = def->CP1_fcr0;
617
618 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
619 }
620
621 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
622 {
623 env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
624
625 /* MVPConf1 implemented, TLB sharable, no gating storage support,
626 programmable cache partitioning implemented, number of allocatable
627 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
628 implemented, 5 TCs implemented. */
629 env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
630 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
631 // TODO: actually do 2 VPEs.
632 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
633 // (0x04 << CP0MVPC0_PTC);
634 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
635 (0x00 << CP0MVPC0_PTC);
636 #if !defined(CONFIG_USER_ONLY)
637 /* Usermode has no TLB support */
638 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
639 #endif
640
641 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
642 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
643 env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
644 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
645 (0x1 << CP0MVPC1_PCP1);
646 }
QEmu