target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "exec/helper-proto.h"
  23 #include "exec/cpu_ldst.h"
  24 #include "sysemu/kvm.h"
  25
  26 #ifndef CONFIG_USER_ONLY
  27 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  28 #endif
  29
  30 /*****************************************************************************/
  31 /* Exceptions processing helpers */
  32
  33 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
  34                                                         uint32_t exception,
  35                                                         int error_code,
  36                                                         uintptr_t pc)
  37 {
  38     CPUState *cs = CPU(mips_env_get_cpu(env));
  39
  40     if (exception < EXCP_SC) {
  41         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  42     }
  43     cs->exception_index = exception;
  44     env->error_code = error_code;
  45
  46     if (pc) {
  47         /* now we have a real cpu fault */
  48         cpu_restore_state(cs, pc);
  49     }
  50
  51     cpu_loop_exit(cs);
  52 }
  53
  54 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  55                                                     uint32_t exception,
  56                                                     uintptr_t pc)
  57 {
  58     do_raise_exception_err(env, exception, 0, pc);
  59 }
  60
  61 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  62                                 int error_code)
  63 {
  64     do_raise_exception_err(env, exception, error_code, 0);
  65 }
  66
  67 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  68 {
  69     do_raise_exception(env, exception, 0);
  70 }
  71
  72 #if defined(CONFIG_USER_ONLY)
  73 #define HELPER_LD(name, insn, type)                                     \
  74 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  75                              int mem_idx)                               \
  76 {                                                                       \
  77     return (type) insn##_raw(addr);                                     \
  78 }
  79 #else
  80 #define HELPER_LD(name, insn, type)                                     \
  81 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  82                              int mem_idx)                               \
  83 {                                                                       \
  84     switch (mem_idx)                                                    \
  85     {                                                                   \
  86     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  87     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  88     default:                                                            \
  89     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  90     }                                                                   \
  91 }
  92 #endif
  93 HELPER_LD(lw, ldl, int32_t)
  94 #ifdef TARGET_MIPS64
  95 HELPER_LD(ld, ldq, int64_t)
  96 #endif
  97 #undef HELPER_LD
  98
  99 #if defined(CONFIG_USER_ONLY)
 100 #define HELPER_ST(name, insn, type)                                     \
 101 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 102                              type val, int mem_idx)                     \
 103 {                                                                       \
 104     insn##_raw(addr, val);                                              \
 105 }
 106 #else
 107 #define HELPER_ST(name, insn, type)                                     \
 108 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 109                              type val, int mem_idx)                     \
 110 {                                                                       \
 111     switch (mem_idx)                                                    \
 112     {                                                                   \
 113     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 114     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 115     default:                                                            \
 116     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 117     }                                                                   \
 118 }
 119 #endif
 120 HELPER_ST(sb, stb, uint8_t)
 121 HELPER_ST(sw, stl, uint32_t)
 122 #ifdef TARGET_MIPS64
 123 HELPER_ST(sd, stq, uint64_t)
 124 #endif
 125 #undef HELPER_ST
 126
 127 target_ulong helper_clo (target_ulong arg1)
 128 {
 129     return clo32(arg1);
 130 }
 131
 132 target_ulong helper_clz (target_ulong arg1)
 133 {
 134     return clz32(arg1);
 135 }
 136
 137 #if defined(TARGET_MIPS64)
 138 target_ulong helper_dclo (target_ulong arg1)
 139 {
 140     return clo64(arg1);
 141 }
 142
 143 target_ulong helper_dclz (target_ulong arg1)
 144 {
 145     return clz64(arg1);
 146 }
 147 #endif /* TARGET_MIPS64 */
 148
 149 /* 64 bits arithmetic for 32 bits hosts */
 150 static inline uint64_t get_HILO(CPUMIPSState *env)
 151 {
 152     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 153 }
 154
 155 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 156 {
 157     target_ulong tmp;
 158     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 159     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 160     return tmp;
 161 }
 162
 163 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 164 {
 165     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 166     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 167     return tmp;
 168 }
 169
 170 /* Multiplication variants of the vr54xx. */
 171 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 172                          target_ulong arg2)
 173 {
 174     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 175                                  (int64_t)(int32_t)arg2));
 176 }
 177
 178 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 179                           target_ulong arg2)
 180 {
 181     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 182                        (uint64_t)(uint32_t)arg2);
 183 }
 184
 185 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 186                          target_ulong arg2)
 187 {
 188     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 189                        (int64_t)(int32_t)arg2);
 190 }
 191
 192 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 193                            target_ulong arg2)
 194 {
 195     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 196                        (int64_t)(int32_t)arg2);
 197 }
 198
 199 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 200                           target_ulong arg2)
 201 {
 202     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 203                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 204 }
 205
 206 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 207                             target_ulong arg2)
 208 {
 209     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 210                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 211 }
 212
 213 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 214                          target_ulong arg2)
 215 {
 216     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 217                        (int64_t)(int32_t)arg2);
 218 }
 219
 220 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 221                            target_ulong arg2)
 222 {
 223     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 224                        (int64_t)(int32_t)arg2);
 225 }
 226
 227 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 228                           target_ulong arg2)
 229 {
 230     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 231                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 232 }
 233
 234 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 235                             target_ulong arg2)
 236 {
 237     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 238                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 239 }
 240
 241 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 242                           target_ulong arg2)
 243 {
 244     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 245 }
 246
 247 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 248                            target_ulong arg2)
 249 {
 250     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 251                        (uint64_t)(uint32_t)arg2);
 252 }
 253
 254 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 255                            target_ulong arg2)
 256 {
 257     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 258                        (int64_t)(int32_t)arg2);
 259 }
 260
 261 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 262                             target_ulong arg2)
 263 {
 264     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 265                        (uint64_t)(uint32_t)arg2);
 266 }
 267
 268 static inline target_ulong bitswap(target_ulong v)
 269 {
 270     v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
 271               ((v & (target_ulong)0x5555555555555555ULL) << 1);
 272     v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
 273               ((v & (target_ulong)0x3333333333333333ULL) << 2);
 274     v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
 275               ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
 276     return v;
 277 }
 278
 279 #ifdef TARGET_MIPS64
 280 target_ulong helper_dbitswap(target_ulong rt)
 281 {
 282     return bitswap(rt);
 283 }
 284 #endif
 285
 286 target_ulong helper_bitswap(target_ulong rt)
 287 {
 288     return (int32_t)bitswap(rt);
 289 }
 290
 291 #ifndef CONFIG_USER_ONLY
 292
 293 static inline hwaddr do_translate_address(CPUMIPSState *env,
 294                                                       target_ulong address,
 295                                                       int rw)
 296 {
 297     hwaddr lladdr;
 298
 299     lladdr = cpu_mips_translate_address(env, address, rw);
 300
 301     if (lladdr == -1LL) {
 302         cpu_loop_exit(CPU(mips_env_get_cpu(env)));
 303     } else {
 304         return lladdr;
 305     }
 306 }
 307
 308 #define HELPER_LD_ATOMIC(name, insn)                                          \
 309 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 310 {                                                                             \
 311     env->lladdr = do_translate_address(env, arg, 0);                          \
 312     env->llval = do_##insn(env, arg, mem_idx);                                \
 313     return env->llval;                                                        \
 314 }
 315 HELPER_LD_ATOMIC(ll, lw)
 316 #ifdef TARGET_MIPS64
 317 HELPER_LD_ATOMIC(lld, ld)
 318 #endif
 319 #undef HELPER_LD_ATOMIC
 320
 321 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 322 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 323                            target_ulong arg2, int mem_idx)                    \
 324 {                                                                             \
 325     target_long tmp;                                                          \
 326                                                                               \
 327     if (arg2 & almask) {                                                      \
 328         env->CP0_BadVAddr = arg2;                                             \
 329         helper_raise_exception(env, EXCP_AdES);                               \
 330     }                                                                         \
 331     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 332         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 333         if (tmp == env->llval) {                                              \
 334             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 335             return 1;                                                         \
 336         }                                                                     \
 337     }                                                                         \
 338     return 0;                                                                 \
 339 }
 340 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 341 #ifdef TARGET_MIPS64
 342 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 343 #endif
 344 #undef HELPER_ST_ATOMIC
 345 #endif
 346
 347 #ifdef TARGET_WORDS_BIGENDIAN
 348 #define GET_LMASK(v) ((v) & 3)
 349 #define GET_OFFSET(addr, offset) (addr + (offset))
 350 #else
 351 #define GET_LMASK(v) (((v) & 3) ^ 3)
 352 #define GET_OFFSET(addr, offset) (addr - (offset))
 353 #endif
 354
 355 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 356                 int mem_idx)
 357 {
 358     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 359
 360     if (GET_LMASK(arg2) <= 2)
 361         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 362
 363     if (GET_LMASK(arg2) <= 1)
 364         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 365
 366     if (GET_LMASK(arg2) == 0)
 367         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 368 }
 369
 370 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 371                 int mem_idx)
 372 {
 373     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 374
 375     if (GET_LMASK(arg2) >= 1)
 376         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 377
 378     if (GET_LMASK(arg2) >= 2)
 379         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 380
 381     if (GET_LMASK(arg2) == 3)
 382         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 383 }
 384
 385 #if defined(TARGET_MIPS64)
 386 /* "half" load and stores.  We must do the memory access inline,
 387    or fault handling won't work.  */
 388
 389 #ifdef TARGET_WORDS_BIGENDIAN
 390 #define GET_LMASK64(v) ((v) & 7)
 391 #else
 392 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 393 #endif
 394
 395 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 396                 int mem_idx)
 397 {
 398     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 399
 400     if (GET_LMASK64(arg2) <= 6)
 401         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 402
 403     if (GET_LMASK64(arg2) <= 5)
 404         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 405
 406     if (GET_LMASK64(arg2) <= 4)
 407         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 408
 409     if (GET_LMASK64(arg2) <= 3)
 410         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 411
 412     if (GET_LMASK64(arg2) <= 2)
 413         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 414
 415     if (GET_LMASK64(arg2) <= 1)
 416         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 417
 418     if (GET_LMASK64(arg2) <= 0)
 419         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 420 }
 421
 422 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 423                 int mem_idx)
 424 {
 425     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 426
 427     if (GET_LMASK64(arg2) >= 1)
 428         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 429
 430     if (GET_LMASK64(arg2) >= 2)
 431         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 432
 433     if (GET_LMASK64(arg2) >= 3)
 434         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 435
 436     if (GET_LMASK64(arg2) >= 4)
 437         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 438
 439     if (GET_LMASK64(arg2) >= 5)
 440         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 441
 442     if (GET_LMASK64(arg2) >= 6)
 443         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 444
 445     if (GET_LMASK64(arg2) == 7)
 446         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 447 }
 448 #endif /* TARGET_MIPS64 */
 449
 450 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 451
 452 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 453                 uint32_t mem_idx)
 454 {
 455     target_ulong base_reglist = reglist & 0xf;
 456     target_ulong do_r31 = reglist & 0x10;
 457
 458     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 459         target_ulong i;
 460
 461         for (i = 0; i < base_reglist; i++) {
 462             env->active_tc.gpr[multiple_regs[i]] =
 463                 (target_long)do_lw(env, addr, mem_idx);
 464             addr += 4;
 465         }
 466     }
 467
 468     if (do_r31) {
 469         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
 470     }
 471 }
 472
 473 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 474                 uint32_t mem_idx)
 475 {
 476     target_ulong base_reglist = reglist & 0xf;
 477     target_ulong do_r31 = reglist & 0x10;
 478
 479     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 480         target_ulong i;
 481
 482         for (i = 0; i < base_reglist; i++) {
 483             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 484             addr += 4;
 485         }
 486     }
 487
 488     if (do_r31) {
 489         do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
 490     }
 491 }
 492
 493 #if defined(TARGET_MIPS64)
 494 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 495                 uint32_t mem_idx)
 496 {
 497     target_ulong base_reglist = reglist & 0xf;
 498     target_ulong do_r31 = reglist & 0x10;
 499
 500     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 501         target_ulong i;
 502
 503         for (i = 0; i < base_reglist; i++) {
 504             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
 505             addr += 8;
 506         }
 507     }
 508
 509     if (do_r31) {
 510         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
 511     }
 512 }
 513
 514 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 515                 uint32_t mem_idx)
 516 {
 517     target_ulong base_reglist = reglist & 0xf;
 518     target_ulong do_r31 = reglist & 0x10;
 519
 520     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 521         target_ulong i;
 522
 523         for (i = 0; i < base_reglist; i++) {
 524             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 525             addr += 8;
 526         }
 527     }
 528
 529     if (do_r31) {
 530         do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
 531     }
 532 }
 533 #endif
 534
 535 #ifndef CONFIG_USER_ONLY
 536 /* SMP helpers.  */
 537 static bool mips_vpe_is_wfi(MIPSCPU *c)
 538 {
 539     CPUState *cpu = CPU(c);
 540     CPUMIPSState *env = &c->env;
 541
 542     /* If the VPE is halted but otherwise active, it means it's waiting for
 543        an interrupt.  */
 544     return cpu->halted && mips_vpe_active(env);
 545 }
 546
 547 static inline void mips_vpe_wake(MIPSCPU *c)
 548 {
 549     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 550        because there might be other conditions that state that c should
 551        be sleeping.  */
 552     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
 553 }
 554
 555 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 556 {
 557     CPUState *cs = CPU(cpu);
 558
 559     /* The VPE was shut off, really go to bed.
 560        Reset any old _WAKE requests.  */
 561     cs->halted = 1;
 562     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
 563 }
 564
 565 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 566 {
 567     CPUMIPSState *c = &cpu->env;
 568
 569     /* FIXME: TC reschedule.  */
 570     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 571         mips_vpe_wake(cpu);
 572     }
 573 }
 574
 575 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 576 {
 577     CPUMIPSState *c = &cpu->env;
 578
 579     /* FIXME: TC reschedule.  */
 580     if (!mips_vpe_active(c)) {
 581         mips_vpe_sleep(cpu);
 582     }
 583 }
 584
 585 /**
 586  * mips_cpu_map_tc:
 587  * @env: CPU from which mapping is performed.
 588  * @tc: Should point to an int with the value of the global TC index.
 589  *
 590  * This function will transform @tc into a local index within the
 591  * returned #CPUMIPSState.
 592  */
 593 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 594           which depends on runtime setup. Can probably be fixed by
 595           walking the list of CPUMIPSStates.  */
 596 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 597 {
 598     MIPSCPU *cpu;
 599     CPUState *cs;
 600     CPUState *other_cs;
 601     int vpe_idx;
 602     int tc_idx = *tc;
 603
 604     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 605         /* Not allowed to address other CPUs.  */
 606         *tc = env->current_tc;
 607         return env;
 608     }
 609
 610     cs = CPU(mips_env_get_cpu(env));
 611     vpe_idx = tc_idx / cs->nr_threads;
 612     *tc = tc_idx % cs->nr_threads;
 613     other_cs = qemu_get_cpu(vpe_idx);
 614     if (other_cs == NULL) {
 615         return env;
 616     }
 617     cpu = MIPS_CPU(other_cs);
 618     return &cpu->env;
 619 }
 620
 621 /* The per VPE CP0_Status register shares some fields with the per TC
 622    CP0_TCStatus registers. These fields are wired to the same registers,
 623    so changes to either of them should be reflected on both registers.
 624
 625    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 626
 627    These helper call synchronizes the regs for a given cpu.  */
 628
 629 /* Called for updates to CP0_Status.  */
 630 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 631 {
 632     int32_t tcstatus, *tcst;
 633     uint32_t v = cpu->CP0_Status;
 634     uint32_t cu, mx, asid, ksu;
 635     uint32_t mask = ((1 << CP0TCSt_TCU3)
 636                        | (1 << CP0TCSt_TCU2)
 637                        | (1 << CP0TCSt_TCU1)
 638                        | (1 << CP0TCSt_TCU0)
 639                        | (1 << CP0TCSt_TMX)
 640                        | (3 << CP0TCSt_TKSU)
 641                        | (0xff << CP0TCSt_TASID));
 642
 643     cu = (v >> CP0St_CU0) & 0xf;
 644     mx = (v >> CP0St_MX) & 0x1;
 645     ksu = (v >> CP0St_KSU) & 0x3;
 646     asid = env->CP0_EntryHi & 0xff;
 647
 648     tcstatus = cu << CP0TCSt_TCU0;
 649     tcstatus |= mx << CP0TCSt_TMX;
 650     tcstatus |= ksu << CP0TCSt_TKSU;
 651     tcstatus |= asid;
 652
 653     if (tc == cpu->current_tc) {
 654         tcst = &cpu->active_tc.CP0_TCStatus;
 655     } else {
 656         tcst = &cpu->tcs[tc].CP0_TCStatus;
 657     }
 658
 659     *tcst &= ~mask;
 660     *tcst |= tcstatus;
 661     compute_hflags(cpu);
 662 }
 663
 664 /* Called for updates to CP0_TCStatus.  */
 665 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 666                              target_ulong v)
 667 {
 668     uint32_t status;
 669     uint32_t tcu, tmx, tasid, tksu;
 670     uint32_t mask = ((1U << CP0St_CU3)
 671                        | (1 << CP0St_CU2)
 672                        | (1 << CP0St_CU1)
 673                        | (1 << CP0St_CU0)
 674                        | (1 << CP0St_MX)
 675                        | (3 << CP0St_KSU));
 676
 677     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 678     tmx = (v >> CP0TCSt_TMX) & 0x1;
 679     tasid = v & 0xff;
 680     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 681
 682     status = tcu << CP0St_CU0;
 683     status |= tmx << CP0St_MX;
 684     status |= tksu << CP0St_KSU;
 685
 686     cpu->CP0_Status &= ~mask;
 687     cpu->CP0_Status |= status;
 688
 689     /* Sync the TASID with EntryHi.  */
 690     cpu->CP0_EntryHi &= ~0xff;
 691     cpu->CP0_EntryHi = tasid;
 692
 693     compute_hflags(cpu);
 694 }
 695
 696 /* Called for updates to CP0_EntryHi.  */
 697 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 698 {
 699     int32_t *tcst;
 700     uint32_t asid, v = cpu->CP0_EntryHi;
 701
 702     asid = v & 0xff;
 703
 704     if (tc == cpu->current_tc) {
 705         tcst = &cpu->active_tc.CP0_TCStatus;
 706     } else {
 707         tcst = &cpu->tcs[tc].CP0_TCStatus;
 708     }
 709
 710     *tcst &= ~0xff;
 711     *tcst |= asid;
 712 }
 713
 714 /* CP0 helpers */
 715 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 716 {
 717     return env->mvp->CP0_MVPControl;
 718 }
 719
 720 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 721 {
 722     return env->mvp->CP0_MVPConf0;
 723 }
 724
 725 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 726 {
 727     return env->mvp->CP0_MVPConf1;
 728 }
 729
 730 target_ulong helper_mfc0_random(CPUMIPSState *env)
 731 {
 732     return (int32_t)cpu_mips_get_random(env);
 733 }
 734
 735 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 736 {
 737     return env->active_tc.CP0_TCStatus;
 738 }
 739
 740 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 741 {
 742     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 743     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 744
 745     if (other_tc == other->current_tc)
 746         return other->active_tc.CP0_TCStatus;
 747     else
 748         return other->tcs[other_tc].CP0_TCStatus;
 749 }
 750
 751 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 752 {
 753     return env->active_tc.CP0_TCBind;
 754 }
 755
 756 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 757 {
 758     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 759     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 760
 761     if (other_tc == other->current_tc)
 762         return other->active_tc.CP0_TCBind;
 763     else
 764         return other->tcs[other_tc].CP0_TCBind;
 765 }
 766
 767 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 768 {
 769     return env->active_tc.PC;
 770 }
 771
 772 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 773 {
 774     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 775     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 776
 777     if (other_tc == other->current_tc)
 778         return other->active_tc.PC;
 779     else
 780         return other->tcs[other_tc].PC;
 781 }
 782
 783 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 784 {
 785     return env->active_tc.CP0_TCHalt;
 786 }
 787
 788 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 789 {
 790     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 791     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 792
 793     if (other_tc == other->current_tc)
 794         return other->active_tc.CP0_TCHalt;
 795     else
 796         return other->tcs[other_tc].CP0_TCHalt;
 797 }
 798
 799 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 800 {
 801     return env->active_tc.CP0_TCContext;
 802 }
 803
 804 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 805 {
 806     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 807     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 808
 809     if (other_tc == other->current_tc)
 810         return other->active_tc.CP0_TCContext;
 811     else
 812         return other->tcs[other_tc].CP0_TCContext;
 813 }
 814
 815 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 816 {
 817     return env->active_tc.CP0_TCSchedule;
 818 }
 819
 820 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 821 {
 822     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 823     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 824
 825     if (other_tc == other->current_tc)
 826         return other->active_tc.CP0_TCSchedule;
 827     else
 828         return other->tcs[other_tc].CP0_TCSchedule;
 829 }
 830
 831 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 832 {
 833     return env->active_tc.CP0_TCScheFBack;
 834 }
 835
 836 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 837 {
 838     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 839     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 840
 841     if (other_tc == other->current_tc)
 842         return other->active_tc.CP0_TCScheFBack;
 843     else
 844         return other->tcs[other_tc].CP0_TCScheFBack;
 845 }
 846
 847 target_ulong helper_mfc0_count(CPUMIPSState *env)
 848 {
 849     return (int32_t)cpu_mips_get_count(env);
 850 }
 851
 852 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 853 {
 854     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 855     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 856
 857     return other->CP0_EntryHi;
 858 }
 859
 860 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 861 {
 862     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 863     int32_t tccause;
 864     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 865
 866     if (other_tc == other->current_tc) {
 867         tccause = other->CP0_Cause;
 868     } else {
 869         tccause = other->CP0_Cause;
 870     }
 871
 872     return tccause;
 873 }
 874
 875 target_ulong helper_mftc0_status(CPUMIPSState *env)
 876 {
 877     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 878     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 879
 880     return other->CP0_Status;
 881 }
 882
 883 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 884 {
 885     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 886 }
 887
 888 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 889 {
 890     return (int32_t)env->CP0_WatchLo[sel];
 891 }
 892
 893 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 894 {
 895     return env->CP0_WatchHi[sel];
 896 }
 897
 898 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 899 {
 900     target_ulong t0 = env->CP0_Debug;
 901     if (env->hflags & MIPS_HFLAG_DM)
 902         t0 |= 1 << CP0DB_DM;
 903
 904     return t0;
 905 }
 906
 907 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 908 {
 909     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 910     int32_t tcstatus;
 911     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 912
 913     if (other_tc == other->current_tc)
 914         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 915     else
 916         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 917
 918     /* XXX: Might be wrong, check with EJTAG spec. */
 919     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 920             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 921 }
 922
 923 #if defined(TARGET_MIPS64)
 924 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 925 {
 926     return env->active_tc.PC;
 927 }
 928
 929 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 930 {
 931     return env->active_tc.CP0_TCHalt;
 932 }
 933
 934 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 935 {
 936     return env->active_tc.CP0_TCContext;
 937 }
 938
 939 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 940 {
 941     return env->active_tc.CP0_TCSchedule;
 942 }
 943
 944 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 945 {
 946     return env->active_tc.CP0_TCScheFBack;
 947 }
 948
 949 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 950 {
 951     return env->lladdr >> env->CP0_LLAddr_shift;
 952 }
 953
 954 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 955 {
 956     return env->CP0_WatchLo[sel];
 957 }
 958 #endif /* TARGET_MIPS64 */
 959
 960 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 961 {
 962     int num = 1;
 963     unsigned int tmp = env->tlb->nb_tlb;
 964
 965     do {
 966         tmp >>= 1;
 967         num <<= 1;
 968     } while (tmp);
 969     env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
 970 }
 971
 972 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 973 {
 974     uint32_t mask = 0;
 975     uint32_t newval;
 976
 977     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 978         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 979                 (1 << CP0MVPCo_EVP);
 980     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 981         mask |= (1 << CP0MVPCo_STLB);
 982     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 983
 984     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 985
 986     env->mvp->CP0_MVPControl = newval;
 987 }
 988
 989 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 990 {
 991     uint32_t mask;
 992     uint32_t newval;
 993
 994     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 995            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 996     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 997
 998     /* Yield scheduler intercept not implemented. */
 999     /* Gating storage scheduler intercept not implemented. */
1000
1001     // TODO: Enable/disable TCs.
1002
1003     env->CP0_VPEControl = newval;
1004 }
1005
1006 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1007 {
1008     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1009     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1010     uint32_t mask;
1011     uint32_t newval;
1012
1013     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1014            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1015     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1016
1017     /* TODO: Enable/disable TCs.  */
1018
1019     other->CP0_VPEControl = newval;
1020 }
1021
1022 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1023 {
1024     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1025     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1026     /* FIXME: Mask away return zero on read bits.  */
1027     return other->CP0_VPEControl;
1028 }
1029
1030 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1031 {
1032     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1033     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1034
1035     return other->CP0_VPEConf0;
1036 }
1037
1038 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1039 {
1040     uint32_t mask = 0;
1041     uint32_t newval;
1042
1043     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1044         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1045             mask |= (0xff << CP0VPEC0_XTC);
1046         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1047     }
1048     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1049
1050     // TODO: TC exclusive handling due to ERL/EXL.
1051
1052     env->CP0_VPEConf0 = newval;
1053 }
1054
1055 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1056 {
1057     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1058     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1059     uint32_t mask = 0;
1060     uint32_t newval;
1061
1062     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1063     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1064
1065     /* TODO: TC exclusive handling due to ERL/EXL.  */
1066     other->CP0_VPEConf0 = newval;
1067 }
1068
1069 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1070 {
1071     uint32_t mask = 0;
1072     uint32_t newval;
1073
1074     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1075         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1076                 (0xff << CP0VPEC1_NCP1);
1077     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1078
1079     /* UDI not implemented. */
1080     /* CP2 not implemented. */
1081
1082     // TODO: Handle FPU (CP1) binding.
1083
1084     env->CP0_VPEConf1 = newval;
1085 }
1086
1087 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1088 {
1089     /* Yield qualifier inputs not implemented. */
1090     env->CP0_YQMask = 0x00000000;
1091 }
1092
1093 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1094 {
1095     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1096 }
1097
1098 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1099 {
1100     /* Large physaddr (PABITS) not implemented */
1101     /* 1k pages not implemented */
1102     env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1103 }
1104
1105 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1106 {
1107     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1108     uint32_t newval;
1109
1110     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1111
1112     env->active_tc.CP0_TCStatus = newval;
1113     sync_c0_tcstatus(env, env->current_tc, newval);
1114 }
1115
1116 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1117 {
1118     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1119     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1120
1121     if (other_tc == other->current_tc)
1122         other->active_tc.CP0_TCStatus = arg1;
1123     else
1124         other->tcs[other_tc].CP0_TCStatus = arg1;
1125     sync_c0_tcstatus(other, other_tc, arg1);
1126 }
1127
1128 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1129 {
1130     uint32_t mask = (1 << CP0TCBd_TBE);
1131     uint32_t newval;
1132
1133     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1134         mask |= (1 << CP0TCBd_CurVPE);
1135     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1136     env->active_tc.CP0_TCBind = newval;
1137 }
1138
1139 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1140 {
1141     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1142     uint32_t mask = (1 << CP0TCBd_TBE);
1143     uint32_t newval;
1144     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1145
1146     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1147         mask |= (1 << CP0TCBd_CurVPE);
1148     if (other_tc == other->current_tc) {
1149         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1150         other->active_tc.CP0_TCBind = newval;
1151     } else {
1152         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1153         other->tcs[other_tc].CP0_TCBind = newval;
1154     }
1155 }
1156
1157 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1158 {
1159     env->active_tc.PC = arg1;
1160     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1161     env->lladdr = 0ULL;
1162     /* MIPS16 not implemented. */
1163 }
1164
1165 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1166 {
1167     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1168     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1169
1170     if (other_tc == other->current_tc) {
1171         other->active_tc.PC = arg1;
1172         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1173         other->lladdr = 0ULL;
1174         /* MIPS16 not implemented. */
1175     } else {
1176         other->tcs[other_tc].PC = arg1;
1177         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1178         other->lladdr = 0ULL;
1179         /* MIPS16 not implemented. */
1180     }
1181 }
1182
1183 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1184 {
1185     MIPSCPU *cpu = mips_env_get_cpu(env);
1186
1187     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1188
1189     // TODO: Halt TC / Restart (if allocated+active) TC.
1190     if (env->active_tc.CP0_TCHalt & 1) {
1191         mips_tc_sleep(cpu, env->current_tc);
1192     } else {
1193         mips_tc_wake(cpu, env->current_tc);
1194     }
1195 }
1196
1197 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1198 {
1199     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1200     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1201     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1202
1203     // TODO: Halt TC / Restart (if allocated+active) TC.
1204
1205     if (other_tc == other->current_tc)
1206         other->active_tc.CP0_TCHalt = arg1;
1207     else
1208         other->tcs[other_tc].CP0_TCHalt = arg1;
1209
1210     if (arg1 & 1) {
1211         mips_tc_sleep(other_cpu, other_tc);
1212     } else {
1213         mips_tc_wake(other_cpu, other_tc);
1214     }
1215 }
1216
1217 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1218 {
1219     env->active_tc.CP0_TCContext = arg1;
1220 }
1221
1222 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1223 {
1224     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1225     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1226
1227     if (other_tc == other->current_tc)
1228         other->active_tc.CP0_TCContext = arg1;
1229     else
1230         other->tcs[other_tc].CP0_TCContext = arg1;
1231 }
1232
1233 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1234 {
1235     env->active_tc.CP0_TCSchedule = arg1;
1236 }
1237
1238 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1239 {
1240     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1241     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1242
1243     if (other_tc == other->current_tc)
1244         other->active_tc.CP0_TCSchedule = arg1;
1245     else
1246         other->tcs[other_tc].CP0_TCSchedule = arg1;
1247 }
1248
1249 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1250 {
1251     env->active_tc.CP0_TCScheFBack = arg1;
1252 }
1253
1254 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1255 {
1256     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1257     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1258
1259     if (other_tc == other->current_tc)
1260         other->active_tc.CP0_TCScheFBack = arg1;
1261     else
1262         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1263 }
1264
1265 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1266 {
1267     /* Large physaddr (PABITS) not implemented */
1268     /* 1k pages not implemented */
1269     env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1270 }
1271
1272 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1273 {
1274     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1275 }
1276
1277 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1278 {
1279     /* 1k pages not implemented */
1280     env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1281 }
1282
1283 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1284 {
1285     /* SmartMIPS not implemented */
1286     /* Large physaddr (PABITS) not implemented */
1287     /* 1k pages not implemented */
1288     env->CP0_PageGrain = 0;
1289 }
1290
1291 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1292 {
1293     env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1294 }
1295
1296 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1297 {
1298     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1299 }
1300
1301 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1302 {
1303     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1304 }
1305
1306 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1307 {
1308     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1309 }
1310
1311 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1312 {
1313     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1314 }
1315
1316 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1317 {
1318     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1319 }
1320
1321 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1322 {
1323     uint32_t mask = 0x0000000F;
1324
1325     if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1326         mask |= (1 << 29);
1327
1328         if (arg1 & (1 << 29)) {
1329             env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1330         } else {
1331             env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1332         }
1333     }
1334
1335     env->CP0_HWREna = arg1 & mask;
1336 }
1337
1338 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1339 {
1340     cpu_mips_store_count(env, arg1);
1341 }
1342
1343 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1344 {
1345     target_ulong old, val;
1346
1347     /* 1k pages not implemented */
1348     val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1349 #if defined(TARGET_MIPS64)
1350     val &= env->SEGMask;
1351 #endif
1352     old = env->CP0_EntryHi;
1353     env->CP0_EntryHi = val;
1354     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1355         sync_c0_entryhi(env, env->current_tc);
1356     }
1357     /* If the ASID changes, flush qemu's TLB.  */
1358     if ((old & 0xFF) != (val & 0xFF))
1359         cpu_mips_tlb_flush(env, 1);
1360 }
1361
1362 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1363 {
1364     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1365     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1366
1367     other->CP0_EntryHi = arg1;
1368     sync_c0_entryhi(other, other_tc);
1369 }
1370
1371 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1372 {
1373     cpu_mips_store_compare(env, arg1);
1374 }
1375
1376 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1377 {
1378     MIPSCPU *cpu = mips_env_get_cpu(env);
1379     uint32_t val, old;
1380     uint32_t mask = env->CP0_Status_rw_bitmask;
1381
1382     val = arg1 & mask;
1383     old = env->CP0_Status;
1384     env->CP0_Status = (env->CP0_Status & ~mask) | val;
1385     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1386         sync_c0_status(env, env, env->current_tc);
1387     } else {
1388         compute_hflags(env);
1389     }
1390
1391     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1392         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1393                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1394                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1395                 env->CP0_Cause);
1396         switch (env->hflags & MIPS_HFLAG_KSU) {
1397         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1398         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1399         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1400         default:
1401             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1402             break;
1403         }
1404     }
1405 }
1406
1407 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1408 {
1409     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1410     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1411
1412     other->CP0_Status = arg1 & ~0xf1000018;
1413     sync_c0_status(env, other, other_tc);
1414 }
1415
1416 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1417 {
1418     /* vectored interrupts not implemented, no performance counters. */
1419     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1420 }
1421
1422 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1423 {
1424     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1425     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1426 }
1427
1428 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1429 {
1430     uint32_t mask = 0x00C00300;
1431     uint32_t old = cpu->CP0_Cause;
1432     int i;
1433
1434     if (cpu->insn_flags & ISA_MIPS32R2) {
1435         mask |= 1 << CP0Ca_DC;
1436     }
1437
1438     cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1439
1440     if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1441         if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1442             cpu_mips_stop_count(cpu);
1443         } else {
1444             cpu_mips_start_count(cpu);
1445         }
1446     }
1447
1448     /* Set/reset software interrupts */
1449     for (i = 0 ; i < 2 ; i++) {
1450         if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1451             cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1452         }
1453     }
1454 }
1455
1456 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1457 {
1458     mtc0_cause(env, arg1);
1459 }
1460
1461 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1462 {
1463     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1464     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1465
1466     mtc0_cause(other, arg1);
1467 }
1468
1469 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1470 {
1471     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1472     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1473
1474     return other->CP0_EPC;
1475 }
1476
1477 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1478 {
1479     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1480     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1481
1482     return other->CP0_EBase;
1483 }
1484
1485 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1486 {
1487     /* vectored interrupts not implemented */
1488     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1489 }
1490
1491 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1492 {
1493     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1494     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1495     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1496 }
1497
1498 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1499 {
1500     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1501     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1502
1503     switch (idx) {
1504     case 0: return other->CP0_Config0;
1505     case 1: return other->CP0_Config1;
1506     case 2: return other->CP0_Config2;
1507     case 3: return other->CP0_Config3;
1508     /* 4 and 5 are reserved.  */
1509     case 6: return other->CP0_Config6;
1510     case 7: return other->CP0_Config7;
1511     default:
1512         break;
1513     }
1514     return 0;
1515 }
1516
1517 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1518 {
1519     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1520 }
1521
1522 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1523 {
1524     /* tertiary/secondary caches not implemented */
1525     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1526 }
1527
1528 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1529 {
1530     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1531                        (arg1 & env->CP0_Config4_rw_bitmask);
1532 }
1533
1534 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1535 {
1536     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1537                        (arg1 & env->CP0_Config5_rw_bitmask);
1538 }
1539
1540 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1541 {
1542     target_long mask = env->CP0_LLAddr_rw_bitmask;
1543     arg1 = arg1 << env->CP0_LLAddr_shift;
1544     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1545 }
1546
1547 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1548 {
1549     /* Watch exceptions for instructions, data loads, data stores
1550        not implemented. */
1551     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1552 }
1553
1554 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1555 {
1556     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1557     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1558 }
1559
1560 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1561 {
1562     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1563     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1564 }
1565
1566 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1567 {
1568     env->CP0_Framemask = arg1; /* XXX */
1569 }
1570
1571 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1572 {
1573     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1574     if (arg1 & (1 << CP0DB_DM))
1575         env->hflags |= MIPS_HFLAG_DM;
1576     else
1577         env->hflags &= ~MIPS_HFLAG_DM;
1578 }
1579
1580 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1581 {
1582     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1583     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1584     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1585
1586     /* XXX: Might be wrong, check with EJTAG spec. */
1587     if (other_tc == other->current_tc)
1588         other->active_tc.CP0_Debug_tcstatus = val;
1589     else
1590         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1591     other->CP0_Debug = (other->CP0_Debug &
1592                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1593                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1594 }
1595
1596 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1597 {
1598     env->CP0_Performance0 = arg1 & 0x000007ff;
1599 }
1600
1601 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1602 {
1603     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1604 }
1605
1606 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1607 {
1608     env->CP0_DataLo = arg1; /* XXX */
1609 }
1610
1611 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1612 {
1613     env->CP0_TagHi = arg1; /* XXX */
1614 }
1615
1616 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1617 {
1618     env->CP0_DataHi = arg1; /* XXX */
1619 }
1620
1621 /* MIPS MT functions */
1622 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1623 {
1624     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1625     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1626
1627     if (other_tc == other->current_tc)
1628         return other->active_tc.gpr[sel];
1629     else
1630         return other->tcs[other_tc].gpr[sel];
1631 }
1632
1633 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1634 {
1635     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1636     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1637
1638     if (other_tc == other->current_tc)
1639         return other->active_tc.LO[sel];
1640     else
1641         return other->tcs[other_tc].LO[sel];
1642 }
1643
1644 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1645 {
1646     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1647     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1648
1649     if (other_tc == other->current_tc)
1650         return other->active_tc.HI[sel];
1651     else
1652         return other->tcs[other_tc].HI[sel];
1653 }
1654
1655 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1656 {
1657     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1658     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1659
1660     if (other_tc == other->current_tc)
1661         return other->active_tc.ACX[sel];
1662     else
1663         return other->tcs[other_tc].ACX[sel];
1664 }
1665
1666 target_ulong helper_mftdsp(CPUMIPSState *env)
1667 {
1668     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1669     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1670
1671     if (other_tc == other->current_tc)
1672         return other->active_tc.DSPControl;
1673     else
1674         return other->tcs[other_tc].DSPControl;
1675 }
1676
1677 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1678 {
1679     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1680     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1681
1682     if (other_tc == other->current_tc)
1683         other->active_tc.gpr[sel] = arg1;
1684     else
1685         other->tcs[other_tc].gpr[sel] = arg1;
1686 }
1687
1688 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1689 {
1690     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1691     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1692
1693     if (other_tc == other->current_tc)
1694         other->active_tc.LO[sel] = arg1;
1695     else
1696         other->tcs[other_tc].LO[sel] = arg1;
1697 }
1698
1699 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1700 {
1701     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1702     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1703
1704     if (other_tc == other->current_tc)
1705         other->active_tc.HI[sel] = arg1;
1706     else
1707         other->tcs[other_tc].HI[sel] = arg1;
1708 }
1709
1710 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1711 {
1712     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1713     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1714
1715     if (other_tc == other->current_tc)
1716         other->active_tc.ACX[sel] = arg1;
1717     else
1718         other->tcs[other_tc].ACX[sel] = arg1;
1719 }
1720
1721 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1722 {
1723     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1724     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1725
1726     if (other_tc == other->current_tc)
1727         other->active_tc.DSPControl = arg1;
1728     else
1729         other->tcs[other_tc].DSPControl = arg1;
1730 }
1731
1732 /* MIPS MT functions */
1733 target_ulong helper_dmt(void)
1734 {
1735     // TODO
1736      return 0;
1737 }
1738
1739 target_ulong helper_emt(void)
1740 {
1741     // TODO
1742     return 0;
1743 }
1744
1745 target_ulong helper_dvpe(CPUMIPSState *env)
1746 {
1747     CPUState *other_cs = first_cpu;
1748     target_ulong prev = env->mvp->CP0_MVPControl;
1749
1750     CPU_FOREACH(other_cs) {
1751         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1752         /* Turn off all VPEs except the one executing the dvpe.  */
1753         if (&other_cpu->env != env) {
1754             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1755             mips_vpe_sleep(other_cpu);
1756         }
1757     }
1758     return prev;
1759 }
1760
1761 target_ulong helper_evpe(CPUMIPSState *env)
1762 {
1763     CPUState *other_cs = first_cpu;
1764     target_ulong prev = env->mvp->CP0_MVPControl;
1765
1766     CPU_FOREACH(other_cs) {
1767         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1768
1769         if (&other_cpu->env != env
1770             /* If the VPE is WFI, don't disturb its sleep.  */
1771             && !mips_vpe_is_wfi(other_cpu)) {
1772             /* Enable the VPE.  */
1773             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1774             mips_vpe_wake(other_cpu); /* And wake it up.  */
1775         }
1776     }
1777     return prev;
1778 }
1779 #endif /* !CONFIG_USER_ONLY */
1780
1781 void helper_fork(target_ulong arg1, target_ulong arg2)
1782 {
1783     // arg1 = rt, arg2 = rs
1784     // TODO: store to TC register
1785 }
1786
1787 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1788 {
1789     target_long arg1 = arg;
1790
1791     if (arg1 < 0) {
1792         /* No scheduling policy implemented. */
1793         if (arg1 != -2) {
1794             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1795                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1796                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1797                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1798                 helper_raise_exception(env, EXCP_THREAD);
1799             }
1800         }
1801     } else if (arg1 == 0) {
1802         if (0 /* TODO: TC underflow */) {
1803             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1804             helper_raise_exception(env, EXCP_THREAD);
1805         } else {
1806             // TODO: Deallocate TC
1807         }
1808     } else if (arg1 > 0) {
1809         /* Yield qualifier inputs not implemented. */
1810         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1811         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1812         helper_raise_exception(env, EXCP_THREAD);
1813     }
1814     return env->CP0_YQMask;
1815 }
1816
1817 #ifndef CONFIG_USER_ONLY
1818 /* TLB management */
1819 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1820 {
1821     MIPSCPU *cpu = mips_env_get_cpu(env);
1822
1823     /* Flush qemu's TLB and discard all shadowed entries.  */
1824     tlb_flush(CPU(cpu), flush_global);
1825     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1826 }
1827
1828 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1829 {
1830     /* Discard entries from env->tlb[first] onwards.  */
1831     while (env->tlb->tlb_in_use > first) {
1832         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1833     }
1834 }
1835
1836 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1837 {
1838     r4k_tlb_t *tlb;
1839
1840     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1841     tlb = &env->tlb->mmu.r4k.tlb[idx];
1842     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1843 #if defined(TARGET_MIPS64)
1844     tlb->VPN &= env->SEGMask;
1845 #endif
1846     tlb->ASID = env->CP0_EntryHi & 0xFF;
1847     tlb->PageMask = env->CP0_PageMask;
1848     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1849     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1850     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1851     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1852     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1853     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1854     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1855     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1856     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1857 }
1858
1859 void r4k_helper_tlbwi(CPUMIPSState *env)
1860 {
1861     r4k_tlb_t *tlb;
1862     int idx;
1863     target_ulong VPN;
1864     uint8_t ASID;
1865     bool G, V0, D0, V1, D1;
1866
1867     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1868     tlb = &env->tlb->mmu.r4k.tlb[idx];
1869     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1870 #if defined(TARGET_MIPS64)
1871     VPN &= env->SEGMask;
1872 #endif
1873     ASID = env->CP0_EntryHi & 0xff;
1874     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1875     V0 = (env->CP0_EntryLo0 & 2) != 0;
1876     D0 = (env->CP0_EntryLo0 & 4) != 0;
1877     V1 = (env->CP0_EntryLo1 & 2) != 0;
1878     D1 = (env->CP0_EntryLo1 & 4) != 0;
1879
1880     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1881        permissions on the current entry. */
1882     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1883         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1884         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1885         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1886     }
1887
1888     r4k_invalidate_tlb(env, idx, 0);
1889     r4k_fill_tlb(env, idx);
1890 }
1891
1892 void r4k_helper_tlbwr(CPUMIPSState *env)
1893 {
1894     int r = cpu_mips_get_random(env);
1895
1896     r4k_invalidate_tlb(env, r, 1);
1897     r4k_fill_tlb(env, r);
1898 }
1899
1900 void r4k_helper_tlbp(CPUMIPSState *env)
1901 {
1902     r4k_tlb_t *tlb;
1903     target_ulong mask;
1904     target_ulong tag;
1905     target_ulong VPN;
1906     uint8_t ASID;
1907     int i;
1908
1909     ASID = env->CP0_EntryHi & 0xFF;
1910     for (i = 0; i < env->tlb->nb_tlb; i++) {
1911         tlb = &env->tlb->mmu.r4k.tlb[i];
1912         /* 1k pages are not supported. */
1913         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1914         tag = env->CP0_EntryHi & ~mask;
1915         VPN = tlb->VPN & ~mask;
1916 #if defined(TARGET_MIPS64)
1917         tag &= env->SEGMask;
1918 #endif
1919         /* Check ASID, virtual page number & size */
1920         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1921             /* TLB match */
1922             env->CP0_Index = i;
1923             break;
1924         }
1925     }
1926     if (i == env->tlb->nb_tlb) {
1927         /* No match.  Discard any shadow entries, if any of them match.  */
1928         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1929             tlb = &env->tlb->mmu.r4k.tlb[i];
1930             /* 1k pages are not supported. */
1931             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1932             tag = env->CP0_EntryHi & ~mask;
1933             VPN = tlb->VPN & ~mask;
1934 #if defined(TARGET_MIPS64)
1935             tag &= env->SEGMask;
1936 #endif
1937             /* Check ASID, virtual page number & size */
1938             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1939                 r4k_mips_tlb_flush_extra (env, i);
1940                 break;
1941             }
1942         }
1943
1944         env->CP0_Index |= 0x80000000;
1945     }
1946 }
1947
1948 void r4k_helper_tlbr(CPUMIPSState *env)
1949 {
1950     r4k_tlb_t *tlb;
1951     uint8_t ASID;
1952     int idx;
1953
1954     ASID = env->CP0_EntryHi & 0xFF;
1955     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1956     tlb = &env->tlb->mmu.r4k.tlb[idx];
1957
1958     /* If this will change the current ASID, flush qemu's TLB.  */
1959     if (ASID != tlb->ASID)
1960         cpu_mips_tlb_flush (env, 1);
1961
1962     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1963
1964     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1965     env->CP0_PageMask = tlb->PageMask;
1966     env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1967                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1968     env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1969                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1970 }
1971
1972 void helper_tlbwi(CPUMIPSState *env)
1973 {
1974     env->tlb->helper_tlbwi(env);
1975 }
1976
1977 void helper_tlbwr(CPUMIPSState *env)
1978 {
1979     env->tlb->helper_tlbwr(env);
1980 }
1981
1982 void helper_tlbp(CPUMIPSState *env)
1983 {
1984     env->tlb->helper_tlbp(env);
1985 }
1986
1987 void helper_tlbr(CPUMIPSState *env)
1988 {
1989     env->tlb->helper_tlbr(env);
1990 }
1991
1992 /* Specials */
1993 target_ulong helper_di(CPUMIPSState *env)
1994 {
1995     target_ulong t0 = env->CP0_Status;
1996
1997     env->CP0_Status = t0 & ~(1 << CP0St_IE);
1998     return t0;
1999 }
2000
2001 target_ulong helper_ei(CPUMIPSState *env)
2002 {
2003     target_ulong t0 = env->CP0_Status;
2004
2005     env->CP0_Status = t0 | (1 << CP0St_IE);
2006     return t0;
2007 }
2008
2009 static void debug_pre_eret(CPUMIPSState *env)
2010 {
2011     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2012         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2013                 env->active_tc.PC, env->CP0_EPC);
2014         if (env->CP0_Status & (1 << CP0St_ERL))
2015             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2016         if (env->hflags & MIPS_HFLAG_DM)
2017             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2018         qemu_log("\n");
2019     }
2020 }
2021
2022 static void debug_post_eret(CPUMIPSState *env)
2023 {
2024     MIPSCPU *cpu = mips_env_get_cpu(env);
2025
2026     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2027         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2028                 env->active_tc.PC, env->CP0_EPC);
2029         if (env->CP0_Status & (1 << CP0St_ERL))
2030             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2031         if (env->hflags & MIPS_HFLAG_DM)
2032             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2033         switch (env->hflags & MIPS_HFLAG_KSU) {
2034         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2035         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2036         case MIPS_HFLAG_KM: qemu_log("\n"); break;
2037         default:
2038             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2039             break;
2040         }
2041     }
2042 }
2043
2044 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2045 {
2046     env->active_tc.PC = error_pc & ~(target_ulong)1;
2047     if (error_pc & 1) {
2048         env->hflags |= MIPS_HFLAG_M16;
2049     } else {
2050         env->hflags &= ~(MIPS_HFLAG_M16);
2051     }
2052 }
2053
2054 void helper_eret(CPUMIPSState *env)
2055 {
2056     debug_pre_eret(env);
2057     if (env->CP0_Status & (1 << CP0St_ERL)) {
2058         set_pc(env, env->CP0_ErrorEPC);
2059         env->CP0_Status &= ~(1 << CP0St_ERL);
2060     } else {
2061         set_pc(env, env->CP0_EPC);
2062         env->CP0_Status &= ~(1 << CP0St_EXL);
2063     }
2064     compute_hflags(env);
2065     debug_post_eret(env);
2066     env->lladdr = 1;
2067 }
2068
2069 void helper_deret(CPUMIPSState *env)
2070 {
2071     debug_pre_eret(env);
2072     set_pc(env, env->CP0_DEPC);
2073
2074     env->hflags &= MIPS_HFLAG_DM;
2075     compute_hflags(env);
2076     debug_post_eret(env);
2077     env->lladdr = 1;
2078 }
2079 #endif /* !CONFIG_USER_ONLY */
2080
2081 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2082 {
2083     if ((env->hflags & MIPS_HFLAG_CP0) ||
2084         (env->CP0_HWREna & (1 << 0)))
2085         return env->CP0_EBase & 0x3ff;
2086     else
2087         helper_raise_exception(env, EXCP_RI);
2088
2089     return 0;
2090 }
2091
2092 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2093 {
2094     if ((env->hflags & MIPS_HFLAG_CP0) ||
2095         (env->CP0_HWREna & (1 << 1)))
2096         return env->SYNCI_Step;
2097     else
2098         helper_raise_exception(env, EXCP_RI);
2099
2100     return 0;
2101 }
2102
2103 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2104 {
2105     if ((env->hflags & MIPS_HFLAG_CP0) ||
2106         (env->CP0_HWREna & (1 << 2)))
2107         return env->CP0_Count;
2108     else
2109         helper_raise_exception(env, EXCP_RI);
2110
2111     return 0;
2112 }
2113
2114 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2115 {
2116     if ((env->hflags & MIPS_HFLAG_CP0) ||
2117         (env->CP0_HWREna & (1 << 3)))
2118         return env->CCRes;
2119     else
2120         helper_raise_exception(env, EXCP_RI);
2121
2122     return 0;
2123 }
2124
2125 void helper_pmon(CPUMIPSState *env, int function)
2126 {
2127     function /= 2;
2128     switch (function) {
2129     case 2: /* TODO: char inbyte(int waitflag); */
2130         if (env->active_tc.gpr[4] == 0)
2131             env->active_tc.gpr[2] = -1;
2132         /* Fall through */
2133     case 11: /* TODO: char inbyte (void); */
2134         env->active_tc.gpr[2] = -1;
2135         break;
2136     case 3:
2137     case 12:
2138         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2139         break;
2140     case 17:
2141         break;
2142     case 158:
2143         {
2144             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2145             printf("%s", fmt);
2146         }
2147         break;
2148     }
2149 }
2150
2151 void helper_wait(CPUMIPSState *env)
2152 {
2153     CPUState *cs = CPU(mips_env_get_cpu(env));
2154
2155     cs->halted = 1;
2156     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2157     helper_raise_exception(env, EXCP_HLT);
2158 }
2159
2160 #if !defined(CONFIG_USER_ONLY)
2161
2162 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2163                                   int is_write, int is_user, uintptr_t retaddr)
2164 {
2165     MIPSCPU *cpu = MIPS_CPU(cs);
2166     CPUMIPSState *env = &cpu->env;
2167
2168     env->CP0_BadVAddr = addr;
2169     do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
2170 }
2171
2172 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2173               uintptr_t retaddr)
2174 {
2175     int ret;
2176
2177     ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2178     if (ret) {
2179         MIPSCPU *cpu = MIPS_CPU(cs);
2180         CPUMIPSState *env = &cpu->env;
2181
2182         do_raise_exception_err(env, cs->exception_index,
2183                                env->error_code, retaddr);
2184     }
2185 }
2186
2187 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2188                                 bool is_write, bool is_exec, int unused,
2189                                 unsigned size)
2190 {
2191     MIPSCPU *cpu = MIPS_CPU(cs);
2192     CPUMIPSState *env = &cpu->env;
2193
2194     /*
2195      * Raising an exception with KVM enabled will crash because it won't be from
2196      * the main execution loop so the longjmp won't have a matching setjmp.
2197      * Until we can trigger a bus error exception through KVM lets just ignore
2198      * the access.
2199      */
2200     if (kvm_enabled()) {
2201         return;
2202     }
2203
2204     if (is_exec) {
2205         helper_raise_exception(env, EXCP_IBE);
2206     } else {
2207         helper_raise_exception(env, EXCP_DBE);
2208     }
2209 }
2210 #endif /* !CONFIG_USER_ONLY */
2211
2212 /* Complex FPU operations which may need stack space. */
2213
2214 #define FLOAT_TWO32 make_float32(1 << 30)
2215 #define FLOAT_TWO64 make_float64(1ULL << 62)
2216 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2217 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2218
2219 /* convert MIPS rounding mode in FCR31 to IEEE library */
2220 static unsigned int ieee_rm[] = {
2221     float_round_nearest_even,
2222     float_round_to_zero,
2223     float_round_up,
2224     float_round_down
2225 };
2226
2227 static inline void restore_rounding_mode(CPUMIPSState *env)
2228 {
2229     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
2230                             &env->active_fpu.fp_status);
2231 }
2232
2233 static inline void restore_flush_mode(CPUMIPSState *env)
2234 {
2235     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
2236                       &env->active_fpu.fp_status);
2237 }
2238
2239 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2240 {
2241     target_ulong arg1 = 0;
2242
2243     switch (reg) {
2244     case 0:
2245         arg1 = (int32_t)env->active_fpu.fcr0;
2246         break;
2247     case 1:
2248         /* UFR Support - Read Status FR */
2249         if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2250             if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2251                 arg1 = (int32_t)
2252                        ((env->CP0_Status & (1  << CP0St_FR)) >> CP0St_FR);
2253             } else {
2254                 helper_raise_exception(env, EXCP_RI);
2255             }
2256         }
2257         break;
2258     case 25:
2259         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2260         break;
2261     case 26:
2262         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2263         break;
2264     case 28:
2265         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2266         break;
2267     default:
2268         arg1 = (int32_t)env->active_fpu.fcr31;
2269         break;
2270     }
2271
2272     return arg1;
2273 }
2274
2275 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2276 {
2277     switch (fs) {
2278     case 1:
2279         /* UFR Alias - Reset Status FR */
2280         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2281             return;
2282         }
2283         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2284             env->CP0_Status &= ~(1 << CP0St_FR);
2285             compute_hflags(env);
2286         } else {
2287             helper_raise_exception(env, EXCP_RI);
2288         }
2289         break;
2290     case 4:
2291         /* UNFR Alias - Set Status FR */
2292         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2293             return;
2294         }
2295         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2296             env->CP0_Status |= (1 << CP0St_FR);
2297             compute_hflags(env);
2298         } else {
2299             helper_raise_exception(env, EXCP_RI);
2300         }
2301         break;
2302     case 25:
2303         if (arg1 & 0xffffff00)
2304             return;
2305         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2306                      ((arg1 & 0x1) << 23);
2307         break;
2308     case 26:
2309         if (arg1 & 0x007c0000)
2310             return;
2311         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2312         break;
2313     case 28:
2314         if (arg1 & 0x007c0000)
2315             return;
2316         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2317                      ((arg1 & 0x4) << 22);
2318         break;
2319     case 31:
2320         if (arg1 & 0x007c0000)
2321             return;
2322         env->active_fpu.fcr31 = arg1;
2323         break;
2324     default:
2325         return;
2326     }
2327     /* set rounding mode */
2328     restore_rounding_mode(env);
2329     /* set flush-to-zero mode */
2330     restore_flush_mode(env);
2331     set_float_exception_flags(0, &env->active_fpu.fp_status);
2332     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2333         do_raise_exception(env, EXCP_FPE, GETPC());
2334 }
2335
2336 static inline int ieee_ex_to_mips(int xcpt)
2337 {
2338     int ret = 0;
2339     if (xcpt) {
2340         if (xcpt & float_flag_invalid) {
2341             ret |= FP_INVALID;
2342         }
2343         if (xcpt & float_flag_overflow) {
2344             ret |= FP_OVERFLOW;
2345         }
2346         if (xcpt & float_flag_underflow) {
2347             ret |= FP_UNDERFLOW;
2348         }
2349         if (xcpt & float_flag_divbyzero) {
2350             ret |= FP_DIV0;
2351         }
2352         if (xcpt & float_flag_inexact) {
2353             ret |= FP_INEXACT;
2354         }
2355     }
2356     return ret;
2357 }
2358
2359 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2360 {
2361     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2362
2363     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2364
2365     if (tmp) {
2366         set_float_exception_flags(0, &env->active_fpu.fp_status);
2367
2368         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2369             do_raise_exception(env, EXCP_FPE, pc);
2370         } else {
2371             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2372         }
2373     }
2374 }
2375
2376 /* Float support.
2377    Single precition routines have a "s" suffix, double precision a
2378    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2379    paired single lower "pl", paired single upper "pu".  */
2380
2381 /* unary operations, modifying fp status  */
2382 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2383 {
2384     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2385     update_fcr31(env, GETPC());
2386     return fdt0;
2387 }
2388
2389 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2390 {
2391     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2392     update_fcr31(env, GETPC());
2393     return fst0;
2394 }
2395
2396 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2397 {
2398     uint64_t fdt2;
2399
2400     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2401     update_fcr31(env, GETPC());
2402     return fdt2;
2403 }
2404
2405 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2406 {
2407     uint64_t fdt2;
2408
2409     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2410     update_fcr31(env, GETPC());
2411     return fdt2;
2412 }
2413
2414 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2415 {
2416     uint64_t fdt2;
2417
2418     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2419     update_fcr31(env, GETPC());
2420     return fdt2;
2421 }
2422
2423 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2424 {
2425     uint64_t dt2;
2426
2427     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2428     if (get_float_exception_flags(&env->active_fpu.fp_status)
2429         & (float_flag_invalid | float_flag_overflow)) {
2430         dt2 = FP_TO_INT64_OVERFLOW;
2431     }
2432     update_fcr31(env, GETPC());
2433     return dt2;
2434 }
2435
2436 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2437 {
2438     uint64_t dt2;
2439
2440     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2441     if (get_float_exception_flags(&env->active_fpu.fp_status)
2442         & (float_flag_invalid | float_flag_overflow)) {
2443         dt2 = FP_TO_INT64_OVERFLOW;
2444     }
2445     update_fcr31(env, GETPC());
2446     return dt2;
2447 }
2448
2449 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2450 {
2451     uint32_t fst2;
2452     uint32_t fsth2;
2453
2454     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2455     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2456     update_fcr31(env, GETPC());
2457     return ((uint64_t)fsth2 << 32) | fst2;
2458 }
2459
2460 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2461 {
2462     uint32_t wt2;
2463     uint32_t wth2;
2464     int excp, excph;
2465
2466     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2467     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2468     if (excp & (float_flag_overflow | float_flag_invalid)) {
2469         wt2 = FP_TO_INT32_OVERFLOW;
2470     }
2471
2472     set_float_exception_flags(0, &env->active_fpu.fp_status);
2473     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2474     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2475     if (excph & (float_flag_overflow | float_flag_invalid)) {
2476         wth2 = FP_TO_INT32_OVERFLOW;
2477     }
2478
2479     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2480     update_fcr31(env, GETPC());
2481
2482     return ((uint64_t)wth2 << 32) | wt2;
2483 }
2484
2485 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2486 {
2487     uint32_t fst2;
2488
2489     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2490     update_fcr31(env, GETPC());
2491     return fst2;
2492 }
2493
2494 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2495 {
2496     uint32_t fst2;
2497
2498     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2499     update_fcr31(env, GETPC());
2500     return fst2;
2501 }
2502
2503 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2504 {
2505     uint32_t fst2;
2506
2507     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2508     update_fcr31(env, GETPC());
2509     return fst2;
2510 }
2511
2512 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2513 {
2514     uint32_t wt2;
2515
2516     wt2 = wt0;
2517     update_fcr31(env, GETPC());
2518     return wt2;
2519 }
2520
2521 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2522 {
2523     uint32_t wt2;
2524
2525     wt2 = wth0;
2526     update_fcr31(env, GETPC());
2527     return wt2;
2528 }
2529
2530 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2531 {
2532     uint32_t wt2;
2533
2534     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2535     update_fcr31(env, GETPC());
2536     if (get_float_exception_flags(&env->active_fpu.fp_status)
2537         & (float_flag_invalid | float_flag_overflow)) {
2538         wt2 = FP_TO_INT32_OVERFLOW;
2539     }
2540     return wt2;
2541 }
2542
2543 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2544 {
2545     uint32_t wt2;
2546
2547     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2548     if (get_float_exception_flags(&env->active_fpu.fp_status)
2549         & (float_flag_invalid | float_flag_overflow)) {
2550         wt2 = FP_TO_INT32_OVERFLOW;
2551     }
2552     update_fcr31(env, GETPC());
2553     return wt2;
2554 }
2555
2556 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2557 {
2558     uint64_t dt2;
2559
2560     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2561     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2562     restore_rounding_mode(env);
2563     if (get_float_exception_flags(&env->active_fpu.fp_status)
2564         & (float_flag_invalid | float_flag_overflow)) {
2565         dt2 = FP_TO_INT64_OVERFLOW;
2566     }
2567     update_fcr31(env, GETPC());
2568     return dt2;
2569 }
2570
2571 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2572 {
2573     uint64_t dt2;
2574
2575     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2576     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2577     restore_rounding_mode(env);
2578     if (get_float_exception_flags(&env->active_fpu.fp_status)
2579         & (float_flag_invalid | float_flag_overflow)) {
2580         dt2 = FP_TO_INT64_OVERFLOW;
2581     }
2582     update_fcr31(env, GETPC());
2583     return dt2;
2584 }
2585
2586 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2587 {
2588     uint32_t wt2;
2589
2590     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2591     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2592     restore_rounding_mode(env);
2593     if (get_float_exception_flags(&env->active_fpu.fp_status)
2594         & (float_flag_invalid | float_flag_overflow)) {
2595         wt2 = FP_TO_INT32_OVERFLOW;
2596     }
2597     update_fcr31(env, GETPC());
2598     return wt2;
2599 }
2600
2601 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2602 {
2603     uint32_t wt2;
2604
2605     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2606     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2607     restore_rounding_mode(env);
2608     if (get_float_exception_flags(&env->active_fpu.fp_status)
2609         & (float_flag_invalid | float_flag_overflow)) {
2610         wt2 = FP_TO_INT32_OVERFLOW;
2611     }
2612     update_fcr31(env, GETPC());
2613     return wt2;
2614 }
2615
2616 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2617 {
2618     uint64_t dt2;
2619
2620     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2621     if (get_float_exception_flags(&env->active_fpu.fp_status)
2622         & (float_flag_invalid | float_flag_overflow)) {
2623         dt2 = FP_TO_INT64_OVERFLOW;
2624     }
2625     update_fcr31(env, GETPC());
2626     return dt2;
2627 }
2628
2629 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2630 {
2631     uint64_t dt2;
2632
2633     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2634     if (get_float_exception_flags(&env->active_fpu.fp_status)
2635         & (float_flag_invalid | float_flag_overflow)) {
2636         dt2 = FP_TO_INT64_OVERFLOW;
2637     }
2638     update_fcr31(env, GETPC());
2639     return dt2;
2640 }
2641
2642 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2643 {
2644     uint32_t wt2;
2645
2646     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2647     if (get_float_exception_flags(&env->active_fpu.fp_status)
2648         & (float_flag_invalid | float_flag_overflow)) {
2649         wt2 = FP_TO_INT32_OVERFLOW;
2650     }
2651     update_fcr31(env, GETPC());
2652     return wt2;
2653 }
2654
2655 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2656 {
2657     uint32_t wt2;
2658
2659     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2660     if (get_float_exception_flags(&env->active_fpu.fp_status)
2661         & (float_flag_invalid | float_flag_overflow)) {
2662         wt2 = FP_TO_INT32_OVERFLOW;
2663     }
2664     update_fcr31(env, GETPC());
2665     return wt2;
2666 }
2667
2668 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2669 {
2670     uint64_t dt2;
2671
2672     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2673     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2674     restore_rounding_mode(env);
2675     if (get_float_exception_flags(&env->active_fpu.fp_status)
2676         & (float_flag_invalid | float_flag_overflow)) {
2677         dt2 = FP_TO_INT64_OVERFLOW;
2678     }
2679     update_fcr31(env, GETPC());
2680     return dt2;
2681 }
2682
2683 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2684 {
2685     uint64_t dt2;
2686
2687     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2688     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2689     restore_rounding_mode(env);
2690     if (get_float_exception_flags(&env->active_fpu.fp_status)
2691         & (float_flag_invalid | float_flag_overflow)) {
2692         dt2 = FP_TO_INT64_OVERFLOW;
2693     }
2694     update_fcr31(env, GETPC());
2695     return dt2;
2696 }
2697
2698 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2699 {
2700     uint32_t wt2;
2701
2702     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2703     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2704     restore_rounding_mode(env);
2705     if (get_float_exception_flags(&env->active_fpu.fp_status)
2706         & (float_flag_invalid | float_flag_overflow)) {
2707         wt2 = FP_TO_INT32_OVERFLOW;
2708     }
2709     update_fcr31(env, GETPC());
2710     return wt2;
2711 }
2712
2713 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2714 {
2715     uint32_t wt2;
2716
2717     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2718     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2719     restore_rounding_mode(env);
2720     if (get_float_exception_flags(&env->active_fpu.fp_status)
2721         & (float_flag_invalid | float_flag_overflow)) {
2722         wt2 = FP_TO_INT32_OVERFLOW;
2723     }
2724     update_fcr31(env, GETPC());
2725     return wt2;
2726 }
2727
2728 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2729 {
2730     uint64_t dt2;
2731
2732     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2733     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2734     restore_rounding_mode(env);
2735     if (get_float_exception_flags(&env->active_fpu.fp_status)
2736         & (float_flag_invalid | float_flag_overflow)) {
2737         dt2 = FP_TO_INT64_OVERFLOW;
2738     }
2739     update_fcr31(env, GETPC());
2740     return dt2;
2741 }
2742
2743 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2744 {
2745     uint64_t dt2;
2746
2747     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2748     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2749     restore_rounding_mode(env);
2750     if (get_float_exception_flags(&env->active_fpu.fp_status)
2751         & (float_flag_invalid | float_flag_overflow)) {
2752         dt2 = FP_TO_INT64_OVERFLOW;
2753     }
2754     update_fcr31(env, GETPC());
2755     return dt2;
2756 }
2757
2758 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2759 {
2760     uint32_t wt2;
2761
2762     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2763     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2764     restore_rounding_mode(env);
2765     if (get_float_exception_flags(&env->active_fpu.fp_status)
2766         & (float_flag_invalid | float_flag_overflow)) {
2767         wt2 = FP_TO_INT32_OVERFLOW;
2768     }
2769     update_fcr31(env, GETPC());
2770     return wt2;
2771 }
2772
2773 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2774 {
2775     uint32_t wt2;
2776
2777     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2778     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2779     restore_rounding_mode(env);
2780     if (get_float_exception_flags(&env->active_fpu.fp_status)
2781         & (float_flag_invalid | float_flag_overflow)) {
2782         wt2 = FP_TO_INT32_OVERFLOW;
2783     }
2784     update_fcr31(env, GETPC());
2785     return wt2;
2786 }
2787
2788 /* unary operations, not modifying fp status  */
2789 #define FLOAT_UNOP(name)                                       \
2790 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2791 {                                                              \
2792     return float64_ ## name(fdt0);                             \
2793 }                                                              \
2794 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2795 {                                                              \
2796     return float32_ ## name(fst0);                             \
2797 }                                                              \
2798 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2799 {                                                              \
2800     uint32_t wt0;                                              \
2801     uint32_t wth0;                                             \
2802                                                                \
2803     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2804     wth0 = float32_ ## name(fdt0 >> 32);                       \
2805     return ((uint64_t)wth0 << 32) | wt0;                       \
2806 }
2807 FLOAT_UNOP(abs)
2808 FLOAT_UNOP(chs)
2809 #undef FLOAT_UNOP
2810
2811 #define FLOAT_FMADDSUB(name, bits, muladd_arg)                          \
2812 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
2813                                           uint ## bits ## _t fs,        \
2814                                           uint ## bits ## _t ft,        \
2815                                           uint ## bits ## _t fd)        \
2816 {                                                                       \
2817     uint ## bits ## _t fdret;                                           \
2818                                                                         \
2819     fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg,            \
2820                                      &env->active_fpu.fp_status);       \
2821     update_fcr31(env, GETPC());                                         \
2822     return fdret;                                                       \
2823 }
2824
2825 FLOAT_FMADDSUB(maddf_s, 32, 0)
2826 FLOAT_FMADDSUB(maddf_d, 64, 0)
2827 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
2828 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
2829 #undef FLOAT_FMADDSUB
2830
2831 #define FLOAT_MINMAX(name, bits, minmaxfunc)                            \
2832 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
2833                                           uint ## bits ## _t fs,        \
2834                                           uint ## bits ## _t ft)        \
2835 {                                                                       \
2836     uint ## bits ## _t fdret;                                           \
2837                                                                         \
2838     fdret = float ## bits ## _ ## minmaxfunc(fs, ft,                    \
2839                                            &env->active_fpu.fp_status); \
2840     update_fcr31(env, GETPC());                                         \
2841     return fdret;                                                       \
2842 }
2843
2844 FLOAT_MINMAX(max_s, 32, maxnum)
2845 FLOAT_MINMAX(max_d, 64, maxnum)
2846 FLOAT_MINMAX(maxa_s, 32, maxnummag)
2847 FLOAT_MINMAX(maxa_d, 64, maxnummag)
2848
2849 FLOAT_MINMAX(min_s, 32, minnum)
2850 FLOAT_MINMAX(min_d, 64, minnum)
2851 FLOAT_MINMAX(mina_s, 32, minnummag)
2852 FLOAT_MINMAX(mina_d, 64, minnummag)
2853 #undef FLOAT_MINMAX
2854
2855 #define FLOAT_RINT(name, bits)                                              \
2856 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,                \
2857                                           uint ## bits ## _t fs)            \
2858 {                                                                           \
2859     uint ## bits ## _t fdret;                                               \
2860                                                                             \
2861     fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
2862     update_fcr31(env, GETPC());                                             \
2863     return fdret;                                                           \
2864 }
2865
2866 FLOAT_RINT(rint_s, 32)
2867 FLOAT_RINT(rint_d, 64)
2868 #undef FLOAT_RINT
2869
2870 #define FLOAT_CLASS_SIGNALING_NAN      0x001
2871 #define FLOAT_CLASS_QUIET_NAN          0x002
2872 #define FLOAT_CLASS_NEGATIVE_INFINITY  0x004
2873 #define FLOAT_CLASS_NEGATIVE_NORMAL    0x008
2874 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
2875 #define FLOAT_CLASS_NEGATIVE_ZERO      0x020
2876 #define FLOAT_CLASS_POSITIVE_INFINITY  0x040
2877 #define FLOAT_CLASS_POSITIVE_NORMAL    0x080
2878 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
2879 #define FLOAT_CLASS_POSITIVE_ZERO      0x200
2880
2881 #define FLOAT_CLASS(name, bits)                                      \
2882 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg)    \
2883 {                                                                    \
2884     if (float ## bits ## _is_signaling_nan(arg)) {                   \
2885         return FLOAT_CLASS_SIGNALING_NAN;                            \
2886     } else if (float ## bits ## _is_quiet_nan(arg)) {                \
2887         return FLOAT_CLASS_QUIET_NAN;                                \
2888     } else if (float ## bits ## _is_neg(arg)) {                      \
2889         if (float ## bits ## _is_infinity(arg)) {                    \
2890             return FLOAT_CLASS_NEGATIVE_INFINITY;                    \
2891         } else if (float ## bits ## _is_zero(arg)) {                 \
2892             return FLOAT_CLASS_NEGATIVE_ZERO;                        \
2893         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
2894             return FLOAT_CLASS_NEGATIVE_SUBNORMAL;                   \
2895         } else {                                                     \
2896             return FLOAT_CLASS_NEGATIVE_NORMAL;                      \
2897         }                                                            \
2898     } else {                                                         \
2899         if (float ## bits ## _is_infinity(arg)) {                    \
2900             return FLOAT_CLASS_POSITIVE_INFINITY;                    \
2901         } else if (float ## bits ## _is_zero(arg)) {                 \
2902             return FLOAT_CLASS_POSITIVE_ZERO;                        \
2903         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
2904             return FLOAT_CLASS_POSITIVE_SUBNORMAL;                   \
2905         } else {                                                     \
2906             return FLOAT_CLASS_POSITIVE_NORMAL;                      \
2907         }                                                            \
2908     }                                                                \
2909 }
2910
2911 FLOAT_CLASS(class_s, 32)
2912 FLOAT_CLASS(class_d, 64)
2913 #undef FLOAT_CLASS
2914
2915 /* MIPS specific unary operations */
2916 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2917 {
2918     uint64_t fdt2;
2919
2920     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2921     update_fcr31(env, GETPC());
2922     return fdt2;
2923 }
2924
2925 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2926 {
2927     uint32_t fst2;
2928
2929     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2930     update_fcr31(env, GETPC());
2931     return fst2;
2932 }
2933
2934 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2935 {
2936     uint64_t fdt2;
2937
2938     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2939     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2940     update_fcr31(env, GETPC());
2941     return fdt2;
2942 }
2943
2944 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2945 {
2946     uint32_t fst2;
2947
2948     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2949     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2950     update_fcr31(env, GETPC());
2951     return fst2;
2952 }
2953
2954 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2955 {
2956     uint64_t fdt2;
2957
2958     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2959     update_fcr31(env, GETPC());
2960     return fdt2;
2961 }
2962
2963 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2964 {
2965     uint32_t fst2;
2966
2967     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2968     update_fcr31(env, GETPC());
2969     return fst2;
2970 }
2971
2972 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2973 {
2974     uint32_t fst2;
2975     uint32_t fsth2;
2976
2977     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2978     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2979     update_fcr31(env, GETPC());
2980     return ((uint64_t)fsth2 << 32) | fst2;
2981 }
2982
2983 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2984 {
2985     uint64_t fdt2;
2986
2987     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2988     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2989     update_fcr31(env, GETPC());
2990     return fdt2;
2991 }
2992
2993 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2994 {
2995     uint32_t fst2;
2996
2997     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2998     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2999     update_fcr31(env, GETPC());
3000     return fst2;
3001 }
3002
3003 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3004 {
3005     uint32_t fst2;
3006     uint32_t fsth2;
3007
3008     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3009     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3010     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3011     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3012     update_fcr31(env, GETPC());
3013     return ((uint64_t)fsth2 << 32) | fst2;
3014 }
3015
3016 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
3017
3018 /* binary operations */
3019 #define FLOAT_BINOP(name)                                          \
3020 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
3021                                      uint64_t fdt0, uint64_t fdt1) \
3022 {                                                                  \
3023     uint64_t dt2;                                                  \
3024                                                                    \
3025     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
3026     update_fcr31(env, GETPC());                                    \
3027     return dt2;                                                    \
3028 }                                                                  \
3029                                                                    \
3030 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
3031                                      uint32_t fst0, uint32_t fst1) \
3032 {                                                                  \
3033     uint32_t wt2;                                                  \
3034                                                                    \
3035     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3036     update_fcr31(env, GETPC());                                    \
3037     return wt2;                                                    \
3038 }                                                                  \
3039                                                                    \
3040 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
3041                                       uint64_t fdt0,               \
3042                                       uint64_t fdt1)               \
3043 {                                                                  \
3044     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
3045     uint32_t fsth0 = fdt0 >> 32;                                   \
3046     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
3047     uint32_t fsth1 = fdt1 >> 32;                                   \
3048     uint32_t wt2;                                                  \
3049     uint32_t wth2;                                                 \
3050                                                                    \
3051     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3052     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
3053     update_fcr31(env, GETPC());                                    \
3054     return ((uint64_t)wth2 << 32) | wt2;                           \
3055 }
3056
3057 FLOAT_BINOP(add)
3058 FLOAT_BINOP(sub)
3059 FLOAT_BINOP(mul)
3060 FLOAT_BINOP(div)
3061 #undef FLOAT_BINOP
3062
3063 #define UNFUSED_FMA(prefix, a, b, c, flags)                          \
3064 {                                                                    \
3065     a = prefix##_mul(a, b, &env->active_fpu.fp_status);              \
3066     if ((flags) & float_muladd_negate_c) {                           \
3067         a = prefix##_sub(a, c, &env->active_fpu.fp_status);          \
3068     } else {                                                         \
3069         a = prefix##_add(a, c, &env->active_fpu.fp_status);          \
3070     }                                                                \
3071     if ((flags) & float_muladd_negate_result) {                      \
3072         a = prefix##_chs(a);                                         \
3073     }                                                                \
3074 }
3075
3076 /* FMA based operations */
3077 #define FLOAT_FMA(name, type)                                        \
3078 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
3079                                      uint64_t fdt0, uint64_t fdt1,   \
3080                                      uint64_t fdt2)                  \
3081 {                                                                    \
3082     UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type);                    \
3083     update_fcr31(env, GETPC());                                      \
3084     return fdt0;                                                     \
3085 }                                                                    \
3086                                                                      \
3087 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
3088                                      uint32_t fst0, uint32_t fst1,   \
3089                                      uint32_t fst2)                  \
3090 {                                                                    \
3091     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3092     update_fcr31(env, GETPC());                                      \
3093     return fst0;                                                     \
3094 }                                                                    \
3095                                                                      \
3096 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
3097                                       uint64_t fdt0, uint64_t fdt1,  \
3098                                       uint64_t fdt2)                 \
3099 {                                                                    \
3100     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
3101     uint32_t fsth0 = fdt0 >> 32;                                     \
3102     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
3103     uint32_t fsth1 = fdt1 >> 32;                                     \
3104     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
3105     uint32_t fsth2 = fdt2 >> 32;                                     \
3106                                                                      \
3107     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3108     UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type);                 \
3109     update_fcr31(env, GETPC());                                      \
3110     return ((uint64_t)fsth0 << 32) | fst0;                           \
3111 }
3112 FLOAT_FMA(madd, 0)
3113 FLOAT_FMA(msub, float_muladd_negate_c)
3114 FLOAT_FMA(nmadd, float_muladd_negate_result)
3115 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3116 #undef FLOAT_FMA
3117
3118 /* MIPS specific binary operations */
3119 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3120 {
3121     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3122     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3123     update_fcr31(env, GETPC());
3124     return fdt2;
3125 }
3126
3127 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3128 {
3129     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3130     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3131     update_fcr31(env, GETPC());
3132     return fst2;
3133 }
3134
3135 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3136 {
3137     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3138     uint32_t fsth0 = fdt0 >> 32;
3139     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3140     uint32_t fsth2 = fdt2 >> 32;
3141
3142     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3143     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3144     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3145     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3146     update_fcr31(env, GETPC());
3147     return ((uint64_t)fsth2 << 32) | fst2;
3148 }
3149
3150 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3151 {
3152     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3153     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3154     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3155     update_fcr31(env, GETPC());
3156     return fdt2;
3157 }
3158
3159 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3160 {
3161     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3162     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3163     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3164     update_fcr31(env, GETPC());
3165     return fst2;
3166 }
3167
3168 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3169 {
3170     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3171     uint32_t fsth0 = fdt0 >> 32;
3172     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3173     uint32_t fsth2 = fdt2 >> 32;
3174
3175     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3176     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3177     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3178     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3179     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3180     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3181     update_fcr31(env, GETPC());
3182     return ((uint64_t)fsth2 << 32) | fst2;
3183 }
3184
3185 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3186 {
3187     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3188     uint32_t fsth0 = fdt0 >> 32;
3189     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3190     uint32_t fsth1 = fdt1 >> 32;
3191     uint32_t fst2;
3192     uint32_t fsth2;
3193
3194     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3195     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3196     update_fcr31(env, GETPC());
3197     return ((uint64_t)fsth2 << 32) | fst2;
3198 }
3199
3200 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3201 {
3202     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3203     uint32_t fsth0 = fdt0 >> 32;
3204     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3205     uint32_t fsth1 = fdt1 >> 32;
3206     uint32_t fst2;
3207     uint32_t fsth2;
3208
3209     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3210     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3211     update_fcr31(env, GETPC());
3212     return ((uint64_t)fsth2 << 32) | fst2;
3213 }
3214
3215 /* compare operations */
3216 #define FOP_COND_D(op, cond)                                   \
3217 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3218                          uint64_t fdt1, int cc)                \
3219 {                                                              \
3220     int c;                                                     \
3221     c = cond;                                                  \
3222     update_fcr31(env, GETPC());                                \
3223     if (c)                                                     \
3224         SET_FP_COND(cc, env->active_fpu);                      \
3225     else                                                       \
3226         CLEAR_FP_COND(cc, env->active_fpu);                    \
3227 }                                                              \
3228 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3229                             uint64_t fdt1, int cc)             \
3230 {                                                              \
3231     int c;                                                     \
3232     fdt0 = float64_abs(fdt0);                                  \
3233     fdt1 = float64_abs(fdt1);                                  \
3234     c = cond;                                                  \
3235     update_fcr31(env, GETPC());                                \
3236     if (c)                                                     \
3237         SET_FP_COND(cc, env->active_fpu);                      \
3238     else                                                       \
3239         CLEAR_FP_COND(cc, env->active_fpu);                    \
3240 }
3241
3242 /* NOTE: the comma operator will make "cond" to eval to false,
3243  * but float64_unordered_quiet() is still called. */
3244 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3245 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3246 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3247 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3248 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3249 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3250 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3251 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3252 /* NOTE: the comma operator will make "cond" to eval to false,
3253  * but float64_unordered() is still called. */
3254 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3255 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3256 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3257 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3258 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3259 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3260 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3261 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3262
3263 #define FOP_COND_S(op, cond)                                   \
3264 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3265                          uint32_t fst1, int cc)                \
3266 {                                                              \
3267     int c;                                                     \
3268     c = cond;                                                  \
3269     update_fcr31(env, GETPC());                                \
3270     if (c)                                                     \
3271         SET_FP_COND(cc, env->active_fpu);                      \
3272     else                                                       \
3273         CLEAR_FP_COND(cc, env->active_fpu);                    \
3274 }                                                              \
3275 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3276                             uint32_t fst1, int cc)             \
3277 {                                                              \
3278     int c;                                                     \
3279     fst0 = float32_abs(fst0);                                  \
3280     fst1 = float32_abs(fst1);                                  \
3281     c = cond;                                                  \
3282     update_fcr31(env, GETPC());                                \
3283     if (c)                                                     \
3284         SET_FP_COND(cc, env->active_fpu);                      \
3285     else                                                       \
3286         CLEAR_FP_COND(cc, env->active_fpu);                    \
3287 }
3288
3289 /* NOTE: the comma operator will make "cond" to eval to false,
3290  * but float32_unordered_quiet() is still called. */
3291 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3292 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3293 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3294 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3295 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3296 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3297 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3298 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3299 /* NOTE: the comma operator will make "cond" to eval to false,
3300  * but float32_unordered() is still called. */
3301 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3302 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3303 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3304 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3305 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3306 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3307 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3308 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3309
3310 #define FOP_COND_PS(op, condl, condh)                           \
3311 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3312                           uint64_t fdt1, int cc)                \
3313 {                                                               \
3314     uint32_t fst0, fsth0, fst1, fsth1;                          \
3315     int ch, cl;                                                 \
3316     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3317     fsth0 = fdt0 >> 32;                                         \
3318     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3319     fsth1 = fdt1 >> 32;                                         \
3320     cl = condl;                                                 \
3321     ch = condh;                                                 \
3322     update_fcr31(env, GETPC());                                 \
3323     if (cl)                                                     \
3324         SET_FP_COND(cc, env->active_fpu);                       \
3325     else                                                        \
3326         CLEAR_FP_COND(cc, env->active_fpu);                     \
3327     if (ch)                                                     \
3328         SET_FP_COND(cc + 1, env->active_fpu);                   \
3329     else                                                        \
3330         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3331 }                                                               \
3332 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3333                              uint64_t fdt1, int cc)             \
3334 {                                                               \
3335     uint32_t fst0, fsth0, fst1, fsth1;                          \
3336     int ch, cl;                                                 \
3337     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3338     fsth0 = float32_abs(fdt0 >> 32);                            \
3339     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3340     fsth1 = float32_abs(fdt1 >> 32);                            \
3341     cl = condl;                                                 \
3342     ch = condh;                                                 \
3343     update_fcr31(env, GETPC());                                 \
3344     if (cl)                                                     \
3345         SET_FP_COND(cc, env->active_fpu);                       \
3346     else                                                        \
3347         CLEAR_FP_COND(cc, env->active_fpu);                     \
3348     if (ch)                                                     \
3349         SET_FP_COND(cc + 1, env->active_fpu);                   \
3350     else                                                        \
3351         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3352 }
3353
3354 /* NOTE: the comma operator will make "cond" to eval to false,
3355  * but float32_unordered_quiet() is still called. */
3356 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3357                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3358 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3359                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3360 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3361                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3362 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3363                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3364 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3365                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3366 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3367                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3368 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3369                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3370 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3371                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3372 /* NOTE: the comma operator will make "cond" to eval to false,
3373  * but float32_unordered() is still called. */
3374 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3375                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3376 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3377                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3378 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3379                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3380 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3381                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3382 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3383                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3384 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3385                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3386 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3387                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3388 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3389                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3390
3391 /* R6 compare operations */
3392 #define FOP_CONDN_D(op, cond)                                       \
3393 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0,  \
3394                          uint64_t fdt1)                             \
3395 {                                                                   \
3396     uint64_t c;                                                     \
3397     c = cond;                                                       \
3398     update_fcr31(env, GETPC());                                     \
3399     if (c) {                                                        \
3400         return -1;                                                  \
3401     } else {                                                        \
3402         return 0;                                                   \
3403     }                                                               \
3404 }
3405
3406 /* NOTE: the comma operator will make "cond" to eval to false,
3407  * but float64_unordered_quiet() is still called. */
3408 FOP_CONDN_D(af,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3409 FOP_CONDN_D(un,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
3410 FOP_CONDN_D(eq,  (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3411 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3412                   || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3413 FOP_CONDN_D(lt,  (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3414 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3415                   || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3416 FOP_CONDN_D(le,  (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3417 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3418                   || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3419 /* NOTE: the comma operator will make "cond" to eval to false,
3420  * but float64_unordered() is still called. */
3421 FOP_CONDN_D(saf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3422 FOP_CONDN_D(sun,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
3423 FOP_CONDN_D(seq,  (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3424 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3425                    || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3426 FOP_CONDN_D(slt,  (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3427 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3428                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3429 FOP_CONDN_D(sle,  (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3430 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3431                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3432 FOP_CONDN_D(or,   (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3433                    || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3434 FOP_CONDN_D(une,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3435                    || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3436                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3437 FOP_CONDN_D(ne,   (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3438                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3439 FOP_CONDN_D(sor,  (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
3440                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3441 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3442                    || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3443                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3444 FOP_CONDN_D(sne,  (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3445                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3446
3447 #define FOP_CONDN_S(op, cond)                                       \
3448 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0,  \
3449                          uint32_t fst1)                             \
3450 {                                                                   \
3451     uint64_t c;                                                     \
3452     c = cond;                                                       \
3453     update_fcr31(env, GETPC());                                     \
3454     if (c) {                                                        \
3455         return -1;                                                  \
3456     } else {                                                        \
3457         return 0;                                                   \
3458     }                                                               \
3459 }
3460
3461 /* NOTE: the comma operator will make "cond" to eval to false,
3462  * but float32_unordered_quiet() is still called. */
3463 FOP_CONDN_S(af,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3464 FOP_CONDN_S(un,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
3465 FOP_CONDN_S(eq,   (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3466 FOP_CONDN_S(ueq,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3467                    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3468 FOP_CONDN_S(lt,   (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3469 FOP_CONDN_S(ult,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3470                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3471 FOP_CONDN_S(le,   (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3472 FOP_CONDN_S(ule,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3473                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3474 /* NOTE: the comma operator will make "cond" to eval to false,
3475  * but float32_unordered() is still called. */
3476 FOP_CONDN_S(saf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3477 FOP_CONDN_S(sun,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
3478 FOP_CONDN_S(seq,  (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3479 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3480                    || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3481 FOP_CONDN_S(slt,  (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3482 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3483                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3484 FOP_CONDN_S(sle,  (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3485 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3486                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3487 FOP_CONDN_S(or,   (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
3488                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3489 FOP_CONDN_S(une,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3490                    || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3491                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3492 FOP_CONDN_S(ne,   (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3493                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3494 FOP_CONDN_S(sor,  (float32_le(fst1, fst0, &env->active_fpu.fp_status)
3495                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3496 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3497                    || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3498                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3499 FOP_CONDN_S(sne,  (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3500                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))