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s390x/cpumodel: document S390FeatDef.bit not applicable
[qemu.git] / hw / arm / pxa2xx.c
blob5805a2c8584052b727c69719cb37dd6217a932b2
1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu/error-report.h"
12 #include "qapi/error.h"
13 #include "qemu-common.h"
14 #include "cpu.h"
15 #include "hw/sysbus.h"
16 #include "hw/arm/pxa.h"
17 #include "sysemu/sysemu.h"
18 #include "hw/char/serial.h"
19 #include "hw/i2c/i2c.h"
20 #include "hw/ssi/ssi.h"
21 #include "chardev/char-fe.h"
22 #include "sysemu/block-backend.h"
23 #include "sysemu/blockdev.h"
24 #include "qemu/cutils.h"
25
26 static struct {
27 hwaddr io_base;
28 int irqn;
29 } pxa255_serial[] = {
30 { 0x40100000, PXA2XX_PIC_FFUART },
31 { 0x40200000, PXA2XX_PIC_BTUART },
32 { 0x40700000, PXA2XX_PIC_STUART },
33 { 0x41600000, PXA25X_PIC_HWUART },
34 { 0, 0 }
35 }, pxa270_serial[] = {
36 { 0x40100000, PXA2XX_PIC_FFUART },
37 { 0x40200000, PXA2XX_PIC_BTUART },
38 { 0x40700000, PXA2XX_PIC_STUART },
39 { 0, 0 }
40 };
41
42 typedef struct PXASSPDef {
43 hwaddr io_base;
44 int irqn;
45 } PXASSPDef;
46
47 #if 0
48 static PXASSPDef pxa250_ssp[] = {
49 { 0x41000000, PXA2XX_PIC_SSP },
50 { 0, 0 }
51 };
52 #endif
53
54 static PXASSPDef pxa255_ssp[] = {
55 { 0x41000000, PXA2XX_PIC_SSP },
56 { 0x41400000, PXA25X_PIC_NSSP },
57 { 0, 0 }
58 };
59
60 #if 0
61 static PXASSPDef pxa26x_ssp[] = {
62 { 0x41000000, PXA2XX_PIC_SSP },
63 { 0x41400000, PXA25X_PIC_NSSP },
64 { 0x41500000, PXA26X_PIC_ASSP },
65 { 0, 0 }
66 };
67 #endif
68
69 static PXASSPDef pxa27x_ssp[] = {
70 { 0x41000000, PXA2XX_PIC_SSP },
71 { 0x41700000, PXA27X_PIC_SSP2 },
72 { 0x41900000, PXA2XX_PIC_SSP3 },
73 { 0, 0 }
74 };
75
76 #define PMCR 0x00 /* Power Manager Control register */
77 #define PSSR 0x04 /* Power Manager Sleep Status register */
78 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
79 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
80 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
81 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
82 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
83 #define PCFR 0x1c /* Power Manager General Configuration register */
84 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
85 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
86 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
87 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
88 #define RCSR 0x30 /* Reset Controller Status register */
89 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
90 #define PTSR 0x38 /* Power Manager Standby Configuration register */
91 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
92 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
93 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
94 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
95 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
96 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
97
98 static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr,
99 unsigned size)
100 {
101 PXA2xxState *s = (PXA2xxState *) opaque;
102
103 switch (addr) {
104 case PMCR ... PCMD31:
105 if (addr & 3)
106 goto fail;
107
108 return s->pm_regs[addr >> 2];
109 default:
110 fail:
111 printf("%s: Bad register " REG_FMT "\n", __func__, addr);
112 break;
113 }
114 return 0;
115 }
116
117 static void pxa2xx_pm_write(void *opaque, hwaddr addr,
118 uint64_t value, unsigned size)
119 {
120 PXA2xxState *s = (PXA2xxState *) opaque;
121
122 switch (addr) {
123 case PMCR:
124 /* Clear the write-one-to-clear bits... */
125 s->pm_regs[addr >> 2] &= ~(value & 0x2a);
126 /* ...and set the plain r/w bits */
127 s->pm_regs[addr >> 2] &= ~0x15;
128 s->pm_regs[addr >> 2] |= value & 0x15;
129 break;
130
131 case PSSR: /* Read-clean registers */
132 case RCSR:
133 case PKSR:
134 s->pm_regs[addr >> 2] &= ~value;
135 break;
136
137 default: /* Read-write registers */
138 if (!(addr & 3)) {
139 s->pm_regs[addr >> 2] = value;
140 break;
141 }
142
143 printf("%s: Bad register " REG_FMT "\n", __func__, addr);
144 break;
145 }
146 }
147
148 static const MemoryRegionOps pxa2xx_pm_ops = {
149 .read = pxa2xx_pm_read,
150 .write = pxa2xx_pm_write,
151 .endianness = DEVICE_NATIVE_ENDIAN,
152 };
153
154 static const VMStateDescription vmstate_pxa2xx_pm = {
155 .name = "pxa2xx_pm",
156 .version_id = 0,
157 .minimum_version_id = 0,
158 .fields = (VMStateField[]) {
159 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
160 VMSTATE_END_OF_LIST()
161 }
162 };
163
164 #define CCCR 0x00 /* Core Clock Configuration register */
165 #define CKEN 0x04 /* Clock Enable register */
166 #define OSCC 0x08 /* Oscillator Configuration register */
167 #define CCSR 0x0c /* Core Clock Status register */
168
169 static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr,
170 unsigned size)
171 {
172 PXA2xxState *s = (PXA2xxState *) opaque;
173
174 switch (addr) {
175 case CCCR:
176 case CKEN:
177 case OSCC:
178 return s->cm_regs[addr >> 2];
179
180 case CCSR:
181 return s->cm_regs[CCCR >> 2] | (3 << 28);
182
183 default:
184 printf("%s: Bad register " REG_FMT "\n", __func__, addr);
185 break;
186 }
187 return 0;
188 }
189
190 static void pxa2xx_cm_write(void *opaque, hwaddr addr,
191 uint64_t value, unsigned size)
192 {
193 PXA2xxState *s = (PXA2xxState *) opaque;
194
195 switch (addr) {
196 case CCCR:
197 case CKEN:
198 s->cm_regs[addr >> 2] = value;
199 break;
200
201 case OSCC:
202 s->cm_regs[addr >> 2] &= ~0x6c;
203 s->cm_regs[addr >> 2] |= value & 0x6e;
204 if ((value >> 1) & 1) /* OON */
205 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
206 break;
207
208 default:
209 printf("%s: Bad register " REG_FMT "\n", __func__, addr);
210 break;
211 }
212 }
213
214 static const MemoryRegionOps pxa2xx_cm_ops = {
215 .read = pxa2xx_cm_read,
216 .write = pxa2xx_cm_write,
217 .endianness = DEVICE_NATIVE_ENDIAN,
218 };
219
220 static const VMStateDescription vmstate_pxa2xx_cm = {
221 .name = "pxa2xx_cm",
222 .version_id = 0,
223 .minimum_version_id = 0,
224 .fields = (VMStateField[]) {
225 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
226 VMSTATE_UINT32(clkcfg, PXA2xxState),
227 VMSTATE_UINT32(pmnc, PXA2xxState),
228 VMSTATE_END_OF_LIST()
229 }
230 };
231
232 static uint64_t pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri)
233 {
234 PXA2xxState *s = (PXA2xxState *)ri->opaque;
235 return s->clkcfg;
236 }
237
238 static void pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
239 uint64_t value)
240 {
241 PXA2xxState *s = (PXA2xxState *)ri->opaque;
242 s->clkcfg = value & 0xf;
243 if (value & 2) {
244 printf("%s: CPU frequency change attempt\n", __func__);
245 }
246 }
247
248 static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
249 uint64_t value)
250 {
251 PXA2xxState *s = (PXA2xxState *)ri->opaque;
252 static const char *pwrmode[8] = {
253 "Normal", "Idle", "Deep-idle", "Standby",
254 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
255 };
256
257 if (value & 8) {
258 printf("%s: CPU voltage change attempt\n", __func__);
259 }
260 switch (value & 7) {
261 case 0:
262 /* Do nothing */
263 break;
264
265 case 1:
266 /* Idle */
267 if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */
268 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
269 break;
270 }
271 /* Fall through. */
272
273 case 2:
274 /* Deep-Idle */
275 cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
276 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
277 goto message;
278
279 case 3:
280 s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC;
281 s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I;
282 s->cpu->env.cp15.sctlr_ns = 0;
283 s->cpu->env.cp15.cpacr_el1 = 0;
284 s->cpu->env.cp15.ttbr0_el[1] = 0;
285 s->cpu->env.cp15.dacr_ns = 0;
286 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
287 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
288
289 /*
290 * The scratch-pad register is almost universally used
291 * for storing the return address on suspend. For the
292 * lack of a resuming bootloader, perform a jump
293 * directly to that address.
294 */
295 memset(s->cpu->env.regs, 0, 4 * 15);
296 s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2];
297
298 #if 0
299 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
300 cpu_physical_memory_write(0, &buffer, 4);
301 buffer = s->pm_regs[PSPR >> 2];
302 cpu_physical_memory_write(8, &buffer, 4);
303 #endif
304
305 /* Suspend */
306 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
307
308 goto message;
309
310 default:
311 message:
312 printf("%s: machine entered %s mode\n", __func__,
313 pwrmode[value & 7]);
314 }
315 }
316
317 static uint64_t pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri)
318 {
319 PXA2xxState *s = (PXA2xxState *)ri->opaque;
320 return s->pmnc;
321 }
322
323 static void pxa2xx_cppmnc_write(CPUARMState *env, const ARMCPRegInfo *ri,
324 uint64_t value)
325 {
326 PXA2xxState *s = (PXA2xxState *)ri->opaque;
327 s->pmnc = value;
328 }
329
330 static uint64_t pxa2xx_cpccnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
331 {
332 PXA2xxState *s = (PXA2xxState *)ri->opaque;
333 if (s->pmnc & 1) {
334 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
335 } else {
336 return 0;
337 }
338 }
339
340 static const ARMCPRegInfo pxa_cp_reginfo[] = {
341 /* cp14 crm==1: perf registers */
342 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
343 .access = PL1_RW, .type = ARM_CP_IO,
344 .readfn = pxa2xx_cppmnc_read, .writefn = pxa2xx_cppmnc_write },
345 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
346 .access = PL1_RW, .type = ARM_CP_IO,
347 .readfn = pxa2xx_cpccnt_read, .writefn = arm_cp_write_ignore },
348 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0,
349 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
350 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0,
351 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
352 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0,
353 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
354 /* cp14 crm==2: performance count registers */
355 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0,
356 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
357 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0,
358 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
359 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0,
360 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
361 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0,
362 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
363 /* cp14 crn==6: CLKCFG */
364 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
365 .access = PL1_RW, .type = ARM_CP_IO,
366 .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write },
367 /* cp14 crn==7: PWRMODE */
368 { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
369 .access = PL1_RW, .type = ARM_CP_IO,
370 .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
371 REGINFO_SENTINEL
372 };
373
374 static void pxa2xx_setup_cp14(PXA2xxState *s)
375 {
376 define_arm_cp_regs_with_opaque(s->cpu, pxa_cp_reginfo, s);
377 }
378
379 #define MDCNFG 0x00 /* SDRAM Configuration register */
380 #define MDREFR 0x04 /* SDRAM Refresh Control register */
381 #define MSC0 0x08 /* Static Memory Control register 0 */
382 #define MSC1 0x0c /* Static Memory Control register 1 */
383 #define MSC2 0x10 /* Static Memory Control register 2 */
384 #define MECR 0x14 /* Expansion Memory Bus Config register */
385 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
386 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
387 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
388 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
389 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
390 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
391 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
392 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
393 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
394 #define ARB_CNTL 0x48 /* Arbiter Control register */
395 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
396 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
397 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
398 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
399 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
400 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
401 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
402
403 static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr,
404 unsigned size)
405 {
406 PXA2xxState *s = (PXA2xxState *) opaque;
407
408 switch (addr) {
409 case MDCNFG ... SA1110:
410 if ((addr & 3) == 0)
411 return s->mm_regs[addr >> 2];
412
413 default:
414 printf("%s: Bad register " REG_FMT "\n", __func__, addr);
415 break;
416 }
417 return 0;
418 }
419
420 static void pxa2xx_mm_write(void *opaque, hwaddr addr,
421 uint64_t value, unsigned size)
422 {
423 PXA2xxState *s = (PXA2xxState *) opaque;
424
425 switch (addr) {
426 case MDCNFG ... SA1110:
427 if ((addr & 3) == 0) {
428 s->mm_regs[addr >> 2] = value;
429 break;
430 }
431
432 default:
433 printf("%s: Bad register " REG_FMT "\n", __func__, addr);
434 break;
435 }
436 }
437
438 static const MemoryRegionOps pxa2xx_mm_ops = {
439 .read = pxa2xx_mm_read,
440 .write = pxa2xx_mm_write,
441 .endianness = DEVICE_NATIVE_ENDIAN,
442 };
443
444 static const VMStateDescription vmstate_pxa2xx_mm = {
445 .name = "pxa2xx_mm",
446 .version_id = 0,
447 .minimum_version_id = 0,
448 .fields = (VMStateField[]) {
449 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
450 VMSTATE_END_OF_LIST()
451 }
452 };
453
454 #define TYPE_PXA2XX_SSP "pxa2xx-ssp"
455 #define PXA2XX_SSP(obj) \
456 OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP)
457
458 /* Synchronous Serial Ports */
459 typedef struct {
460 /*< private >*/
461 SysBusDevice parent_obj;
462 /*< public >*/
463
464 MemoryRegion iomem;
465 qemu_irq irq;
466 uint32_t enable;
467 SSIBus *bus;
468
469 uint32_t sscr[2];
470 uint32_t sspsp;
471 uint32_t ssto;
472 uint32_t ssitr;
473 uint32_t sssr;
474 uint8_t sstsa;
475 uint8_t ssrsa;
476 uint8_t ssacd;
477
478 uint32_t rx_fifo[16];
479 uint32_t rx_level;
480 uint32_t rx_start;
481 } PXA2xxSSPState;
482
483 static bool pxa2xx_ssp_vmstate_validate(void *opaque, int version_id)
484 {
485 PXA2xxSSPState *s = opaque;
486
487 return s->rx_start < sizeof(s->rx_fifo);
488 }
489
490 static const VMStateDescription vmstate_pxa2xx_ssp = {
491 .name = "pxa2xx-ssp",
492 .version_id = 1,
493 .minimum_version_id = 1,
494 .fields = (VMStateField[]) {
495 VMSTATE_UINT32(enable, PXA2xxSSPState),
496 VMSTATE_UINT32_ARRAY(sscr, PXA2xxSSPState, 2),
497 VMSTATE_UINT32(sspsp, PXA2xxSSPState),
498 VMSTATE_UINT32(ssto, PXA2xxSSPState),
499 VMSTATE_UINT32(ssitr, PXA2xxSSPState),
500 VMSTATE_UINT32(sssr, PXA2xxSSPState),
501 VMSTATE_UINT8(sstsa, PXA2xxSSPState),
502 VMSTATE_UINT8(ssrsa, PXA2xxSSPState),
503 VMSTATE_UINT8(ssacd, PXA2xxSSPState),
504 VMSTATE_UINT32(rx_level, PXA2xxSSPState),
505 VMSTATE_UINT32(rx_start, PXA2xxSSPState),
506 VMSTATE_VALIDATE("fifo is 16 bytes", pxa2xx_ssp_vmstate_validate),
507 VMSTATE_UINT32_ARRAY(rx_fifo, PXA2xxSSPState, 16),
508 VMSTATE_END_OF_LIST()
509 }
510 };
511
512 #define SSCR0 0x00 /* SSP Control register 0 */
513 #define SSCR1 0x04 /* SSP Control register 1 */
514 #define SSSR 0x08 /* SSP Status register */
515 #define SSITR 0x0c /* SSP Interrupt Test register */
516 #define SSDR 0x10 /* SSP Data register */
517 #define SSTO 0x28 /* SSP Time-Out register */
518 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
519 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
520 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
521 #define SSTSS 0x38 /* SSP Time Slot Status register */
522 #define SSACD 0x3c /* SSP Audio Clock Divider register */
523
524 /* Bitfields for above registers */
525 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
526 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
527 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
528 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
529 #define SSCR0_SSE (1 << 7)
530 #define SSCR0_RIM (1 << 22)
531 #define SSCR0_TIM (1 << 23)
532 #define SSCR0_MOD (1U << 31)
533 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
534 #define SSCR1_RIE (1 << 0)
535 #define SSCR1_TIE (1 << 1)
536 #define SSCR1_LBM (1 << 2)
537 #define SSCR1_MWDS (1 << 5)
538 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
539 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
540 #define SSCR1_EFWR (1 << 14)
541 #define SSCR1_PINTE (1 << 18)
542 #define SSCR1_TINTE (1 << 19)
543 #define SSCR1_RSRE (1 << 20)
544 #define SSCR1_TSRE (1 << 21)
545 #define SSCR1_EBCEI (1 << 29)
546 #define SSITR_INT (7 << 5)
547 #define SSSR_TNF (1 << 2)
548 #define SSSR_RNE (1 << 3)
549 #define SSSR_TFS (1 << 5)
550 #define SSSR_RFS (1 << 6)
551 #define SSSR_ROR (1 << 7)
552 #define SSSR_PINT (1 << 18)
553 #define SSSR_TINT (1 << 19)
554 #define SSSR_EOC (1 << 20)
555 #define SSSR_TUR (1 << 21)
556 #define SSSR_BCE (1 << 23)
557 #define SSSR_RW 0x00bc0080
558
559 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
560 {
561 int level = 0;
562
563 level |= s->ssitr & SSITR_INT;
564 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
565 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
566 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
567 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
568 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
569 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
570 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
571 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
572 qemu_set_irq(s->irq, !!level);
573 }
574
575 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
576 {
577 s->sssr &= ~(0xf << 12); /* Clear RFL */
578 s->sssr &= ~(0xf << 8); /* Clear TFL */
579 s->sssr &= ~SSSR_TFS;
580 s->sssr &= ~SSSR_TNF;
581 if (s->enable) {
582 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
583 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
584 s->sssr |= SSSR_RFS;
585 else
586 s->sssr &= ~SSSR_RFS;
587 if (s->rx_level)
588 s->sssr |= SSSR_RNE;
589 else
590 s->sssr &= ~SSSR_RNE;
591 /* TX FIFO is never filled, so it is always in underrun
592 condition if SSP is enabled */
593 s->sssr |= SSSR_TFS;
594 s->sssr |= SSSR_TNF;
595 }
596
597 pxa2xx_ssp_int_update(s);
598 }
599
600 static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr,
601 unsigned size)
602 {
603 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
604 uint32_t retval;
605
606 switch (addr) {
607 case SSCR0:
608 return s->sscr[0];
609 case SSCR1:
610 return s->sscr[1];
611 case SSPSP:
612 return s->sspsp;
613 case SSTO:
614 return s->ssto;
615 case SSITR:
616 return s->ssitr;
617 case SSSR:
618 return s->sssr | s->ssitr;
619 case SSDR:
620 if (!s->enable)
621 return 0xffffffff;
622 if (s->rx_level < 1) {
623 printf("%s: SSP Rx Underrun\n", __func__);
624 return 0xffffffff;
625 }
626 s->rx_level --;
627 retval = s->rx_fifo[s->rx_start ++];
628 s->rx_start &= 0xf;
629 pxa2xx_ssp_fifo_update(s);
630 return retval;
631 case SSTSA:
632 return s->sstsa;
633 case SSRSA:
634 return s->ssrsa;
635 case SSTSS:
636 return 0;
637 case SSACD:
638 return s->ssacd;
639 default:
640 printf("%s: Bad register " REG_FMT "\n", __func__, addr);
641 break;
642 }
643 return 0;
644 }
645
646 static void pxa2xx_ssp_write(void *opaque, hwaddr addr,
647 uint64_t value64, unsigned size)
648 {
649 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
650 uint32_t value = value64;
651
652 switch (addr) {
653 case SSCR0:
654 s->sscr[0] = value & 0xc7ffffff;
655 s->enable = value & SSCR0_SSE;
656 if (value & SSCR0_MOD)
657 printf("%s: Attempt to use network mode\n", __func__);
658 if (s->enable && SSCR0_DSS(value) < 4)
659 printf("%s: Wrong data size: %i bits\n", __func__,
660 SSCR0_DSS(value));
661 if (!(value & SSCR0_SSE)) {
662 s->sssr = 0;
663 s->ssitr = 0;
664 s->rx_level = 0;
665 }
666 pxa2xx_ssp_fifo_update(s);
667 break;
668
669 case SSCR1:
670 s->sscr[1] = value;
671 if (value & (SSCR1_LBM | SSCR1_EFWR))
672 printf("%s: Attempt to use SSP test mode\n", __func__);
673 pxa2xx_ssp_fifo_update(s);
674 break;
675
676 case SSPSP:
677 s->sspsp = value;
678 break;
679
680 case SSTO:
681 s->ssto = value;
682 break;
683
684 case SSITR:
685 s->ssitr = value & SSITR_INT;
686 pxa2xx_ssp_int_update(s);
687 break;
688
689 case SSSR:
690 s->sssr &= ~(value & SSSR_RW);
691 pxa2xx_ssp_int_update(s);
692 break;
693
694 case SSDR:
695 if (SSCR0_UWIRE(s->sscr[0])) {
696 if (s->sscr[1] & SSCR1_MWDS)
697 value &= 0xffff;
698 else
699 value &= 0xff;
700 } else
701 /* Note how 32bits overflow does no harm here */
702 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
703
704 /* Data goes from here to the Tx FIFO and is shifted out from
705 * there directly to the slave, no need to buffer it.
706 */
707 if (s->enable) {
708 uint32_t readval;
709 readval = ssi_transfer(s->bus, value);
710 if (s->rx_level < 0x10) {
711 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
712 } else {
713 s->sssr |= SSSR_ROR;
714 }
715 }
716 pxa2xx_ssp_fifo_update(s);
717 break;
718
719 case SSTSA:
720 s->sstsa = value;
721 break;
722
723 case SSRSA:
724 s->ssrsa = value;
725 break;
726
727 case SSACD:
728 s->ssacd = value;
729 break;
730
731 default:
732 printf("%s: Bad register " REG_FMT "\n", __func__, addr);
733 break;
734 }
735 }
736
737 static const MemoryRegionOps pxa2xx_ssp_ops = {
738 .read = pxa2xx_ssp_read,
739 .write = pxa2xx_ssp_write,
740 .endianness = DEVICE_NATIVE_ENDIAN,
741 };
742
743 static void pxa2xx_ssp_reset(DeviceState *d)
744 {
745 PXA2xxSSPState *s = PXA2XX_SSP(d);
746
747 s->enable = 0;
748 s->sscr[0] = s->sscr[1] = 0;
749 s->sspsp = 0;
750 s->ssto = 0;
751 s->ssitr = 0;
752 s->sssr = 0;
753 s->sstsa = 0;
754 s->ssrsa = 0;
755 s->ssacd = 0;
756 s->rx_start = s->rx_level = 0;
757 }
758
759 static void pxa2xx_ssp_init(Object *obj)
760 {
761 DeviceState *dev = DEVICE(obj);
762 PXA2xxSSPState *s = PXA2XX_SSP(obj);
763 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
764 sysbus_init_irq(sbd, &s->irq);
765
766 memory_region_init_io(&s->iomem, obj, &pxa2xx_ssp_ops, s,
767 "pxa2xx-ssp", 0x1000);
768 sysbus_init_mmio(sbd, &s->iomem);
769
770 s->bus = ssi_create_bus(dev, "ssi");
771 }
772
773 /* Real-Time Clock */
774 #define RCNR 0x00 /* RTC Counter register */
775 #define RTAR 0x04 /* RTC Alarm register */
776 #define RTSR 0x08 /* RTC Status register */
777 #define RTTR 0x0c /* RTC Timer Trim register */
778 #define RDCR 0x10 /* RTC Day Counter register */
779 #define RYCR 0x14 /* RTC Year Counter register */
780 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
781 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
782 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
783 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
784 #define SWCR 0x28 /* RTC Stopwatch Counter register */
785 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
786 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
787 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
788 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
789
790 #define TYPE_PXA2XX_RTC "pxa2xx_rtc"
791 #define PXA2XX_RTC(obj) \
792 OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC)
793
794 typedef struct {
795 /*< private >*/
796 SysBusDevice parent_obj;
797 /*< public >*/
798
799 MemoryRegion iomem;
800 uint32_t rttr;
801 uint32_t rtsr;
802 uint32_t rtar;
803 uint32_t rdar1;
804 uint32_t rdar2;
805 uint32_t ryar1;
806 uint32_t ryar2;
807 uint32_t swar1;
808 uint32_t swar2;
809 uint32_t piar;
810 uint32_t last_rcnr;
811 uint32_t last_rdcr;
812 uint32_t last_rycr;
813 uint32_t last_swcr;
814 uint32_t last_rtcpicr;
815 int64_t last_hz;
816 int64_t last_sw;
817 int64_t last_pi;
818 QEMUTimer *rtc_hz;
819 QEMUTimer *rtc_rdal1;
820 QEMUTimer *rtc_rdal2;
821 QEMUTimer *rtc_swal1;
822 QEMUTimer *rtc_swal2;
823 QEMUTimer *rtc_pi;
824 qemu_irq rtc_irq;
825 } PXA2xxRTCState;
826
827 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
828 {
829 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
830 }
831
832 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
833 {
834 int64_t rt = qemu_clock_get_ms(rtc_clock);
835 s->last_rcnr += ((rt - s->last_hz) << 15) /
836 (1000 * ((s->rttr & 0xffff) + 1));
837 s->last_rdcr += ((rt - s->last_hz) << 15) /
838 (1000 * ((s->rttr & 0xffff) + 1));
839 s->last_hz = rt;
840 }
841
842 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
843 {
844 int64_t rt = qemu_clock_get_ms(rtc_clock);
845 if (s->rtsr & (1 << 12))
846 s->last_swcr += (rt - s->last_sw) / 10;
847 s->last_sw = rt;
848 }
849
850 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
851 {
852 int64_t rt = qemu_clock_get_ms(rtc_clock);
853 if (s->rtsr & (1 << 15))
854 s->last_swcr += rt - s->last_pi;
855 s->last_pi = rt;
856 }
857
858 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
859 uint32_t rtsr)
860 {
861 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
862 timer_mod(s->rtc_hz, s->last_hz +
863 (((s->rtar - s->last_rcnr) * 1000 *
864 ((s->rttr & 0xffff) + 1)) >> 15));
865 else
866 timer_del(s->rtc_hz);
867
868 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
869 timer_mod(s->rtc_rdal1, s->last_hz +
870 (((s->rdar1 - s->last_rdcr) * 1000 *
871 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
872 else
873 timer_del(s->rtc_rdal1);
874
875 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
876 timer_mod(s->rtc_rdal2, s->last_hz +
877 (((s->rdar2 - s->last_rdcr) * 1000 *
878 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
879 else
880 timer_del(s->rtc_rdal2);
881
882 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
883 timer_mod(s->rtc_swal1, s->last_sw +
884 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
885 else
886 timer_del(s->rtc_swal1);
887
888 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
889 timer_mod(s->rtc_swal2, s->last_sw +
890 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
891 else
892 timer_del(s->rtc_swal2);
893
894 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
895 timer_mod(s->rtc_pi, s->last_pi +
896 (s->piar & 0xffff) - s->last_rtcpicr);
897 else
898 timer_del(s->rtc_pi);
899 }
900
901 static inline void pxa2xx_rtc_hz_tick(void *opaque)
902 {
903 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
904 s->rtsr |= (1 << 0);
905 pxa2xx_rtc_alarm_update(s, s->rtsr);
906 pxa2xx_rtc_int_update(s);
907 }
908
909 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
910 {
911 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
912 s->rtsr |= (1 << 4);
913 pxa2xx_rtc_alarm_update(s, s->rtsr);
914 pxa2xx_rtc_int_update(s);
915 }
916
917 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
918 {
919 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
920 s->rtsr |= (1 << 6);
921 pxa2xx_rtc_alarm_update(s, s->rtsr);
922 pxa2xx_rtc_int_update(s);
923 }
924
925 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
926 {
927 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
928 s->rtsr |= (1 << 8);
929 pxa2xx_rtc_alarm_update(s, s->rtsr);
930 pxa2xx_rtc_int_update(s);
931 }
932
933 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
934 {
935 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
936 s->rtsr |= (1 << 10);
937 pxa2xx_rtc_alarm_update(s, s->rtsr);
938 pxa2xx_rtc_int_update(s);
939 }
940
941 static inline void pxa2xx_rtc_pi_tick(void *opaque)
942 {
943 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
944 s->rtsr |= (1 << 13);
945 pxa2xx_rtc_piupdate(s);
946 s->last_rtcpicr = 0;
947 pxa2xx_rtc_alarm_update(s, s->rtsr);
948 pxa2xx_rtc_int_update(s);
949 }
950
951 static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr,
952 unsigned size)
953 {
954 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
955
956 switch (addr) {
957 case RTTR:
958 return s->rttr;
959 case RTSR:
960 return s->rtsr;
961 case RTAR:
962 return s->rtar;
963 case RDAR1:
964 return s->rdar1;
965 case RDAR2:
966 return s->rdar2;
967 case RYAR1:
968 return s->ryar1;
969 case RYAR2:
970 return s->ryar2;
971 case SWAR1:
972 return s->swar1;
973 case SWAR2:
974 return s->swar2;
975 case PIAR:
976 return s->piar;
977 case RCNR:
978 return s->last_rcnr +
979 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
980 (1000 * ((s->rttr & 0xffff) + 1));
981 case RDCR:
982 return s->last_rdcr +
983 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
984 (1000 * ((s->rttr & 0xffff) + 1));
985 case RYCR:
986 return s->last_rycr;
987 case SWCR:
988 if (s->rtsr & (1 << 12))
989 return s->last_swcr +
990 (qemu_clock_get_ms(rtc_clock) - s->last_sw) / 10;
991 else
992 return s->last_swcr;
993 default:
994 printf("%s: Bad register " REG_FMT "\n", __func__, addr);
995 break;
996 }
997 return 0;
998 }
999
1000 static void pxa2xx_rtc_write(void *opaque, hwaddr addr,
1001 uint64_t value64, unsigned size)
1002 {
1003 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1004 uint32_t value = value64;
1005
1006 switch (addr) {
1007 case RTTR:
1008 if (!(s->rttr & (1U << 31))) {
1009 pxa2xx_rtc_hzupdate(s);
1010 s->rttr = value;
1011 pxa2xx_rtc_alarm_update(s, s->rtsr);
1012 }
1013 break;
1014
1015 case RTSR:
1016 if ((s->rtsr ^ value) & (1 << 15))
1017 pxa2xx_rtc_piupdate(s);
1018
1019 if ((s->rtsr ^ value) & (1 << 12))
1020 pxa2xx_rtc_swupdate(s);
1021
1022 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1023 pxa2xx_rtc_alarm_update(s, value);
1024
1025 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1026 pxa2xx_rtc_int_update(s);
1027 break;
1028
1029 case RTAR:
1030 s->rtar = value;
1031 pxa2xx_rtc_alarm_update(s, s->rtsr);
1032 break;
1033
1034 case RDAR1:
1035 s->rdar1 = value;
1036 pxa2xx_rtc_alarm_update(s, s->rtsr);
1037 break;
1038
1039 case RDAR2:
1040 s->rdar2 = value;
1041 pxa2xx_rtc_alarm_update(s, s->rtsr);
1042 break;
1043
1044 case RYAR1:
1045 s->ryar1 = value;
1046 pxa2xx_rtc_alarm_update(s, s->rtsr);
1047 break;
1048
1049 case RYAR2:
1050 s->ryar2 = value;
1051 pxa2xx_rtc_alarm_update(s, s->rtsr);
1052 break;
1053
1054 case SWAR1:
1055 pxa2xx_rtc_swupdate(s);
1056 s->swar1 = value;
1057 s->last_swcr = 0;
1058 pxa2xx_rtc_alarm_update(s, s->rtsr);
1059 break;
1060
1061 case SWAR2:
1062 s->swar2 = value;
1063 pxa2xx_rtc_alarm_update(s, s->rtsr);
1064 break;
1065
1066 case PIAR:
1067 s->piar = value;
1068 pxa2xx_rtc_alarm_update(s, s->rtsr);
1069 break;
1070
1071 case RCNR:
1072 pxa2xx_rtc_hzupdate(s);
1073 s->last_rcnr = value;
1074 pxa2xx_rtc_alarm_update(s, s->rtsr);
1075 break;
1076
1077 case RDCR:
1078 pxa2xx_rtc_hzupdate(s);
1079 s->last_rdcr = value;
1080 pxa2xx_rtc_alarm_update(s, s->rtsr);
1081 break;
1082
1083 case RYCR:
1084 s->last_rycr = value;
1085 break;
1086
1087 case SWCR:
1088 pxa2xx_rtc_swupdate(s);
1089 s->last_swcr = value;
1090 pxa2xx_rtc_alarm_update(s, s->rtsr);
1091 break;
1092
1093 case RTCPICR:
1094 pxa2xx_rtc_piupdate(s);
1095 s->last_rtcpicr = value & 0xffff;
1096 pxa2xx_rtc_alarm_update(s, s->rtsr);
1097 break;
1098
1099 default:
1100 printf("%s: Bad register " REG_FMT "\n", __func__, addr);
1101 }
1102 }
1103
1104 static const MemoryRegionOps pxa2xx_rtc_ops = {
1105 .read = pxa2xx_rtc_read,
1106 .write = pxa2xx_rtc_write,
1107 .endianness = DEVICE_NATIVE_ENDIAN,
1108 };
1109
1110 static void pxa2xx_rtc_init(Object *obj)
1111 {
1112 PXA2xxRTCState *s = PXA2XX_RTC(obj);
1113 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
1114 struct tm tm;
1115 int wom;
1116
1117 s->rttr = 0x7fff;
1118 s->rtsr = 0;
1119
1120 qemu_get_timedate(&tm, 0);
1121 wom = ((tm.tm_mday - 1) / 7) + 1;
1122
1123 s->last_rcnr = (uint32_t) mktimegm(&tm);
1124 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1125 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1126 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1127 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1128 s->last_swcr = (tm.tm_hour << 19) |
1129 (tm.tm_min << 13) | (tm.tm_sec << 7);
1130 s->last_rtcpicr = 0;
1131 s->last_hz = s->last_sw = s->last_pi = qemu_clock_get_ms(rtc_clock);
1132
1133 s->rtc_hz = timer_new_ms(rtc_clock, pxa2xx_rtc_hz_tick, s);
1134 s->rtc_rdal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s);
1135 s->rtc_rdal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s);
1136 s->rtc_swal1 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s);
1137 s->rtc_swal2 = timer_new_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s);
1138 s->rtc_pi = timer_new_ms(rtc_clock, pxa2xx_rtc_pi_tick, s);
1139
1140 sysbus_init_irq(dev, &s->rtc_irq);
1141
1142 memory_region_init_io(&s->iomem, obj, &pxa2xx_rtc_ops, s,
1143 "pxa2xx-rtc", 0x10000);
1144 sysbus_init_mmio(dev, &s->iomem);
1145 }
1146
1147 static int pxa2xx_rtc_pre_save(void *opaque)
1148 {
1149 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1150
1151 pxa2xx_rtc_hzupdate(s);
1152 pxa2xx_rtc_piupdate(s);
1153 pxa2xx_rtc_swupdate(s);
1154
1155 return 0;
1156 }
1157
1158 static int pxa2xx_rtc_post_load(void *opaque, int version_id)
1159 {
1160 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1161
1162 pxa2xx_rtc_alarm_update(s, s->rtsr);
1163
1164 return 0;
1165 }
1166
1167 static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
1168 .name = "pxa2xx_rtc",
1169 .version_id = 0,
1170 .minimum_version_id = 0,
1171 .pre_save = pxa2xx_rtc_pre_save,
1172 .post_load = pxa2xx_rtc_post_load,
1173 .fields = (VMStateField[]) {
1174 VMSTATE_UINT32(rttr, PXA2xxRTCState),
1175 VMSTATE_UINT32(rtsr, PXA2xxRTCState),
1176 VMSTATE_UINT32(rtar, PXA2xxRTCState),
1177 VMSTATE_UINT32(rdar1, PXA2xxRTCState),
1178 VMSTATE_UINT32(rdar2, PXA2xxRTCState),
1179 VMSTATE_UINT32(ryar1, PXA2xxRTCState),
1180 VMSTATE_UINT32(ryar2, PXA2xxRTCState),
1181 VMSTATE_UINT32(swar1, PXA2xxRTCState),
1182 VMSTATE_UINT32(swar2, PXA2xxRTCState),
1183 VMSTATE_UINT32(piar, PXA2xxRTCState),
1184 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState),
1185 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState),
1186 VMSTATE_UINT32(last_rycr, PXA2xxRTCState),
1187 VMSTATE_UINT32(last_swcr, PXA2xxRTCState),
1188 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState),
1189 VMSTATE_INT64(last_hz, PXA2xxRTCState),
1190 VMSTATE_INT64(last_sw, PXA2xxRTCState),
1191 VMSTATE_INT64(last_pi, PXA2xxRTCState),
1192 VMSTATE_END_OF_LIST(),
1193 },
1194 };
1195
1196 static void pxa2xx_rtc_sysbus_class_init(ObjectClass *klass, void *data)
1197 {
1198 DeviceClass *dc = DEVICE_CLASS(klass);
1199
1200 dc->desc = "PXA2xx RTC Controller";
1201 dc->vmsd = &vmstate_pxa2xx_rtc_regs;
1202 }
1203
1204 static const TypeInfo pxa2xx_rtc_sysbus_info = {
1205 .name = TYPE_PXA2XX_RTC,
1206 .parent = TYPE_SYS_BUS_DEVICE,
1207 .instance_size = sizeof(PXA2xxRTCState),
1208 .instance_init = pxa2xx_rtc_init,
1209 .class_init = pxa2xx_rtc_sysbus_class_init,
1210 };
1211
1212 /* I2C Interface */
1213
1214 #define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave"
1215 #define PXA2XX_I2C_SLAVE(obj) \
1216 OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE)
1217
1218 typedef struct PXA2xxI2CSlaveState {
1219 I2CSlave parent_obj;
1220
1221 PXA2xxI2CState *host;
1222 } PXA2xxI2CSlaveState;
1223
1224 #define TYPE_PXA2XX_I2C "pxa2xx_i2c"
1225 #define PXA2XX_I2C(obj) \
1226 OBJECT_CHECK(PXA2xxI2CState, (obj), TYPE_PXA2XX_I2C)
1227
1228 struct PXA2xxI2CState {
1229 /*< private >*/
1230 SysBusDevice parent_obj;
1231 /*< public >*/
1232
1233 MemoryRegion iomem;
1234 PXA2xxI2CSlaveState *slave;
1235 I2CBus *bus;
1236 qemu_irq irq;
1237 uint32_t offset;
1238 uint32_t region_size;
1239
1240 uint16_t control;
1241 uint16_t status;
1242 uint8_t ibmr;
1243 uint8_t data;
1244 };
1245
1246 #define IBMR 0x80 /* I2C Bus Monitor register */
1247 #define IDBR 0x88 /* I2C Data Buffer register */
1248 #define ICR 0x90 /* I2C Control register */
1249 #define ISR 0x98 /* I2C Status register */
1250 #define ISAR 0xa0 /* I2C Slave Address register */
1251
1252 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1253 {
1254 uint16_t level = 0;
1255 level |= s->status & s->control & (1 << 10); /* BED */
1256 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1257 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1258 level |= s->status & (1 << 9); /* SAD */
1259 qemu_set_irq(s->irq, !!level);
1260 }
1261
1262 /* These are only stubs now. */
1263 static int pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event event)
1264 {
1265 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1266 PXA2xxI2CState *s = slave->host;
1267
1268 switch (event) {
1269 case I2C_START_SEND:
1270 s->status |= (1 << 9); /* set SAD */
1271 s->status &= ~(1 << 0); /* clear RWM */
1272 break;
1273 case I2C_START_RECV:
1274 s->status |= (1 << 9); /* set SAD */
1275 s->status |= 1 << 0; /* set RWM */
1276 break;
1277 case I2C_FINISH:
1278 s->status |= (1 << 4); /* set SSD */
1279 break;
1280 case I2C_NACK:
1281 s->status |= 1 << 1; /* set ACKNAK */
1282 break;
1283 }
1284 pxa2xx_i2c_update(s);
1285
1286 return 0;
1287 }
1288
1289 static int pxa2xx_i2c_rx(I2CSlave *i2c)
1290 {
1291 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1292 PXA2xxI2CState *s = slave->host;
1293
1294 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) {
1295 return 0;
1296 }
1297
1298 if (s->status & (1 << 0)) { /* RWM */
1299 s->status |= 1 << 6; /* set ITE */
1300 }
1301 pxa2xx_i2c_update(s);
1302
1303 return s->data;
1304 }
1305
1306 static int pxa2xx_i2c_tx(I2CSlave *i2c, uint8_t data)
1307 {
1308 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
1309 PXA2xxI2CState *s = slave->host;
1310
1311 if ((s->control & (1 << 14)) || !(s->control & (1 << 6))) {
1312 return 1;
1313 }
1314
1315 if (!(s->status & (1 << 0))) { /* RWM */
1316 s->status |= 1 << 7; /* set IRF */
1317 s->data = data;
1318 }
1319 pxa2xx_i2c_update(s);
1320
1321 return 1;
1322 }
1323
1324 static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr,
1325 unsigned size)
1326 {
1327 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1328 I2CSlave *slave;
1329
1330 addr -= s->offset;
1331 switch (addr) {
1332 case ICR:
1333 return s->control;
1334 case ISR:
1335 return s->status | (i2c_bus_busy(s->bus) << 2);
1336 case ISAR:
1337 slave = I2C_SLAVE(s->slave);
1338 return slave->address;
1339 case IDBR:
1340 return s->data;
1341 case IBMR:
1342 if (s->status & (1 << 2))
1343 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1344 else
1345 s->ibmr = 0;
1346 return s->ibmr;
1347 default:
1348 printf("%s: Bad register " REG_FMT "\n", __func__, addr);
1349 break;
1350 }
1351 return 0;
1352 }
1353
1354 static void pxa2xx_i2c_write(void *opaque, hwaddr addr,
1355 uint64_t value64, unsigned size)
1356 {
1357 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1358 uint32_t value = value64;
1359 int ack;
1360
1361 addr -= s->offset;
1362 switch (addr) {
1363 case ICR:
1364 s->control = value & 0xfff7;
1365 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1366 /* TODO: slave mode */
1367 if (value & (1 << 0)) { /* START condition */
1368 if (s->data & 1)
1369 s->status |= 1 << 0; /* set RWM */
1370 else
1371 s->status &= ~(1 << 0); /* clear RWM */
1372 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1373 } else {
1374 if (s->status & (1 << 0)) { /* RWM */
1375 s->data = i2c_recv(s->bus);
1376 if (value & (1 << 2)) /* ACKNAK */
1377 i2c_nack(s->bus);
1378 ack = 1;
1379 } else
1380 ack = !i2c_send(s->bus, s->data);
1381 }
1382
1383 if (value & (1 << 1)) /* STOP condition */
1384 i2c_end_transfer(s->bus);
1385
1386 if (ack) {
1387 if (value & (1 << 0)) /* START condition */
1388 s->status |= 1 << 6; /* set ITE */
1389 else
1390 if (s->status & (1 << 0)) /* RWM */
1391 s->status |= 1 << 7; /* set IRF */
1392 else
1393 s->status |= 1 << 6; /* set ITE */
1394 s->status &= ~(1 << 1); /* clear ACKNAK */
1395 } else {
1396 s->status |= 1 << 6; /* set ITE */
1397 s->status |= 1 << 10; /* set BED */
1398 s->status |= 1 << 1; /* set ACKNAK */
1399 }
1400 }
1401 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1402 if (value & (1 << 4)) /* MA */
1403 i2c_end_transfer(s->bus);
1404 pxa2xx_i2c_update(s);
1405 break;
1406
1407 case ISR:
1408 s->status &= ~(value & 0x07f0);
1409 pxa2xx_i2c_update(s);
1410 break;
1411
1412 case ISAR:
1413 i2c_set_slave_address(I2C_SLAVE(s->slave), value & 0x7f);
1414 break;
1415
1416 case IDBR:
1417 s->data = value & 0xff;
1418 break;
1419
1420 default:
1421 printf("%s: Bad register " REG_FMT "\n", __func__, addr);
1422 }
1423 }
1424
1425 static const MemoryRegionOps pxa2xx_i2c_ops = {
1426 .read = pxa2xx_i2c_read,
1427 .write = pxa2xx_i2c_write,
1428 .endianness = DEVICE_NATIVE_ENDIAN,
1429 };
1430
1431 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1432 .name = "pxa2xx_i2c_slave",
1433 .version_id = 1,
1434 .minimum_version_id = 1,
1435 .fields = (VMStateField[]) {
1436 VMSTATE_I2C_SLAVE(parent_obj, PXA2xxI2CSlaveState),
1437 VMSTATE_END_OF_LIST()
1438 }
1439 };
1440
1441 static const VMStateDescription vmstate_pxa2xx_i2c = {
1442 .name = "pxa2xx_i2c",
1443 .version_id = 1,
1444 .minimum_version_id = 1,
1445 .fields = (VMStateField[]) {
1446 VMSTATE_UINT16(control, PXA2xxI2CState),
1447 VMSTATE_UINT16(status, PXA2xxI2CState),
1448 VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1449 VMSTATE_UINT8(data, PXA2xxI2CState),
1450 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1451 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState),
1452 VMSTATE_END_OF_LIST()
1453 }
1454 };
1455
1456 static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data)
1457 {
1458 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
1459
1460 k->event = pxa2xx_i2c_event;
1461 k->recv = pxa2xx_i2c_rx;
1462 k->send = pxa2xx_i2c_tx;
1463 }
1464
1465 static const TypeInfo pxa2xx_i2c_slave_info = {
1466 .name = TYPE_PXA2XX_I2C_SLAVE,
1467 .parent = TYPE_I2C_SLAVE,
1468 .instance_size = sizeof(PXA2xxI2CSlaveState),
1469 .class_init = pxa2xx_i2c_slave_class_init,
1470 };
1471
1472 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
1473 qemu_irq irq, uint32_t region_size)
1474 {
1475 DeviceState *dev;
1476 SysBusDevice *i2c_dev;
1477 PXA2xxI2CState *s;
1478 I2CBus *i2cbus;
1479
1480 dev = qdev_create(NULL, TYPE_PXA2XX_I2C);
1481 qdev_prop_set_uint32(dev, "size", region_size + 1);
1482 qdev_prop_set_uint32(dev, "offset", base & region_size);
1483 qdev_init_nofail(dev);
1484
1485 i2c_dev = SYS_BUS_DEVICE(dev);
1486 sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
1487 sysbus_connect_irq(i2c_dev, 0, irq);
1488
1489 s = PXA2XX_I2C(i2c_dev);
1490 /* FIXME: Should the slave device really be on a separate bus? */
1491 i2cbus = i2c_init_bus(dev, "dummy");
1492 dev = i2c_create_slave(i2cbus, TYPE_PXA2XX_I2C_SLAVE, 0);
1493 s->slave = PXA2XX_I2C_SLAVE(dev);
1494 s->slave->host = s;
1495
1496 return s;
1497 }
1498
1499 static void pxa2xx_i2c_initfn(Object *obj)
1500 {
1501 DeviceState *dev = DEVICE(obj);
1502 PXA2xxI2CState *s = PXA2XX_I2C(obj);
1503 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1504
1505 s->bus = i2c_init_bus(dev, NULL);
1506
1507 memory_region_init_io(&s->iomem, obj, &pxa2xx_i2c_ops, s,
1508 "pxa2xx-i2c", s->region_size);
1509 sysbus_init_mmio(sbd, &s->iomem);
1510 sysbus_init_irq(sbd, &s->irq);
1511 }
1512
1513 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1514 {
1515 return s->bus;
1516 }
1517
1518 static Property pxa2xx_i2c_properties[] = {
1519 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000),
1520 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0),
1521 DEFINE_PROP_END_OF_LIST(),
1522 };
1523
1524 static void pxa2xx_i2c_class_init(ObjectClass *klass, void *data)
1525 {
1526 DeviceClass *dc = DEVICE_CLASS(klass);
1527
1528 dc->desc = "PXA2xx I2C Bus Controller";
1529 dc->vmsd = &vmstate_pxa2xx_i2c;
1530 dc->props = pxa2xx_i2c_properties;
1531 }
1532
1533 static const TypeInfo pxa2xx_i2c_info = {
1534 .name = TYPE_PXA2XX_I2C,
1535 .parent = TYPE_SYS_BUS_DEVICE,
1536 .instance_size = sizeof(PXA2xxI2CState),
1537 .instance_init = pxa2xx_i2c_initfn,
1538 .class_init = pxa2xx_i2c_class_init,
1539 };
1540
1541 /* PXA Inter-IC Sound Controller */
1542 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1543 {
1544 i2s->rx_len = 0;
1545 i2s->tx_len = 0;
1546 i2s->fifo_len = 0;
1547 i2s->clk = 0x1a;
1548 i2s->control[0] = 0x00;
1549 i2s->control[1] = 0x00;
1550 i2s->status = 0x00;
1551 i2s->mask = 0x00;
1552 }
1553
1554 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1555 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1556 #define SACR_DREC(val) (val & (1 << 3))
1557 #define SACR_DPRL(val) (val & (1 << 4))
1558
1559 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1560 {
1561 int rfs, tfs;
1562 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1563 !SACR_DREC(i2s->control[1]);
1564 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1565 i2s->enable && !SACR_DPRL(i2s->control[1]);
1566
1567 qemu_set_irq(i2s->rx_dma, rfs);
1568 qemu_set_irq(i2s->tx_dma, tfs);
1569
1570 i2s->status &= 0xe0;
1571 if (i2s->fifo_len < 16 || !i2s->enable)
1572 i2s->status |= 1 << 0; /* TNF */
1573 if (i2s->rx_len)
1574 i2s->status |= 1 << 1; /* RNE */
1575 if (i2s->enable)
1576 i2s->status |= 1 << 2; /* BSY */
1577 if (tfs)
1578 i2s->status |= 1 << 3; /* TFS */
1579 if (rfs)
1580 i2s->status |= 1 << 4; /* RFS */
1581 if (!(i2s->tx_len && i2s->enable))
1582 i2s->status |= i2s->fifo_len << 8; /* TFL */
1583 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1584
1585 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1586 }
1587
1588 #define SACR0 0x00 /* Serial Audio Global Control register */
1589 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1590 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1591 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1592 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1593 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1594 #define SADR 0x80 /* Serial Audio Data register */
1595
1596 static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr,
1597 unsigned size)
1598 {
1599 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1600
1601 switch (addr) {
1602 case SACR0:
1603 return s->control[0];
1604 case SACR1:
1605 return s->control[1];
1606 case SASR0:
1607 return s->status;
1608 case SAIMR:
1609 return s->mask;
1610 case SAICR:
1611 return 0;
1612 case SADIV:
1613 return s->clk;
1614 case SADR:
1615 if (s->rx_len > 0) {
1616 s->rx_len --;
1617 pxa2xx_i2s_update(s);
1618 return s->codec_in(s->opaque);
1619 }
1620 return 0;
1621 default:
1622 printf("%s: Bad register " REG_FMT "\n", __func__, addr);
1623 break;
1624 }
1625 return 0;
1626 }
1627
1628 static void pxa2xx_i2s_write(void *opaque, hwaddr addr,
1629 uint64_t value, unsigned size)
1630 {
1631 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1632 uint32_t *sample;
1633
1634 switch (addr) {
1635 case SACR0:
1636 if (value & (1 << 3)) /* RST */
1637 pxa2xx_i2s_reset(s);
1638 s->control[0] = value & 0xff3d;
1639 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1640 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1641 s->codec_out(s->opaque, *sample);
1642 s->status &= ~(1 << 7); /* I2SOFF */
1643 }
1644 if (value & (1 << 4)) /* EFWR */
1645 printf("%s: Attempt to use special function\n", __func__);
1646 s->enable = (value & 9) == 1; /* ENB && !RST*/
1647 pxa2xx_i2s_update(s);
1648 break;
1649 case SACR1:
1650 s->control[1] = value & 0x0039;
1651 if (value & (1 << 5)) /* ENLBF */
1652 printf("%s: Attempt to use loopback function\n", __func__);
1653 if (value & (1 << 4)) /* DPRL */
1654 s->fifo_len = 0;
1655 pxa2xx_i2s_update(s);
1656 break;
1657 case SAIMR:
1658 s->mask = value & 0x0078;
1659 pxa2xx_i2s_update(s);
1660 break;
1661 case SAICR:
1662 s->status &= ~(value & (3 << 5));
1663 pxa2xx_i2s_update(s);
1664 break;
1665 case SADIV:
1666 s->clk = value & 0x007f;
1667 break;
1668 case SADR:
1669 if (s->tx_len && s->enable) {
1670 s->tx_len --;
1671 pxa2xx_i2s_update(s);
1672 s->codec_out(s->opaque, value);
1673 } else if (s->fifo_len < 16) {
1674 s->fifo[s->fifo_len ++] = value;
1675 pxa2xx_i2s_update(s);
1676 }
1677 break;
1678 default:
1679 printf("%s: Bad register " REG_FMT "\n", __func__, addr);
1680 }
1681 }
1682
1683 static const MemoryRegionOps pxa2xx_i2s_ops = {
1684 .read = pxa2xx_i2s_read,
1685 .write = pxa2xx_i2s_write,
1686 .endianness = DEVICE_NATIVE_ENDIAN,
1687 };
1688
1689 static const VMStateDescription vmstate_pxa2xx_i2s = {
1690 .name = "pxa2xx_i2s",
1691 .version_id = 0,
1692 .minimum_version_id = 0,
1693 .fields = (VMStateField[]) {
1694 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
1695 VMSTATE_UINT32(status, PXA2xxI2SState),
1696 VMSTATE_UINT32(mask, PXA2xxI2SState),
1697 VMSTATE_UINT32(clk, PXA2xxI2SState),
1698 VMSTATE_INT32(enable, PXA2xxI2SState),
1699 VMSTATE_INT32(rx_len, PXA2xxI2SState),
1700 VMSTATE_INT32(tx_len, PXA2xxI2SState),
1701 VMSTATE_INT32(fifo_len, PXA2xxI2SState),
1702 VMSTATE_END_OF_LIST()
1703 }
1704 };
1705
1706 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1707 {
1708 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1709 uint32_t *sample;
1710
1711 /* Signal FIFO errors */
1712 if (s->enable && s->tx_len)
1713 s->status |= 1 << 5; /* TUR */
1714 if (s->enable && s->rx_len)
1715 s->status |= 1 << 6; /* ROR */
1716
1717 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1718 * handle the cases where it makes a difference. */
1719 s->tx_len = tx - s->fifo_len;
1720 s->rx_len = rx;
1721 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1722 if (s->enable)
1723 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1724 s->codec_out(s->opaque, *sample);
1725 pxa2xx_i2s_update(s);
1726 }
1727
1728 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
1729 hwaddr base,
1730 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
1731 {
1732 PXA2xxI2SState *s = g_new0(PXA2xxI2SState, 1);
1733
1734 s->irq = irq;
1735 s->rx_dma = rx_dma;
1736 s->tx_dma = tx_dma;
1737 s->data_req = pxa2xx_i2s_data_req;
1738
1739 pxa2xx_i2s_reset(s);
1740
1741 memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s,
1742 "pxa2xx-i2s", 0x100000);
1743 memory_region_add_subregion(sysmem, base, &s->iomem);
1744
1745 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s);
1746
1747 return s;
1748 }
1749
1750 /* PXA Fast Infra-red Communications Port */
1751 #define TYPE_PXA2XX_FIR "pxa2xx-fir"
1752 #define PXA2XX_FIR(obj) OBJECT_CHECK(PXA2xxFIrState, (obj), TYPE_PXA2XX_FIR)
1753
1754 struct PXA2xxFIrState {
1755 /*< private >*/
1756 SysBusDevice parent_obj;
1757 /*< public >*/
1758
1759 MemoryRegion iomem;
1760 qemu_irq irq;
1761 qemu_irq rx_dma;
1762 qemu_irq tx_dma;
1763 uint32_t enable;
1764 CharBackend chr;
1765
1766 uint8_t control[3];
1767 uint8_t status[2];
1768
1769 uint32_t rx_len;
1770 uint32_t rx_start;
1771 uint8_t rx_fifo[64];
1772 };
1773
1774 static void pxa2xx_fir_reset(DeviceState *d)
1775 {
1776 PXA2xxFIrState *s = PXA2XX_FIR(d);
1777
1778 s->control[0] = 0x00;
1779 s->control[1] = 0x00;
1780 s->control[2] = 0x00;
1781 s->status[0] = 0x00;
1782 s->status[1] = 0x00;
1783 s->enable = 0;
1784 }
1785
1786 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1787 {
1788 static const int tresh[4] = { 8, 16, 32, 0 };
1789 int intr = 0;
1790 if ((s->control[0] & (1 << 4)) && /* RXE */
1791 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1792 s->status[0] |= 1 << 4; /* RFS */
1793 else
1794 s->status[0] &= ~(1 << 4); /* RFS */
1795 if (s->control[0] & (1 << 3)) /* TXE */
1796 s->status[0] |= 1 << 3; /* TFS */
1797 else
1798 s->status[0] &= ~(1 << 3); /* TFS */
1799 if (s->rx_len)
1800 s->status[1] |= 1 << 2; /* RNE */
1801 else
1802 s->status[1] &= ~(1 << 2); /* RNE */
1803 if (s->control[0] & (1 << 4)) /* RXE */
1804 s->status[1] |= 1 << 0; /* RSY */
1805 else
1806 s->status[1] &= ~(1 << 0); /* RSY */
1807
1808 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1809 (s->status[0] & (1 << 4)); /* RFS */
1810 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1811 (s->status[0] & (1 << 3)); /* TFS */
1812 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1813 (s->status[0] & (1 << 6)); /* EOC */
1814 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1815 (s->status[0] & (1 << 1)); /* TUR */
1816 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1817
1818 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
1819 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
1820
1821 qemu_set_irq(s->irq, intr && s->enable);
1822 }
1823
1824 #define ICCR0 0x00 /* FICP Control register 0 */
1825 #define ICCR1 0x04 /* FICP Control register 1 */
1826 #define ICCR2 0x08 /* FICP Control register 2 */
1827 #define ICDR 0x0c /* FICP Data register */
1828 #define ICSR0 0x14 /* FICP Status register 0 */
1829 #define ICSR1 0x18 /* FICP Status register 1 */
1830 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1831
1832 static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr,
1833 unsigned size)
1834 {
1835 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1836 uint8_t ret;
1837
1838 switch (addr) {
1839 case ICCR0:
1840 return s->control[0];
1841 case ICCR1:
1842 return s->control[1];
1843 case ICCR2:
1844 return s->control[2];
1845 case ICDR:
1846 s->status[0] &= ~0x01;
1847 s->status[1] &= ~0x72;
1848 if (s->rx_len) {
1849 s->rx_len --;
1850 ret = s->rx_fifo[s->rx_start ++];
1851 s->rx_start &= 63;
1852 pxa2xx_fir_update(s);
1853 return ret;
1854 }
1855 printf("%s: Rx FIFO underrun.\n", __func__);
1856 break;
1857 case ICSR0:
1858 return s->status[0];
1859 case ICSR1:
1860 return s->status[1] | (1 << 3); /* TNF */
1861 case ICFOR:
1862 return s->rx_len;
1863 default:
1864 printf("%s: Bad register " REG_FMT "\n", __func__, addr);
1865 break;
1866 }
1867 return 0;
1868 }
1869
1870 static void pxa2xx_fir_write(void *opaque, hwaddr addr,
1871 uint64_t value64, unsigned size)
1872 {
1873 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1874 uint32_t value = value64;
1875 uint8_t ch;
1876
1877 switch (addr) {
1878 case ICCR0:
1879 s->control[0] = value;
1880 if (!(value & (1 << 4))) /* RXE */
1881 s->rx_len = s->rx_start = 0;
1882 if (!(value & (1 << 3))) { /* TXE */
1883 /* Nop */
1884 }
1885 s->enable = value & 1; /* ITR */
1886 if (!s->enable)
1887 s->status[0] = 0;
1888 pxa2xx_fir_update(s);
1889 break;
1890 case ICCR1:
1891 s->control[1] = value;
1892 break;
1893 case ICCR2:
1894 s->control[2] = value & 0x3f;
1895 pxa2xx_fir_update(s);
1896 break;
1897 case ICDR:
1898 if (s->control[2] & (1 << 2)) { /* TXP */
1899 ch = value;
1900 } else {
1901 ch = ~value;
1902 }
1903 if (s->enable && (s->control[0] & (1 << 3))) { /* TXE */
1904 /* XXX this blocks entire thread. Rewrite to use
1905 * qemu_chr_fe_write and background I/O callbacks */
1906 qemu_chr_fe_write_all(&s->chr, &ch, 1);
1907 }
1908 break;
1909 case ICSR0:
1910 s->status[0] &= ~(value & 0x66);
1911 pxa2xx_fir_update(s);
1912 break;
1913 case ICFOR:
1914 break;
1915 default:
1916 printf("%s: Bad register " REG_FMT "\n", __func__, addr);
1917 }
1918 }
1919
1920 static const MemoryRegionOps pxa2xx_fir_ops = {
1921 .read = pxa2xx_fir_read,
1922 .write = pxa2xx_fir_write,
1923 .endianness = DEVICE_NATIVE_ENDIAN,
1924 };
1925
1926 static int pxa2xx_fir_is_empty(void *opaque)
1927 {
1928 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1929 return (s->rx_len < 64);
1930 }
1931
1932 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1933 {
1934 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1935 if (!(s->control[0] & (1 << 4))) /* RXE */
1936 return;
1937
1938 while (size --) {
1939 s->status[1] |= 1 << 4; /* EOF */
1940 if (s->rx_len >= 64) {
1941 s->status[1] |= 1 << 6; /* ROR */
1942 break;
1943 }
1944
1945 if (s->control[2] & (1 << 3)) /* RXP */
1946 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1947 else
1948 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1949 }
1950
1951 pxa2xx_fir_update(s);
1952 }
1953
1954 static void pxa2xx_fir_event(void *opaque, int event)
1955 {
1956 }
1957
1958 static void pxa2xx_fir_instance_init(Object *obj)
1959 {
1960 PXA2xxFIrState *s = PXA2XX_FIR(obj);
1961 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1962
1963 memory_region_init_io(&s->iomem, obj, &pxa2xx_fir_ops, s,
1964 "pxa2xx-fir", 0x1000);
1965 sysbus_init_mmio(sbd, &s->iomem);
1966 sysbus_init_irq(sbd, &s->irq);
1967 sysbus_init_irq(sbd, &s->rx_dma);
1968 sysbus_init_irq(sbd, &s->tx_dma);
1969 }
1970
1971 static void pxa2xx_fir_realize(DeviceState *dev, Error **errp)
1972 {
1973 PXA2xxFIrState *s = PXA2XX_FIR(dev);
1974
1975 qemu_chr_fe_set_handlers(&s->chr, pxa2xx_fir_is_empty,
1976 pxa2xx_fir_rx, pxa2xx_fir_event, NULL, s, NULL,
1977 true);
1978 }
1979
1980 static bool pxa2xx_fir_vmstate_validate(void *opaque, int version_id)
1981 {
1982 PXA2xxFIrState *s = opaque;
1983
1984 return s->rx_start < ARRAY_SIZE(s->rx_fifo);
1985 }
1986
1987 static const VMStateDescription pxa2xx_fir_vmsd = {
1988 .name = "pxa2xx-fir",
1989 .version_id = 1,
1990 .minimum_version_id = 1,
1991 .fields = (VMStateField[]) {
1992 VMSTATE_UINT32(enable, PXA2xxFIrState),
1993 VMSTATE_UINT8_ARRAY(control, PXA2xxFIrState, 3),
1994 VMSTATE_UINT8_ARRAY(status, PXA2xxFIrState, 2),
1995 VMSTATE_UINT32(rx_len, PXA2xxFIrState),
1996 VMSTATE_UINT32(rx_start, PXA2xxFIrState),
1997 VMSTATE_VALIDATE("fifo is 64 bytes", pxa2xx_fir_vmstate_validate),
1998 VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxFIrState, 64),
1999 VMSTATE_END_OF_LIST()
2000 }
2001 };
2002
2003 static Property pxa2xx_fir_properties[] = {
2004 DEFINE_PROP_CHR("chardev", PXA2xxFIrState, chr),
2005 DEFINE_PROP_END_OF_LIST(),
2006 };
2007
2008 static void pxa2xx_fir_class_init(ObjectClass *klass, void *data)
2009 {
2010 DeviceClass *dc = DEVICE_CLASS(klass);
2011
2012 dc->realize = pxa2xx_fir_realize;
2013 dc->vmsd = &pxa2xx_fir_vmsd;
2014 dc->props = pxa2xx_fir_properties;
2015 dc->reset = pxa2xx_fir_reset;
2016 }
2017
2018 static const TypeInfo pxa2xx_fir_info = {
2019 .name = TYPE_PXA2XX_FIR,
2020 .parent = TYPE_SYS_BUS_DEVICE,
2021 .instance_size = sizeof(PXA2xxFIrState),
2022 .class_init = pxa2xx_fir_class_init,
2023 .instance_init = pxa2xx_fir_instance_init,
2024 };
2025
2026 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
2027 hwaddr base,
2028 qemu_irq irq, qemu_irq rx_dma,
2029 qemu_irq tx_dma,
2030 Chardev *chr)
2031 {
2032 DeviceState *dev;
2033 SysBusDevice *sbd;
2034
2035 dev = qdev_create(NULL, TYPE_PXA2XX_FIR);
2036 qdev_prop_set_chr(dev, "chardev", chr);
2037 qdev_init_nofail(dev);
2038 sbd = SYS_BUS_DEVICE(dev);
2039 sysbus_mmio_map(sbd, 0, base);
2040 sysbus_connect_irq(sbd, 0, irq);
2041 sysbus_connect_irq(sbd, 1, rx_dma);
2042 sysbus_connect_irq(sbd, 2, tx_dma);
2043 return PXA2XX_FIR(dev);
2044 }
2045
2046 static void pxa2xx_reset(void *opaque, int line, int level)
2047 {
2048 PXA2xxState *s = (PXA2xxState *) opaque;
2049
2050 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2051 cpu_reset(CPU(s->cpu));
2052 /* TODO: reset peripherals */
2053 }
2054 }
2055
2056 /* Initialise a PXA270 integrated chip (ARM based core). */
2057 PXA2xxState *pxa270_init(MemoryRegion *address_space,
2058 unsigned int sdram_size, const char *cpu_type)
2059 {
2060 PXA2xxState *s;
2061 int i;
2062 DriveInfo *dinfo;
2063 s = g_new0(PXA2xxState, 1);
2064
2065 if (strncmp(cpu_type, "pxa27", 5)) {
2066 error_report("Machine requires a PXA27x processor");
2067 exit(1);
2068 }
2069
2070 s->cpu = ARM_CPU(cpu_create(cpu_type));
2071 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
2072
2073 /* SDRAM & Internal Memory Storage */
2074 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size,
2075 &error_fatal);
2076 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2077 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000,
2078 &error_fatal);
2079 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2080 &s->internal);
2081
2082 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2083
2084 s->dma = pxa27x_dma_init(0x40000000,
2085 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2086
2087 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2088 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2089 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2090 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2091 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2092 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
2093 NULL);
2094
2095 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 121);
2096
2097 dinfo = drive_get(IF_SD, 0, 0);
2098 if (!dinfo) {
2099 error_report("missing SecureDigital device");
2100 exit(1);
2101 }
2102 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000,
2103 blk_by_legacy_dinfo(dinfo),
2104 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2105 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2106 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2107
2108 for (i = 0; pxa270_serial[i].io_base; i++) {
2109 if (serial_hds[i]) {
2110 serial_mm_init(address_space, pxa270_serial[i].io_base, 2,
2111 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2112 14857000 / 16, serial_hds[i],
2113 DEVICE_NATIVE_ENDIAN);
2114 } else {
2115 break;
2116 }
2117 }
2118 if (serial_hds[i])
2119 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2120 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2121 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2122 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2123 serial_hds[i]);
2124
2125 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2126 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2127
2128 s->cm_base = 0x41300000;
2129 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2130 s->clkcfg = 0x00000009; /* Turbo mode active */
2131 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2132 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2133 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2134
2135 pxa2xx_setup_cp14(s);
2136
2137 s->mm_base = 0x48000000;
2138 s->mm_regs[MDMRS >> 2] = 0x00020002;
2139 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2140 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2141 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2142 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2143 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2144
2145 s->pm_base = 0x40f00000;
2146 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2147 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2148 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2149
2150 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2151 s->ssp = g_new0(SSIBus *, i);
2152 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2153 DeviceState *dev;
2154 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa27x_ssp[i].io_base,
2155 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
2156 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2157 }
2158
2159 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2160 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2161
2162 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2163 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2164
2165 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2166 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2167
2168 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2169 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2170 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2171 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2172
2173 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2174 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2175 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2176 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2177
2178 s->kp = pxa27x_keypad_init(address_space, 0x41500000,
2179 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
2180
2181 /* GPIO1 resets the processor */
2182 /* The handler can be overridden by board-specific code */
2183 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2184 return s;
2185 }
2186
2187 /* Initialise a PXA255 integrated chip (ARM based core). */
2188 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
2189 {
2190 PXA2xxState *s;
2191 int i;
2192 DriveInfo *dinfo;
2193
2194 s = g_new0(PXA2xxState, 1);
2195
2196 s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME("pxa255")));
2197 s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);
2198
2199 /* SDRAM & Internal Memory Storage */
2200 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size,
2201 &error_fatal);
2202 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2203 memory_region_init_ram(&s->internal, NULL, "pxa255.internal",
2204 PXA2XX_INTERNAL_SIZE, &error_fatal);
2205 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2206 &s->internal);
2207
2208 s->pic = pxa2xx_pic_init(0x40d00000, s->cpu);
2209
2210 s->dma = pxa255_dma_init(0x40000000,
2211 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2212
2213 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2214 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2215 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2216 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2217 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2218 NULL);
2219
2220 s->gpio = pxa2xx_gpio_init(0x40e00000, s->cpu, s->pic, 85);
2221
2222 dinfo = drive_get(IF_SD, 0, 0);
2223 if (!dinfo) {
2224 error_report("missing SecureDigital device");
2225 exit(1);
2226 }
2227 s->mmc = pxa2xx_mmci_init(address_space, 0x41100000,
2228 blk_by_legacy_dinfo(dinfo),
2229 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2230 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2231 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2232
2233 for (i = 0; pxa255_serial[i].io_base; i++) {
2234 if (serial_hds[i]) {
2235 serial_mm_init(address_space, pxa255_serial[i].io_base, 2,
2236 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2237 14745600 / 16, serial_hds[i],
2238 DEVICE_NATIVE_ENDIAN);
2239 } else {
2240 break;
2241 }
2242 }
2243 if (serial_hds[i])
2244 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2245 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2246 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2247 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2248 serial_hds[i]);
2249
2250 s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000,
2251 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2252
2253 s->cm_base = 0x41300000;
2254 s->cm_regs[CCCR >> 2] = 0x00000121; /* from datasheet */
2255 s->cm_regs[CKEN >> 2] = 0x00017def; /* from datasheet */
2256
2257 s->clkcfg = 0x00000009; /* Turbo mode active */
2258 memory_region_init_io(&s->cm_iomem, NULL, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2259 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2260 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2261
2262 pxa2xx_setup_cp14(s);
2263
2264 s->mm_base = 0x48000000;
2265 s->mm_regs[MDMRS >> 2] = 0x00020002;
2266 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2267 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2268 memory_region_init_io(&s->mm_iomem, NULL, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2269 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2270 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2271
2272 s->pm_base = 0x40f00000;
2273 memory_region_init_io(&s->pm_iomem, NULL, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2274 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2275 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2276
2277 for (i = 0; pxa255_ssp[i].io_base; i ++);
2278 s->ssp = g_new0(SSIBus *, i);
2279 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2280 DeviceState *dev;
2281 dev = sysbus_create_simple(TYPE_PXA2XX_SSP, pxa255_ssp[i].io_base,
2282 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
2283 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2284 }
2285
2286 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2287 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2288
2289 s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
2290 s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
2291
2292 sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
2293 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2294
2295 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2296 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2297 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2298 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2299
2300 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2301 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2302 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2303 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2304
2305 /* GPIO1 resets the processor */
2306 /* The handler can be overridden by board-specific code */
2307 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2308 return s;
2309 }
2310
2311 static void pxa2xx_ssp_class_init(ObjectClass *klass, void *data)
2312 {
2313 DeviceClass *dc = DEVICE_CLASS(klass);
2314
2315 dc->reset = pxa2xx_ssp_reset;
2316 dc->vmsd = &vmstate_pxa2xx_ssp;
2317 }
2318
2319 static const TypeInfo pxa2xx_ssp_info = {
2320 .name = TYPE_PXA2XX_SSP,
2321 .parent = TYPE_SYS_BUS_DEVICE,
2322 .instance_size = sizeof(PXA2xxSSPState),
2323 .instance_init = pxa2xx_ssp_init,
2324 .class_init = pxa2xx_ssp_class_init,
2325 };
2326
2327 static void pxa2xx_register_types(void)
2328 {
2329 type_register_static(&pxa2xx_i2c_slave_info);
2330 type_register_static(&pxa2xx_ssp_info);
2331 type_register_static(&pxa2xx_i2c_info);
2332 type_register_static(&pxa2xx_rtc_sysbus_info);
2333 type_register_static(&pxa2xx_fir_info);
2334 }
2335
2336 type_init(pxa2xx_register_types)
QEmu