Fix typos in comments (chek -> check)
[qemu.git] / target-i386 / kvm.c
blobfaedc6c254f9fc0bea0b8c1cd32307c66c84a73f
1 /*
2 * QEMU KVM support
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
20 #include <linux/kvm.h>
22 #include "qemu-common.h"
23 #include "sysemu.h"
24 #include "kvm.h"
25 #include "cpu.h"
26 #include "gdbstub.h"
27 #include "host-utils.h"
28 #include "hw/pc.h"
29 #include "hw/apic.h"
30 #include "ioport.h"
32 #ifdef CONFIG_KVM_PARA
33 #include <linux/kvm_para.h>
34 #endif
36 //#define DEBUG_KVM
38 #ifdef DEBUG_KVM
39 #define DPRINTF(fmt, ...) \
40 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
41 #else
42 #define DPRINTF(fmt, ...) \
43 do { } while (0)
44 #endif
46 #define MSR_KVM_WALL_CLOCK 0x11
47 #define MSR_KVM_SYSTEM_TIME 0x12
49 #ifndef BUS_MCEERR_AR
50 #define BUS_MCEERR_AR 4
51 #endif
52 #ifndef BUS_MCEERR_AO
53 #define BUS_MCEERR_AO 5
54 #endif
56 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
57 KVM_CAP_INFO(SET_TSS_ADDR),
58 KVM_CAP_INFO(EXT_CPUID),
59 KVM_CAP_INFO(MP_STATE),
60 KVM_CAP_LAST_INFO
63 static bool has_msr_star;
64 static bool has_msr_hsave_pa;
65 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
66 static bool has_msr_async_pf_en;
67 #endif
68 static int lm_capable_kernel;
70 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
72 struct kvm_cpuid2 *cpuid;
73 int r, size;
75 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
76 cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
77 cpuid->nent = max;
78 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
79 if (r == 0 && cpuid->nent >= max) {
80 r = -E2BIG;
82 if (r < 0) {
83 if (r == -E2BIG) {
84 qemu_free(cpuid);
85 return NULL;
86 } else {
87 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
88 strerror(-r));
89 exit(1);
92 return cpuid;
95 #ifdef CONFIG_KVM_PARA
96 struct kvm_para_features {
97 int cap;
98 int feature;
99 } para_features[] = {
100 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
101 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
102 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
103 #ifdef KVM_CAP_ASYNC_PF
104 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
105 #endif
106 { -1, -1 }
109 static int get_para_features(CPUState *env)
111 int i, features = 0;
113 for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
114 if (kvm_check_extension(env->kvm_state, para_features[i].cap)) {
115 features |= (1 << para_features[i].feature);
119 return features;
121 #endif
124 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
125 uint32_t index, int reg)
127 struct kvm_cpuid2 *cpuid;
128 int i, max;
129 uint32_t ret = 0;
130 uint32_t cpuid_1_edx;
131 #ifdef CONFIG_KVM_PARA
132 int has_kvm_features = 0;
133 #endif
135 max = 1;
136 while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
137 max *= 2;
140 for (i = 0; i < cpuid->nent; ++i) {
141 if (cpuid->entries[i].function == function &&
142 cpuid->entries[i].index == index) {
143 #ifdef CONFIG_KVM_PARA
144 if (cpuid->entries[i].function == KVM_CPUID_FEATURES) {
145 has_kvm_features = 1;
147 #endif
148 switch (reg) {
149 case R_EAX:
150 ret = cpuid->entries[i].eax;
151 break;
152 case R_EBX:
153 ret = cpuid->entries[i].ebx;
154 break;
155 case R_ECX:
156 ret = cpuid->entries[i].ecx;
157 break;
158 case R_EDX:
159 ret = cpuid->entries[i].edx;
160 switch (function) {
161 case 1:
162 /* KVM before 2.6.30 misreports the following features */
163 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
164 break;
165 case 0x80000001:
166 /* On Intel, kvm returns cpuid according to the Intel spec,
167 * so add missing bits according to the AMD spec:
169 cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
170 ret |= cpuid_1_edx & 0x183f7ff;
171 break;
173 break;
178 qemu_free(cpuid);
180 #ifdef CONFIG_KVM_PARA
181 /* fallback for older kernels */
182 if (!has_kvm_features && (function == KVM_CPUID_FEATURES)) {
183 ret = get_para_features(env);
185 #endif
187 return ret;
190 typedef struct HWPoisonPage {
191 ram_addr_t ram_addr;
192 QLIST_ENTRY(HWPoisonPage) list;
193 } HWPoisonPage;
195 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
196 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
198 static void kvm_unpoison_all(void *param)
200 HWPoisonPage *page, *next_page;
202 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
203 QLIST_REMOVE(page, list);
204 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
205 qemu_free(page);
209 #ifdef KVM_CAP_MCE
210 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
212 HWPoisonPage *page;
214 QLIST_FOREACH(page, &hwpoison_page_list, list) {
215 if (page->ram_addr == ram_addr) {
216 return;
219 page = qemu_malloc(sizeof(HWPoisonPage));
220 page->ram_addr = ram_addr;
221 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
224 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
225 int *max_banks)
227 int r;
229 r = kvm_check_extension(s, KVM_CAP_MCE);
230 if (r > 0) {
231 *max_banks = r;
232 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
234 return -ENOSYS;
237 static void kvm_mce_inject(CPUState *env, target_phys_addr_t paddr, int code)
239 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
240 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
241 uint64_t mcg_status = MCG_STATUS_MCIP;
243 if (code == BUS_MCEERR_AR) {
244 status |= MCI_STATUS_AR | 0x134;
245 mcg_status |= MCG_STATUS_EIPV;
246 } else {
247 status |= 0xc0;
248 mcg_status |= MCG_STATUS_RIPV;
250 cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr,
251 (MCM_ADDR_PHYS << 6) | 0xc,
252 cpu_x86_support_mca_broadcast(env) ?
253 MCE_INJECT_BROADCAST : 0);
255 #endif /* KVM_CAP_MCE */
257 static void hardware_memory_error(void)
259 fprintf(stderr, "Hardware memory error!\n");
260 exit(1);
263 int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr)
265 #ifdef KVM_CAP_MCE
266 ram_addr_t ram_addr;
267 target_phys_addr_t paddr;
269 if ((env->mcg_cap & MCG_SER_P) && addr
270 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
271 if (qemu_ram_addr_from_host(addr, &ram_addr) ||
272 !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr,
273 &paddr)) {
274 fprintf(stderr, "Hardware memory error for memory used by "
275 "QEMU itself instead of guest system!\n");
276 /* Hope we are lucky for AO MCE */
277 if (code == BUS_MCEERR_AO) {
278 return 0;
279 } else {
280 hardware_memory_error();
283 kvm_hwpoison_page_add(ram_addr);
284 kvm_mce_inject(env, paddr, code);
285 } else
286 #endif /* KVM_CAP_MCE */
288 if (code == BUS_MCEERR_AO) {
289 return 0;
290 } else if (code == BUS_MCEERR_AR) {
291 hardware_memory_error();
292 } else {
293 return 1;
296 return 0;
299 int kvm_arch_on_sigbus(int code, void *addr)
301 #ifdef KVM_CAP_MCE
302 if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
303 ram_addr_t ram_addr;
304 target_phys_addr_t paddr;
306 /* Hope we are lucky for AO MCE */
307 if (qemu_ram_addr_from_host(addr, &ram_addr) ||
308 !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr,
309 &paddr)) {
310 fprintf(stderr, "Hardware memory error for memory used by "
311 "QEMU itself instead of guest system!: %p\n", addr);
312 return 0;
314 kvm_hwpoison_page_add(ram_addr);
315 kvm_mce_inject(first_cpu, paddr, code);
316 } else
317 #endif /* KVM_CAP_MCE */
319 if (code == BUS_MCEERR_AO) {
320 return 0;
321 } else if (code == BUS_MCEERR_AR) {
322 hardware_memory_error();
323 } else {
324 return 1;
327 return 0;
330 static int kvm_inject_mce_oldstyle(CPUState *env)
332 #ifdef KVM_CAP_MCE
333 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
334 unsigned int bank, bank_num = env->mcg_cap & 0xff;
335 struct kvm_x86_mce mce;
337 env->exception_injected = -1;
340 * There must be at least one bank in use if an MCE is pending.
341 * Find it and use its values for the event injection.
343 for (bank = 0; bank < bank_num; bank++) {
344 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
345 break;
348 assert(bank < bank_num);
350 mce.bank = bank;
351 mce.status = env->mce_banks[bank * 4 + 1];
352 mce.mcg_status = env->mcg_status;
353 mce.addr = env->mce_banks[bank * 4 + 2];
354 mce.misc = env->mce_banks[bank * 4 + 3];
356 return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
358 #endif /* KVM_CAP_MCE */
359 return 0;
362 static void cpu_update_state(void *opaque, int running, int reason)
364 CPUState *env = opaque;
366 if (running) {
367 env->tsc_valid = false;
371 int kvm_arch_init_vcpu(CPUState *env)
373 struct {
374 struct kvm_cpuid2 cpuid;
375 struct kvm_cpuid_entry2 entries[100];
376 } __attribute__((packed)) cpuid_data;
377 uint32_t limit, i, j, cpuid_i;
378 uint32_t unused;
379 struct kvm_cpuid_entry2 *c;
380 #ifdef CONFIG_KVM_PARA
381 uint32_t signature[3];
382 #endif
384 env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
386 i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
387 env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
388 env->cpuid_ext_features |= i;
390 env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
391 0, R_EDX);
392 env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
393 0, R_ECX);
394 env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(env, 0x8000000A,
395 0, R_EDX);
398 cpuid_i = 0;
400 #ifdef CONFIG_KVM_PARA
401 /* Paravirtualization CPUIDs */
402 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
403 c = &cpuid_data.entries[cpuid_i++];
404 memset(c, 0, sizeof(*c));
405 c->function = KVM_CPUID_SIGNATURE;
406 c->eax = 0;
407 c->ebx = signature[0];
408 c->ecx = signature[1];
409 c->edx = signature[2];
411 c = &cpuid_data.entries[cpuid_i++];
412 memset(c, 0, sizeof(*c));
413 c->function = KVM_CPUID_FEATURES;
414 c->eax = env->cpuid_kvm_features & kvm_arch_get_supported_cpuid(env,
415 KVM_CPUID_FEATURES, 0, R_EAX);
417 #ifdef KVM_CAP_ASYNC_PF
418 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
419 #endif
421 #endif
423 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
425 for (i = 0; i <= limit; i++) {
426 c = &cpuid_data.entries[cpuid_i++];
428 switch (i) {
429 case 2: {
430 /* Keep reading function 2 till all the input is received */
431 int times;
433 c->function = i;
434 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
435 KVM_CPUID_FLAG_STATE_READ_NEXT;
436 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
437 times = c->eax & 0xff;
439 for (j = 1; j < times; ++j) {
440 c = &cpuid_data.entries[cpuid_i++];
441 c->function = i;
442 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
443 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
445 break;
447 case 4:
448 case 0xb:
449 case 0xd:
450 for (j = 0; ; j++) {
451 c->function = i;
452 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
453 c->index = j;
454 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
456 if (i == 4 && c->eax == 0) {
457 break;
459 if (i == 0xb && !(c->ecx & 0xff00)) {
460 break;
462 if (i == 0xd && c->eax == 0) {
463 break;
465 c = &cpuid_data.entries[cpuid_i++];
467 break;
468 default:
469 c->function = i;
470 c->flags = 0;
471 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
472 break;
475 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
477 for (i = 0x80000000; i <= limit; i++) {
478 c = &cpuid_data.entries[cpuid_i++];
480 c->function = i;
481 c->flags = 0;
482 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
485 cpuid_data.cpuid.nent = cpuid_i;
487 #ifdef KVM_CAP_MCE
488 if (((env->cpuid_version >> 8)&0xF) >= 6
489 && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
490 && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
491 uint64_t mcg_cap;
492 int banks;
493 int ret;
495 ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
496 if (ret < 0) {
497 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
498 return ret;
501 if (banks > MCE_BANKS_DEF) {
502 banks = MCE_BANKS_DEF;
504 mcg_cap &= MCE_CAP_DEF;
505 mcg_cap |= banks;
506 ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap);
507 if (ret < 0) {
508 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
509 return ret;
512 env->mcg_cap = mcg_cap;
514 #endif
516 qemu_add_vm_change_state_handler(cpu_update_state, env);
518 return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
521 void kvm_arch_reset_vcpu(CPUState *env)
523 env->exception_injected = -1;
524 env->interrupt_injected = -1;
525 env->xcr0 = 1;
526 if (kvm_irqchip_in_kernel()) {
527 env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
528 KVM_MP_STATE_UNINITIALIZED;
529 } else {
530 env->mp_state = KVM_MP_STATE_RUNNABLE;
534 static int kvm_get_supported_msrs(KVMState *s)
536 static int kvm_supported_msrs;
537 int ret = 0;
539 /* first time */
540 if (kvm_supported_msrs == 0) {
541 struct kvm_msr_list msr_list, *kvm_msr_list;
543 kvm_supported_msrs = -1;
545 /* Obtain MSR list from KVM. These are the MSRs that we must
546 * save/restore */
547 msr_list.nmsrs = 0;
548 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
549 if (ret < 0 && ret != -E2BIG) {
550 return ret;
552 /* Old kernel modules had a bug and could write beyond the provided
553 memory. Allocate at least a safe amount of 1K. */
554 kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
555 msr_list.nmsrs *
556 sizeof(msr_list.indices[0])));
558 kvm_msr_list->nmsrs = msr_list.nmsrs;
559 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
560 if (ret >= 0) {
561 int i;
563 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
564 if (kvm_msr_list->indices[i] == MSR_STAR) {
565 has_msr_star = true;
566 continue;
568 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
569 has_msr_hsave_pa = true;
570 continue;
575 qemu_free(kvm_msr_list);
578 return ret;
581 int kvm_arch_init(KVMState *s)
583 uint64_t identity_base = 0xfffbc000;
584 int ret;
585 struct utsname utsname;
587 ret = kvm_get_supported_msrs(s);
588 if (ret < 0) {
589 return ret;
592 uname(&utsname);
593 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
596 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
597 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
598 * Since these must be part of guest physical memory, we need to allocate
599 * them, both by setting their start addresses in the kernel and by
600 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
602 * Older KVM versions may not support setting the identity map base. In
603 * that case we need to stick with the default, i.e. a 256K maximum BIOS
604 * size.
606 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
607 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
608 /* Allows up to 16M BIOSes. */
609 identity_base = 0xfeffc000;
611 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
612 if (ret < 0) {
613 return ret;
616 #endif
617 /* Set TSS base one page after EPT identity map. */
618 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
619 if (ret < 0) {
620 return ret;
623 /* Tell fw_cfg to notify the BIOS to reserve the range. */
624 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
625 if (ret < 0) {
626 fprintf(stderr, "e820_add_entry() table is full\n");
627 return ret;
629 qemu_register_reset(kvm_unpoison_all, NULL);
631 return 0;
634 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
636 lhs->selector = rhs->selector;
637 lhs->base = rhs->base;
638 lhs->limit = rhs->limit;
639 lhs->type = 3;
640 lhs->present = 1;
641 lhs->dpl = 3;
642 lhs->db = 0;
643 lhs->s = 1;
644 lhs->l = 0;
645 lhs->g = 0;
646 lhs->avl = 0;
647 lhs->unusable = 0;
650 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
652 unsigned flags = rhs->flags;
653 lhs->selector = rhs->selector;
654 lhs->base = rhs->base;
655 lhs->limit = rhs->limit;
656 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
657 lhs->present = (flags & DESC_P_MASK) != 0;
658 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
659 lhs->db = (flags >> DESC_B_SHIFT) & 1;
660 lhs->s = (flags & DESC_S_MASK) != 0;
661 lhs->l = (flags >> DESC_L_SHIFT) & 1;
662 lhs->g = (flags & DESC_G_MASK) != 0;
663 lhs->avl = (flags & DESC_AVL_MASK) != 0;
664 lhs->unusable = 0;
667 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
669 lhs->selector = rhs->selector;
670 lhs->base = rhs->base;
671 lhs->limit = rhs->limit;
672 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
673 (rhs->present * DESC_P_MASK) |
674 (rhs->dpl << DESC_DPL_SHIFT) |
675 (rhs->db << DESC_B_SHIFT) |
676 (rhs->s * DESC_S_MASK) |
677 (rhs->l << DESC_L_SHIFT) |
678 (rhs->g * DESC_G_MASK) |
679 (rhs->avl * DESC_AVL_MASK);
682 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
684 if (set) {
685 *kvm_reg = *qemu_reg;
686 } else {
687 *qemu_reg = *kvm_reg;
691 static int kvm_getput_regs(CPUState *env, int set)
693 struct kvm_regs regs;
694 int ret = 0;
696 if (!set) {
697 ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
698 if (ret < 0) {
699 return ret;
703 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
704 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
705 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
706 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
707 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
708 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
709 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
710 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
711 #ifdef TARGET_X86_64
712 kvm_getput_reg(&regs.r8, &env->regs[8], set);
713 kvm_getput_reg(&regs.r9, &env->regs[9], set);
714 kvm_getput_reg(&regs.r10, &env->regs[10], set);
715 kvm_getput_reg(&regs.r11, &env->regs[11], set);
716 kvm_getput_reg(&regs.r12, &env->regs[12], set);
717 kvm_getput_reg(&regs.r13, &env->regs[13], set);
718 kvm_getput_reg(&regs.r14, &env->regs[14], set);
719 kvm_getput_reg(&regs.r15, &env->regs[15], set);
720 #endif
722 kvm_getput_reg(&regs.rflags, &env->eflags, set);
723 kvm_getput_reg(&regs.rip, &env->eip, set);
725 if (set) {
726 ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
729 return ret;
732 static int kvm_put_fpu(CPUState *env)
734 struct kvm_fpu fpu;
735 int i;
737 memset(&fpu, 0, sizeof fpu);
738 fpu.fsw = env->fpus & ~(7 << 11);
739 fpu.fsw |= (env->fpstt & 7) << 11;
740 fpu.fcw = env->fpuc;
741 for (i = 0; i < 8; ++i) {
742 fpu.ftwx |= (!env->fptags[i]) << i;
744 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
745 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
746 fpu.mxcsr = env->mxcsr;
748 return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
751 #ifdef KVM_CAP_XSAVE
752 #define XSAVE_CWD_RIP 2
753 #define XSAVE_CWD_RDP 4
754 #define XSAVE_MXCSR 6
755 #define XSAVE_ST_SPACE 8
756 #define XSAVE_XMM_SPACE 40
757 #define XSAVE_XSTATE_BV 128
758 #define XSAVE_YMMH_SPACE 144
759 #endif
761 static int kvm_put_xsave(CPUState *env)
763 #ifdef KVM_CAP_XSAVE
764 int i, r;
765 struct kvm_xsave* xsave;
766 uint16_t cwd, swd, twd, fop;
768 if (!kvm_has_xsave()) {
769 return kvm_put_fpu(env);
772 xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
773 memset(xsave, 0, sizeof(struct kvm_xsave));
774 cwd = swd = twd = fop = 0;
775 swd = env->fpus & ~(7 << 11);
776 swd |= (env->fpstt & 7) << 11;
777 cwd = env->fpuc;
778 for (i = 0; i < 8; ++i) {
779 twd |= (!env->fptags[i]) << i;
781 xsave->region[0] = (uint32_t)(swd << 16) + cwd;
782 xsave->region[1] = (uint32_t)(fop << 16) + twd;
783 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
784 sizeof env->fpregs);
785 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
786 sizeof env->xmm_regs);
787 xsave->region[XSAVE_MXCSR] = env->mxcsr;
788 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
789 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
790 sizeof env->ymmh_regs);
791 r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
792 qemu_free(xsave);
793 return r;
794 #else
795 return kvm_put_fpu(env);
796 #endif
799 static int kvm_put_xcrs(CPUState *env)
801 #ifdef KVM_CAP_XCRS
802 struct kvm_xcrs xcrs;
804 if (!kvm_has_xcrs()) {
805 return 0;
808 xcrs.nr_xcrs = 1;
809 xcrs.flags = 0;
810 xcrs.xcrs[0].xcr = 0;
811 xcrs.xcrs[0].value = env->xcr0;
812 return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
813 #else
814 return 0;
815 #endif
818 static int kvm_put_sregs(CPUState *env)
820 struct kvm_sregs sregs;
822 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
823 if (env->interrupt_injected >= 0) {
824 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
825 (uint64_t)1 << (env->interrupt_injected % 64);
828 if ((env->eflags & VM_MASK)) {
829 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
830 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
831 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
832 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
833 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
834 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
835 } else {
836 set_seg(&sregs.cs, &env->segs[R_CS]);
837 set_seg(&sregs.ds, &env->segs[R_DS]);
838 set_seg(&sregs.es, &env->segs[R_ES]);
839 set_seg(&sregs.fs, &env->segs[R_FS]);
840 set_seg(&sregs.gs, &env->segs[R_GS]);
841 set_seg(&sregs.ss, &env->segs[R_SS]);
844 set_seg(&sregs.tr, &env->tr);
845 set_seg(&sregs.ldt, &env->ldt);
847 sregs.idt.limit = env->idt.limit;
848 sregs.idt.base = env->idt.base;
849 sregs.gdt.limit = env->gdt.limit;
850 sregs.gdt.base = env->gdt.base;
852 sregs.cr0 = env->cr[0];
853 sregs.cr2 = env->cr[2];
854 sregs.cr3 = env->cr[3];
855 sregs.cr4 = env->cr[4];
857 sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
858 sregs.apic_base = cpu_get_apic_base(env->apic_state);
860 sregs.efer = env->efer;
862 return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
865 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
866 uint32_t index, uint64_t value)
868 entry->index = index;
869 entry->data = value;
872 static int kvm_put_msrs(CPUState *env, int level)
874 struct {
875 struct kvm_msrs info;
876 struct kvm_msr_entry entries[100];
877 } msr_data;
878 struct kvm_msr_entry *msrs = msr_data.entries;
879 int n = 0;
881 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
882 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
883 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
884 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
885 if (has_msr_star) {
886 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
888 if (has_msr_hsave_pa) {
889 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
891 #ifdef TARGET_X86_64
892 if (lm_capable_kernel) {
893 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
894 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
895 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
896 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
898 #endif
899 if (level == KVM_PUT_FULL_STATE) {
901 * KVM is yet unable to synchronize TSC values of multiple VCPUs on
902 * writeback. Until this is fixed, we only write the offset to SMP
903 * guests after migration, desynchronizing the VCPUs, but avoiding
904 * huge jump-backs that would occur without any writeback at all.
906 if (smp_cpus == 1 || env->tsc != 0) {
907 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
911 * The following paravirtual MSRs have side effects on the guest or are
912 * too heavy for normal writeback. Limit them to reset or full state
913 * updates.
915 if (level >= KVM_PUT_RESET_STATE) {
916 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
917 env->system_time_msr);
918 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
919 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
920 if (has_msr_async_pf_en) {
921 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
922 env->async_pf_en_msr);
924 #endif
926 #ifdef KVM_CAP_MCE
927 if (env->mcg_cap) {
928 int i;
930 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
931 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
932 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
933 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
936 #endif
938 msr_data.info.nmsrs = n;
940 return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
945 static int kvm_get_fpu(CPUState *env)
947 struct kvm_fpu fpu;
948 int i, ret;
950 ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
951 if (ret < 0) {
952 return ret;
955 env->fpstt = (fpu.fsw >> 11) & 7;
956 env->fpus = fpu.fsw;
957 env->fpuc = fpu.fcw;
958 for (i = 0; i < 8; ++i) {
959 env->fptags[i] = !((fpu.ftwx >> i) & 1);
961 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
962 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
963 env->mxcsr = fpu.mxcsr;
965 return 0;
968 static int kvm_get_xsave(CPUState *env)
970 #ifdef KVM_CAP_XSAVE
971 struct kvm_xsave* xsave;
972 int ret, i;
973 uint16_t cwd, swd, twd, fop;
975 if (!kvm_has_xsave()) {
976 return kvm_get_fpu(env);
979 xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
980 ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
981 if (ret < 0) {
982 qemu_free(xsave);
983 return ret;
986 cwd = (uint16_t)xsave->region[0];
987 swd = (uint16_t)(xsave->region[0] >> 16);
988 twd = (uint16_t)xsave->region[1];
989 fop = (uint16_t)(xsave->region[1] >> 16);
990 env->fpstt = (swd >> 11) & 7;
991 env->fpus = swd;
992 env->fpuc = cwd;
993 for (i = 0; i < 8; ++i) {
994 env->fptags[i] = !((twd >> i) & 1);
996 env->mxcsr = xsave->region[XSAVE_MXCSR];
997 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
998 sizeof env->fpregs);
999 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1000 sizeof env->xmm_regs);
1001 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1002 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1003 sizeof env->ymmh_regs);
1004 qemu_free(xsave);
1005 return 0;
1006 #else
1007 return kvm_get_fpu(env);
1008 #endif
1011 static int kvm_get_xcrs(CPUState *env)
1013 #ifdef KVM_CAP_XCRS
1014 int i, ret;
1015 struct kvm_xcrs xcrs;
1017 if (!kvm_has_xcrs()) {
1018 return 0;
1021 ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
1022 if (ret < 0) {
1023 return ret;
1026 for (i = 0; i < xcrs.nr_xcrs; i++) {
1027 /* Only support xcr0 now */
1028 if (xcrs.xcrs[0].xcr == 0) {
1029 env->xcr0 = xcrs.xcrs[0].value;
1030 break;
1033 return 0;
1034 #else
1035 return 0;
1036 #endif
1039 static int kvm_get_sregs(CPUState *env)
1041 struct kvm_sregs sregs;
1042 uint32_t hflags;
1043 int bit, i, ret;
1045 ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
1046 if (ret < 0) {
1047 return ret;
1050 /* There can only be one pending IRQ set in the bitmap at a time, so try
1051 to find it and save its number instead (-1 for none). */
1052 env->interrupt_injected = -1;
1053 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1054 if (sregs.interrupt_bitmap[i]) {
1055 bit = ctz64(sregs.interrupt_bitmap[i]);
1056 env->interrupt_injected = i * 64 + bit;
1057 break;
1061 get_seg(&env->segs[R_CS], &sregs.cs);
1062 get_seg(&env->segs[R_DS], &sregs.ds);
1063 get_seg(&env->segs[R_ES], &sregs.es);
1064 get_seg(&env->segs[R_FS], &sregs.fs);
1065 get_seg(&env->segs[R_GS], &sregs.gs);
1066 get_seg(&env->segs[R_SS], &sregs.ss);
1068 get_seg(&env->tr, &sregs.tr);
1069 get_seg(&env->ldt, &sregs.ldt);
1071 env->idt.limit = sregs.idt.limit;
1072 env->idt.base = sregs.idt.base;
1073 env->gdt.limit = sregs.gdt.limit;
1074 env->gdt.base = sregs.gdt.base;
1076 env->cr[0] = sregs.cr0;
1077 env->cr[2] = sregs.cr2;
1078 env->cr[3] = sregs.cr3;
1079 env->cr[4] = sregs.cr4;
1081 cpu_set_apic_base(env->apic_state, sregs.apic_base);
1083 env->efer = sregs.efer;
1084 //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
1086 #define HFLAG_COPY_MASK \
1087 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1088 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1089 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1090 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1092 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1093 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1094 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1095 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1096 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1097 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1098 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1100 if (env->efer & MSR_EFER_LMA) {
1101 hflags |= HF_LMA_MASK;
1104 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1105 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1106 } else {
1107 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1108 (DESC_B_SHIFT - HF_CS32_SHIFT);
1109 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1110 (DESC_B_SHIFT - HF_SS32_SHIFT);
1111 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1112 !(hflags & HF_CS32_MASK)) {
1113 hflags |= HF_ADDSEG_MASK;
1114 } else {
1115 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1116 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1119 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1121 return 0;
1124 static int kvm_get_msrs(CPUState *env)
1126 struct {
1127 struct kvm_msrs info;
1128 struct kvm_msr_entry entries[100];
1129 } msr_data;
1130 struct kvm_msr_entry *msrs = msr_data.entries;
1131 int ret, i, n;
1133 n = 0;
1134 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1135 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1136 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1137 msrs[n++].index = MSR_PAT;
1138 if (has_msr_star) {
1139 msrs[n++].index = MSR_STAR;
1141 if (has_msr_hsave_pa) {
1142 msrs[n++].index = MSR_VM_HSAVE_PA;
1145 if (!env->tsc_valid) {
1146 msrs[n++].index = MSR_IA32_TSC;
1147 env->tsc_valid = !vm_running;
1150 #ifdef TARGET_X86_64
1151 if (lm_capable_kernel) {
1152 msrs[n++].index = MSR_CSTAR;
1153 msrs[n++].index = MSR_KERNELGSBASE;
1154 msrs[n++].index = MSR_FMASK;
1155 msrs[n++].index = MSR_LSTAR;
1157 #endif
1158 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1159 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1160 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
1161 if (has_msr_async_pf_en) {
1162 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1164 #endif
1166 #ifdef KVM_CAP_MCE
1167 if (env->mcg_cap) {
1168 msrs[n++].index = MSR_MCG_STATUS;
1169 msrs[n++].index = MSR_MCG_CTL;
1170 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1171 msrs[n++].index = MSR_MC0_CTL + i;
1174 #endif
1176 msr_data.info.nmsrs = n;
1177 ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1178 if (ret < 0) {
1179 return ret;
1182 for (i = 0; i < ret; i++) {
1183 switch (msrs[i].index) {
1184 case MSR_IA32_SYSENTER_CS:
1185 env->sysenter_cs = msrs[i].data;
1186 break;
1187 case MSR_IA32_SYSENTER_ESP:
1188 env->sysenter_esp = msrs[i].data;
1189 break;
1190 case MSR_IA32_SYSENTER_EIP:
1191 env->sysenter_eip = msrs[i].data;
1192 break;
1193 case MSR_PAT:
1194 env->pat = msrs[i].data;
1195 break;
1196 case MSR_STAR:
1197 env->star = msrs[i].data;
1198 break;
1199 #ifdef TARGET_X86_64
1200 case MSR_CSTAR:
1201 env->cstar = msrs[i].data;
1202 break;
1203 case MSR_KERNELGSBASE:
1204 env->kernelgsbase = msrs[i].data;
1205 break;
1206 case MSR_FMASK:
1207 env->fmask = msrs[i].data;
1208 break;
1209 case MSR_LSTAR:
1210 env->lstar = msrs[i].data;
1211 break;
1212 #endif
1213 case MSR_IA32_TSC:
1214 env->tsc = msrs[i].data;
1215 break;
1216 case MSR_VM_HSAVE_PA:
1217 env->vm_hsave = msrs[i].data;
1218 break;
1219 case MSR_KVM_SYSTEM_TIME:
1220 env->system_time_msr = msrs[i].data;
1221 break;
1222 case MSR_KVM_WALL_CLOCK:
1223 env->wall_clock_msr = msrs[i].data;
1224 break;
1225 #ifdef KVM_CAP_MCE
1226 case MSR_MCG_STATUS:
1227 env->mcg_status = msrs[i].data;
1228 break;
1229 case MSR_MCG_CTL:
1230 env->mcg_ctl = msrs[i].data;
1231 break;
1232 #endif
1233 default:
1234 #ifdef KVM_CAP_MCE
1235 if (msrs[i].index >= MSR_MC0_CTL &&
1236 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1237 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1239 #endif
1240 break;
1241 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
1242 case MSR_KVM_ASYNC_PF_EN:
1243 env->async_pf_en_msr = msrs[i].data;
1244 break;
1245 #endif
1249 return 0;
1252 static int kvm_put_mp_state(CPUState *env)
1254 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1256 return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1259 static int kvm_get_mp_state(CPUState *env)
1261 struct kvm_mp_state mp_state;
1262 int ret;
1264 ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1265 if (ret < 0) {
1266 return ret;
1268 env->mp_state = mp_state.mp_state;
1269 if (kvm_irqchip_in_kernel()) {
1270 env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1272 return 0;
1275 static int kvm_put_vcpu_events(CPUState *env, int level)
1277 #ifdef KVM_CAP_VCPU_EVENTS
1278 struct kvm_vcpu_events events;
1280 if (!kvm_has_vcpu_events()) {
1281 return 0;
1284 events.exception.injected = (env->exception_injected >= 0);
1285 events.exception.nr = env->exception_injected;
1286 events.exception.has_error_code = env->has_error_code;
1287 events.exception.error_code = env->error_code;
1289 events.interrupt.injected = (env->interrupt_injected >= 0);
1290 events.interrupt.nr = env->interrupt_injected;
1291 events.interrupt.soft = env->soft_interrupt;
1293 events.nmi.injected = env->nmi_injected;
1294 events.nmi.pending = env->nmi_pending;
1295 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1297 events.sipi_vector = env->sipi_vector;
1299 events.flags = 0;
1300 if (level >= KVM_PUT_RESET_STATE) {
1301 events.flags |=
1302 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1305 return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1306 #else
1307 return 0;
1308 #endif
1311 static int kvm_get_vcpu_events(CPUState *env)
1313 #ifdef KVM_CAP_VCPU_EVENTS
1314 struct kvm_vcpu_events events;
1315 int ret;
1317 if (!kvm_has_vcpu_events()) {
1318 return 0;
1321 ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1322 if (ret < 0) {
1323 return ret;
1325 env->exception_injected =
1326 events.exception.injected ? events.exception.nr : -1;
1327 env->has_error_code = events.exception.has_error_code;
1328 env->error_code = events.exception.error_code;
1330 env->interrupt_injected =
1331 events.interrupt.injected ? events.interrupt.nr : -1;
1332 env->soft_interrupt = events.interrupt.soft;
1334 env->nmi_injected = events.nmi.injected;
1335 env->nmi_pending = events.nmi.pending;
1336 if (events.nmi.masked) {
1337 env->hflags2 |= HF2_NMI_MASK;
1338 } else {
1339 env->hflags2 &= ~HF2_NMI_MASK;
1342 env->sipi_vector = events.sipi_vector;
1343 #endif
1345 return 0;
1348 static int kvm_guest_debug_workarounds(CPUState *env)
1350 int ret = 0;
1351 #ifdef KVM_CAP_SET_GUEST_DEBUG
1352 unsigned long reinject_trap = 0;
1354 if (!kvm_has_vcpu_events()) {
1355 if (env->exception_injected == 1) {
1356 reinject_trap = KVM_GUESTDBG_INJECT_DB;
1357 } else if (env->exception_injected == 3) {
1358 reinject_trap = KVM_GUESTDBG_INJECT_BP;
1360 env->exception_injected = -1;
1364 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1365 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1366 * by updating the debug state once again if single-stepping is on.
1367 * Another reason to call kvm_update_guest_debug here is a pending debug
1368 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1369 * reinject them via SET_GUEST_DEBUG.
1371 if (reinject_trap ||
1372 (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1373 ret = kvm_update_guest_debug(env, reinject_trap);
1375 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1376 return ret;
1379 static int kvm_put_debugregs(CPUState *env)
1381 #ifdef KVM_CAP_DEBUGREGS
1382 struct kvm_debugregs dbgregs;
1383 int i;
1385 if (!kvm_has_debugregs()) {
1386 return 0;
1389 for (i = 0; i < 4; i++) {
1390 dbgregs.db[i] = env->dr[i];
1392 dbgregs.dr6 = env->dr[6];
1393 dbgregs.dr7 = env->dr[7];
1394 dbgregs.flags = 0;
1396 return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1397 #else
1398 return 0;
1399 #endif
1402 static int kvm_get_debugregs(CPUState *env)
1404 #ifdef KVM_CAP_DEBUGREGS
1405 struct kvm_debugregs dbgregs;
1406 int i, ret;
1408 if (!kvm_has_debugregs()) {
1409 return 0;
1412 ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1413 if (ret < 0) {
1414 return ret;
1416 for (i = 0; i < 4; i++) {
1417 env->dr[i] = dbgregs.db[i];
1419 env->dr[4] = env->dr[6] = dbgregs.dr6;
1420 env->dr[5] = env->dr[7] = dbgregs.dr7;
1421 #endif
1423 return 0;
1426 int kvm_arch_put_registers(CPUState *env, int level)
1428 int ret;
1430 assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1432 ret = kvm_getput_regs(env, 1);
1433 if (ret < 0) {
1434 return ret;
1436 ret = kvm_put_xsave(env);
1437 if (ret < 0) {
1438 return ret;
1440 ret = kvm_put_xcrs(env);
1441 if (ret < 0) {
1442 return ret;
1444 ret = kvm_put_sregs(env);
1445 if (ret < 0) {
1446 return ret;
1448 /* must be before kvm_put_msrs */
1449 ret = kvm_inject_mce_oldstyle(env);
1450 if (ret < 0) {
1451 return ret;
1453 ret = kvm_put_msrs(env, level);
1454 if (ret < 0) {
1455 return ret;
1457 if (level >= KVM_PUT_RESET_STATE) {
1458 ret = kvm_put_mp_state(env);
1459 if (ret < 0) {
1460 return ret;
1463 ret = kvm_put_vcpu_events(env, level);
1464 if (ret < 0) {
1465 return ret;
1467 ret = kvm_put_debugregs(env);
1468 if (ret < 0) {
1469 return ret;
1471 /* must be last */
1472 ret = kvm_guest_debug_workarounds(env);
1473 if (ret < 0) {
1474 return ret;
1476 return 0;
1479 int kvm_arch_get_registers(CPUState *env)
1481 int ret;
1483 assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1485 ret = kvm_getput_regs(env, 0);
1486 if (ret < 0) {
1487 return ret;
1489 ret = kvm_get_xsave(env);
1490 if (ret < 0) {
1491 return ret;
1493 ret = kvm_get_xcrs(env);
1494 if (ret < 0) {
1495 return ret;
1497 ret = kvm_get_sregs(env);
1498 if (ret < 0) {
1499 return ret;
1501 ret = kvm_get_msrs(env);
1502 if (ret < 0) {
1503 return ret;
1505 ret = kvm_get_mp_state(env);
1506 if (ret < 0) {
1507 return ret;
1509 ret = kvm_get_vcpu_events(env);
1510 if (ret < 0) {
1511 return ret;
1513 ret = kvm_get_debugregs(env);
1514 if (ret < 0) {
1515 return ret;
1517 return 0;
1520 void kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1522 int ret;
1524 /* Inject NMI */
1525 if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1526 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1527 DPRINTF("injected NMI\n");
1528 ret = kvm_vcpu_ioctl(env, KVM_NMI);
1529 if (ret < 0) {
1530 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1531 strerror(-ret));
1535 if (!kvm_irqchip_in_kernel()) {
1536 /* Force the VCPU out of its inner loop to process the INIT request */
1537 if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1538 env->exit_request = 1;
1541 /* Try to inject an interrupt if the guest can accept it */
1542 if (run->ready_for_interrupt_injection &&
1543 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1544 (env->eflags & IF_MASK)) {
1545 int irq;
1547 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1548 irq = cpu_get_pic_interrupt(env);
1549 if (irq >= 0) {
1550 struct kvm_interrupt intr;
1552 intr.irq = irq;
1553 DPRINTF("injected interrupt %d\n", irq);
1554 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1555 if (ret < 0) {
1556 fprintf(stderr,
1557 "KVM: injection failed, interrupt lost (%s)\n",
1558 strerror(-ret));
1563 /* If we have an interrupt but the guest is not ready to receive an
1564 * interrupt, request an interrupt window exit. This will
1565 * cause a return to userspace as soon as the guest is ready to
1566 * receive interrupts. */
1567 if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1568 run->request_interrupt_window = 1;
1569 } else {
1570 run->request_interrupt_window = 0;
1573 DPRINTF("setting tpr\n");
1574 run->cr8 = cpu_get_apic_tpr(env->apic_state);
1578 void kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1580 if (run->if_flag) {
1581 env->eflags |= IF_MASK;
1582 } else {
1583 env->eflags &= ~IF_MASK;
1585 cpu_set_apic_tpr(env->apic_state, run->cr8);
1586 cpu_set_apic_base(env->apic_state, run->apic_base);
1589 int kvm_arch_process_async_events(CPUState *env)
1591 if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1592 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1593 assert(env->mcg_cap);
1595 env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1597 kvm_cpu_synchronize_state(env);
1599 if (env->exception_injected == EXCP08_DBLE) {
1600 /* this means triple fault */
1601 qemu_system_reset_request();
1602 env->exit_request = 1;
1603 return 0;
1605 env->exception_injected = EXCP12_MCHK;
1606 env->has_error_code = 0;
1608 env->halted = 0;
1609 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1610 env->mp_state = KVM_MP_STATE_RUNNABLE;
1614 if (kvm_irqchip_in_kernel()) {
1615 return 0;
1618 if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1619 (env->eflags & IF_MASK)) ||
1620 (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1621 env->halted = 0;
1623 if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1624 kvm_cpu_synchronize_state(env);
1625 do_cpu_init(env);
1627 if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1628 kvm_cpu_synchronize_state(env);
1629 do_cpu_sipi(env);
1632 return env->halted;
1635 static int kvm_handle_halt(CPUState *env)
1637 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1638 (env->eflags & IF_MASK)) &&
1639 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1640 env->halted = 1;
1641 return EXCP_HLT;
1644 return 0;
1647 #ifdef KVM_CAP_SET_GUEST_DEBUG
1648 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1650 static const uint8_t int3 = 0xcc;
1652 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1653 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1654 return -EINVAL;
1656 return 0;
1659 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1661 uint8_t int3;
1663 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1664 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1665 return -EINVAL;
1667 return 0;
1670 static struct {
1671 target_ulong addr;
1672 int len;
1673 int type;
1674 } hw_breakpoint[4];
1676 static int nb_hw_breakpoint;
1678 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1680 int n;
1682 for (n = 0; n < nb_hw_breakpoint; n++) {
1683 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1684 (hw_breakpoint[n].len == len || len == -1)) {
1685 return n;
1688 return -1;
1691 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1692 target_ulong len, int type)
1694 switch (type) {
1695 case GDB_BREAKPOINT_HW:
1696 len = 1;
1697 break;
1698 case GDB_WATCHPOINT_WRITE:
1699 case GDB_WATCHPOINT_ACCESS:
1700 switch (len) {
1701 case 1:
1702 break;
1703 case 2:
1704 case 4:
1705 case 8:
1706 if (addr & (len - 1)) {
1707 return -EINVAL;
1709 break;
1710 default:
1711 return -EINVAL;
1713 break;
1714 default:
1715 return -ENOSYS;
1718 if (nb_hw_breakpoint == 4) {
1719 return -ENOBUFS;
1721 if (find_hw_breakpoint(addr, len, type) >= 0) {
1722 return -EEXIST;
1724 hw_breakpoint[nb_hw_breakpoint].addr = addr;
1725 hw_breakpoint[nb_hw_breakpoint].len = len;
1726 hw_breakpoint[nb_hw_breakpoint].type = type;
1727 nb_hw_breakpoint++;
1729 return 0;
1732 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1733 target_ulong len, int type)
1735 int n;
1737 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1738 if (n < 0) {
1739 return -ENOENT;
1741 nb_hw_breakpoint--;
1742 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1744 return 0;
1747 void kvm_arch_remove_all_hw_breakpoints(void)
1749 nb_hw_breakpoint = 0;
1752 static CPUWatchpoint hw_watchpoint;
1754 static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
1756 int ret = 0;
1757 int n;
1759 if (arch_info->exception == 1) {
1760 if (arch_info->dr6 & (1 << 14)) {
1761 if (cpu_single_env->singlestep_enabled) {
1762 ret = EXCP_DEBUG;
1764 } else {
1765 for (n = 0; n < 4; n++) {
1766 if (arch_info->dr6 & (1 << n)) {
1767 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1768 case 0x0:
1769 ret = EXCP_DEBUG;
1770 break;
1771 case 0x1:
1772 ret = EXCP_DEBUG;
1773 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1774 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1775 hw_watchpoint.flags = BP_MEM_WRITE;
1776 break;
1777 case 0x3:
1778 ret = EXCP_DEBUG;
1779 cpu_single_env->watchpoint_hit = &hw_watchpoint;
1780 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1781 hw_watchpoint.flags = BP_MEM_ACCESS;
1782 break;
1787 } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1788 ret = EXCP_DEBUG;
1790 if (ret == 0) {
1791 cpu_synchronize_state(cpu_single_env);
1792 assert(cpu_single_env->exception_injected == -1);
1794 /* pass to guest */
1795 cpu_single_env->exception_injected = arch_info->exception;
1796 cpu_single_env->has_error_code = 0;
1799 return ret;
1802 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1804 const uint8_t type_code[] = {
1805 [GDB_BREAKPOINT_HW] = 0x0,
1806 [GDB_WATCHPOINT_WRITE] = 0x1,
1807 [GDB_WATCHPOINT_ACCESS] = 0x3
1809 const uint8_t len_code[] = {
1810 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1812 int n;
1814 if (kvm_sw_breakpoints_active(env)) {
1815 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1817 if (nb_hw_breakpoint > 0) {
1818 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1819 dbg->arch.debugreg[7] = 0x0600;
1820 for (n = 0; n < nb_hw_breakpoint; n++) {
1821 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1822 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1823 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1824 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1828 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1830 static bool host_supports_vmx(void)
1832 uint32_t ecx, unused;
1834 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1835 return ecx & CPUID_EXT_VMX;
1838 #define VMX_INVALID_GUEST_STATE 0x80000021
1840 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1842 uint64_t code;
1843 int ret;
1845 switch (run->exit_reason) {
1846 case KVM_EXIT_HLT:
1847 DPRINTF("handle_hlt\n");
1848 ret = kvm_handle_halt(env);
1849 break;
1850 case KVM_EXIT_SET_TPR:
1851 ret = 0;
1852 break;
1853 case KVM_EXIT_FAIL_ENTRY:
1854 code = run->fail_entry.hardware_entry_failure_reason;
1855 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
1856 code);
1857 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
1858 fprintf(stderr,
1859 "\nIf you're runnning a guest on an Intel machine without "
1860 "unrestricted mode\n"
1861 "support, the failure can be most likely due to the guest "
1862 "entering an invalid\n"
1863 "state for Intel VT. For example, the guest maybe running "
1864 "in big real mode\n"
1865 "which is not supported on less recent Intel processors."
1866 "\n\n");
1868 ret = -1;
1869 break;
1870 case KVM_EXIT_EXCEPTION:
1871 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
1872 run->ex.exception, run->ex.error_code);
1873 ret = -1;
1874 break;
1875 #ifdef KVM_CAP_SET_GUEST_DEBUG
1876 case KVM_EXIT_DEBUG:
1877 DPRINTF("kvm_exit_debug\n");
1878 ret = kvm_handle_debug(&run->debug.arch);
1879 break;
1880 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1881 default:
1882 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1883 ret = -1;
1884 break;
1887 return ret;
1890 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1892 return !(env->cr[0] & CR0_PE_MASK) ||
1893 ((env->segs[R_CS].selector & 3) != 3);