2 * ARM GIC support - common bits of emulated and KVM kernel model
4 * Copyright (c) 2012 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "gic_internal.h"
23 #include "hw/arm/linux-boot-if.h"
25 static void gic_pre_save(void *opaque
)
27 GICState
*s
= (GICState
*)opaque
;
28 ARMGICCommonClass
*c
= ARM_GIC_COMMON_GET_CLASS(s
);
35 static int gic_post_load(void *opaque
, int version_id
)
37 GICState
*s
= (GICState
*)opaque
;
38 ARMGICCommonClass
*c
= ARM_GIC_COMMON_GET_CLASS(s
);
46 static const VMStateDescription vmstate_gic_irq_state
= {
47 .name
= "arm_gic_irq_state",
49 .minimum_version_id
= 1,
50 .fields
= (VMStateField
[]) {
51 VMSTATE_UINT8(enabled
, gic_irq_state
),
52 VMSTATE_UINT8(pending
, gic_irq_state
),
53 VMSTATE_UINT8(active
, gic_irq_state
),
54 VMSTATE_UINT8(level
, gic_irq_state
),
55 VMSTATE_BOOL(model
, gic_irq_state
),
56 VMSTATE_BOOL(edge_trigger
, gic_irq_state
),
57 VMSTATE_UINT8(group
, gic_irq_state
),
62 static const VMStateDescription vmstate_gic
= {
65 .minimum_version_id
= 12,
66 .pre_save
= gic_pre_save
,
67 .post_load
= gic_post_load
,
68 .fields
= (VMStateField
[]) {
69 VMSTATE_UINT32(ctlr
, GICState
),
70 VMSTATE_UINT32_ARRAY(cpu_ctlr
, GICState
, GIC_NCPU
),
71 VMSTATE_STRUCT_ARRAY(irq_state
, GICState
, GIC_MAXIRQ
, 1,
72 vmstate_gic_irq_state
, gic_irq_state
),
73 VMSTATE_UINT8_ARRAY(irq_target
, GICState
, GIC_MAXIRQ
),
74 VMSTATE_UINT8_2DARRAY(priority1
, GICState
, GIC_INTERNAL
, GIC_NCPU
),
75 VMSTATE_UINT8_ARRAY(priority2
, GICState
, GIC_MAXIRQ
- GIC_INTERNAL
),
76 VMSTATE_UINT8_2DARRAY(sgi_pending
, GICState
, GIC_NR_SGIS
, GIC_NCPU
),
77 VMSTATE_UINT16_ARRAY(priority_mask
, GICState
, GIC_NCPU
),
78 VMSTATE_UINT16_ARRAY(running_priority
, GICState
, GIC_NCPU
),
79 VMSTATE_UINT16_ARRAY(current_pending
, GICState
, GIC_NCPU
),
80 VMSTATE_UINT8_ARRAY(bpr
, GICState
, GIC_NCPU
),
81 VMSTATE_UINT8_ARRAY(abpr
, GICState
, GIC_NCPU
),
82 VMSTATE_UINT32_2DARRAY(apr
, GICState
, GIC_NR_APRS
, GIC_NCPU
),
83 VMSTATE_UINT32_2DARRAY(nsapr
, GICState
, GIC_NR_APRS
, GIC_NCPU
),
88 void gic_init_irqs_and_mmio(GICState
*s
, qemu_irq_handler handler
,
89 const MemoryRegionOps
*ops
)
91 SysBusDevice
*sbd
= SYS_BUS_DEVICE(s
);
92 int i
= s
->num_irq
- GIC_INTERNAL
;
94 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
95 * GPIO array layout is thus:
97 * [N..N+31] PPIs for CPU 0
98 * [N+32..N+63] PPIs for CPU 1
101 if (s
->revision
!= REV_NVIC
) {
102 i
+= (GIC_INTERNAL
* s
->num_cpu
);
104 qdev_init_gpio_in(DEVICE(s
), handler
, i
);
106 for (i
= 0; i
< s
->num_cpu
; i
++) {
107 sysbus_init_irq(sbd
, &s
->parent_irq
[i
]);
109 for (i
= 0; i
< s
->num_cpu
; i
++) {
110 sysbus_init_irq(sbd
, &s
->parent_fiq
[i
]);
114 memory_region_init_io(&s
->iomem
, OBJECT(s
), ops
, s
, "gic_dist", 0x1000);
115 sysbus_init_mmio(sbd
, &s
->iomem
);
117 if (s
->revision
!= REV_NVIC
) {
118 /* This is the main CPU interface "for this core". It is always
119 * present because it is required by both software emulation and KVM.
120 * NVIC is not handled here because its CPU interface is different,
121 * neither it can use KVM.
123 memory_region_init_io(&s
->cpuiomem
[0], OBJECT(s
), ops
? &ops
[1] : NULL
,
124 s
, "gic_cpu", s
->revision
== 2 ? 0x2000 : 0x100);
125 sysbus_init_mmio(sbd
, &s
->cpuiomem
[0]);
129 static void arm_gic_common_realize(DeviceState
*dev
, Error
**errp
)
131 GICState
*s
= ARM_GIC_COMMON(dev
);
132 int num_irq
= s
->num_irq
;
134 if (s
->num_cpu
> GIC_NCPU
) {
135 error_setg(errp
, "requested %u CPUs exceeds GIC maximum %d",
136 s
->num_cpu
, GIC_NCPU
);
139 s
->num_irq
+= GIC_BASE_IRQ
;
140 if (s
->num_irq
> GIC_MAXIRQ
) {
142 "requested %u interrupt lines exceeds GIC maximum %d",
143 num_irq
, GIC_MAXIRQ
);
146 /* ITLinesNumber is represented as (N / 32) - 1 (see
147 * gic_dist_readb) so this is an implementation imposed
148 * restriction, not an architectural one:
150 if (s
->num_irq
< 32 || (s
->num_irq
% 32)) {
152 "%d interrupt lines unsupported: not divisible by 32",
157 if (s
->security_extn
&&
158 (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
)) {
159 error_setg(errp
, "this GIC revision does not implement "
160 "the security extensions");
165 static void arm_gic_common_reset(DeviceState
*dev
)
167 GICState
*s
= ARM_GIC_COMMON(dev
);
171 /* If we're resetting a TZ-aware GIC as if secure firmware
172 * had set it up ready to start a kernel in non-secure,
173 * we need to set interrupt priorities to a "zero for the
174 * NS view" value. This is particularly critical for the
175 * priority_mask[] values, because if they are zero then NS
176 * code cannot ever rewrite the priority to anything else.
178 if (s
->security_extn
&& s
->irq_reset_nonsecure
) {
184 memset(s
->irq_state
, 0, GIC_MAXIRQ
* sizeof(gic_irq_state
));
185 for (i
= 0 ; i
< s
->num_cpu
; i
++) {
186 if (s
->revision
== REV_11MPCORE
) {
187 s
->priority_mask
[i
] = 0xf0;
189 s
->priority_mask
[i
] = resetprio
;
191 s
->current_pending
[i
] = 1023;
192 s
->running_priority
[i
] = 0x100;
194 s
->bpr
[i
] = GIC_MIN_BPR
;
195 s
->abpr
[i
] = GIC_MIN_ABPR
;
196 for (j
= 0; j
< GIC_INTERNAL
; j
++) {
197 s
->priority1
[j
][i
] = resetprio
;
199 for (j
= 0; j
< GIC_NR_SGIS
; j
++) {
200 s
->sgi_pending
[j
][i
] = 0;
203 for (i
= 0; i
< GIC_NR_SGIS
; i
++) {
204 GIC_SET_ENABLED(i
, ALL_CPU_MASK
);
205 GIC_SET_EDGE_TRIGGER(i
);
208 for (i
= 0; i
< ARRAY_SIZE(s
->priority2
); i
++) {
209 s
->priority2
[i
] = resetprio
;
212 for (i
= 0; i
< GIC_MAXIRQ
; i
++) {
213 /* For uniprocessor GICs all interrupts always target the sole CPU */
214 if (s
->num_cpu
== 1) {
215 s
->irq_target
[i
] = 1;
217 s
->irq_target
[i
] = 0;
220 if (s
->security_extn
&& s
->irq_reset_nonsecure
) {
221 for (i
= 0; i
< GIC_MAXIRQ
; i
++) {
222 GIC_SET_GROUP(i
, ALL_CPU_MASK
);
229 static void arm_gic_common_linux_init(ARMLinuxBootIf
*obj
,
232 GICState
*s
= ARM_GIC_COMMON(obj
);
234 if (s
->security_extn
&& !secure_boot
) {
235 /* We're directly booting a kernel into NonSecure. If this GIC
236 * implements the security extensions then we must configure it
237 * to have all the interrupts be NonSecure (this is a job that
238 * is done by the Secure boot firmware in real hardware, and in
239 * this mode QEMU is acting as a minimalist firmware-and-bootloader
242 s
->irq_reset_nonsecure
= true;
246 static Property arm_gic_common_properties
[] = {
247 DEFINE_PROP_UINT32("num-cpu", GICState
, num_cpu
, 1),
248 DEFINE_PROP_UINT32("num-irq", GICState
, num_irq
, 32),
249 /* Revision can be 1 or 2 for GIC architecture specification
250 * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
251 * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".)
253 DEFINE_PROP_UINT32("revision", GICState
, revision
, 1),
254 /* True if the GIC should implement the security extensions */
255 DEFINE_PROP_BOOL("has-security-extensions", GICState
, security_extn
, 0),
256 DEFINE_PROP_END_OF_LIST(),
259 static void arm_gic_common_class_init(ObjectClass
*klass
, void *data
)
261 DeviceClass
*dc
= DEVICE_CLASS(klass
);
262 ARMLinuxBootIfClass
*albifc
= ARM_LINUX_BOOT_IF_CLASS(klass
);
264 dc
->reset
= arm_gic_common_reset
;
265 dc
->realize
= arm_gic_common_realize
;
266 dc
->props
= arm_gic_common_properties
;
267 dc
->vmsd
= &vmstate_gic
;
268 albifc
->arm_linux_init
= arm_gic_common_linux_init
;
271 static const TypeInfo arm_gic_common_type
= {
272 .name
= TYPE_ARM_GIC_COMMON
,
273 .parent
= TYPE_SYS_BUS_DEVICE
,
274 .instance_size
= sizeof(GICState
),
275 .class_size
= sizeof(ARMGICCommonClass
),
276 .class_init
= arm_gic_common_class_init
,
278 .interfaces
= (InterfaceInfo
[]) {
279 { TYPE_ARM_LINUX_BOOT_IF
},
284 static void register_types(void)
286 type_register_static(&arm_gic_common_type
);
289 type_init(register_types
)