2 * VT82C686B south bridge support
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
7 * This code is licensed under the GNU GPL v2.
23 #include "qemu-timer.h"
25 typedef uint32_t pci_addr_t
;
27 //#define DEBUG_VT82C686B
29 #ifdef DEBUG_VT82C686B
30 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
32 #define DPRINTF(fmt, ...)
35 typedef struct SuperIOConfig
42 typedef struct VT82C686BState
{
44 SuperIOConfig superio_conf
;
47 static void superio_ioport_writeb(void *opaque
, uint32_t addr
, uint32_t data
)
50 SuperIOConfig
*superio_conf
= opaque
;
52 DPRINTF("superio_ioport_writeb address 0x%x val 0x%x \n", addr
, data
);
54 superio_conf
->index
= data
& 0xff;
57 switch (superio_conf
->index
) {
73 switch (superio_conf
->index
) {
75 if ((data
& 0xff) != 0xfe) {
76 DPRINTF("chage uart 1 base. unsupported yet \n");
80 if ((data
& 0xff) != 0xbe) {
81 DPRINTF("chage uart 2 base. unsupported yet \n");
86 superio_conf
->config
[superio_conf
->index
] = data
& 0xff;
90 superio_conf
->config
[superio_conf
->index
] = data
& 0xff;
94 static uint32_t superio_ioport_readb(void *opaque
, uint32_t addr
)
96 SuperIOConfig
*superio_conf
= opaque
;
98 DPRINTF("superio_ioport_readb address 0x%x \n", addr
);
99 return (superio_conf
->config
[superio_conf
->index
]);
102 static void vt82c686b_reset(void * opaque
)
104 PCIDevice
*d
= opaque
;
105 uint8_t *pci_conf
= d
->config
;
106 VT82C686BState
*vt82c
= DO_UPCAST(VT82C686BState
, dev
, d
);
108 pci_set_long(pci_conf
+ PCI_CAPABILITY_LIST
, 0x000000c0);
109 pci_set_word(pci_conf
+ PCI_COMMAND
, PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
|
110 PCI_COMMAND_MASTER
| PCI_COMMAND_SPECIAL
);
111 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_DEVSEL_MEDIUM
);
113 pci_conf
[0x48] = 0x01; /* Miscellaneous Control 3 */
114 pci_conf
[0x4a] = 0x04; /* IDE interrupt Routing */
115 pci_conf
[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
116 pci_conf
[0x50] = 0x2d; /* PnP DMA Request Control */
117 pci_conf
[0x59] = 0x04;
118 pci_conf
[0x5a] = 0x04; /* KBC/RTC Control*/
119 pci_conf
[0x5f] = 0x04;
120 pci_conf
[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
122 vt82c
->superio_conf
.config
[0xe0] = 0x3c;
123 vt82c
->superio_conf
.config
[0xe2] = 0x03;
124 vt82c
->superio_conf
.config
[0xe3] = 0xfc;
125 vt82c
->superio_conf
.config
[0xe6] = 0xde;
126 vt82c
->superio_conf
.config
[0xe7] = 0xfe;
127 vt82c
->superio_conf
.config
[0xe8] = 0xbe;
130 /* write config pci function0 registers. PCI-ISA bridge */
131 static void vt82c686b_write_config(PCIDevice
* d
, uint32_t address
,
132 uint32_t val
, int len
)
134 VT82C686BState
*vt686
= DO_UPCAST(VT82C686BState
, dev
, d
);
136 DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x \n",
139 pci_default_write_config(d
, address
, val
, len
);
140 if (address
== 0x85) { /* enable or disable super IO configure */
142 /* floppy also uses 0x3f0 and 0x3f1.
143 * But we do not emulate flopy,so just set it here. */
144 isa_unassign_ioport(0x3f0, 2);
145 register_ioport_read(0x3f0, 2, 1, superio_ioport_readb
,
146 &vt686
->superio_conf
);
147 register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb
,
148 &vt686
->superio_conf
);
150 isa_unassign_ioport(0x3f0, 2);
155 #define ACPI_DBG_IO_ADDR 0xb044
157 typedef struct VT686PMState
{
165 uint32_t smb_io_base
;
168 typedef struct VT686AC97State
{
172 typedef struct VT686MC97State
{
176 #define RTC_EN (1 << 10)
177 #define PWRBTN_EN (1 << 8)
178 #define GBL_EN (1 << 5)
179 #define TMROF_EN (1 << 0)
180 #define SUS_EN (1 << 13)
182 #define ACPI_ENABLE 0xf1
183 #define ACPI_DISABLE 0xf0
185 static int get_pmsts(VT686PMState
*s
)
187 int64_t d
= acpi_pm_tmr_get_clock();
188 if (d
>= s
->tmr
.overflow_time
) {
189 s
->pmsts
|= ACPI_BITMASK_TIMER_STATUS
;
194 static void pm_update_sci(VT686PMState
*s
)
196 int sci_level
, pmsts
;
198 pmsts
= get_pmsts(s
);
199 sci_level
= (((pmsts
& s
->pmen
) &
200 (RTC_EN
| PWRBTN_EN
| GBL_EN
| TMROF_EN
)) != 0);
201 qemu_set_irq(s
->dev
.irq
[0], sci_level
);
202 /* schedule a timer interruption if needed */
203 acpi_pm_tmr_update(&s
->tmr
, (s
->pmen
& ACPI_BITMASK_TIMER_ENABLE
) &&
204 !(pmsts
& ACPI_BITMASK_TIMER_STATUS
));
207 static void pm_tmr_timer(ACPIPMTimer
*tmr
)
209 VT686PMState
*s
= container_of(tmr
, VT686PMState
, tmr
);
213 static void pm_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
215 VT686PMState
*s
= opaque
;
222 pmsts
= get_pmsts(s
);
223 if (pmsts
& val
& TMROF_EN
) {
224 /* if TMRSTS is reset, then compute the new overflow time */
225 acpi_pm_tmr_calc_overflow_time(&s
->tmr
);
238 s
->pmcntrl
= val
& ~(SUS_EN
);
240 /* change suspend type */
241 sus_typ
= (val
>> 10) & 3;
243 case 0: /* soft power off */
244 qemu_system_shutdown_request();
255 DPRINTF("PM writew port=0x%04x val=0x%02x\n", addr
, val
);
258 static uint32_t pm_ioport_readw(void *opaque
, uint32_t addr
)
260 VT686PMState
*s
= opaque
;
278 DPRINTF("PM readw port=0x%04x val=0x%02x\n", addr
, val
);
282 static void pm_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
285 DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr
, val
);
288 static uint32_t pm_ioport_readl(void *opaque
, uint32_t addr
)
290 VT686PMState
*s
= opaque
;
296 val
= acpi_pm_tmr_get(&s
->tmr
);
302 DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr
, val
);
306 static void pm_io_space_update(VT686PMState
*s
)
310 if (s
->dev
.config
[0x80] & 1) {
311 pm_io_base
= pci_get_long(s
->dev
.config
+ 0x40);
312 pm_io_base
&= 0xffc0;
314 /* XXX: need to improve memory and ioport allocation */
315 DPRINTF("PM: mapping to 0x%x\n", pm_io_base
);
316 register_ioport_write(pm_io_base
, 64, 2, pm_ioport_writew
, s
);
317 register_ioport_read(pm_io_base
, 64, 2, pm_ioport_readw
, s
);
318 register_ioport_write(pm_io_base
, 64, 4, pm_ioport_writel
, s
);
319 register_ioport_read(pm_io_base
, 64, 4, pm_ioport_readl
, s
);
323 static void pm_write_config(PCIDevice
*d
,
324 uint32_t address
, uint32_t val
, int len
)
326 DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x \n",
328 pci_default_write_config(d
, address
, val
, len
);
331 static int vmstate_acpi_post_load(void *opaque
, int version_id
)
333 VT686PMState
*s
= opaque
;
335 pm_io_space_update(s
);
339 static const VMStateDescription vmstate_acpi
= {
340 .name
= "vt82c686b_pm",
342 .minimum_version_id
= 1,
343 .minimum_version_id_old
= 1,
344 .post_load
= vmstate_acpi_post_load
,
345 .fields
= (VMStateField
[]) {
346 VMSTATE_PCI_DEVICE(dev
, VT686PMState
),
347 VMSTATE_UINT16(pmsts
, VT686PMState
),
348 VMSTATE_UINT16(pmen
, VT686PMState
),
349 VMSTATE_UINT16(pmcntrl
, VT686PMState
),
350 VMSTATE_STRUCT(apm
, VT686PMState
, 0, vmstate_apm
, APMState
),
351 VMSTATE_TIMER(tmr
.timer
, VT686PMState
),
352 VMSTATE_INT64(tmr
.overflow_time
, VT686PMState
),
353 VMSTATE_END_OF_LIST()
358 * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
359 * just register a PCI device now, functionalities will be implemented later.
362 static int vt82c686b_ac97_initfn(PCIDevice
*dev
)
364 VT686AC97State
*s
= DO_UPCAST(VT686AC97State
, dev
, dev
);
365 uint8_t *pci_conf
= s
->dev
.config
;
367 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_VIA
);
368 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_VIA_AC97
);
369 pci_config_set_class(pci_conf
, PCI_CLASS_MULTIMEDIA_AUDIO
);
370 pci_config_set_revision(pci_conf
, 0x50);
372 pci_set_word(pci_conf
+ PCI_COMMAND
, PCI_COMMAND_INVALIDATE
|
374 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_CAP_LIST
|
375 PCI_STATUS_DEVSEL_MEDIUM
);
376 pci_set_long(pci_conf
+ PCI_INTERRUPT_PIN
, 0x03);
381 void vt82c686b_ac97_init(PCIBus
*bus
, int devfn
)
385 dev
= pci_create(bus
, devfn
, "VT82C686B_AC97");
386 qdev_init_nofail(&dev
->qdev
);
389 static PCIDeviceInfo via_ac97_info
= {
390 .qdev
.name
= "VT82C686B_AC97",
392 .qdev
.size
= sizeof(VT686AC97State
),
393 .init
= vt82c686b_ac97_initfn
,
396 static void vt82c686b_ac97_register(void)
398 pci_qdev_register(&via_ac97_info
);
401 device_init(vt82c686b_ac97_register
);
403 static int vt82c686b_mc97_initfn(PCIDevice
*dev
)
405 VT686MC97State
*s
= DO_UPCAST(VT686MC97State
, dev
, dev
);
406 uint8_t *pci_conf
= s
->dev
.config
;
408 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_VIA
);
409 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_VIA_MC97
);
410 pci_config_set_class(pci_conf
, PCI_CLASS_COMMUNICATION_OTHER
);
411 pci_config_set_revision(pci_conf
, 0x30);
413 pci_set_word(pci_conf
+ PCI_COMMAND
, PCI_COMMAND_INVALIDATE
|
414 PCI_COMMAND_VGA_PALETTE
);
415 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_DEVSEL_MEDIUM
);
416 pci_set_long(pci_conf
+ PCI_INTERRUPT_PIN
, 0x03);
421 void vt82c686b_mc97_init(PCIBus
*bus
, int devfn
)
425 dev
= pci_create(bus
, devfn
, "VT82C686B_MC97");
426 qdev_init_nofail(&dev
->qdev
);
429 static PCIDeviceInfo via_mc97_info
= {
430 .qdev
.name
= "VT82C686B_MC97",
432 .qdev
.size
= sizeof(VT686MC97State
),
433 .init
= vt82c686b_mc97_initfn
,
436 static void vt82c686b_mc97_register(void)
438 pci_qdev_register(&via_mc97_info
);
441 device_init(vt82c686b_mc97_register
);
443 /* vt82c686 pm init */
444 static int vt82c686b_pm_initfn(PCIDevice
*dev
)
446 VT686PMState
*s
= DO_UPCAST(VT686PMState
, dev
, dev
);
449 pci_conf
= s
->dev
.config
;
450 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_VIA
);
451 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_VIA_ACPI
);
452 pci_config_set_class(pci_conf
, PCI_CLASS_BRIDGE_OTHER
);
453 pci_config_set_revision(pci_conf
, 0x40);
455 pci_set_word(pci_conf
+ PCI_COMMAND
, 0);
456 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_FAST_BACK
|
457 PCI_STATUS_DEVSEL_MEDIUM
);
459 /* 0x48-0x4B is Power Management I/O Base */
460 pci_set_long(pci_conf
+ 0x48, 0x00000001);
462 /* SMB ports:0xeee0~0xeeef */
463 s
->smb_io_base
=((s
->smb_io_base
& 0xfff0) + 0x0);
464 pci_conf
[0x90] = s
->smb_io_base
| 1;
465 pci_conf
[0x91] = s
->smb_io_base
>> 8;
466 pci_conf
[0xd2] = 0x90;
467 register_ioport_write(s
->smb_io_base
, 0xf, 1, smb_ioport_writeb
, &s
->smb
);
468 register_ioport_read(s
->smb_io_base
, 0xf, 1, smb_ioport_readb
, &s
->smb
);
470 apm_init(&s
->apm
, NULL
, s
);
472 acpi_pm_tmr_init(&s
->tmr
, pm_tmr_timer
);
474 pm_smbus_init(&s
->dev
.qdev
, &s
->smb
);
479 i2c_bus
*vt82c686b_pm_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
,
485 dev
= pci_create(bus
, devfn
, "VT82C686B_PM");
486 qdev_prop_set_uint32(&dev
->qdev
, "smb_io_base", smb_io_base
);
488 s
= DO_UPCAST(VT686PMState
, dev
, dev
);
490 qdev_init_nofail(&dev
->qdev
);
495 static PCIDeviceInfo via_pm_info
= {
496 .qdev
.name
= "VT82C686B_PM",
498 .qdev
.size
= sizeof(VT686PMState
),
499 .qdev
.vmsd
= &vmstate_acpi
,
500 .init
= vt82c686b_pm_initfn
,
501 .config_write
= pm_write_config
,
502 .qdev
.props
= (Property
[]) {
503 DEFINE_PROP_UINT32("smb_io_base", VT686PMState
, smb_io_base
, 0),
504 DEFINE_PROP_END_OF_LIST(),
508 static void vt82c686b_pm_register(void)
510 pci_qdev_register(&via_pm_info
);
513 device_init(vt82c686b_pm_register
);
515 static const VMStateDescription vmstate_via
= {
518 .minimum_version_id
= 1,
519 .minimum_version_id_old
= 1,
520 .fields
= (VMStateField
[]) {
521 VMSTATE_PCI_DEVICE(dev
, VT82C686BState
),
522 VMSTATE_END_OF_LIST()
526 /* init the PCI-to-ISA bridge */
527 static int vt82c686b_initfn(PCIDevice
*d
)
533 isa_bus_new(&d
->qdev
);
535 pci_conf
= d
->config
;
536 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_VIA
);
537 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_VIA_ISA_BRIDGE
);
538 pci_config_set_class(pci_conf
, PCI_CLASS_BRIDGE_ISA
);
539 pci_config_set_prog_interface(pci_conf
, 0x0);
540 pci_config_set_revision(pci_conf
,0x40); /* Revision 4.0 */
543 for (i
= 0x00; i
< 0xff; i
++) {
544 if (i
<=0x03 || (i
>=0x08 && i
<=0x3f)) {
549 qemu_register_reset(vt82c686b_reset
, d
);
554 int vt82c686b_init(PCIBus
*bus
, int devfn
)
558 d
= pci_create_simple_multifunction(bus
, devfn
, true, "VT82C686B");
563 static PCIDeviceInfo via_info
= {
564 .qdev
.name
= "VT82C686B",
565 .qdev
.desc
= "ISA bridge",
566 .qdev
.size
= sizeof(VT82C686BState
),
567 .qdev
.vmsd
= &vmstate_via
,
569 .init
= vt82c686b_initfn
,
570 .config_write
= vt82c686b_write_config
,
573 static void vt82c686b_register(void)
575 pci_qdev_register(&via_info
);
577 device_init(vt82c686b_register
);