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tcg-aarch64: Don't handle mov/movi in tcg_out_op
[qemu.git] / linux-user / main.c
blobbe9491bc7db5ae44a336a5437f3c0848b383b7f8
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <stdarg.h>
22 #include <string.h>
23 #include <errno.h>
24 #include <unistd.h>
25 #include <sys/mman.h>
26 #include <sys/syscall.h>
27 #include <sys/resource.h>
28
29 #include "qemu.h"
30 #include "qemu-common.h"
31 #include "qemu/cache-utils.h"
32 #include "cpu.h"
33 #include "tcg.h"
34 #include "qemu/timer.h"
35 #include "qemu/envlist.h"
36 #include "elf.h"
37
38 char *exec_path;
39
40 int singlestep;
41 const char *filename;
42 const char *argv0;
43 int gdbstub_port;
44 envlist_t *envlist;
45 static const char *cpu_model;
46 unsigned long mmap_min_addr;
47 #if defined(CONFIG_USE_GUEST_BASE)
48 unsigned long guest_base;
49 int have_guest_base;
50 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
51 /*
52 * When running 32-on-64 we should make sure we can fit all of the possible
53 * guest address space into a contiguous chunk of virtual host memory.
54 *
55 * This way we will never overlap with our own libraries or binaries or stack
56 * or anything else that QEMU maps.
57 */
58 # ifdef TARGET_MIPS
59 /* MIPS only supports 31 bits of virtual address space for user space */
60 unsigned long reserved_va = 0x77000000;
61 # else
62 unsigned long reserved_va = 0xf7000000;
63 # endif
64 #else
65 unsigned long reserved_va;
66 #endif
67 #endif
68
69 static void usage(void);
70
71 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
72 const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
73
74 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
75 we allocate a bigger stack. Need a better solution, for example
76 by remapping the process stack directly at the right place */
77 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
78
79 void gemu_log(const char *fmt, ...)
80 {
81 va_list ap;
82
83 va_start(ap, fmt);
84 vfprintf(stderr, fmt, ap);
85 va_end(ap);
86 }
87
88 #if defined(TARGET_I386)
89 int cpu_get_pic_interrupt(CPUX86State *env)
90 {
91 return -1;
92 }
93 #endif
94
95 /***********************************************************/
96 /* Helper routines for implementing atomic operations. */
97
98 /* To implement exclusive operations we force all cpus to syncronise.
99 We don't require a full sync, only that no cpus are executing guest code.
100 The alternative is to map target atomic ops onto host equivalents,
101 which requires quite a lot of per host/target work. */
102 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
103 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
104 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
105 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
106 static int pending_cpus;
107
108 /* Make sure everything is in a consistent state for calling fork(). */
109 void fork_start(void)
110 {
111 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
112 pthread_mutex_lock(&exclusive_lock);
113 mmap_fork_start();
114 }
115
116 void fork_end(int child)
117 {
118 mmap_fork_end(child);
119 if (child) {
120 CPUState *cpu, *next_cpu;
121 /* Child processes created by fork() only have a single thread.
122 Discard information about the parent threads. */
123 CPU_FOREACH_SAFE(cpu, next_cpu) {
124 if (cpu != thread_cpu) {
125 QTAILQ_REMOVE(&cpus, thread_cpu, node);
126 }
127 }
128 pending_cpus = 0;
129 pthread_mutex_init(&exclusive_lock, NULL);
130 pthread_mutex_init(&cpu_list_mutex, NULL);
131 pthread_cond_init(&exclusive_cond, NULL);
132 pthread_cond_init(&exclusive_resume, NULL);
133 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
134 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr);
135 } else {
136 pthread_mutex_unlock(&exclusive_lock);
137 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
138 }
139 }
140
141 /* Wait for pending exclusive operations to complete. The exclusive lock
142 must be held. */
143 static inline void exclusive_idle(void)
144 {
145 while (pending_cpus) {
146 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
147 }
148 }
149
150 /* Start an exclusive operation.
151 Must only be called from outside cpu_arm_exec. */
152 static inline void start_exclusive(void)
153 {
154 CPUState *other_cpu;
155
156 pthread_mutex_lock(&exclusive_lock);
157 exclusive_idle();
158
159 pending_cpus = 1;
160 /* Make all other cpus stop executing. */
161 CPU_FOREACH(other_cpu) {
162 if (other_cpu->running) {
163 pending_cpus++;
164 cpu_exit(other_cpu);
165 }
166 }
167 if (pending_cpus > 1) {
168 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
169 }
170 }
171
172 /* Finish an exclusive operation. */
173 static inline void end_exclusive(void)
174 {
175 pending_cpus = 0;
176 pthread_cond_broadcast(&exclusive_resume);
177 pthread_mutex_unlock(&exclusive_lock);
178 }
179
180 /* Wait for exclusive ops to finish, and begin cpu execution. */
181 static inline void cpu_exec_start(CPUState *cpu)
182 {
183 pthread_mutex_lock(&exclusive_lock);
184 exclusive_idle();
185 cpu->running = true;
186 pthread_mutex_unlock(&exclusive_lock);
187 }
188
189 /* Mark cpu as not executing, and release pending exclusive ops. */
190 static inline void cpu_exec_end(CPUState *cpu)
191 {
192 pthread_mutex_lock(&exclusive_lock);
193 cpu->running = false;
194 if (pending_cpus > 1) {
195 pending_cpus--;
196 if (pending_cpus == 1) {
197 pthread_cond_signal(&exclusive_cond);
198 }
199 }
200 exclusive_idle();
201 pthread_mutex_unlock(&exclusive_lock);
202 }
203
204 void cpu_list_lock(void)
205 {
206 pthread_mutex_lock(&cpu_list_mutex);
207 }
208
209 void cpu_list_unlock(void)
210 {
211 pthread_mutex_unlock(&cpu_list_mutex);
212 }
213
214
215 #ifdef TARGET_I386
216 /***********************************************************/
217 /* CPUX86 core interface */
218
219 void cpu_smm_update(CPUX86State *env)
220 {
221 }
222
223 uint64_t cpu_get_tsc(CPUX86State *env)
224 {
225 return cpu_get_real_ticks();
226 }
227
228 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
229 int flags)
230 {
231 unsigned int e1, e2;
232 uint32_t *p;
233 e1 = (addr << 16) | (limit & 0xffff);
234 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
235 e2 |= flags;
236 p = ptr;
237 p[0] = tswap32(e1);
238 p[1] = tswap32(e2);
239 }
240
241 static uint64_t *idt_table;
242 #ifdef TARGET_X86_64
243 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
244 uint64_t addr, unsigned int sel)
245 {
246 uint32_t *p, e1, e2;
247 e1 = (addr & 0xffff) | (sel << 16);
248 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
249 p = ptr;
250 p[0] = tswap32(e1);
251 p[1] = tswap32(e2);
252 p[2] = tswap32(addr >> 32);
253 p[3] = 0;
254 }
255 /* only dpl matters as we do only user space emulation */
256 static void set_idt(int n, unsigned int dpl)
257 {
258 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
259 }
260 #else
261 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
262 uint32_t addr, unsigned int sel)
263 {
264 uint32_t *p, e1, e2;
265 e1 = (addr & 0xffff) | (sel << 16);
266 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
267 p = ptr;
268 p[0] = tswap32(e1);
269 p[1] = tswap32(e2);
270 }
271
272 /* only dpl matters as we do only user space emulation */
273 static void set_idt(int n, unsigned int dpl)
274 {
275 set_gate(idt_table + n, 0, dpl, 0, 0);
276 }
277 #endif
278
279 void cpu_loop(CPUX86State *env)
280 {
281 CPUState *cs = CPU(x86_env_get_cpu(env));
282 int trapnr;
283 abi_ulong pc;
284 target_siginfo_t info;
285
286 for(;;) {
287 trapnr = cpu_x86_exec(env);
288 switch(trapnr) {
289 case 0x80:
290 /* linux syscall from int $0x80 */
291 env->regs[R_EAX] = do_syscall(env,
292 env->regs[R_EAX],
293 env->regs[R_EBX],
294 env->regs[R_ECX],
295 env->regs[R_EDX],
296 env->regs[R_ESI],
297 env->regs[R_EDI],
298 env->regs[R_EBP],
299 0, 0);
300 break;
301 #ifndef TARGET_ABI32
302 case EXCP_SYSCALL:
303 /* linux syscall from syscall instruction */
304 env->regs[R_EAX] = do_syscall(env,
305 env->regs[R_EAX],
306 env->regs[R_EDI],
307 env->regs[R_ESI],
308 env->regs[R_EDX],
309 env->regs[10],
310 env->regs[8],
311 env->regs[9],
312 0, 0);
313 env->eip = env->exception_next_eip;
314 break;
315 #endif
316 case EXCP0B_NOSEG:
317 case EXCP0C_STACK:
318 info.si_signo = SIGBUS;
319 info.si_errno = 0;
320 info.si_code = TARGET_SI_KERNEL;
321 info._sifields._sigfault._addr = 0;
322 queue_signal(env, info.si_signo, &info);
323 break;
324 case EXCP0D_GPF:
325 /* XXX: potential problem if ABI32 */
326 #ifndef TARGET_X86_64
327 if (env->eflags & VM_MASK) {
328 handle_vm86_fault(env);
329 } else
330 #endif
331 {
332 info.si_signo = SIGSEGV;
333 info.si_errno = 0;
334 info.si_code = TARGET_SI_KERNEL;
335 info._sifields._sigfault._addr = 0;
336 queue_signal(env, info.si_signo, &info);
337 }
338 break;
339 case EXCP0E_PAGE:
340 info.si_signo = SIGSEGV;
341 info.si_errno = 0;
342 if (!(env->error_code & 1))
343 info.si_code = TARGET_SEGV_MAPERR;
344 else
345 info.si_code = TARGET_SEGV_ACCERR;
346 info._sifields._sigfault._addr = env->cr[2];
347 queue_signal(env, info.si_signo, &info);
348 break;
349 case EXCP00_DIVZ:
350 #ifndef TARGET_X86_64
351 if (env->eflags & VM_MASK) {
352 handle_vm86_trap(env, trapnr);
353 } else
354 #endif
355 {
356 /* division by zero */
357 info.si_signo = SIGFPE;
358 info.si_errno = 0;
359 info.si_code = TARGET_FPE_INTDIV;
360 info._sifields._sigfault._addr = env->eip;
361 queue_signal(env, info.si_signo, &info);
362 }
363 break;
364 case EXCP01_DB:
365 case EXCP03_INT3:
366 #ifndef TARGET_X86_64
367 if (env->eflags & VM_MASK) {
368 handle_vm86_trap(env, trapnr);
369 } else
370 #endif
371 {
372 info.si_signo = SIGTRAP;
373 info.si_errno = 0;
374 if (trapnr == EXCP01_DB) {
375 info.si_code = TARGET_TRAP_BRKPT;
376 info._sifields._sigfault._addr = env->eip;
377 } else {
378 info.si_code = TARGET_SI_KERNEL;
379 info._sifields._sigfault._addr = 0;
380 }
381 queue_signal(env, info.si_signo, &info);
382 }
383 break;
384 case EXCP04_INTO:
385 case EXCP05_BOUND:
386 #ifndef TARGET_X86_64
387 if (env->eflags & VM_MASK) {
388 handle_vm86_trap(env, trapnr);
389 } else
390 #endif
391 {
392 info.si_signo = SIGSEGV;
393 info.si_errno = 0;
394 info.si_code = TARGET_SI_KERNEL;
395 info._sifields._sigfault._addr = 0;
396 queue_signal(env, info.si_signo, &info);
397 }
398 break;
399 case EXCP06_ILLOP:
400 info.si_signo = SIGILL;
401 info.si_errno = 0;
402 info.si_code = TARGET_ILL_ILLOPN;
403 info._sifields._sigfault._addr = env->eip;
404 queue_signal(env, info.si_signo, &info);
405 break;
406 case EXCP_INTERRUPT:
407 /* just indicate that signals should be handled asap */
408 break;
409 case EXCP_DEBUG:
410 {
411 int sig;
412
413 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
414 if (sig)
415 {
416 info.si_signo = sig;
417 info.si_errno = 0;
418 info.si_code = TARGET_TRAP_BRKPT;
419 queue_signal(env, info.si_signo, &info);
420 }
421 }
422 break;
423 default:
424 pc = env->segs[R_CS].base + env->eip;
425 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
426 (long)pc, trapnr);
427 abort();
428 }
429 process_pending_signals(env);
430 }
431 }
432 #endif
433
434 #ifdef TARGET_ARM
435
436 #define get_user_code_u32(x, gaddr, doswap) \
437 ({ abi_long __r = get_user_u32((x), (gaddr)); \
438 if (!__r && (doswap)) { \
439 (x) = bswap32(x); \
440 } \
441 __r; \
442 })
443
444 #define get_user_code_u16(x, gaddr, doswap) \
445 ({ abi_long __r = get_user_u16((x), (gaddr)); \
446 if (!__r && (doswap)) { \
447 (x) = bswap16(x); \
448 } \
449 __r; \
450 })
451
452 #ifdef TARGET_ABI32
453 /* Commpage handling -- there is no commpage for AArch64 */
454
455 /*
456 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
457 * Input:
458 * r0 = pointer to oldval
459 * r1 = pointer to newval
460 * r2 = pointer to target value
461 *
462 * Output:
463 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
464 * C set if *ptr was changed, clear if no exchange happened
465 *
466 * Note segv's in kernel helpers are a bit tricky, we can set the
467 * data address sensibly but the PC address is just the entry point.
468 */
469 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
470 {
471 uint64_t oldval, newval, val;
472 uint32_t addr, cpsr;
473 target_siginfo_t info;
474
475 /* Based on the 32 bit code in do_kernel_trap */
476
477 /* XXX: This only works between threads, not between processes.
478 It's probably possible to implement this with native host
479 operations. However things like ldrex/strex are much harder so
480 there's not much point trying. */
481 start_exclusive();
482 cpsr = cpsr_read(env);
483 addr = env->regs[2];
484
485 if (get_user_u64(oldval, env->regs[0])) {
486 env->cp15.c6_data = env->regs[0];
487 goto segv;
488 };
489
490 if (get_user_u64(newval, env->regs[1])) {
491 env->cp15.c6_data = env->regs[1];
492 goto segv;
493 };
494
495 if (get_user_u64(val, addr)) {
496 env->cp15.c6_data = addr;
497 goto segv;
498 }
499
500 if (val == oldval) {
501 val = newval;
502
503 if (put_user_u64(val, addr)) {
504 env->cp15.c6_data = addr;
505 goto segv;
506 };
507
508 env->regs[0] = 0;
509 cpsr |= CPSR_C;
510 } else {
511 env->regs[0] = -1;
512 cpsr &= ~CPSR_C;
513 }
514 cpsr_write(env, cpsr, CPSR_C);
515 end_exclusive();
516 return;
517
518 segv:
519 end_exclusive();
520 /* We get the PC of the entry address - which is as good as anything,
521 on a real kernel what you get depends on which mode it uses. */
522 info.si_signo = SIGSEGV;
523 info.si_errno = 0;
524 /* XXX: check env->error_code */
525 info.si_code = TARGET_SEGV_MAPERR;
526 info._sifields._sigfault._addr = env->cp15.c6_data;
527 queue_signal(env, info.si_signo, &info);
528
529 end_exclusive();
530 }
531
532 /* Handle a jump to the kernel code page. */
533 static int
534 do_kernel_trap(CPUARMState *env)
535 {
536 uint32_t addr;
537 uint32_t cpsr;
538 uint32_t val;
539
540 switch (env->regs[15]) {
541 case 0xffff0fa0: /* __kernel_memory_barrier */
542 /* ??? No-op. Will need to do better for SMP. */
543 break;
544 case 0xffff0fc0: /* __kernel_cmpxchg */
545 /* XXX: This only works between threads, not between processes.
546 It's probably possible to implement this with native host
547 operations. However things like ldrex/strex are much harder so
548 there's not much point trying. */
549 start_exclusive();
550 cpsr = cpsr_read(env);
551 addr = env->regs[2];
552 /* FIXME: This should SEGV if the access fails. */
553 if (get_user_u32(val, addr))
554 val = ~env->regs[0];
555 if (val == env->regs[0]) {
556 val = env->regs[1];
557 /* FIXME: Check for segfaults. */
558 put_user_u32(val, addr);
559 env->regs[0] = 0;
560 cpsr |= CPSR_C;
561 } else {
562 env->regs[0] = -1;
563 cpsr &= ~CPSR_C;
564 }
565 cpsr_write(env, cpsr, CPSR_C);
566 end_exclusive();
567 break;
568 case 0xffff0fe0: /* __kernel_get_tls */
569 env->regs[0] = env->cp15.tpidrro_el0;
570 break;
571 case 0xffff0f60: /* __kernel_cmpxchg64 */
572 arm_kernel_cmpxchg64_helper(env);
573 break;
574
575 default:
576 return 1;
577 }
578 /* Jump back to the caller. */
579 addr = env->regs[14];
580 if (addr & 1) {
581 env->thumb = 1;
582 addr &= ~1;
583 }
584 env->regs[15] = addr;
585
586 return 0;
587 }
588
589 /* Store exclusive handling for AArch32 */
590 static int do_strex(CPUARMState *env)
591 {
592 uint64_t val;
593 int size;
594 int rc = 1;
595 int segv = 0;
596 uint32_t addr;
597 start_exclusive();
598 if (env->exclusive_addr != env->exclusive_test) {
599 goto fail;
600 }
601 /* We know we're always AArch32 so the address is in uint32_t range
602 * unless it was the -1 exclusive-monitor-lost value (which won't
603 * match exclusive_test above).
604 */
605 assert(extract64(env->exclusive_addr, 32, 32) == 0);
606 addr = env->exclusive_addr;
607 size = env->exclusive_info & 0xf;
608 switch (size) {
609 case 0:
610 segv = get_user_u8(val, addr);
611 break;
612 case 1:
613 segv = get_user_u16(val, addr);
614 break;
615 case 2:
616 case 3:
617 segv = get_user_u32(val, addr);
618 break;
619 default:
620 abort();
621 }
622 if (segv) {
623 env->cp15.c6_data = addr;
624 goto done;
625 }
626 if (size == 3) {
627 uint32_t valhi;
628 segv = get_user_u32(valhi, addr + 4);
629 if (segv) {
630 env->cp15.c6_data = addr + 4;
631 goto done;
632 }
633 val = deposit64(val, 32, 32, valhi);
634 }
635 if (val != env->exclusive_val) {
636 goto fail;
637 }
638
639 val = env->regs[(env->exclusive_info >> 8) & 0xf];
640 switch (size) {
641 case 0:
642 segv = put_user_u8(val, addr);
643 break;
644 case 1:
645 segv = put_user_u16(val, addr);
646 break;
647 case 2:
648 case 3:
649 segv = put_user_u32(val, addr);
650 break;
651 }
652 if (segv) {
653 env->cp15.c6_data = addr;
654 goto done;
655 }
656 if (size == 3) {
657 val = env->regs[(env->exclusive_info >> 12) & 0xf];
658 segv = put_user_u32(val, addr + 4);
659 if (segv) {
660 env->cp15.c6_data = addr + 4;
661 goto done;
662 }
663 }
664 rc = 0;
665 fail:
666 env->regs[15] += 4;
667 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
668 done:
669 end_exclusive();
670 return segv;
671 }
672
673 void cpu_loop(CPUARMState *env)
674 {
675 CPUState *cs = CPU(arm_env_get_cpu(env));
676 int trapnr;
677 unsigned int n, insn;
678 target_siginfo_t info;
679 uint32_t addr;
680
681 for(;;) {
682 cpu_exec_start(cs);
683 trapnr = cpu_arm_exec(env);
684 cpu_exec_end(cs);
685 switch(trapnr) {
686 case EXCP_UDEF:
687 {
688 TaskState *ts = env->opaque;
689 uint32_t opcode;
690 int rc;
691
692 /* we handle the FPU emulation here, as Linux */
693 /* we get the opcode */
694 /* FIXME - what to do if get_user() fails? */
695 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
696
697 rc = EmulateAll(opcode, &ts->fpa, env);
698 if (rc == 0) { /* illegal instruction */
699 info.si_signo = SIGILL;
700 info.si_errno = 0;
701 info.si_code = TARGET_ILL_ILLOPN;
702 info._sifields._sigfault._addr = env->regs[15];
703 queue_signal(env, info.si_signo, &info);
704 } else if (rc < 0) { /* FP exception */
705 int arm_fpe=0;
706
707 /* translate softfloat flags to FPSR flags */
708 if (-rc & float_flag_invalid)
709 arm_fpe |= BIT_IOC;
710 if (-rc & float_flag_divbyzero)
711 arm_fpe |= BIT_DZC;
712 if (-rc & float_flag_overflow)
713 arm_fpe |= BIT_OFC;
714 if (-rc & float_flag_underflow)
715 arm_fpe |= BIT_UFC;
716 if (-rc & float_flag_inexact)
717 arm_fpe |= BIT_IXC;
718
719 FPSR fpsr = ts->fpa.fpsr;
720 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
721
722 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
723 info.si_signo = SIGFPE;
724 info.si_errno = 0;
725
726 /* ordered by priority, least first */
727 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
728 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
729 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
730 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
731 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
732
733 info._sifields._sigfault._addr = env->regs[15];
734 queue_signal(env, info.si_signo, &info);
735 } else {
736 env->regs[15] += 4;
737 }
738
739 /* accumulate unenabled exceptions */
740 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
741 fpsr |= BIT_IXC;
742 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
743 fpsr |= BIT_UFC;
744 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
745 fpsr |= BIT_OFC;
746 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
747 fpsr |= BIT_DZC;
748 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
749 fpsr |= BIT_IOC;
750 ts->fpa.fpsr=fpsr;
751 } else { /* everything OK */
752 /* increment PC */
753 env->regs[15] += 4;
754 }
755 }
756 break;
757 case EXCP_SWI:
758 case EXCP_BKPT:
759 {
760 env->eabi = 1;
761 /* system call */
762 if (trapnr == EXCP_BKPT) {
763 if (env->thumb) {
764 /* FIXME - what to do if get_user() fails? */
765 get_user_code_u16(insn, env->regs[15], env->bswap_code);
766 n = insn & 0xff;
767 env->regs[15] += 2;
768 } else {
769 /* FIXME - what to do if get_user() fails? */
770 get_user_code_u32(insn, env->regs[15], env->bswap_code);
771 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
772 env->regs[15] += 4;
773 }
774 } else {
775 if (env->thumb) {
776 /* FIXME - what to do if get_user() fails? */
777 get_user_code_u16(insn, env->regs[15] - 2,
778 env->bswap_code);
779 n = insn & 0xff;
780 } else {
781 /* FIXME - what to do if get_user() fails? */
782 get_user_code_u32(insn, env->regs[15] - 4,
783 env->bswap_code);
784 n = insn & 0xffffff;
785 }
786 }
787
788 if (n == ARM_NR_cacheflush) {
789 /* nop */
790 } else if (n == ARM_NR_semihosting
791 || n == ARM_NR_thumb_semihosting) {
792 env->regs[0] = do_arm_semihosting (env);
793 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
794 /* linux syscall */
795 if (env->thumb || n == 0) {
796 n = env->regs[7];
797 } else {
798 n -= ARM_SYSCALL_BASE;
799 env->eabi = 0;
800 }
801 if ( n > ARM_NR_BASE) {
802 switch (n) {
803 case ARM_NR_cacheflush:
804 /* nop */
805 break;
806 case ARM_NR_set_tls:
807 cpu_set_tls(env, env->regs[0]);
808 env->regs[0] = 0;
809 break;
810 default:
811 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
812 n);
813 env->regs[0] = -TARGET_ENOSYS;
814 break;
815 }
816 } else {
817 env->regs[0] = do_syscall(env,
818 n,
819 env->regs[0],
820 env->regs[1],
821 env->regs[2],
822 env->regs[3],
823 env->regs[4],
824 env->regs[5],
825 0, 0);
826 }
827 } else {
828 goto error;
829 }
830 }
831 break;
832 case EXCP_INTERRUPT:
833 /* just indicate that signals should be handled asap */
834 break;
835 case EXCP_PREFETCH_ABORT:
836 addr = env->cp15.c6_insn;
837 goto do_segv;
838 case EXCP_DATA_ABORT:
839 addr = env->cp15.c6_data;
840 do_segv:
841 {
842 info.si_signo = SIGSEGV;
843 info.si_errno = 0;
844 /* XXX: check env->error_code */
845 info.si_code = TARGET_SEGV_MAPERR;
846 info._sifields._sigfault._addr = addr;
847 queue_signal(env, info.si_signo, &info);
848 }
849 break;
850 case EXCP_DEBUG:
851 {
852 int sig;
853
854 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
855 if (sig)
856 {
857 info.si_signo = sig;
858 info.si_errno = 0;
859 info.si_code = TARGET_TRAP_BRKPT;
860 queue_signal(env, info.si_signo, &info);
861 }
862 }
863 break;
864 case EXCP_KERNEL_TRAP:
865 if (do_kernel_trap(env))
866 goto error;
867 break;
868 case EXCP_STREX:
869 if (do_strex(env)) {
870 addr = env->cp15.c6_data;
871 goto do_segv;
872 }
873 break;
874 default:
875 error:
876 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
877 trapnr);
878 cpu_dump_state(cs, stderr, fprintf, 0);
879 abort();
880 }
881 process_pending_signals(env);
882 }
883 }
884
885 #else
886
887 /*
888 * Handle AArch64 store-release exclusive
889 *
890 * rs = gets the status result of store exclusive
891 * rt = is the register that is stored
892 * rt2 = is the second register store (in STP)
893 *
894 */
895 static int do_strex_a64(CPUARMState *env)
896 {
897 uint64_t val;
898 int size;
899 bool is_pair;
900 int rc = 1;
901 int segv = 0;
902 uint64_t addr;
903 int rs, rt, rt2;
904
905 start_exclusive();
906 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
907 size = extract32(env->exclusive_info, 0, 2);
908 is_pair = extract32(env->exclusive_info, 2, 1);
909 rs = extract32(env->exclusive_info, 4, 5);
910 rt = extract32(env->exclusive_info, 9, 5);
911 rt2 = extract32(env->exclusive_info, 14, 5);
912
913 addr = env->exclusive_addr;
914
915 if (addr != env->exclusive_test) {
916 goto finish;
917 }
918
919 switch (size) {
920 case 0:
921 segv = get_user_u8(val, addr);
922 break;
923 case 1:
924 segv = get_user_u16(val, addr);
925 break;
926 case 2:
927 segv = get_user_u32(val, addr);
928 break;
929 case 3:
930 segv = get_user_u64(val, addr);
931 break;
932 default:
933 abort();
934 }
935 if (segv) {
936 env->cp15.c6_data = addr;
937 goto error;
938 }
939 if (val != env->exclusive_val) {
940 goto finish;
941 }
942 if (is_pair) {
943 if (size == 2) {
944 segv = get_user_u32(val, addr + 4);
945 } else {
946 segv = get_user_u64(val, addr + 8);
947 }
948 if (segv) {
949 env->cp15.c6_data = addr + (size == 2 ? 4 : 8);
950 goto error;
951 }
952 if (val != env->exclusive_high) {
953 goto finish;
954 }
955 }
956 /* handle the zero register */
957 val = rt == 31 ? 0 : env->xregs[rt];
958 switch (size) {
959 case 0:
960 segv = put_user_u8(val, addr);
961 break;
962 case 1:
963 segv = put_user_u16(val, addr);
964 break;
965 case 2:
966 segv = put_user_u32(val, addr);
967 break;
968 case 3:
969 segv = put_user_u64(val, addr);
970 break;
971 }
972 if (segv) {
973 goto error;
974 }
975 if (is_pair) {
976 /* handle the zero register */
977 val = rt2 == 31 ? 0 : env->xregs[rt2];
978 if (size == 2) {
979 segv = put_user_u32(val, addr + 4);
980 } else {
981 segv = put_user_u64(val, addr + 8);
982 }
983 if (segv) {
984 env->cp15.c6_data = addr + (size == 2 ? 4 : 8);
985 goto error;
986 }
987 }
988 rc = 0;
989 finish:
990 env->pc += 4;
991 /* rs == 31 encodes a write to the ZR, thus throwing away
992 * the status return. This is rather silly but valid.
993 */
994 if (rs < 31) {
995 env->xregs[rs] = rc;
996 }
997 error:
998 /* instruction faulted, PC does not advance */
999 /* either way a strex releases any exclusive lock we have */
1000 env->exclusive_addr = -1;
1001 end_exclusive();
1002 return segv;
1003 }
1004
1005 /* AArch64 main loop */
1006 void cpu_loop(CPUARMState *env)
1007 {
1008 CPUState *cs = CPU(arm_env_get_cpu(env));
1009 int trapnr, sig;
1010 target_siginfo_t info;
1011 uint32_t addr;
1012
1013 for (;;) {
1014 cpu_exec_start(cs);
1015 trapnr = cpu_arm_exec(env);
1016 cpu_exec_end(cs);
1017
1018 switch (trapnr) {
1019 case EXCP_SWI:
1020 env->xregs[0] = do_syscall(env,
1021 env->xregs[8],
1022 env->xregs[0],
1023 env->xregs[1],
1024 env->xregs[2],
1025 env->xregs[3],
1026 env->xregs[4],
1027 env->xregs[5],
1028 0, 0);
1029 break;
1030 case EXCP_INTERRUPT:
1031 /* just indicate that signals should be handled asap */
1032 break;
1033 case EXCP_UDEF:
1034 info.si_signo = SIGILL;
1035 info.si_errno = 0;
1036 info.si_code = TARGET_ILL_ILLOPN;
1037 info._sifields._sigfault._addr = env->pc;
1038 queue_signal(env, info.si_signo, &info);
1039 break;
1040 case EXCP_PREFETCH_ABORT:
1041 addr = env->cp15.c6_insn;
1042 goto do_segv;
1043 case EXCP_DATA_ABORT:
1044 addr = env->cp15.c6_data;
1045 do_segv:
1046 info.si_signo = SIGSEGV;
1047 info.si_errno = 0;
1048 /* XXX: check env->error_code */
1049 info.si_code = TARGET_SEGV_MAPERR;
1050 info._sifields._sigfault._addr = addr;
1051 queue_signal(env, info.si_signo, &info);
1052 break;
1053 case EXCP_DEBUG:
1054 case EXCP_BKPT:
1055 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1056 if (sig) {
1057 info.si_signo = sig;
1058 info.si_errno = 0;
1059 info.si_code = TARGET_TRAP_BRKPT;
1060 queue_signal(env, info.si_signo, &info);
1061 }
1062 break;
1063 case EXCP_STREX:
1064 if (do_strex_a64(env)) {
1065 addr = env->cp15.c6_data;
1066 goto do_segv;
1067 }
1068 break;
1069 default:
1070 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1071 trapnr);
1072 cpu_dump_state(cs, stderr, fprintf, 0);
1073 abort();
1074 }
1075 process_pending_signals(env);
1076 /* Exception return on AArch64 always clears the exclusive monitor,
1077 * so any return to running guest code implies this.
1078 * A strex (successful or otherwise) also clears the monitor, so
1079 * we don't need to specialcase EXCP_STREX.
1080 */
1081 env->exclusive_addr = -1;
1082 }
1083 }
1084 #endif /* ndef TARGET_ABI32 */
1085
1086 #endif
1087
1088 #ifdef TARGET_UNICORE32
1089
1090 void cpu_loop(CPUUniCore32State *env)
1091 {
1092 CPUState *cs = CPU(uc32_env_get_cpu(env));
1093 int trapnr;
1094 unsigned int n, insn;
1095 target_siginfo_t info;
1096
1097 for (;;) {
1098 cpu_exec_start(cs);
1099 trapnr = uc32_cpu_exec(env);
1100 cpu_exec_end(cs);
1101 switch (trapnr) {
1102 case UC32_EXCP_PRIV:
1103 {
1104 /* system call */
1105 get_user_u32(insn, env->regs[31] - 4);
1106 n = insn & 0xffffff;
1107
1108 if (n >= UC32_SYSCALL_BASE) {
1109 /* linux syscall */
1110 n -= UC32_SYSCALL_BASE;
1111 if (n == UC32_SYSCALL_NR_set_tls) {
1112 cpu_set_tls(env, env->regs[0]);
1113 env->regs[0] = 0;
1114 } else {
1115 env->regs[0] = do_syscall(env,
1116 n,
1117 env->regs[0],
1118 env->regs[1],
1119 env->regs[2],
1120 env->regs[3],
1121 env->regs[4],
1122 env->regs[5],
1123 0, 0);
1124 }
1125 } else {
1126 goto error;
1127 }
1128 }
1129 break;
1130 case UC32_EXCP_DTRAP:
1131 case UC32_EXCP_ITRAP:
1132 info.si_signo = SIGSEGV;
1133 info.si_errno = 0;
1134 /* XXX: check env->error_code */
1135 info.si_code = TARGET_SEGV_MAPERR;
1136 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1137 queue_signal(env, info.si_signo, &info);
1138 break;
1139 case EXCP_INTERRUPT:
1140 /* just indicate that signals should be handled asap */
1141 break;
1142 case EXCP_DEBUG:
1143 {
1144 int sig;
1145
1146 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1147 if (sig) {
1148 info.si_signo = sig;
1149 info.si_errno = 0;
1150 info.si_code = TARGET_TRAP_BRKPT;
1151 queue_signal(env, info.si_signo, &info);
1152 }
1153 }
1154 break;
1155 default:
1156 goto error;
1157 }
1158 process_pending_signals(env);
1159 }
1160
1161 error:
1162 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1163 cpu_dump_state(cs, stderr, fprintf, 0);
1164 abort();
1165 }
1166 #endif
1167
1168 #ifdef TARGET_SPARC
1169 #define SPARC64_STACK_BIAS 2047
1170
1171 //#define DEBUG_WIN
1172
1173 /* WARNING: dealing with register windows _is_ complicated. More info
1174 can be found at http://www.sics.se/~psm/sparcstack.html */
1175 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1176 {
1177 index = (index + cwp * 16) % (16 * env->nwindows);
1178 /* wrap handling : if cwp is on the last window, then we use the
1179 registers 'after' the end */
1180 if (index < 8 && env->cwp == env->nwindows - 1)
1181 index += 16 * env->nwindows;
1182 return index;
1183 }
1184
1185 /* save the register window 'cwp1' */
1186 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1187 {
1188 unsigned int i;
1189 abi_ulong sp_ptr;
1190
1191 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1192 #ifdef TARGET_SPARC64
1193 if (sp_ptr & 3)
1194 sp_ptr += SPARC64_STACK_BIAS;
1195 #endif
1196 #if defined(DEBUG_WIN)
1197 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1198 sp_ptr, cwp1);
1199 #endif
1200 for(i = 0; i < 16; i++) {
1201 /* FIXME - what to do if put_user() fails? */
1202 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1203 sp_ptr += sizeof(abi_ulong);
1204 }
1205 }
1206
1207 static void save_window(CPUSPARCState *env)
1208 {
1209 #ifndef TARGET_SPARC64
1210 unsigned int new_wim;
1211 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1212 ((1LL << env->nwindows) - 1);
1213 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1214 env->wim = new_wim;
1215 #else
1216 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1217 env->cansave++;
1218 env->canrestore--;
1219 #endif
1220 }
1221
1222 static void restore_window(CPUSPARCState *env)
1223 {
1224 #ifndef TARGET_SPARC64
1225 unsigned int new_wim;
1226 #endif
1227 unsigned int i, cwp1;
1228 abi_ulong sp_ptr;
1229
1230 #ifndef TARGET_SPARC64
1231 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1232 ((1LL << env->nwindows) - 1);
1233 #endif
1234
1235 /* restore the invalid window */
1236 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1237 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1238 #ifdef TARGET_SPARC64
1239 if (sp_ptr & 3)
1240 sp_ptr += SPARC64_STACK_BIAS;
1241 #endif
1242 #if defined(DEBUG_WIN)
1243 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1244 sp_ptr, cwp1);
1245 #endif
1246 for(i = 0; i < 16; i++) {
1247 /* FIXME - what to do if get_user() fails? */
1248 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1249 sp_ptr += sizeof(abi_ulong);
1250 }
1251 #ifdef TARGET_SPARC64
1252 env->canrestore++;
1253 if (env->cleanwin < env->nwindows - 1)
1254 env->cleanwin++;
1255 env->cansave--;
1256 #else
1257 env->wim = new_wim;
1258 #endif
1259 }
1260
1261 static void flush_windows(CPUSPARCState *env)
1262 {
1263 int offset, cwp1;
1264
1265 offset = 1;
1266 for(;;) {
1267 /* if restore would invoke restore_window(), then we can stop */
1268 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1269 #ifndef TARGET_SPARC64
1270 if (env->wim & (1 << cwp1))
1271 break;
1272 #else
1273 if (env->canrestore == 0)
1274 break;
1275 env->cansave++;
1276 env->canrestore--;
1277 #endif
1278 save_window_offset(env, cwp1);
1279 offset++;
1280 }
1281 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1282 #ifndef TARGET_SPARC64
1283 /* set wim so that restore will reload the registers */
1284 env->wim = 1 << cwp1;
1285 #endif
1286 #if defined(DEBUG_WIN)
1287 printf("flush_windows: nb=%d\n", offset - 1);
1288 #endif
1289 }
1290
1291 void cpu_loop (CPUSPARCState *env)
1292 {
1293 CPUState *cs = CPU(sparc_env_get_cpu(env));
1294 int trapnr;
1295 abi_long ret;
1296 target_siginfo_t info;
1297
1298 while (1) {
1299 trapnr = cpu_sparc_exec (env);
1300
1301 /* Compute PSR before exposing state. */
1302 if (env->cc_op != CC_OP_FLAGS) {
1303 cpu_get_psr(env);
1304 }
1305
1306 switch (trapnr) {
1307 #ifndef TARGET_SPARC64
1308 case 0x88:
1309 case 0x90:
1310 #else
1311 case 0x110:
1312 case 0x16d:
1313 #endif
1314 ret = do_syscall (env, env->gregs[1],
1315 env->regwptr[0], env->regwptr[1],
1316 env->regwptr[2], env->regwptr[3],
1317 env->regwptr[4], env->regwptr[5],
1318 0, 0);
1319 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1320 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1321 env->xcc |= PSR_CARRY;
1322 #else
1323 env->psr |= PSR_CARRY;
1324 #endif
1325 ret = -ret;
1326 } else {
1327 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1328 env->xcc &= ~PSR_CARRY;
1329 #else
1330 env->psr &= ~PSR_CARRY;
1331 #endif
1332 }
1333 env->regwptr[0] = ret;
1334 /* next instruction */
1335 env->pc = env->npc;
1336 env->npc = env->npc + 4;
1337 break;
1338 case 0x83: /* flush windows */
1339 #ifdef TARGET_ABI32
1340 case 0x103:
1341 #endif
1342 flush_windows(env);
1343 /* next instruction */
1344 env->pc = env->npc;
1345 env->npc = env->npc + 4;
1346 break;
1347 #ifndef TARGET_SPARC64
1348 case TT_WIN_OVF: /* window overflow */
1349 save_window(env);
1350 break;
1351 case TT_WIN_UNF: /* window underflow */
1352 restore_window(env);
1353 break;
1354 case TT_TFAULT:
1355 case TT_DFAULT:
1356 {
1357 info.si_signo = TARGET_SIGSEGV;
1358 info.si_errno = 0;
1359 /* XXX: check env->error_code */
1360 info.si_code = TARGET_SEGV_MAPERR;
1361 info._sifields._sigfault._addr = env->mmuregs[4];
1362 queue_signal(env, info.si_signo, &info);
1363 }
1364 break;
1365 #else
1366 case TT_SPILL: /* window overflow */
1367 save_window(env);
1368 break;
1369 case TT_FILL: /* window underflow */
1370 restore_window(env);
1371 break;
1372 case TT_TFAULT:
1373 case TT_DFAULT:
1374 {
1375 info.si_signo = TARGET_SIGSEGV;
1376 info.si_errno = 0;
1377 /* XXX: check env->error_code */
1378 info.si_code = TARGET_SEGV_MAPERR;
1379 if (trapnr == TT_DFAULT)
1380 info._sifields._sigfault._addr = env->dmmuregs[4];
1381 else
1382 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1383 queue_signal(env, info.si_signo, &info);
1384 }
1385 break;
1386 #ifndef TARGET_ABI32
1387 case 0x16e:
1388 flush_windows(env);
1389 sparc64_get_context(env);
1390 break;
1391 case 0x16f:
1392 flush_windows(env);
1393 sparc64_set_context(env);
1394 break;
1395 #endif
1396 #endif
1397 case EXCP_INTERRUPT:
1398 /* just indicate that signals should be handled asap */
1399 break;
1400 case TT_ILL_INSN:
1401 {
1402 info.si_signo = TARGET_SIGILL;
1403 info.si_errno = 0;
1404 info.si_code = TARGET_ILL_ILLOPC;
1405 info._sifields._sigfault._addr = env->pc;
1406 queue_signal(env, info.si_signo, &info);
1407 }
1408 break;
1409 case EXCP_DEBUG:
1410 {
1411 int sig;
1412
1413 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1414 if (sig)
1415 {
1416 info.si_signo = sig;
1417 info.si_errno = 0;
1418 info.si_code = TARGET_TRAP_BRKPT;
1419 queue_signal(env, info.si_signo, &info);
1420 }
1421 }
1422 break;
1423 default:
1424 printf ("Unhandled trap: 0x%x\n", trapnr);
1425 cpu_dump_state(cs, stderr, fprintf, 0);
1426 exit (1);
1427 }
1428 process_pending_signals (env);
1429 }
1430 }
1431
1432 #endif
1433
1434 #ifdef TARGET_PPC
1435 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1436 {
1437 /* TO FIX */
1438 return 0;
1439 }
1440
1441 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1442 {
1443 return cpu_ppc_get_tb(env);
1444 }
1445
1446 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1447 {
1448 return cpu_ppc_get_tb(env) >> 32;
1449 }
1450
1451 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1452 {
1453 return cpu_ppc_get_tb(env);
1454 }
1455
1456 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1457 {
1458 return cpu_ppc_get_tb(env) >> 32;
1459 }
1460
1461 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1462 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1463
1464 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1465 {
1466 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1467 }
1468
1469 /* XXX: to be fixed */
1470 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1471 {
1472 return -1;
1473 }
1474
1475 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1476 {
1477 return -1;
1478 }
1479
1480 #define EXCP_DUMP(env, fmt, ...) \
1481 do { \
1482 CPUState *cs = ENV_GET_CPU(env); \
1483 fprintf(stderr, fmt , ## __VA_ARGS__); \
1484 cpu_dump_state(cs, stderr, fprintf, 0); \
1485 qemu_log(fmt, ## __VA_ARGS__); \
1486 if (qemu_log_enabled()) { \
1487 log_cpu_state(cs, 0); \
1488 } \
1489 } while (0)
1490
1491 static int do_store_exclusive(CPUPPCState *env)
1492 {
1493 target_ulong addr;
1494 target_ulong page_addr;
1495 target_ulong val, val2 __attribute__((unused));
1496 int flags;
1497 int segv = 0;
1498
1499 addr = env->reserve_ea;
1500 page_addr = addr & TARGET_PAGE_MASK;
1501 start_exclusive();
1502 mmap_lock();
1503 flags = page_get_flags(page_addr);
1504 if ((flags & PAGE_READ) == 0) {
1505 segv = 1;
1506 } else {
1507 int reg = env->reserve_info & 0x1f;
1508 int size = (env->reserve_info >> 5) & 0xf;
1509 int stored = 0;
1510
1511 if (addr == env->reserve_addr) {
1512 switch (size) {
1513 case 1: segv = get_user_u8(val, addr); break;
1514 case 2: segv = get_user_u16(val, addr); break;
1515 case 4: segv = get_user_u32(val, addr); break;
1516 #if defined(TARGET_PPC64)
1517 case 8: segv = get_user_u64(val, addr); break;
1518 case 16: {
1519 segv = get_user_u64(val, addr);
1520 if (!segv) {
1521 segv = get_user_u64(val2, addr + 8);
1522 }
1523 break;
1524 }
1525 #endif
1526 default: abort();
1527 }
1528 if (!segv && val == env->reserve_val) {
1529 val = env->gpr[reg];
1530 switch (size) {
1531 case 1: segv = put_user_u8(val, addr); break;
1532 case 2: segv = put_user_u16(val, addr); break;
1533 case 4: segv = put_user_u32(val, addr); break;
1534 #if defined(TARGET_PPC64)
1535 case 8: segv = put_user_u64(val, addr); break;
1536 case 16: {
1537 if (val2 == env->reserve_val2) {
1538 segv = put_user_u64(val, addr);
1539 if (!segv) {
1540 segv = put_user_u64(val2, addr + 8);
1541 }
1542 }
1543 break;
1544 }
1545 #endif
1546 default: abort();
1547 }
1548 if (!segv) {
1549 stored = 1;
1550 }
1551 }
1552 }
1553 env->crf[0] = (stored << 1) | xer_so;
1554 env->reserve_addr = (target_ulong)-1;
1555 }
1556 if (!segv) {
1557 env->nip += 4;
1558 }
1559 mmap_unlock();
1560 end_exclusive();
1561 return segv;
1562 }
1563
1564 void cpu_loop(CPUPPCState *env)
1565 {
1566 CPUState *cs = CPU(ppc_env_get_cpu(env));
1567 target_siginfo_t info;
1568 int trapnr;
1569 target_ulong ret;
1570
1571 for(;;) {
1572 cpu_exec_start(cs);
1573 trapnr = cpu_ppc_exec(env);
1574 cpu_exec_end(cs);
1575 switch(trapnr) {
1576 case POWERPC_EXCP_NONE:
1577 /* Just go on */
1578 break;
1579 case POWERPC_EXCP_CRITICAL: /* Critical input */
1580 cpu_abort(env, "Critical interrupt while in user mode. "
1581 "Aborting\n");
1582 break;
1583 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1584 cpu_abort(env, "Machine check exception while in user mode. "
1585 "Aborting\n");
1586 break;
1587 case POWERPC_EXCP_DSI: /* Data storage exception */
1588 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1589 env->spr[SPR_DAR]);
1590 /* XXX: check this. Seems bugged */
1591 switch (env->error_code & 0xFF000000) {
1592 case 0x40000000:
1593 info.si_signo = TARGET_SIGSEGV;
1594 info.si_errno = 0;
1595 info.si_code = TARGET_SEGV_MAPERR;
1596 break;
1597 case 0x04000000:
1598 info.si_signo = TARGET_SIGILL;
1599 info.si_errno = 0;
1600 info.si_code = TARGET_ILL_ILLADR;
1601 break;
1602 case 0x08000000:
1603 info.si_signo = TARGET_SIGSEGV;
1604 info.si_errno = 0;
1605 info.si_code = TARGET_SEGV_ACCERR;
1606 break;
1607 default:
1608 /* Let's send a regular segfault... */
1609 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1610 env->error_code);
1611 info.si_signo = TARGET_SIGSEGV;
1612 info.si_errno = 0;
1613 info.si_code = TARGET_SEGV_MAPERR;
1614 break;
1615 }
1616 info._sifields._sigfault._addr = env->nip;
1617 queue_signal(env, info.si_signo, &info);
1618 break;
1619 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1620 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1621 "\n", env->spr[SPR_SRR0]);
1622 /* XXX: check this */
1623 switch (env->error_code & 0xFF000000) {
1624 case 0x40000000:
1625 info.si_signo = TARGET_SIGSEGV;
1626 info.si_errno = 0;
1627 info.si_code = TARGET_SEGV_MAPERR;
1628 break;
1629 case 0x10000000:
1630 case 0x08000000:
1631 info.si_signo = TARGET_SIGSEGV;
1632 info.si_errno = 0;
1633 info.si_code = TARGET_SEGV_ACCERR;
1634 break;
1635 default:
1636 /* Let's send a regular segfault... */
1637 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1638 env->error_code);
1639 info.si_signo = TARGET_SIGSEGV;
1640 info.si_errno = 0;
1641 info.si_code = TARGET_SEGV_MAPERR;
1642 break;
1643 }
1644 info._sifields._sigfault._addr = env->nip - 4;
1645 queue_signal(env, info.si_signo, &info);
1646 break;
1647 case POWERPC_EXCP_EXTERNAL: /* External input */
1648 cpu_abort(env, "External interrupt while in user mode. "
1649 "Aborting\n");
1650 break;
1651 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1652 EXCP_DUMP(env, "Unaligned memory access\n");
1653 /* XXX: check this */
1654 info.si_signo = TARGET_SIGBUS;
1655 info.si_errno = 0;
1656 info.si_code = TARGET_BUS_ADRALN;
1657 info._sifields._sigfault._addr = env->nip - 4;
1658 queue_signal(env, info.si_signo, &info);
1659 break;
1660 case POWERPC_EXCP_PROGRAM: /* Program exception */
1661 /* XXX: check this */
1662 switch (env->error_code & ~0xF) {
1663 case POWERPC_EXCP_FP:
1664 EXCP_DUMP(env, "Floating point program exception\n");
1665 info.si_signo = TARGET_SIGFPE;
1666 info.si_errno = 0;
1667 switch (env->error_code & 0xF) {
1668 case POWERPC_EXCP_FP_OX:
1669 info.si_code = TARGET_FPE_FLTOVF;
1670 break;
1671 case POWERPC_EXCP_FP_UX:
1672 info.si_code = TARGET_FPE_FLTUND;
1673 break;
1674 case POWERPC_EXCP_FP_ZX:
1675 case POWERPC_EXCP_FP_VXZDZ:
1676 info.si_code = TARGET_FPE_FLTDIV;
1677 break;
1678 case POWERPC_EXCP_FP_XX:
1679 info.si_code = TARGET_FPE_FLTRES;
1680 break;
1681 case POWERPC_EXCP_FP_VXSOFT:
1682 info.si_code = TARGET_FPE_FLTINV;
1683 break;
1684 case POWERPC_EXCP_FP_VXSNAN:
1685 case POWERPC_EXCP_FP_VXISI:
1686 case POWERPC_EXCP_FP_VXIDI:
1687 case POWERPC_EXCP_FP_VXIMZ:
1688 case POWERPC_EXCP_FP_VXVC:
1689 case POWERPC_EXCP_FP_VXSQRT:
1690 case POWERPC_EXCP_FP_VXCVI:
1691 info.si_code = TARGET_FPE_FLTSUB;
1692 break;
1693 default:
1694 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1695 env->error_code);
1696 break;
1697 }
1698 break;
1699 case POWERPC_EXCP_INVAL:
1700 EXCP_DUMP(env, "Invalid instruction\n");
1701 info.si_signo = TARGET_SIGILL;
1702 info.si_errno = 0;
1703 switch (env->error_code & 0xF) {
1704 case POWERPC_EXCP_INVAL_INVAL:
1705 info.si_code = TARGET_ILL_ILLOPC;
1706 break;
1707 case POWERPC_EXCP_INVAL_LSWX:
1708 info.si_code = TARGET_ILL_ILLOPN;
1709 break;
1710 case POWERPC_EXCP_INVAL_SPR:
1711 info.si_code = TARGET_ILL_PRVREG;
1712 break;
1713 case POWERPC_EXCP_INVAL_FP:
1714 info.si_code = TARGET_ILL_COPROC;
1715 break;
1716 default:
1717 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1718 env->error_code & 0xF);
1719 info.si_code = TARGET_ILL_ILLADR;
1720 break;
1721 }
1722 break;
1723 case POWERPC_EXCP_PRIV:
1724 EXCP_DUMP(env, "Privilege violation\n");
1725 info.si_signo = TARGET_SIGILL;
1726 info.si_errno = 0;
1727 switch (env->error_code & 0xF) {
1728 case POWERPC_EXCP_PRIV_OPC:
1729 info.si_code = TARGET_ILL_PRVOPC;
1730 break;
1731 case POWERPC_EXCP_PRIV_REG:
1732 info.si_code = TARGET_ILL_PRVREG;
1733 break;
1734 default:
1735 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1736 env->error_code & 0xF);
1737 info.si_code = TARGET_ILL_PRVOPC;
1738 break;
1739 }
1740 break;
1741 case POWERPC_EXCP_TRAP:
1742 cpu_abort(env, "Tried to call a TRAP\n");
1743 break;
1744 default:
1745 /* Should not happen ! */
1746 cpu_abort(env, "Unknown program exception (%02x)\n",
1747 env->error_code);
1748 break;
1749 }
1750 info._sifields._sigfault._addr = env->nip - 4;
1751 queue_signal(env, info.si_signo, &info);
1752 break;
1753 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1754 EXCP_DUMP(env, "No floating point allowed\n");
1755 info.si_signo = TARGET_SIGILL;
1756 info.si_errno = 0;
1757 info.si_code = TARGET_ILL_COPROC;
1758 info._sifields._sigfault._addr = env->nip - 4;
1759 queue_signal(env, info.si_signo, &info);
1760 break;
1761 case POWERPC_EXCP_SYSCALL: /* System call exception */
1762 cpu_abort(env, "Syscall exception while in user mode. "
1763 "Aborting\n");
1764 break;
1765 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1766 EXCP_DUMP(env, "No APU instruction allowed\n");
1767 info.si_signo = TARGET_SIGILL;
1768 info.si_errno = 0;
1769 info.si_code = TARGET_ILL_COPROC;
1770 info._sifields._sigfault._addr = env->nip - 4;
1771 queue_signal(env, info.si_signo, &info);
1772 break;
1773 case POWERPC_EXCP_DECR: /* Decrementer exception */
1774 cpu_abort(env, "Decrementer interrupt while in user mode. "
1775 "Aborting\n");
1776 break;
1777 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1778 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1779 "Aborting\n");
1780 break;
1781 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1782 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1783 "Aborting\n");
1784 break;
1785 case POWERPC_EXCP_DTLB: /* Data TLB error */
1786 cpu_abort(env, "Data TLB exception while in user mode. "
1787 "Aborting\n");
1788 break;
1789 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1790 cpu_abort(env, "Instruction TLB exception while in user mode. "
1791 "Aborting\n");
1792 break;
1793 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1794 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1795 info.si_signo = TARGET_SIGILL;
1796 info.si_errno = 0;
1797 info.si_code = TARGET_ILL_COPROC;
1798 info._sifields._sigfault._addr = env->nip - 4;
1799 queue_signal(env, info.si_signo, &info);
1800 break;
1801 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1802 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1803 break;
1804 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1805 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1806 break;
1807 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1808 cpu_abort(env, "Performance monitor exception not handled\n");
1809 break;
1810 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1811 cpu_abort(env, "Doorbell interrupt while in user mode. "
1812 "Aborting\n");
1813 break;
1814 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1815 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1816 "Aborting\n");
1817 break;
1818 case POWERPC_EXCP_RESET: /* System reset exception */
1819 cpu_abort(env, "Reset interrupt while in user mode. "
1820 "Aborting\n");
1821 break;
1822 case POWERPC_EXCP_DSEG: /* Data segment exception */
1823 cpu_abort(env, "Data segment exception while in user mode. "
1824 "Aborting\n");
1825 break;
1826 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1827 cpu_abort(env, "Instruction segment exception "
1828 "while in user mode. Aborting\n");
1829 break;
1830 /* PowerPC 64 with hypervisor mode support */
1831 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1832 cpu_abort(env, "Hypervisor decrementer interrupt "
1833 "while in user mode. Aborting\n");
1834 break;
1835 case POWERPC_EXCP_TRACE: /* Trace exception */
1836 /* Nothing to do:
1837 * we use this exception to emulate step-by-step execution mode.
1838 */
1839 break;
1840 /* PowerPC 64 with hypervisor mode support */
1841 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1842 cpu_abort(env, "Hypervisor data storage exception "
1843 "while in user mode. Aborting\n");
1844 break;
1845 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1846 cpu_abort(env, "Hypervisor instruction storage exception "
1847 "while in user mode. Aborting\n");
1848 break;
1849 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1850 cpu_abort(env, "Hypervisor data segment exception "
1851 "while in user mode. Aborting\n");
1852 break;
1853 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1854 cpu_abort(env, "Hypervisor instruction segment exception "
1855 "while in user mode. Aborting\n");
1856 break;
1857 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1858 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1859 info.si_signo = TARGET_SIGILL;
1860 info.si_errno = 0;
1861 info.si_code = TARGET_ILL_COPROC;
1862 info._sifields._sigfault._addr = env->nip - 4;
1863 queue_signal(env, info.si_signo, &info);
1864 break;
1865 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1866 cpu_abort(env, "Programmable interval timer interrupt "
1867 "while in user mode. Aborting\n");
1868 break;
1869 case POWERPC_EXCP_IO: /* IO error exception */
1870 cpu_abort(env, "IO error exception while in user mode. "
1871 "Aborting\n");
1872 break;
1873 case POWERPC_EXCP_RUNM: /* Run mode exception */
1874 cpu_abort(env, "Run mode exception while in user mode. "
1875 "Aborting\n");
1876 break;
1877 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1878 cpu_abort(env, "Emulation trap exception not handled\n");
1879 break;
1880 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1881 cpu_abort(env, "Instruction fetch TLB exception "
1882 "while in user-mode. Aborting");
1883 break;
1884 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1885 cpu_abort(env, "Data load TLB exception while in user-mode. "
1886 "Aborting");
1887 break;
1888 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1889 cpu_abort(env, "Data store TLB exception while in user-mode. "
1890 "Aborting");
1891 break;
1892 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1893 cpu_abort(env, "Floating-point assist exception not handled\n");
1894 break;
1895 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1896 cpu_abort(env, "Instruction address breakpoint exception "
1897 "not handled\n");
1898 break;
1899 case POWERPC_EXCP_SMI: /* System management interrupt */
1900 cpu_abort(env, "System management interrupt while in user mode. "
1901 "Aborting\n");
1902 break;
1903 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1904 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1905 "Aborting\n");
1906 break;
1907 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1908 cpu_abort(env, "Performance monitor exception not handled\n");
1909 break;
1910 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1911 cpu_abort(env, "Vector assist exception not handled\n");
1912 break;
1913 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1914 cpu_abort(env, "Soft patch exception not handled\n");
1915 break;
1916 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1917 cpu_abort(env, "Maintenance exception while in user mode. "
1918 "Aborting\n");
1919 break;
1920 case POWERPC_EXCP_STOP: /* stop translation */
1921 /* We did invalidate the instruction cache. Go on */
1922 break;
1923 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1924 /* We just stopped because of a branch. Go on */
1925 break;
1926 case POWERPC_EXCP_SYSCALL_USER:
1927 /* system call in user-mode emulation */
1928 /* WARNING:
1929 * PPC ABI uses overflow flag in cr0 to signal an error
1930 * in syscalls.
1931 */
1932 env->crf[0] &= ~0x1;
1933 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1934 env->gpr[5], env->gpr[6], env->gpr[7],
1935 env->gpr[8], 0, 0);
1936 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1937 /* Returning from a successful sigreturn syscall.
1938 Avoid corrupting register state. */
1939 break;
1940 }
1941 if (ret > (target_ulong)(-515)) {
1942 env->crf[0] |= 0x1;
1943 ret = -ret;
1944 }
1945 env->gpr[3] = ret;
1946 break;
1947 case POWERPC_EXCP_STCX:
1948 if (do_store_exclusive(env)) {
1949 info.si_signo = TARGET_SIGSEGV;
1950 info.si_errno = 0;
1951 info.si_code = TARGET_SEGV_MAPERR;
1952 info._sifields._sigfault._addr = env->nip;
1953 queue_signal(env, info.si_signo, &info);
1954 }
1955 break;
1956 case EXCP_DEBUG:
1957 {
1958 int sig;
1959
1960 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1961 if (sig) {
1962 info.si_signo = sig;
1963 info.si_errno = 0;
1964 info.si_code = TARGET_TRAP_BRKPT;
1965 queue_signal(env, info.si_signo, &info);
1966 }
1967 }
1968 break;
1969 case EXCP_INTERRUPT:
1970 /* just indicate that signals should be handled asap */
1971 break;
1972 default:
1973 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1974 break;
1975 }
1976 process_pending_signals(env);
1977 }
1978 }
1979 #endif
1980
1981 #ifdef TARGET_MIPS
1982
1983 # ifdef TARGET_ABI_MIPSO32
1984 # define MIPS_SYS(name, args) args,
1985 static const uint8_t mips_syscall_args[] = {
1986 MIPS_SYS(sys_syscall , 8) /* 4000 */
1987 MIPS_SYS(sys_exit , 1)
1988 MIPS_SYS(sys_fork , 0)
1989 MIPS_SYS(sys_read , 3)
1990 MIPS_SYS(sys_write , 3)
1991 MIPS_SYS(sys_open , 3) /* 4005 */
1992 MIPS_SYS(sys_close , 1)
1993 MIPS_SYS(sys_waitpid , 3)
1994 MIPS_SYS(sys_creat , 2)
1995 MIPS_SYS(sys_link , 2)
1996 MIPS_SYS(sys_unlink , 1) /* 4010 */
1997 MIPS_SYS(sys_execve , 0)
1998 MIPS_SYS(sys_chdir , 1)
1999 MIPS_SYS(sys_time , 1)
2000 MIPS_SYS(sys_mknod , 3)
2001 MIPS_SYS(sys_chmod , 2) /* 4015 */
2002 MIPS_SYS(sys_lchown , 3)
2003 MIPS_SYS(sys_ni_syscall , 0)
2004 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2005 MIPS_SYS(sys_lseek , 3)
2006 MIPS_SYS(sys_getpid , 0) /* 4020 */
2007 MIPS_SYS(sys_mount , 5)
2008 MIPS_SYS(sys_umount , 1)
2009 MIPS_SYS(sys_setuid , 1)
2010 MIPS_SYS(sys_getuid , 0)
2011 MIPS_SYS(sys_stime , 1) /* 4025 */
2012 MIPS_SYS(sys_ptrace , 4)
2013 MIPS_SYS(sys_alarm , 1)
2014 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2015 MIPS_SYS(sys_pause , 0)
2016 MIPS_SYS(sys_utime , 2) /* 4030 */
2017 MIPS_SYS(sys_ni_syscall , 0)
2018 MIPS_SYS(sys_ni_syscall , 0)
2019 MIPS_SYS(sys_access , 2)
2020 MIPS_SYS(sys_nice , 1)
2021 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2022 MIPS_SYS(sys_sync , 0)
2023 MIPS_SYS(sys_kill , 2)
2024 MIPS_SYS(sys_rename , 2)
2025 MIPS_SYS(sys_mkdir , 2)
2026 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2027 MIPS_SYS(sys_dup , 1)
2028 MIPS_SYS(sys_pipe , 0)
2029 MIPS_SYS(sys_times , 1)
2030 MIPS_SYS(sys_ni_syscall , 0)
2031 MIPS_SYS(sys_brk , 1) /* 4045 */
2032 MIPS_SYS(sys_setgid , 1)
2033 MIPS_SYS(sys_getgid , 0)
2034 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2035 MIPS_SYS(sys_geteuid , 0)
2036 MIPS_SYS(sys_getegid , 0) /* 4050 */
2037 MIPS_SYS(sys_acct , 0)
2038 MIPS_SYS(sys_umount2 , 2)
2039 MIPS_SYS(sys_ni_syscall , 0)
2040 MIPS_SYS(sys_ioctl , 3)
2041 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2042 MIPS_SYS(sys_ni_syscall , 2)
2043 MIPS_SYS(sys_setpgid , 2)
2044 MIPS_SYS(sys_ni_syscall , 0)
2045 MIPS_SYS(sys_olduname , 1)
2046 MIPS_SYS(sys_umask , 1) /* 4060 */
2047 MIPS_SYS(sys_chroot , 1)
2048 MIPS_SYS(sys_ustat , 2)
2049 MIPS_SYS(sys_dup2 , 2)
2050 MIPS_SYS(sys_getppid , 0)
2051 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2052 MIPS_SYS(sys_setsid , 0)
2053 MIPS_SYS(sys_sigaction , 3)
2054 MIPS_SYS(sys_sgetmask , 0)
2055 MIPS_SYS(sys_ssetmask , 1)
2056 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2057 MIPS_SYS(sys_setregid , 2)
2058 MIPS_SYS(sys_sigsuspend , 0)
2059 MIPS_SYS(sys_sigpending , 1)
2060 MIPS_SYS(sys_sethostname , 2)
2061 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2062 MIPS_SYS(sys_getrlimit , 2)
2063 MIPS_SYS(sys_getrusage , 2)
2064 MIPS_SYS(sys_gettimeofday, 2)
2065 MIPS_SYS(sys_settimeofday, 2)
2066 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2067 MIPS_SYS(sys_setgroups , 2)
2068 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2069 MIPS_SYS(sys_symlink , 2)
2070 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2071 MIPS_SYS(sys_readlink , 3) /* 4085 */
2072 MIPS_SYS(sys_uselib , 1)
2073 MIPS_SYS(sys_swapon , 2)
2074 MIPS_SYS(sys_reboot , 3)
2075 MIPS_SYS(old_readdir , 3)
2076 MIPS_SYS(old_mmap , 6) /* 4090 */
2077 MIPS_SYS(sys_munmap , 2)
2078 MIPS_SYS(sys_truncate , 2)
2079 MIPS_SYS(sys_ftruncate , 2)
2080 MIPS_SYS(sys_fchmod , 2)
2081 MIPS_SYS(sys_fchown , 3) /* 4095 */
2082 MIPS_SYS(sys_getpriority , 2)
2083 MIPS_SYS(sys_setpriority , 3)
2084 MIPS_SYS(sys_ni_syscall , 0)
2085 MIPS_SYS(sys_statfs , 2)
2086 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2087 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2088 MIPS_SYS(sys_socketcall , 2)
2089 MIPS_SYS(sys_syslog , 3)
2090 MIPS_SYS(sys_setitimer , 3)
2091 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2092 MIPS_SYS(sys_newstat , 2)
2093 MIPS_SYS(sys_newlstat , 2)
2094 MIPS_SYS(sys_newfstat , 2)
2095 MIPS_SYS(sys_uname , 1)
2096 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2097 MIPS_SYS(sys_vhangup , 0)
2098 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2099 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2100 MIPS_SYS(sys_wait4 , 4)
2101 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2102 MIPS_SYS(sys_sysinfo , 1)
2103 MIPS_SYS(sys_ipc , 6)
2104 MIPS_SYS(sys_fsync , 1)
2105 MIPS_SYS(sys_sigreturn , 0)
2106 MIPS_SYS(sys_clone , 6) /* 4120 */
2107 MIPS_SYS(sys_setdomainname, 2)
2108 MIPS_SYS(sys_newuname , 1)
2109 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2110 MIPS_SYS(sys_adjtimex , 1)
2111 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2112 MIPS_SYS(sys_sigprocmask , 3)
2113 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2114 MIPS_SYS(sys_init_module , 5)
2115 MIPS_SYS(sys_delete_module, 1)
2116 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2117 MIPS_SYS(sys_quotactl , 0)
2118 MIPS_SYS(sys_getpgid , 1)
2119 MIPS_SYS(sys_fchdir , 1)
2120 MIPS_SYS(sys_bdflush , 2)
2121 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2122 MIPS_SYS(sys_personality , 1)
2123 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2124 MIPS_SYS(sys_setfsuid , 1)
2125 MIPS_SYS(sys_setfsgid , 1)
2126 MIPS_SYS(sys_llseek , 5) /* 4140 */
2127 MIPS_SYS(sys_getdents , 3)
2128 MIPS_SYS(sys_select , 5)
2129 MIPS_SYS(sys_flock , 2)
2130 MIPS_SYS(sys_msync , 3)
2131 MIPS_SYS(sys_readv , 3) /* 4145 */
2132 MIPS_SYS(sys_writev , 3)
2133 MIPS_SYS(sys_cacheflush , 3)
2134 MIPS_SYS(sys_cachectl , 3)
2135 MIPS_SYS(sys_sysmips , 4)
2136 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2137 MIPS_SYS(sys_getsid , 1)
2138 MIPS_SYS(sys_fdatasync , 0)
2139 MIPS_SYS(sys_sysctl , 1)
2140 MIPS_SYS(sys_mlock , 2)
2141 MIPS_SYS(sys_munlock , 2) /* 4155 */
2142 MIPS_SYS(sys_mlockall , 1)
2143 MIPS_SYS(sys_munlockall , 0)
2144 MIPS_SYS(sys_sched_setparam, 2)
2145 MIPS_SYS(sys_sched_getparam, 2)
2146 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2147 MIPS_SYS(sys_sched_getscheduler, 1)
2148 MIPS_SYS(sys_sched_yield , 0)
2149 MIPS_SYS(sys_sched_get_priority_max, 1)
2150 MIPS_SYS(sys_sched_get_priority_min, 1)
2151 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2152 MIPS_SYS(sys_nanosleep, 2)
2153 MIPS_SYS(sys_mremap , 5)
2154 MIPS_SYS(sys_accept , 3)
2155 MIPS_SYS(sys_bind , 3)
2156 MIPS_SYS(sys_connect , 3) /* 4170 */
2157 MIPS_SYS(sys_getpeername , 3)
2158 MIPS_SYS(sys_getsockname , 3)
2159 MIPS_SYS(sys_getsockopt , 5)
2160 MIPS_SYS(sys_listen , 2)
2161 MIPS_SYS(sys_recv , 4) /* 4175 */
2162 MIPS_SYS(sys_recvfrom , 6)
2163 MIPS_SYS(sys_recvmsg , 3)
2164 MIPS_SYS(sys_send , 4)
2165 MIPS_SYS(sys_sendmsg , 3)
2166 MIPS_SYS(sys_sendto , 6) /* 4180 */
2167 MIPS_SYS(sys_setsockopt , 5)
2168 MIPS_SYS(sys_shutdown , 2)
2169 MIPS_SYS(sys_socket , 3)
2170 MIPS_SYS(sys_socketpair , 4)
2171 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2172 MIPS_SYS(sys_getresuid , 3)
2173 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2174 MIPS_SYS(sys_poll , 3)
2175 MIPS_SYS(sys_nfsservctl , 3)
2176 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2177 MIPS_SYS(sys_getresgid , 3)
2178 MIPS_SYS(sys_prctl , 5)
2179 MIPS_SYS(sys_rt_sigreturn, 0)
2180 MIPS_SYS(sys_rt_sigaction, 4)
2181 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2182 MIPS_SYS(sys_rt_sigpending, 2)
2183 MIPS_SYS(sys_rt_sigtimedwait, 4)
2184 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2185 MIPS_SYS(sys_rt_sigsuspend, 0)
2186 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2187 MIPS_SYS(sys_pwrite64 , 6)
2188 MIPS_SYS(sys_chown , 3)
2189 MIPS_SYS(sys_getcwd , 2)
2190 MIPS_SYS(sys_capget , 2)
2191 MIPS_SYS(sys_capset , 2) /* 4205 */
2192 MIPS_SYS(sys_sigaltstack , 2)
2193 MIPS_SYS(sys_sendfile , 4)
2194 MIPS_SYS(sys_ni_syscall , 0)
2195 MIPS_SYS(sys_ni_syscall , 0)
2196 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2197 MIPS_SYS(sys_truncate64 , 4)
2198 MIPS_SYS(sys_ftruncate64 , 4)
2199 MIPS_SYS(sys_stat64 , 2)
2200 MIPS_SYS(sys_lstat64 , 2)
2201 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2202 MIPS_SYS(sys_pivot_root , 2)
2203 MIPS_SYS(sys_mincore , 3)
2204 MIPS_SYS(sys_madvise , 3)
2205 MIPS_SYS(sys_getdents64 , 3)
2206 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2207 MIPS_SYS(sys_ni_syscall , 0)
2208 MIPS_SYS(sys_gettid , 0)
2209 MIPS_SYS(sys_readahead , 5)
2210 MIPS_SYS(sys_setxattr , 5)
2211 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2212 MIPS_SYS(sys_fsetxattr , 5)
2213 MIPS_SYS(sys_getxattr , 4)
2214 MIPS_SYS(sys_lgetxattr , 4)
2215 MIPS_SYS(sys_fgetxattr , 4)
2216 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2217 MIPS_SYS(sys_llistxattr , 3)
2218 MIPS_SYS(sys_flistxattr , 3)
2219 MIPS_SYS(sys_removexattr , 2)
2220 MIPS_SYS(sys_lremovexattr, 2)
2221 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2222 MIPS_SYS(sys_tkill , 2)
2223 MIPS_SYS(sys_sendfile64 , 5)
2224 MIPS_SYS(sys_futex , 6)
2225 MIPS_SYS(sys_sched_setaffinity, 3)
2226 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2227 MIPS_SYS(sys_io_setup , 2)
2228 MIPS_SYS(sys_io_destroy , 1)
2229 MIPS_SYS(sys_io_getevents, 5)
2230 MIPS_SYS(sys_io_submit , 3)
2231 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2232 MIPS_SYS(sys_exit_group , 1)
2233 MIPS_SYS(sys_lookup_dcookie, 3)
2234 MIPS_SYS(sys_epoll_create, 1)
2235 MIPS_SYS(sys_epoll_ctl , 4)
2236 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2237 MIPS_SYS(sys_remap_file_pages, 5)
2238 MIPS_SYS(sys_set_tid_address, 1)
2239 MIPS_SYS(sys_restart_syscall, 0)
2240 MIPS_SYS(sys_fadvise64_64, 7)
2241 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2242 MIPS_SYS(sys_fstatfs64 , 2)
2243 MIPS_SYS(sys_timer_create, 3)
2244 MIPS_SYS(sys_timer_settime, 4)
2245 MIPS_SYS(sys_timer_gettime, 2)
2246 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2247 MIPS_SYS(sys_timer_delete, 1)
2248 MIPS_SYS(sys_clock_settime, 2)
2249 MIPS_SYS(sys_clock_gettime, 2)
2250 MIPS_SYS(sys_clock_getres, 2)
2251 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2252 MIPS_SYS(sys_tgkill , 3)
2253 MIPS_SYS(sys_utimes , 2)
2254 MIPS_SYS(sys_mbind , 4)
2255 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2256 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2257 MIPS_SYS(sys_mq_open , 4)
2258 MIPS_SYS(sys_mq_unlink , 1)
2259 MIPS_SYS(sys_mq_timedsend, 5)
2260 MIPS_SYS(sys_mq_timedreceive, 5)
2261 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2262 MIPS_SYS(sys_mq_getsetattr, 3)
2263 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2264 MIPS_SYS(sys_waitid , 4)
2265 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2266 MIPS_SYS(sys_add_key , 5)
2267 MIPS_SYS(sys_request_key, 4)
2268 MIPS_SYS(sys_keyctl , 5)
2269 MIPS_SYS(sys_set_thread_area, 1)
2270 MIPS_SYS(sys_inotify_init, 0)
2271 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2272 MIPS_SYS(sys_inotify_rm_watch, 2)
2273 MIPS_SYS(sys_migrate_pages, 4)
2274 MIPS_SYS(sys_openat, 4)
2275 MIPS_SYS(sys_mkdirat, 3)
2276 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2277 MIPS_SYS(sys_fchownat, 5)
2278 MIPS_SYS(sys_futimesat, 3)
2279 MIPS_SYS(sys_fstatat64, 4)
2280 MIPS_SYS(sys_unlinkat, 3)
2281 MIPS_SYS(sys_renameat, 4) /* 4295 */
2282 MIPS_SYS(sys_linkat, 5)
2283 MIPS_SYS(sys_symlinkat, 3)
2284 MIPS_SYS(sys_readlinkat, 4)
2285 MIPS_SYS(sys_fchmodat, 3)
2286 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2287 MIPS_SYS(sys_pselect6, 6)
2288 MIPS_SYS(sys_ppoll, 5)
2289 MIPS_SYS(sys_unshare, 1)
2290 MIPS_SYS(sys_splice, 6)
2291 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2292 MIPS_SYS(sys_tee, 4)
2293 MIPS_SYS(sys_vmsplice, 4)
2294 MIPS_SYS(sys_move_pages, 6)
2295 MIPS_SYS(sys_set_robust_list, 2)
2296 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2297 MIPS_SYS(sys_kexec_load, 4)
2298 MIPS_SYS(sys_getcpu, 3)
2299 MIPS_SYS(sys_epoll_pwait, 6)
2300 MIPS_SYS(sys_ioprio_set, 3)
2301 MIPS_SYS(sys_ioprio_get, 2)
2302 MIPS_SYS(sys_utimensat, 4)
2303 MIPS_SYS(sys_signalfd, 3)
2304 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2305 MIPS_SYS(sys_eventfd, 1)
2306 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2307 MIPS_SYS(sys_timerfd_create, 2)
2308 MIPS_SYS(sys_timerfd_gettime, 2)
2309 MIPS_SYS(sys_timerfd_settime, 4)
2310 MIPS_SYS(sys_signalfd4, 4)
2311 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2312 MIPS_SYS(sys_epoll_create1, 1)
2313 MIPS_SYS(sys_dup3, 3)
2314 MIPS_SYS(sys_pipe2, 2)
2315 MIPS_SYS(sys_inotify_init1, 1)
2316 MIPS_SYS(sys_preadv, 6) /* 4330 */
2317 MIPS_SYS(sys_pwritev, 6)
2318 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2319 MIPS_SYS(sys_perf_event_open, 5)
2320 MIPS_SYS(sys_accept4, 4)
2321 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2322 MIPS_SYS(sys_fanotify_init, 2)
2323 MIPS_SYS(sys_fanotify_mark, 6)
2324 MIPS_SYS(sys_prlimit64, 4)
2325 MIPS_SYS(sys_name_to_handle_at, 5)
2326 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2327 MIPS_SYS(sys_clock_adjtime, 2)
2328 MIPS_SYS(sys_syncfs, 1)
2329 };
2330 # undef MIPS_SYS
2331 # endif /* O32 */
2332
2333 static int do_store_exclusive(CPUMIPSState *env)
2334 {
2335 target_ulong addr;
2336 target_ulong page_addr;
2337 target_ulong val;
2338 int flags;
2339 int segv = 0;
2340 int reg;
2341 int d;
2342
2343 addr = env->lladdr;
2344 page_addr = addr & TARGET_PAGE_MASK;
2345 start_exclusive();
2346 mmap_lock();
2347 flags = page_get_flags(page_addr);
2348 if ((flags & PAGE_READ) == 0) {
2349 segv = 1;
2350 } else {
2351 reg = env->llreg & 0x1f;
2352 d = (env->llreg & 0x20) != 0;
2353 if (d) {
2354 segv = get_user_s64(val, addr);
2355 } else {
2356 segv = get_user_s32(val, addr);
2357 }
2358 if (!segv) {
2359 if (val != env->llval) {
2360 env->active_tc.gpr[reg] = 0;
2361 } else {
2362 if (d) {
2363 segv = put_user_u64(env->llnewval, addr);
2364 } else {
2365 segv = put_user_u32(env->llnewval, addr);
2366 }
2367 if (!segv) {
2368 env->active_tc.gpr[reg] = 1;
2369 }
2370 }
2371 }
2372 }
2373 env->lladdr = -1;
2374 if (!segv) {
2375 env->active_tc.PC += 4;
2376 }
2377 mmap_unlock();
2378 end_exclusive();
2379 return segv;
2380 }
2381
2382 /* Break codes */
2383 enum {
2384 BRK_OVERFLOW = 6,
2385 BRK_DIVZERO = 7
2386 };
2387
2388 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2389 unsigned int code)
2390 {
2391 int ret = -1;
2392
2393 switch (code) {
2394 case BRK_OVERFLOW:
2395 case BRK_DIVZERO:
2396 info->si_signo = TARGET_SIGFPE;
2397 info->si_errno = 0;
2398 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2399 queue_signal(env, info->si_signo, &*info);
2400 ret = 0;
2401 break;
2402 default:
2403 break;
2404 }
2405
2406 return ret;
2407 }
2408
2409 void cpu_loop(CPUMIPSState *env)
2410 {
2411 CPUState *cs = CPU(mips_env_get_cpu(env));
2412 target_siginfo_t info;
2413 int trapnr;
2414 abi_long ret;
2415 # ifdef TARGET_ABI_MIPSO32
2416 unsigned int syscall_num;
2417 # endif
2418
2419 for(;;) {
2420 cpu_exec_start(cs);
2421 trapnr = cpu_mips_exec(env);
2422 cpu_exec_end(cs);
2423 switch(trapnr) {
2424 case EXCP_SYSCALL:
2425 env->active_tc.PC += 4;
2426 # ifdef TARGET_ABI_MIPSO32
2427 syscall_num = env->active_tc.gpr[2] - 4000;
2428 if (syscall_num >= sizeof(mips_syscall_args)) {
2429 ret = -TARGET_ENOSYS;
2430 } else {
2431 int nb_args;
2432 abi_ulong sp_reg;
2433 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2434
2435 nb_args = mips_syscall_args[syscall_num];
2436 sp_reg = env->active_tc.gpr[29];
2437 switch (nb_args) {
2438 /* these arguments are taken from the stack */
2439 case 8:
2440 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2441 goto done_syscall;
2442 }
2443 case 7:
2444 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2445 goto done_syscall;
2446 }
2447 case 6:
2448 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2449 goto done_syscall;
2450 }
2451 case 5:
2452 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2453 goto done_syscall;
2454 }
2455 default:
2456 break;
2457 }
2458 ret = do_syscall(env, env->active_tc.gpr[2],
2459 env->active_tc.gpr[4],
2460 env->active_tc.gpr[5],
2461 env->active_tc.gpr[6],
2462 env->active_tc.gpr[7],
2463 arg5, arg6, arg7, arg8);
2464 }
2465 done_syscall:
2466 # else
2467 ret = do_syscall(env, env->active_tc.gpr[2],
2468 env->active_tc.gpr[4], env->active_tc.gpr[5],
2469 env->active_tc.gpr[6], env->active_tc.gpr[7],
2470 env->active_tc.gpr[8], env->active_tc.gpr[9],
2471 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2472 # endif /* O32 */
2473 if (ret == -TARGET_QEMU_ESIGRETURN) {
2474 /* Returning from a successful sigreturn syscall.
2475 Avoid clobbering register state. */
2476 break;
2477 }
2478 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2479 env->active_tc.gpr[7] = 1; /* error flag */
2480 ret = -ret;
2481 } else {
2482 env->active_tc.gpr[7] = 0; /* error flag */
2483 }
2484 env->active_tc.gpr[2] = ret;
2485 break;
2486 case EXCP_TLBL:
2487 case EXCP_TLBS:
2488 case EXCP_AdEL:
2489 case EXCP_AdES:
2490 info.si_signo = TARGET_SIGSEGV;
2491 info.si_errno = 0;
2492 /* XXX: check env->error_code */
2493 info.si_code = TARGET_SEGV_MAPERR;
2494 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2495 queue_signal(env, info.si_signo, &info);
2496 break;
2497 case EXCP_CpU:
2498 case EXCP_RI:
2499 info.si_signo = TARGET_SIGILL;
2500 info.si_errno = 0;
2501 info.si_code = 0;
2502 queue_signal(env, info.si_signo, &info);
2503 break;
2504 case EXCP_INTERRUPT:
2505 /* just indicate that signals should be handled asap */
2506 break;
2507 case EXCP_DEBUG:
2508 {
2509 int sig;
2510
2511 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2512 if (sig)
2513 {
2514 info.si_signo = sig;
2515 info.si_errno = 0;
2516 info.si_code = TARGET_TRAP_BRKPT;
2517 queue_signal(env, info.si_signo, &info);
2518 }
2519 }
2520 break;
2521 case EXCP_SC:
2522 if (do_store_exclusive(env)) {
2523 info.si_signo = TARGET_SIGSEGV;
2524 info.si_errno = 0;
2525 info.si_code = TARGET_SEGV_MAPERR;
2526 info._sifields._sigfault._addr = env->active_tc.PC;
2527 queue_signal(env, info.si_signo, &info);
2528 }
2529 break;
2530 case EXCP_DSPDIS:
2531 info.si_signo = TARGET_SIGILL;
2532 info.si_errno = 0;
2533 info.si_code = TARGET_ILL_ILLOPC;
2534 queue_signal(env, info.si_signo, &info);
2535 break;
2536 /* The code below was inspired by the MIPS Linux kernel trap
2537 * handling code in arch/mips/kernel/traps.c.
2538 */
2539 case EXCP_BREAK:
2540 {
2541 abi_ulong trap_instr;
2542 unsigned int code;
2543
2544 if (env->hflags & MIPS_HFLAG_M16) {
2545 if (env->insn_flags & ASE_MICROMIPS) {
2546 /* microMIPS mode */
2547 ret = get_user_u16(trap_instr, env->active_tc.PC);
2548 if (ret != 0) {
2549 goto error;
2550 }
2551
2552 if ((trap_instr >> 10) == 0x11) {
2553 /* 16-bit instruction */
2554 code = trap_instr & 0xf;
2555 } else {
2556 /* 32-bit instruction */
2557 abi_ulong instr_lo;
2558
2559 ret = get_user_u16(instr_lo,
2560 env->active_tc.PC + 2);
2561 if (ret != 0) {
2562 goto error;
2563 }
2564 trap_instr = (trap_instr << 16) | instr_lo;
2565 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2566 /* Unfortunately, microMIPS also suffers from
2567 the old assembler bug... */
2568 if (code >= (1 << 10)) {
2569 code >>= 10;
2570 }
2571 }
2572 } else {
2573 /* MIPS16e mode */
2574 ret = get_user_u16(trap_instr, env->active_tc.PC);
2575 if (ret != 0) {
2576 goto error;
2577 }
2578 code = (trap_instr >> 6) & 0x3f;
2579 }
2580 } else {
2581 ret = get_user_ual(trap_instr, env->active_tc.PC);
2582 if (ret != 0) {
2583 goto error;
2584 }
2585
2586 /* As described in the original Linux kernel code, the
2587 * below checks on 'code' are to work around an old
2588 * assembly bug.
2589 */
2590 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2591 if (code >= (1 << 10)) {
2592 code >>= 10;
2593 }
2594 }
2595
2596 if (do_break(env, &info, code) != 0) {
2597 goto error;
2598 }
2599 }
2600 break;
2601 case EXCP_TRAP:
2602 {
2603 abi_ulong trap_instr;
2604 unsigned int code = 0;
2605
2606 if (env->hflags & MIPS_HFLAG_M16) {
2607 /* microMIPS mode */
2608 abi_ulong instr[2];
2609
2610 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2611 get_user_u16(instr[1], env->active_tc.PC + 2);
2612
2613 trap_instr = (instr[0] << 16) | instr[1];
2614 } else {
2615 ret = get_user_ual(trap_instr, env->active_tc.PC);
2616 }
2617
2618 if (ret != 0) {
2619 goto error;
2620 }
2621
2622 /* The immediate versions don't provide a code. */
2623 if (!(trap_instr & 0xFC000000)) {
2624 if (env->hflags & MIPS_HFLAG_M16) {
2625 /* microMIPS mode */
2626 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2627 } else {
2628 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2629 }
2630 }
2631
2632 if (do_break(env, &info, code) != 0) {
2633 goto error;
2634 }
2635 }
2636 break;
2637 default:
2638 error:
2639 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2640 trapnr);
2641 cpu_dump_state(cs, stderr, fprintf, 0);
2642 abort();
2643 }
2644 process_pending_signals(env);
2645 }
2646 }
2647 #endif
2648
2649 #ifdef TARGET_OPENRISC
2650
2651 void cpu_loop(CPUOpenRISCState *env)
2652 {
2653 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2654 int trapnr, gdbsig;
2655
2656 for (;;) {
2657 trapnr = cpu_exec(env);
2658 gdbsig = 0;
2659
2660 switch (trapnr) {
2661 case EXCP_RESET:
2662 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2663 exit(1);
2664 break;
2665 case EXCP_BUSERR:
2666 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2667 gdbsig = SIGBUS;
2668 break;
2669 case EXCP_DPF:
2670 case EXCP_IPF:
2671 cpu_dump_state(cs, stderr, fprintf, 0);
2672 gdbsig = TARGET_SIGSEGV;
2673 break;
2674 case EXCP_TICK:
2675 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2676 break;
2677 case EXCP_ALIGN:
2678 qemu_log("\nAlignment pc is %#x\n", env->pc);
2679 gdbsig = SIGBUS;
2680 break;
2681 case EXCP_ILLEGAL:
2682 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2683 gdbsig = SIGILL;
2684 break;
2685 case EXCP_INT:
2686 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2687 break;
2688 case EXCP_DTLBMISS:
2689 case EXCP_ITLBMISS:
2690 qemu_log("\nTLB miss\n");
2691 break;
2692 case EXCP_RANGE:
2693 qemu_log("\nRange\n");
2694 gdbsig = SIGSEGV;
2695 break;
2696 case EXCP_SYSCALL:
2697 env->pc += 4; /* 0xc00; */
2698 env->gpr[11] = do_syscall(env,
2699 env->gpr[11], /* return value */
2700 env->gpr[3], /* r3 - r7 are params */
2701 env->gpr[4],
2702 env->gpr[5],
2703 env->gpr[6],
2704 env->gpr[7],
2705 env->gpr[8], 0, 0);
2706 break;
2707 case EXCP_FPE:
2708 qemu_log("\nFloating point error\n");
2709 break;
2710 case EXCP_TRAP:
2711 qemu_log("\nTrap\n");
2712 gdbsig = SIGTRAP;
2713 break;
2714 case EXCP_NR:
2715 qemu_log("\nNR\n");
2716 break;
2717 default:
2718 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2719 trapnr);
2720 cpu_dump_state(cs, stderr, fprintf, 0);
2721 gdbsig = TARGET_SIGILL;
2722 break;
2723 }
2724 if (gdbsig) {
2725 gdb_handlesig(cs, gdbsig);
2726 if (gdbsig != TARGET_SIGTRAP) {
2727 exit(1);
2728 }
2729 }
2730
2731 process_pending_signals(env);
2732 }
2733 }
2734
2735 #endif /* TARGET_OPENRISC */
2736
2737 #ifdef TARGET_SH4
2738 void cpu_loop(CPUSH4State *env)
2739 {
2740 CPUState *cs = CPU(sh_env_get_cpu(env));
2741 int trapnr, ret;
2742 target_siginfo_t info;
2743
2744 while (1) {
2745 trapnr = cpu_sh4_exec (env);
2746
2747 switch (trapnr) {
2748 case 0x160:
2749 env->pc += 2;
2750 ret = do_syscall(env,
2751 env->gregs[3],
2752 env->gregs[4],
2753 env->gregs[5],
2754 env->gregs[6],
2755 env->gregs[7],
2756 env->gregs[0],
2757 env->gregs[1],
2758 0, 0);
2759 env->gregs[0] = ret;
2760 break;
2761 case EXCP_INTERRUPT:
2762 /* just indicate that signals should be handled asap */
2763 break;
2764 case EXCP_DEBUG:
2765 {
2766 int sig;
2767
2768 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2769 if (sig)
2770 {
2771 info.si_signo = sig;
2772 info.si_errno = 0;
2773 info.si_code = TARGET_TRAP_BRKPT;
2774 queue_signal(env, info.si_signo, &info);
2775 }
2776 }
2777 break;
2778 case 0xa0:
2779 case 0xc0:
2780 info.si_signo = SIGSEGV;
2781 info.si_errno = 0;
2782 info.si_code = TARGET_SEGV_MAPERR;
2783 info._sifields._sigfault._addr = env->tea;
2784 queue_signal(env, info.si_signo, &info);
2785 break;
2786
2787 default:
2788 printf ("Unhandled trap: 0x%x\n", trapnr);
2789 cpu_dump_state(cs, stderr, fprintf, 0);
2790 exit (1);
2791 }
2792 process_pending_signals (env);
2793 }
2794 }
2795 #endif
2796
2797 #ifdef TARGET_CRIS
2798 void cpu_loop(CPUCRISState *env)
2799 {
2800 CPUState *cs = CPU(cris_env_get_cpu(env));
2801 int trapnr, ret;
2802 target_siginfo_t info;
2803
2804 while (1) {
2805 trapnr = cpu_cris_exec (env);
2806 switch (trapnr) {
2807 case 0xaa:
2808 {
2809 info.si_signo = SIGSEGV;
2810 info.si_errno = 0;
2811 /* XXX: check env->error_code */
2812 info.si_code = TARGET_SEGV_MAPERR;
2813 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2814 queue_signal(env, info.si_signo, &info);
2815 }
2816 break;
2817 case EXCP_INTERRUPT:
2818 /* just indicate that signals should be handled asap */
2819 break;
2820 case EXCP_BREAK:
2821 ret = do_syscall(env,
2822 env->regs[9],
2823 env->regs[10],
2824 env->regs[11],
2825 env->regs[12],
2826 env->regs[13],
2827 env->pregs[7],
2828 env->pregs[11],
2829 0, 0);
2830 env->regs[10] = ret;
2831 break;
2832 case EXCP_DEBUG:
2833 {
2834 int sig;
2835
2836 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2837 if (sig)
2838 {
2839 info.si_signo = sig;
2840 info.si_errno = 0;
2841 info.si_code = TARGET_TRAP_BRKPT;
2842 queue_signal(env, info.si_signo, &info);
2843 }
2844 }
2845 break;
2846 default:
2847 printf ("Unhandled trap: 0x%x\n", trapnr);
2848 cpu_dump_state(cs, stderr, fprintf, 0);
2849 exit (1);
2850 }
2851 process_pending_signals (env);
2852 }
2853 }
2854 #endif
2855
2856 #ifdef TARGET_MICROBLAZE
2857 void cpu_loop(CPUMBState *env)
2858 {
2859 CPUState *cs = CPU(mb_env_get_cpu(env));
2860 int trapnr, ret;
2861 target_siginfo_t info;
2862
2863 while (1) {
2864 trapnr = cpu_mb_exec (env);
2865 switch (trapnr) {
2866 case 0xaa:
2867 {
2868 info.si_signo = SIGSEGV;
2869 info.si_errno = 0;
2870 /* XXX: check env->error_code */
2871 info.si_code = TARGET_SEGV_MAPERR;
2872 info._sifields._sigfault._addr = 0;
2873 queue_signal(env, info.si_signo, &info);
2874 }
2875 break;
2876 case EXCP_INTERRUPT:
2877 /* just indicate that signals should be handled asap */
2878 break;
2879 case EXCP_BREAK:
2880 /* Return address is 4 bytes after the call. */
2881 env->regs[14] += 4;
2882 env->sregs[SR_PC] = env->regs[14];
2883 ret = do_syscall(env,
2884 env->regs[12],
2885 env->regs[5],
2886 env->regs[6],
2887 env->regs[7],
2888 env->regs[8],
2889 env->regs[9],
2890 env->regs[10],
2891 0, 0);
2892 env->regs[3] = ret;
2893 break;
2894 case EXCP_HW_EXCP:
2895 env->regs[17] = env->sregs[SR_PC] + 4;
2896 if (env->iflags & D_FLAG) {
2897 env->sregs[SR_ESR] |= 1 << 12;
2898 env->sregs[SR_PC] -= 4;
2899 /* FIXME: if branch was immed, replay the imm as well. */
2900 }
2901
2902 env->iflags &= ~(IMM_FLAG | D_FLAG);
2903
2904 switch (env->sregs[SR_ESR] & 31) {
2905 case ESR_EC_DIVZERO:
2906 info.si_signo = SIGFPE;
2907 info.si_errno = 0;
2908 info.si_code = TARGET_FPE_FLTDIV;
2909 info._sifields._sigfault._addr = 0;
2910 queue_signal(env, info.si_signo, &info);
2911 break;
2912 case ESR_EC_FPU:
2913 info.si_signo = SIGFPE;
2914 info.si_errno = 0;
2915 if (env->sregs[SR_FSR] & FSR_IO) {
2916 info.si_code = TARGET_FPE_FLTINV;
2917 }
2918 if (env->sregs[SR_FSR] & FSR_DZ) {
2919 info.si_code = TARGET_FPE_FLTDIV;
2920 }
2921 info._sifields._sigfault._addr = 0;
2922 queue_signal(env, info.si_signo, &info);
2923 break;
2924 default:
2925 printf ("Unhandled hw-exception: 0x%x\n",
2926 env->sregs[SR_ESR] & ESR_EC_MASK);
2927 cpu_dump_state(cs, stderr, fprintf, 0);
2928 exit (1);
2929 break;
2930 }
2931 break;
2932 case EXCP_DEBUG:
2933 {
2934 int sig;
2935
2936 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2937 if (sig)
2938 {
2939 info.si_signo = sig;
2940 info.si_errno = 0;
2941 info.si_code = TARGET_TRAP_BRKPT;
2942 queue_signal(env, info.si_signo, &info);
2943 }
2944 }
2945 break;
2946 default:
2947 printf ("Unhandled trap: 0x%x\n", trapnr);
2948 cpu_dump_state(cs, stderr, fprintf, 0);
2949 exit (1);
2950 }
2951 process_pending_signals (env);
2952 }
2953 }
2954 #endif
2955
2956 #ifdef TARGET_M68K
2957
2958 void cpu_loop(CPUM68KState *env)
2959 {
2960 CPUState *cs = CPU(m68k_env_get_cpu(env));
2961 int trapnr;
2962 unsigned int n;
2963 target_siginfo_t info;
2964 TaskState *ts = env->opaque;
2965
2966 for(;;) {
2967 trapnr = cpu_m68k_exec(env);
2968 switch(trapnr) {
2969 case EXCP_ILLEGAL:
2970 {
2971 if (ts->sim_syscalls) {
2972 uint16_t nr;
2973 nr = lduw(env->pc + 2);
2974 env->pc += 4;
2975 do_m68k_simcall(env, nr);
2976 } else {
2977 goto do_sigill;
2978 }
2979 }
2980 break;
2981 case EXCP_HALT_INSN:
2982 /* Semihosing syscall. */
2983 env->pc += 4;
2984 do_m68k_semihosting(env, env->dregs[0]);
2985 break;
2986 case EXCP_LINEA:
2987 case EXCP_LINEF:
2988 case EXCP_UNSUPPORTED:
2989 do_sigill:
2990 info.si_signo = SIGILL;
2991 info.si_errno = 0;
2992 info.si_code = TARGET_ILL_ILLOPN;
2993 info._sifields._sigfault._addr = env->pc;
2994 queue_signal(env, info.si_signo, &info);
2995 break;
2996 case EXCP_TRAP0:
2997 {
2998 ts->sim_syscalls = 0;
2999 n = env->dregs[0];
3000 env->pc += 2;
3001 env->dregs[0] = do_syscall(env,
3002 n,
3003 env->dregs[1],
3004 env->dregs[2],
3005 env->dregs[3],
3006 env->dregs[4],
3007 env->dregs[5],
3008 env->aregs[0],
3009 0, 0);
3010 }
3011 break;
3012 case EXCP_INTERRUPT:
3013 /* just indicate that signals should be handled asap */
3014 break;
3015 case EXCP_ACCESS:
3016 {
3017 info.si_signo = SIGSEGV;
3018 info.si_errno = 0;
3019 /* XXX: check env->error_code */
3020 info.si_code = TARGET_SEGV_MAPERR;
3021 info._sifields._sigfault._addr = env->mmu.ar;
3022 queue_signal(env, info.si_signo, &info);
3023 }
3024 break;
3025 case EXCP_DEBUG:
3026 {
3027 int sig;
3028
3029 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3030 if (sig)
3031 {
3032 info.si_signo = sig;
3033 info.si_errno = 0;
3034 info.si_code = TARGET_TRAP_BRKPT;
3035 queue_signal(env, info.si_signo, &info);
3036 }
3037 }
3038 break;
3039 default:
3040 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
3041 trapnr);
3042 cpu_dump_state(cs, stderr, fprintf, 0);
3043 abort();
3044 }
3045 process_pending_signals(env);
3046 }
3047 }
3048 #endif /* TARGET_M68K */
3049
3050 #ifdef TARGET_ALPHA
3051 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3052 {
3053 target_ulong addr, val, tmp;
3054 target_siginfo_t info;
3055 int ret = 0;
3056
3057 addr = env->lock_addr;
3058 tmp = env->lock_st_addr;
3059 env->lock_addr = -1;
3060 env->lock_st_addr = 0;
3061
3062 start_exclusive();
3063 mmap_lock();
3064
3065 if (addr == tmp) {
3066 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3067 goto do_sigsegv;
3068 }
3069
3070 if (val == env->lock_value) {
3071 tmp = env->ir[reg];
3072 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3073 goto do_sigsegv;
3074 }
3075 ret = 1;
3076 }
3077 }
3078 env->ir[reg] = ret;
3079 env->pc += 4;
3080
3081 mmap_unlock();
3082 end_exclusive();
3083 return;
3084
3085 do_sigsegv:
3086 mmap_unlock();
3087 end_exclusive();
3088
3089 info.si_signo = TARGET_SIGSEGV;
3090 info.si_errno = 0;
3091 info.si_code = TARGET_SEGV_MAPERR;
3092 info._sifields._sigfault._addr = addr;
3093 queue_signal(env, TARGET_SIGSEGV, &info);
3094 }
3095
3096 void cpu_loop(CPUAlphaState *env)
3097 {
3098 CPUState *cs = CPU(alpha_env_get_cpu(env));
3099 int trapnr;
3100 target_siginfo_t info;
3101 abi_long sysret;
3102
3103 while (1) {
3104 trapnr = cpu_alpha_exec (env);
3105
3106 /* All of the traps imply a transition through PALcode, which
3107 implies an REI instruction has been executed. Which means
3108 that the intr_flag should be cleared. */
3109 env->intr_flag = 0;
3110
3111 switch (trapnr) {
3112 case EXCP_RESET:
3113 fprintf(stderr, "Reset requested. Exit\n");
3114 exit(1);
3115 break;
3116 case EXCP_MCHK:
3117 fprintf(stderr, "Machine check exception. Exit\n");
3118 exit(1);
3119 break;
3120 case EXCP_SMP_INTERRUPT:
3121 case EXCP_CLK_INTERRUPT:
3122 case EXCP_DEV_INTERRUPT:
3123 fprintf(stderr, "External interrupt. Exit\n");
3124 exit(1);
3125 break;
3126 case EXCP_MMFAULT:
3127 env->lock_addr = -1;
3128 info.si_signo = TARGET_SIGSEGV;
3129 info.si_errno = 0;
3130 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3131 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3132 info._sifields._sigfault._addr = env->trap_arg0;
3133 queue_signal(env, info.si_signo, &info);
3134 break;
3135 case EXCP_UNALIGN:
3136 env->lock_addr = -1;
3137 info.si_signo = TARGET_SIGBUS;
3138 info.si_errno = 0;
3139 info.si_code = TARGET_BUS_ADRALN;
3140 info._sifields._sigfault._addr = env->trap_arg0;
3141 queue_signal(env, info.si_signo, &info);
3142 break;
3143 case EXCP_OPCDEC:
3144 do_sigill:
3145 env->lock_addr = -1;
3146 info.si_signo = TARGET_SIGILL;
3147 info.si_errno = 0;
3148 info.si_code = TARGET_ILL_ILLOPC;
3149 info._sifields._sigfault._addr = env->pc;
3150 queue_signal(env, info.si_signo, &info);
3151 break;
3152 case EXCP_ARITH:
3153 env->lock_addr = -1;
3154 info.si_signo = TARGET_SIGFPE;
3155 info.si_errno = 0;
3156 info.si_code = TARGET_FPE_FLTINV;
3157 info._sifields._sigfault._addr = env->pc;
3158 queue_signal(env, info.si_signo, &info);
3159 break;
3160 case EXCP_FEN:
3161 /* No-op. Linux simply re-enables the FPU. */
3162 break;
3163 case EXCP_CALL_PAL:
3164 env->lock_addr = -1;
3165 switch (env->error_code) {
3166 case 0x80:
3167 /* BPT */
3168 info.si_signo = TARGET_SIGTRAP;
3169 info.si_errno = 0;
3170 info.si_code = TARGET_TRAP_BRKPT;
3171 info._sifields._sigfault._addr = env->pc;
3172 queue_signal(env, info.si_signo, &info);
3173 break;
3174 case 0x81:
3175 /* BUGCHK */
3176 info.si_signo = TARGET_SIGTRAP;
3177 info.si_errno = 0;
3178 info.si_code = 0;
3179 info._sifields._sigfault._addr = env->pc;
3180 queue_signal(env, info.si_signo, &info);
3181 break;
3182 case 0x83:
3183 /* CALLSYS */
3184 trapnr = env->ir[IR_V0];
3185 sysret = do_syscall(env, trapnr,
3186 env->ir[IR_A0], env->ir[IR_A1],
3187 env->ir[IR_A2], env->ir[IR_A3],
3188 env->ir[IR_A4], env->ir[IR_A5],
3189 0, 0);
3190 if (trapnr == TARGET_NR_sigreturn
3191 || trapnr == TARGET_NR_rt_sigreturn) {
3192 break;
3193 }
3194 /* Syscall writes 0 to V0 to bypass error check, similar
3195 to how this is handled internal to Linux kernel.
3196 (Ab)use trapnr temporarily as boolean indicating error. */
3197 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3198 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3199 env->ir[IR_A3] = trapnr;
3200 break;
3201 case 0x86:
3202 /* IMB */
3203 /* ??? We can probably elide the code using page_unprotect
3204 that is checking for self-modifying code. Instead we
3205 could simply call tb_flush here. Until we work out the
3206 changes required to turn off the extra write protection,
3207 this can be a no-op. */
3208 break;
3209 case 0x9E:
3210 /* RDUNIQUE */
3211 /* Handled in the translator for usermode. */
3212 abort();
3213 case 0x9F:
3214 /* WRUNIQUE */
3215 /* Handled in the translator for usermode. */
3216 abort();
3217 case 0xAA:
3218 /* GENTRAP */
3219 info.si_signo = TARGET_SIGFPE;
3220 switch (env->ir[IR_A0]) {
3221 case TARGET_GEN_INTOVF:
3222 info.si_code = TARGET_FPE_INTOVF;
3223 break;
3224 case TARGET_GEN_INTDIV:
3225 info.si_code = TARGET_FPE_INTDIV;
3226 break;
3227 case TARGET_GEN_FLTOVF:
3228 info.si_code = TARGET_FPE_FLTOVF;
3229 break;
3230 case TARGET_GEN_FLTUND:
3231 info.si_code = TARGET_FPE_FLTUND;
3232 break;
3233 case TARGET_GEN_FLTINV:
3234 info.si_code = TARGET_FPE_FLTINV;
3235 break;
3236 case TARGET_GEN_FLTINE:
3237 info.si_code = TARGET_FPE_FLTRES;
3238 break;
3239 case TARGET_GEN_ROPRAND:
3240 info.si_code = 0;
3241 break;
3242 default:
3243 info.si_signo = TARGET_SIGTRAP;
3244 info.si_code = 0;
3245 break;
3246 }
3247 info.si_errno = 0;
3248 info._sifields._sigfault._addr = env->pc;
3249 queue_signal(env, info.si_signo, &info);
3250 break;
3251 default:
3252 goto do_sigill;
3253 }
3254 break;
3255 case EXCP_DEBUG:
3256 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3257 if (info.si_signo) {
3258 env->lock_addr = -1;
3259 info.si_errno = 0;
3260 info.si_code = TARGET_TRAP_BRKPT;
3261 queue_signal(env, info.si_signo, &info);
3262 }
3263 break;
3264 case EXCP_STL_C:
3265 case EXCP_STQ_C:
3266 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3267 break;
3268 case EXCP_INTERRUPT:
3269 /* Just indicate that signals should be handled asap. */
3270 break;
3271 default:
3272 printf ("Unhandled trap: 0x%x\n", trapnr);
3273 cpu_dump_state(cs, stderr, fprintf, 0);
3274 exit (1);
3275 }
3276 process_pending_signals (env);
3277 }
3278 }
3279 #endif /* TARGET_ALPHA */
3280
3281 #ifdef TARGET_S390X
3282 void cpu_loop(CPUS390XState *env)
3283 {
3284 CPUState *cs = CPU(s390_env_get_cpu(env));
3285 int trapnr, n, sig;
3286 target_siginfo_t info;
3287 target_ulong addr;
3288
3289 while (1) {
3290 trapnr = cpu_s390x_exec(env);
3291 switch (trapnr) {
3292 case EXCP_INTERRUPT:
3293 /* Just indicate that signals should be handled asap. */
3294 break;
3295
3296 case EXCP_SVC:
3297 n = env->int_svc_code;
3298 if (!n) {
3299 /* syscalls > 255 */
3300 n = env->regs[1];
3301 }
3302 env->psw.addr += env->int_svc_ilen;
3303 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3304 env->regs[4], env->regs[5],
3305 env->regs[6], env->regs[7], 0, 0);
3306 break;
3307
3308 case EXCP_DEBUG:
3309 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3310 if (sig) {
3311 n = TARGET_TRAP_BRKPT;
3312 goto do_signal_pc;
3313 }
3314 break;
3315 case EXCP_PGM:
3316 n = env->int_pgm_code;
3317 switch (n) {
3318 case PGM_OPERATION:
3319 case PGM_PRIVILEGED:
3320 sig = SIGILL;
3321 n = TARGET_ILL_ILLOPC;
3322 goto do_signal_pc;
3323 case PGM_PROTECTION:
3324 case PGM_ADDRESSING:
3325 sig = SIGSEGV;
3326 /* XXX: check env->error_code */
3327 n = TARGET_SEGV_MAPERR;
3328 addr = env->__excp_addr;
3329 goto do_signal;
3330 case PGM_EXECUTE:
3331 case PGM_SPECIFICATION:
3332 case PGM_SPECIAL_OP:
3333 case PGM_OPERAND:
3334 do_sigill_opn:
3335 sig = SIGILL;
3336 n = TARGET_ILL_ILLOPN;
3337 goto do_signal_pc;
3338
3339 case PGM_FIXPT_OVERFLOW:
3340 sig = SIGFPE;
3341 n = TARGET_FPE_INTOVF;
3342 goto do_signal_pc;
3343 case PGM_FIXPT_DIVIDE:
3344 sig = SIGFPE;
3345 n = TARGET_FPE_INTDIV;
3346 goto do_signal_pc;
3347
3348 case PGM_DATA:
3349 n = (env->fpc >> 8) & 0xff;
3350 if (n == 0xff) {
3351 /* compare-and-trap */
3352 goto do_sigill_opn;
3353 } else {
3354 /* An IEEE exception, simulated or otherwise. */
3355 if (n & 0x80) {
3356 n = TARGET_FPE_FLTINV;
3357 } else if (n & 0x40) {
3358 n = TARGET_FPE_FLTDIV;
3359 } else if (n & 0x20) {
3360 n = TARGET_FPE_FLTOVF;
3361 } else if (n & 0x10) {
3362 n = TARGET_FPE_FLTUND;
3363 } else if (n & 0x08) {
3364 n = TARGET_FPE_FLTRES;
3365 } else {
3366 /* ??? Quantum exception; BFP, DFP error. */
3367 goto do_sigill_opn;
3368 }
3369 sig = SIGFPE;
3370 goto do_signal_pc;
3371 }
3372
3373 default:
3374 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3375 cpu_dump_state(cs, stderr, fprintf, 0);
3376 exit(1);
3377 }
3378 break;
3379
3380 do_signal_pc:
3381 addr = env->psw.addr;
3382 do_signal:
3383 info.si_signo = sig;
3384 info.si_errno = 0;
3385 info.si_code = n;
3386 info._sifields._sigfault._addr = addr;
3387 queue_signal(env, info.si_signo, &info);
3388 break;
3389
3390 default:
3391 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3392 cpu_dump_state(cs, stderr, fprintf, 0);
3393 exit(1);
3394 }
3395 process_pending_signals (env);
3396 }
3397 }
3398
3399 #endif /* TARGET_S390X */
3400
3401 THREAD CPUState *thread_cpu;
3402
3403 void task_settid(TaskState *ts)
3404 {
3405 if (ts->ts_tid == 0) {
3406 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3407 }
3408 }
3409
3410 void stop_all_tasks(void)
3411 {
3412 /*
3413 * We trust that when using NPTL, start_exclusive()
3414 * handles thread stopping correctly.
3415 */
3416 start_exclusive();
3417 }
3418
3419 /* Assumes contents are already zeroed. */
3420 void init_task_state(TaskState *ts)
3421 {
3422 int i;
3423
3424 ts->used = 1;
3425 ts->first_free = ts->sigqueue_table;
3426 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3427 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3428 }
3429 ts->sigqueue_table[i].next = NULL;
3430 }
3431
3432 CPUArchState *cpu_copy(CPUArchState *env)
3433 {
3434 CPUArchState *new_env = cpu_init(cpu_model);
3435 #if defined(TARGET_HAS_ICE)
3436 CPUBreakpoint *bp;
3437 CPUWatchpoint *wp;
3438 #endif
3439
3440 /* Reset non arch specific state */
3441 cpu_reset(ENV_GET_CPU(new_env));
3442
3443 memcpy(new_env, env, sizeof(CPUArchState));
3444
3445 /* Clone all break/watchpoints.
3446 Note: Once we support ptrace with hw-debug register access, make sure
3447 BP_CPU break/watchpoints are handled correctly on clone. */
3448 QTAILQ_INIT(&env->breakpoints);
3449 QTAILQ_INIT(&env->watchpoints);
3450 #if defined(TARGET_HAS_ICE)
3451 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
3452 cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
3453 }
3454 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
3455 cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
3456 wp->flags, NULL);
3457 }
3458 #endif
3459
3460 return new_env;
3461 }
3462
3463 static void handle_arg_help(const char *arg)
3464 {
3465 usage();
3466 }
3467
3468 static void handle_arg_log(const char *arg)
3469 {
3470 int mask;
3471
3472 mask = qemu_str_to_log_mask(arg);
3473 if (!mask) {
3474 qemu_print_log_usage(stdout);
3475 exit(1);
3476 }
3477 qemu_set_log(mask);
3478 }
3479
3480 static void handle_arg_log_filename(const char *arg)
3481 {
3482 qemu_set_log_filename(arg);
3483 }
3484
3485 static void handle_arg_set_env(const char *arg)
3486 {
3487 char *r, *p, *token;
3488 r = p = strdup(arg);
3489 while ((token = strsep(&p, ",")) != NULL) {
3490 if (envlist_setenv(envlist, token) != 0) {
3491 usage();
3492 }
3493 }
3494 free(r);
3495 }
3496
3497 static void handle_arg_unset_env(const char *arg)
3498 {
3499 char *r, *p, *token;
3500 r = p = strdup(arg);
3501 while ((token = strsep(&p, ",")) != NULL) {
3502 if (envlist_unsetenv(envlist, token) != 0) {
3503 usage();
3504 }
3505 }
3506 free(r);
3507 }
3508
3509 static void handle_arg_argv0(const char *arg)
3510 {
3511 argv0 = strdup(arg);
3512 }
3513
3514 static void handle_arg_stack_size(const char *arg)
3515 {
3516 char *p;
3517 guest_stack_size = strtoul(arg, &p, 0);
3518 if (guest_stack_size == 0) {
3519 usage();
3520 }
3521
3522 if (*p == 'M') {
3523 guest_stack_size *= 1024 * 1024;
3524 } else if (*p == 'k' || *p == 'K') {
3525 guest_stack_size *= 1024;
3526 }
3527 }
3528
3529 static void handle_arg_ld_prefix(const char *arg)
3530 {
3531 interp_prefix = strdup(arg);
3532 }
3533
3534 static void handle_arg_pagesize(const char *arg)
3535 {
3536 qemu_host_page_size = atoi(arg);
3537 if (qemu_host_page_size == 0 ||
3538 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3539 fprintf(stderr, "page size must be a power of two\n");
3540 exit(1);
3541 }
3542 }
3543
3544 static void handle_arg_gdb(const char *arg)
3545 {
3546 gdbstub_port = atoi(arg);
3547 }
3548
3549 static void handle_arg_uname(const char *arg)
3550 {
3551 qemu_uname_release = strdup(arg);
3552 }
3553
3554 static void handle_arg_cpu(const char *arg)
3555 {
3556 cpu_model = strdup(arg);
3557 if (cpu_model == NULL || is_help_option(cpu_model)) {
3558 /* XXX: implement xxx_cpu_list for targets that still miss it */
3559 #if defined(cpu_list)
3560 cpu_list(stdout, &fprintf);
3561 #endif
3562 exit(1);
3563 }
3564 }
3565
3566 #if defined(CONFIG_USE_GUEST_BASE)
3567 static void handle_arg_guest_base(const char *arg)
3568 {
3569 guest_base = strtol(arg, NULL, 0);
3570 have_guest_base = 1;
3571 }
3572
3573 static void handle_arg_reserved_va(const char *arg)
3574 {
3575 char *p;
3576 int shift = 0;
3577 reserved_va = strtoul(arg, &p, 0);
3578 switch (*p) {
3579 case 'k':
3580 case 'K':
3581 shift = 10;
3582 break;
3583 case 'M':
3584 shift = 20;
3585 break;
3586 case 'G':
3587 shift = 30;
3588 break;
3589 }
3590 if (shift) {
3591 unsigned long unshifted = reserved_va;
3592 p++;
3593 reserved_va <<= shift;
3594 if (((reserved_va >> shift) != unshifted)
3595 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3596 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3597 #endif
3598 ) {
3599 fprintf(stderr, "Reserved virtual address too big\n");
3600 exit(1);
3601 }
3602 }
3603 if (*p) {
3604 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3605 exit(1);
3606 }
3607 }
3608 #endif
3609
3610 static void handle_arg_singlestep(const char *arg)
3611 {
3612 singlestep = 1;
3613 }
3614
3615 static void handle_arg_strace(const char *arg)
3616 {
3617 do_strace = 1;
3618 }
3619
3620 static void handle_arg_version(const char *arg)
3621 {
3622 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
3623 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
3624 exit(0);
3625 }
3626
3627 struct qemu_argument {
3628 const char *argv;
3629 const char *env;
3630 bool has_arg;
3631 void (*handle_opt)(const char *arg);
3632 const char *example;
3633 const char *help;
3634 };
3635
3636 static const struct qemu_argument arg_table[] = {
3637 {"h", "", false, handle_arg_help,
3638 "", "print this help"},
3639 {"g", "QEMU_GDB", true, handle_arg_gdb,
3640 "port", "wait gdb connection to 'port'"},
3641 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3642 "path", "set the elf interpreter prefix to 'path'"},
3643 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3644 "size", "set the stack size to 'size' bytes"},
3645 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
3646 "model", "select CPU (-cpu help for list)"},
3647 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3648 "var=value", "sets targets environment variable (see below)"},
3649 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3650 "var", "unsets targets environment variable (see below)"},
3651 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3652 "argv0", "forces target process argv[0] to be 'argv0'"},
3653 {"r", "QEMU_UNAME", true, handle_arg_uname,
3654 "uname", "set qemu uname release string to 'uname'"},
3655 #if defined(CONFIG_USE_GUEST_BASE)
3656 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3657 "address", "set guest_base address to 'address'"},
3658 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3659 "size", "reserve 'size' bytes for guest virtual address space"},
3660 #endif
3661 {"d", "QEMU_LOG", true, handle_arg_log,
3662 "item[,...]", "enable logging of specified items "
3663 "(use '-d help' for a list of items)"},
3664 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
3665 "logfile", "write logs to 'logfile' (default stderr)"},
3666 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3667 "pagesize", "set the host page size to 'pagesize'"},
3668 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3669 "", "run in singlestep mode"},
3670 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3671 "", "log system calls"},
3672 {"version", "QEMU_VERSION", false, handle_arg_version,
3673 "", "display version information and exit"},
3674 {NULL, NULL, false, NULL, NULL, NULL}
3675 };
3676
3677 static void usage(void)
3678 {
3679 const struct qemu_argument *arginfo;
3680 int maxarglen;
3681 int maxenvlen;
3682
3683 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3684 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
3685 "\n"
3686 "Options and associated environment variables:\n"
3687 "\n");
3688
3689 /* Calculate column widths. We must always have at least enough space
3690 * for the column header.
3691 */
3692 maxarglen = strlen("Argument");
3693 maxenvlen = strlen("Env-variable");
3694
3695 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3696 int arglen = strlen(arginfo->argv);
3697 if (arginfo->has_arg) {
3698 arglen += strlen(arginfo->example) + 1;
3699 }
3700 if (strlen(arginfo->env) > maxenvlen) {
3701 maxenvlen = strlen(arginfo->env);
3702 }
3703 if (arglen > maxarglen) {
3704 maxarglen = arglen;
3705 }
3706 }
3707
3708 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3709 maxenvlen, "Env-variable");
3710
3711 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3712 if (arginfo->has_arg) {
3713 printf("-%s %-*s %-*s %s\n", arginfo->argv,
3714 (int)(maxarglen - strlen(arginfo->argv) - 1),
3715 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
3716 } else {
3717 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
3718 maxenvlen, arginfo->env,
3719 arginfo->help);
3720 }
3721 }
3722
3723 printf("\n"
3724 "Defaults:\n"
3725 "QEMU_LD_PREFIX = %s\n"
3726 "QEMU_STACK_SIZE = %ld byte\n",
3727 interp_prefix,
3728 guest_stack_size);
3729
3730 printf("\n"
3731 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3732 "QEMU_UNSET_ENV environment variables to set and unset\n"
3733 "environment variables for the target process.\n"
3734 "It is possible to provide several variables by separating them\n"
3735 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3736 "provide the -E and -U options multiple times.\n"
3737 "The following lines are equivalent:\n"
3738 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3739 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3740 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3741 "Note that if you provide several changes to a single variable\n"
3742 "the last change will stay in effect.\n");
3743
3744 exit(1);
3745 }
3746
3747 static int parse_args(int argc, char **argv)
3748 {
3749 const char *r;
3750 int optind;
3751 const struct qemu_argument *arginfo;
3752
3753 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3754 if (arginfo->env == NULL) {
3755 continue;
3756 }
3757
3758 r = getenv(arginfo->env);
3759 if (r != NULL) {
3760 arginfo->handle_opt(r);
3761 }
3762 }
3763
3764 optind = 1;
3765 for (;;) {
3766 if (optind >= argc) {
3767 break;
3768 }
3769 r = argv[optind];
3770 if (r[0] != '-') {
3771 break;
3772 }
3773 optind++;
3774 r++;
3775 if (!strcmp(r, "-")) {
3776 break;
3777 }
3778
3779 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3780 if (!strcmp(r, arginfo->argv)) {
3781 if (arginfo->has_arg) {
3782 if (optind >= argc) {
3783 usage();
3784 }
3785 arginfo->handle_opt(argv[optind]);
3786 optind++;
3787 } else {
3788 arginfo->handle_opt(NULL);
3789 }
3790 break;
3791 }
3792 }
3793
3794 /* no option matched the current argv */
3795 if (arginfo->handle_opt == NULL) {
3796 usage();
3797 }
3798 }
3799
3800 if (optind >= argc) {
3801 usage();
3802 }
3803
3804 filename = argv[optind];
3805 exec_path = argv[optind];
3806
3807 return optind;
3808 }
3809
3810 int main(int argc, char **argv, char **envp)
3811 {
3812 struct target_pt_regs regs1, *regs = &regs1;
3813 struct image_info info1, *info = &info1;
3814 struct linux_binprm bprm;
3815 TaskState *ts;
3816 CPUArchState *env;
3817 CPUState *cpu;
3818 int optind;
3819 char **target_environ, **wrk;
3820 char **target_argv;
3821 int target_argc;
3822 int i;
3823 int ret;
3824 int execfd;
3825
3826 module_call_init(MODULE_INIT_QOM);
3827
3828 qemu_init_auxval(envp);
3829 qemu_cache_utils_init();
3830
3831 if ((envlist = envlist_create()) == NULL) {
3832 (void) fprintf(stderr, "Unable to allocate envlist\n");
3833 exit(1);
3834 }
3835
3836 /* add current environment into the list */
3837 for (wrk = environ; *wrk != NULL; wrk++) {
3838 (void) envlist_setenv(envlist, *wrk);
3839 }
3840
3841 /* Read the stack limit from the kernel. If it's "unlimited",
3842 then we can do little else besides use the default. */
3843 {
3844 struct rlimit lim;
3845 if (getrlimit(RLIMIT_STACK, &lim) == 0
3846 && lim.rlim_cur != RLIM_INFINITY
3847 && lim.rlim_cur == (target_long)lim.rlim_cur) {
3848 guest_stack_size = lim.rlim_cur;
3849 }
3850 }
3851
3852 cpu_model = NULL;
3853 #if defined(cpudef_setup)
3854 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3855 #endif
3856
3857 optind = parse_args(argc, argv);
3858
3859 /* Zero out regs */
3860 memset(regs, 0, sizeof(struct target_pt_regs));
3861
3862 /* Zero out image_info */
3863 memset(info, 0, sizeof(struct image_info));
3864
3865 memset(&bprm, 0, sizeof (bprm));
3866
3867 /* Scan interp_prefix dir for replacement files. */
3868 init_paths(interp_prefix);
3869
3870 init_qemu_uname_release();
3871
3872 if (cpu_model == NULL) {
3873 #if defined(TARGET_I386)
3874 #ifdef TARGET_X86_64
3875 cpu_model = "qemu64";
3876 #else
3877 cpu_model = "qemu32";
3878 #endif
3879 #elif defined(TARGET_ARM)
3880 cpu_model = "any";
3881 #elif defined(TARGET_UNICORE32)
3882 cpu_model = "any";
3883 #elif defined(TARGET_M68K)
3884 cpu_model = "any";
3885 #elif defined(TARGET_SPARC)
3886 #ifdef TARGET_SPARC64
3887 cpu_model = "TI UltraSparc II";
3888 #else
3889 cpu_model = "Fujitsu MB86904";
3890 #endif
3891 #elif defined(TARGET_MIPS)
3892 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3893 cpu_model = "20Kc";
3894 #else
3895 cpu_model = "24Kf";
3896 #endif
3897 #elif defined TARGET_OPENRISC
3898 cpu_model = "or1200";
3899 #elif defined(TARGET_PPC)
3900 #ifdef TARGET_PPC64
3901 cpu_model = "970fx";
3902 #else
3903 cpu_model = "750";
3904 #endif
3905 #else
3906 cpu_model = "any";
3907 #endif
3908 }
3909 tcg_exec_init(0);
3910 cpu_exec_init_all();
3911 /* NOTE: we need to init the CPU at this stage to get
3912 qemu_host_page_size */
3913 env = cpu_init(cpu_model);
3914 if (!env) {
3915 fprintf(stderr, "Unable to find CPU definition\n");
3916 exit(1);
3917 }
3918 cpu = ENV_GET_CPU(env);
3919 cpu_reset(cpu);
3920
3921 thread_cpu = cpu;
3922
3923 if (getenv("QEMU_STRACE")) {
3924 do_strace = 1;
3925 }
3926
3927 target_environ = envlist_to_environ(envlist, NULL);
3928 envlist_free(envlist);
3929
3930 #if defined(CONFIG_USE_GUEST_BASE)
3931 /*
3932 * Now that page sizes are configured in cpu_init() we can do
3933 * proper page alignment for guest_base.
3934 */
3935 guest_base = HOST_PAGE_ALIGN(guest_base);
3936
3937 if (reserved_va || have_guest_base) {
3938 guest_base = init_guest_space(guest_base, reserved_va, 0,
3939 have_guest_base);
3940 if (guest_base == (unsigned long)-1) {
3941 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3942 "space for use as guest address space (check your virtual "
3943 "memory ulimit setting or reserve less using -R option)\n",
3944 reserved_va);
3945 exit(1);
3946 }
3947
3948 if (reserved_va) {
3949 mmap_next_start = reserved_va;
3950 }
3951 }
3952 #endif /* CONFIG_USE_GUEST_BASE */
3953
3954 /*
3955 * Read in mmap_min_addr kernel parameter. This value is used
3956 * When loading the ELF image to determine whether guest_base
3957 * is needed. It is also used in mmap_find_vma.
3958 */
3959 {
3960 FILE *fp;
3961
3962 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3963 unsigned long tmp;
3964 if (fscanf(fp, "%lu", &tmp) == 1) {
3965 mmap_min_addr = tmp;
3966 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3967 }
3968 fclose(fp);
3969 }
3970 }
3971
3972 /*
3973 * Prepare copy of argv vector for target.
3974 */
3975 target_argc = argc - optind;
3976 target_argv = calloc(target_argc + 1, sizeof (char *));
3977 if (target_argv == NULL) {
3978 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
3979 exit(1);
3980 }
3981
3982 /*
3983 * If argv0 is specified (using '-0' switch) we replace
3984 * argv[0] pointer with the given one.
3985 */
3986 i = 0;
3987 if (argv0 != NULL) {
3988 target_argv[i++] = strdup(argv0);
3989 }
3990 for (; i < target_argc; i++) {
3991 target_argv[i] = strdup(argv[optind + i]);
3992 }
3993 target_argv[target_argc] = NULL;
3994
3995 ts = g_malloc0 (sizeof(TaskState));
3996 init_task_state(ts);
3997 /* build Task State */
3998 ts->info = info;
3999 ts->bprm = &bprm;
4000 env->opaque = ts;
4001 task_settid(ts);
4002
4003 execfd = qemu_getauxval(AT_EXECFD);
4004 if (execfd == 0) {
4005 execfd = open(filename, O_RDONLY);
4006 if (execfd < 0) {
4007 printf("Error while loading %s: %s\n", filename, strerror(errno));
4008 _exit(1);
4009 }
4010 }
4011
4012 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
4013 info, &bprm);
4014 if (ret != 0) {
4015 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4016 _exit(1);
4017 }
4018
4019 for (wrk = target_environ; *wrk; wrk++) {
4020 free(*wrk);
4021 }
4022
4023 free(target_environ);
4024
4025 if (qemu_log_enabled()) {
4026 #if defined(CONFIG_USE_GUEST_BASE)
4027 qemu_log("guest_base 0x%lx\n", guest_base);
4028 #endif
4029 log_page_dump();
4030
4031 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4032 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4033 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4034 info->start_code);
4035 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4036 info->start_data);
4037 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4038 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4039 info->start_stack);
4040 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4041 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4042 }
4043
4044 target_set_brk(info->brk);
4045 syscall_init();
4046 signal_init();
4047
4048 #if defined(CONFIG_USE_GUEST_BASE)
4049 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4050 generating the prologue until now so that the prologue can take
4051 the real value of GUEST_BASE into account. */
4052 tcg_prologue_init(&tcg_ctx);
4053 #endif
4054
4055 #if defined(TARGET_I386)
4056 cpu_x86_set_cpl(env, 3);
4057
4058 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4059 env->hflags |= HF_PE_MASK;
4060 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4061 env->cr[4] |= CR4_OSFXSR_MASK;
4062 env->hflags |= HF_OSFXSR_MASK;
4063 }
4064 #ifndef TARGET_ABI32
4065 /* enable 64 bit mode if possible */
4066 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4067 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4068 exit(1);
4069 }
4070 env->cr[4] |= CR4_PAE_MASK;
4071 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4072 env->hflags |= HF_LMA_MASK;
4073 #endif
4074
4075 /* flags setup : we activate the IRQs by default as in user mode */
4076 env->eflags |= IF_MASK;
4077
4078 /* linux register setup */
4079 #ifndef TARGET_ABI32
4080 env->regs[R_EAX] = regs->rax;
4081 env->regs[R_EBX] = regs->rbx;
4082 env->regs[R_ECX] = regs->rcx;
4083 env->regs[R_EDX] = regs->rdx;
4084 env->regs[R_ESI] = regs->rsi;
4085 env->regs[R_EDI] = regs->rdi;
4086 env->regs[R_EBP] = regs->rbp;
4087 env->regs[R_ESP] = regs->rsp;
4088 env->eip = regs->rip;
4089 #else
4090 env->regs[R_EAX] = regs->eax;
4091 env->regs[R_EBX] = regs->ebx;
4092 env->regs[R_ECX] = regs->ecx;
4093 env->regs[R_EDX] = regs->edx;
4094 env->regs[R_ESI] = regs->esi;
4095 env->regs[R_EDI] = regs->edi;
4096 env->regs[R_EBP] = regs->ebp;
4097 env->regs[R_ESP] = regs->esp;
4098 env->eip = regs->eip;
4099 #endif
4100
4101 /* linux interrupt setup */
4102 #ifndef TARGET_ABI32
4103 env->idt.limit = 511;
4104 #else
4105 env->idt.limit = 255;
4106 #endif
4107 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4108 PROT_READ|PROT_WRITE,
4109 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4110 idt_table = g2h(env->idt.base);
4111 set_idt(0, 0);
4112 set_idt(1, 0);
4113 set_idt(2, 0);
4114 set_idt(3, 3);
4115 set_idt(4, 3);
4116 set_idt(5, 0);
4117 set_idt(6, 0);
4118 set_idt(7, 0);
4119 set_idt(8, 0);
4120 set_idt(9, 0);
4121 set_idt(10, 0);
4122 set_idt(11, 0);
4123 set_idt(12, 0);
4124 set_idt(13, 0);
4125 set_idt(14, 0);
4126 set_idt(15, 0);
4127 set_idt(16, 0);
4128 set_idt(17, 0);
4129 set_idt(18, 0);
4130 set_idt(19, 0);
4131 set_idt(0x80, 3);
4132
4133 /* linux segment setup */
4134 {
4135 uint64_t *gdt_table;
4136 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4137 PROT_READ|PROT_WRITE,
4138 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4139 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4140 gdt_table = g2h(env->gdt.base);
4141 #ifdef TARGET_ABI32
4142 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4143 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4144 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4145 #else
4146 /* 64 bit code segment */
4147 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4148 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4149 DESC_L_MASK |
4150 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4151 #endif
4152 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4153 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4154 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4155 }
4156 cpu_x86_load_seg(env, R_CS, __USER_CS);
4157 cpu_x86_load_seg(env, R_SS, __USER_DS);
4158 #ifdef TARGET_ABI32
4159 cpu_x86_load_seg(env, R_DS, __USER_DS);
4160 cpu_x86_load_seg(env, R_ES, __USER_DS);
4161 cpu_x86_load_seg(env, R_FS, __USER_DS);
4162 cpu_x86_load_seg(env, R_GS, __USER_DS);
4163 /* This hack makes Wine work... */
4164 env->segs[R_FS].selector = 0;
4165 #else
4166 cpu_x86_load_seg(env, R_DS, 0);
4167 cpu_x86_load_seg(env, R_ES, 0);
4168 cpu_x86_load_seg(env, R_FS, 0);
4169 cpu_x86_load_seg(env, R_GS, 0);
4170 #endif
4171 #elif defined(TARGET_AARCH64)
4172 {
4173 int i;
4174
4175 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4176 fprintf(stderr,
4177 "The selected ARM CPU does not support 64 bit mode\n");
4178 exit(1);
4179 }
4180
4181 for (i = 0; i < 31; i++) {
4182 env->xregs[i] = regs->regs[i];
4183 }
4184 env->pc = regs->pc;
4185 env->xregs[31] = regs->sp;
4186 }
4187 #elif defined(TARGET_ARM)
4188 {
4189 int i;
4190 cpsr_write(env, regs->uregs[16], 0xffffffff);
4191 for(i = 0; i < 16; i++) {
4192 env->regs[i] = regs->uregs[i];
4193 }
4194 /* Enable BE8. */
4195 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4196 && (info->elf_flags & EF_ARM_BE8)) {
4197 env->bswap_code = 1;
4198 }
4199 }
4200 #elif defined(TARGET_UNICORE32)
4201 {
4202 int i;
4203 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4204 for (i = 0; i < 32; i++) {
4205 env->regs[i] = regs->uregs[i];
4206 }
4207 }
4208 #elif defined(TARGET_SPARC)
4209 {
4210 int i;
4211 env->pc = regs->pc;
4212 env->npc = regs->npc;
4213 env->y = regs->y;
4214 for(i = 0; i < 8; i++)
4215 env->gregs[i] = regs->u_regs[i];
4216 for(i = 0; i < 8; i++)
4217 env->regwptr[i] = regs->u_regs[i + 8];
4218 }
4219 #elif defined(TARGET_PPC)
4220 {
4221 int i;
4222
4223 #if defined(TARGET_PPC64)
4224 #if defined(TARGET_ABI32)
4225 env->msr &= ~((target_ulong)1 << MSR_SF);
4226 #else
4227 env->msr |= (target_ulong)1 << MSR_SF;
4228 #endif
4229 #endif
4230 env->nip = regs->nip;
4231 for(i = 0; i < 32; i++) {
4232 env->gpr[i] = regs->gpr[i];
4233 }
4234 }
4235 #elif defined(TARGET_M68K)
4236 {
4237 env->pc = regs->pc;
4238 env->dregs[0] = regs->d0;
4239 env->dregs[1] = regs->d1;
4240 env->dregs[2] = regs->d2;
4241 env->dregs[3] = regs->d3;
4242 env->dregs[4] = regs->d4;
4243 env->dregs[5] = regs->d5;
4244 env->dregs[6] = regs->d6;
4245 env->dregs[7] = regs->d7;
4246 env->aregs[0] = regs->a0;
4247 env->aregs[1] = regs->a1;
4248 env->aregs[2] = regs->a2;
4249 env->aregs[3] = regs->a3;
4250 env->aregs[4] = regs->a4;
4251 env->aregs[5] = regs->a5;
4252 env->aregs[6] = regs->a6;
4253 env->aregs[7] = regs->usp;
4254 env->sr = regs->sr;
4255 ts->sim_syscalls = 1;
4256 }
4257 #elif defined(TARGET_MICROBLAZE)
4258 {
4259 env->regs[0] = regs->r0;
4260 env->regs[1] = regs->r1;
4261 env->regs[2] = regs->r2;
4262 env->regs[3] = regs->r3;
4263 env->regs[4] = regs->r4;
4264 env->regs[5] = regs->r5;
4265 env->regs[6] = regs->r6;
4266 env->regs[7] = regs->r7;
4267 env->regs[8] = regs->r8;
4268 env->regs[9] = regs->r9;
4269 env->regs[10] = regs->r10;
4270 env->regs[11] = regs->r11;
4271 env->regs[12] = regs->r12;
4272 env->regs[13] = regs->r13;
4273 env->regs[14] = regs->r14;
4274 env->regs[15] = regs->r15;
4275 env->regs[16] = regs->r16;
4276 env->regs[17] = regs->r17;
4277 env->regs[18] = regs->r18;
4278 env->regs[19] = regs->r19;
4279 env->regs[20] = regs->r20;
4280 env->regs[21] = regs->r21;
4281 env->regs[22] = regs->r22;
4282 env->regs[23] = regs->r23;
4283 env->regs[24] = regs->r24;
4284 env->regs[25] = regs->r25;
4285 env->regs[26] = regs->r26;
4286 env->regs[27] = regs->r27;
4287 env->regs[28] = regs->r28;
4288 env->regs[29] = regs->r29;
4289 env->regs[30] = regs->r30;
4290 env->regs[31] = regs->r31;
4291 env->sregs[SR_PC] = regs->pc;
4292 }
4293 #elif defined(TARGET_MIPS)
4294 {
4295 int i;
4296
4297 for(i = 0; i < 32; i++) {
4298 env->active_tc.gpr[i] = regs->regs[i];
4299 }
4300 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4301 if (regs->cp0_epc & 1) {
4302 env->hflags |= MIPS_HFLAG_M16;
4303 }
4304 }
4305 #elif defined(TARGET_OPENRISC)
4306 {
4307 int i;
4308
4309 for (i = 0; i < 32; i++) {
4310 env->gpr[i] = regs->gpr[i];
4311 }
4312
4313 env->sr = regs->sr;
4314 env->pc = regs->pc;
4315 }
4316 #elif defined(TARGET_SH4)
4317 {
4318 int i;
4319
4320 for(i = 0; i < 16; i++) {
4321 env->gregs[i] = regs->regs[i];
4322 }
4323 env->pc = regs->pc;
4324 }
4325 #elif defined(TARGET_ALPHA)
4326 {
4327 int i;
4328
4329 for(i = 0; i < 28; i++) {
4330 env->ir[i] = ((abi_ulong *)regs)[i];
4331 }
4332 env->ir[IR_SP] = regs->usp;
4333 env->pc = regs->pc;
4334 }
4335 #elif defined(TARGET_CRIS)
4336 {
4337 env->regs[0] = regs->r0;
4338 env->regs[1] = regs->r1;
4339 env->regs[2] = regs->r2;
4340 env->regs[3] = regs->r3;
4341 env->regs[4] = regs->r4;
4342 env->regs[5] = regs->r5;
4343 env->regs[6] = regs->r6;
4344 env->regs[7] = regs->r7;
4345 env->regs[8] = regs->r8;
4346 env->regs[9] = regs->r9;
4347 env->regs[10] = regs->r10;
4348 env->regs[11] = regs->r11;
4349 env->regs[12] = regs->r12;
4350 env->regs[13] = regs->r13;
4351 env->regs[14] = info->start_stack;
4352 env->regs[15] = regs->acr;
4353 env->pc = regs->erp;
4354 }
4355 #elif defined(TARGET_S390X)
4356 {
4357 int i;
4358 for (i = 0; i < 16; i++) {
4359 env->regs[i] = regs->gprs[i];
4360 }
4361 env->psw.mask = regs->psw.mask;
4362 env->psw.addr = regs->psw.addr;
4363 }
4364 #else
4365 #error unsupported target CPU
4366 #endif
4367
4368 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4369 ts->stack_base = info->start_stack;
4370 ts->heap_base = info->brk;
4371 /* This will be filled in on the first SYS_HEAPINFO call. */
4372 ts->heap_limit = 0;
4373 #endif
4374
4375 if (gdbstub_port) {
4376 if (gdbserver_start(gdbstub_port) < 0) {
4377 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4378 gdbstub_port);
4379 exit(1);
4380 }
4381 gdb_handlesig(cpu, 0);
4382 }
4383 cpu_loop(env);
4384 /* never exits */
4385 return 0;
4386 }
QEmu