target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/qmp/qerror.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32 #include "kvm_arm.h"
  33
  34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  35 {
  36     ARMCPU *cpu = ARM_CPU(cs);
  37
  38     cpu->env.regs[15] = value;
  39 }
  40
  41 static bool arm_cpu_has_work(CPUState *cs)
  42 {
  43     ARMCPU *cpu = ARM_CPU(cs);
  44
  45     return !cpu->powered_off
  46         && cs->interrupt_request &
  47         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  48          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  49          | CPU_INTERRUPT_EXITTB);
  50 }
  51
  52 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  53 {
  54     /* Reset a single ARMCPRegInfo register */
  55     ARMCPRegInfo *ri = value;
  56     ARMCPU *cpu = opaque;
  57
  58     if (ri->type & ARM_CP_SPECIAL) {
  59         return;
  60     }
  61
  62     if (ri->resetfn) {
  63         ri->resetfn(&cpu->env, ri);
  64         return;
  65     }
  66
  67     /* A zero offset is never possible as it would be regs[0]
  68      * so we use it to indicate that reset is being handled elsewhere.
  69      * This is basically only used for fields in non-core coprocessors
  70      * (like the pxa2xx ones).
  71      */
  72     if (!ri->fieldoffset) {
  73         return;
  74     }
  75
  76     if (cpreg_field_is_64bit(ri)) {
  77         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  78     } else {
  79         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  80     }
  81 }
  82
  83 /* CPUClass::reset() */
  84 static void arm_cpu_reset(CPUState *s)
  85 {
  86     ARMCPU *cpu = ARM_CPU(s);
  87     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  88     CPUARMState *env = &cpu->env;
  89
  90     acc->parent_reset(s);
  91
  92     memset(env, 0, offsetof(CPUARMState, features));
  93     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  94     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  95     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  96     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  97     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
  98
  99     cpu->powered_off = cpu->start_powered_off;
 100     s->halted = cpu->start_powered_off;
 101
 102     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 103         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 104     }
 105
 106     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 107         /* 64 bit CPUs always start in 64 bit mode */
 108         env->aarch64 = 1;
 109 #if defined(CONFIG_USER_ONLY)
 110         env->pstate = PSTATE_MODE_EL0t;
 111         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 112         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 113         /* and to the FP/Neon instructions */
 114         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
 115 #else
 116         /* Reset into the highest available EL */
 117         if (arm_feature(env, ARM_FEATURE_EL3)) {
 118             env->pstate = PSTATE_MODE_EL3h;
 119         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 120             env->pstate = PSTATE_MODE_EL2h;
 121         } else {
 122             env->pstate = PSTATE_MODE_EL1h;
 123         }
 124         env->pc = cpu->rvbar;
 125 #endif
 126     } else {
 127 #if defined(CONFIG_USER_ONLY)
 128         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 129         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
 130 #endif
 131     }
 132
 133 #if defined(CONFIG_USER_ONLY)
 134     env->uncached_cpsr = ARM_CPU_MODE_USR;
 135     /* For user mode we must enable access to coprocessors */
 136     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 137     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 138         env->cp15.c15_cpar = 3;
 139     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 140         env->cp15.c15_cpar = 1;
 141     }
 142 #else
 143     /* SVC mode with interrupts disabled.  */
 144     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 145     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 146     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 147      * clear at reset. Initial SP and PC are loaded from ROM.
 148      */
 149     if (IS_M(env)) {
 150         uint32_t initial_msp; /* Loaded from 0x0 */
 151         uint32_t initial_pc; /* Loaded from 0x4 */
 152         uint8_t *rom;
 153
 154         env->daif &= ~PSTATE_I;
 155         rom = rom_ptr(0);
 156         if (rom) {
 157             /* Address zero is covered by ROM which hasn't yet been
 158              * copied into physical memory.
 159              */
 160             initial_msp = ldl_p(rom);
 161             initial_pc = ldl_p(rom + 4);
 162         } else {
 163             /* Address zero not covered by a ROM blob, or the ROM blob
 164              * is in non-modifiable memory and this is a second reset after
 165              * it got copied into memory. In the latter case, rom_ptr
 166              * will return a NULL pointer and we should use ldl_phys instead.
 167              */
 168             initial_msp = ldl_phys(s->as, 0);
 169             initial_pc = ldl_phys(s->as, 4);
 170         }
 171
 172         env->regs[13] = initial_msp & 0xFFFFFFFC;
 173         env->regs[15] = initial_pc & ~1;
 174         env->thumb = initial_pc & 1;
 175     }
 176
 177     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 178      * executing as AArch32 then check if highvecs are enabled and
 179      * adjust the PC accordingly.
 180      */
 181     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 182         env->regs[15] = 0xFFFF0000;
 183     }
 184
 185     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 186 #endif
 187     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 188     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 189     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 190     set_float_detect_tininess(float_tininess_before_rounding,
 191                               &env->vfp.fp_status);
 192     set_float_detect_tininess(float_tininess_before_rounding,
 193                               &env->vfp.standard_fp_status);
 194     tlb_flush(s, 1);
 195
 196 #ifndef CONFIG_USER_ONLY
 197     if (kvm_enabled()) {
 198         kvm_arm_reset_vcpu(cpu);
 199     }
 200 #endif
 201
 202     hw_breakpoint_update_all(cpu);
 203     hw_watchpoint_update_all(cpu);
 204 }
 205
 206 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 207 {
 208     CPUClass *cc = CPU_GET_CLASS(cs);
 209     CPUARMState *env = cs->env_ptr;
 210     uint32_t cur_el = arm_current_el(env);
 211     bool secure = arm_is_secure(env);
 212     uint32_t target_el;
 213     uint32_t excp_idx;
 214     bool ret = false;
 215
 216     if (interrupt_request & CPU_INTERRUPT_FIQ) {
 217         excp_idx = EXCP_FIQ;
 218         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 219         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 220             cs->exception_index = excp_idx;
 221             env->exception.target_el = target_el;
 222             cc->do_interrupt(cs);
 223             ret = true;
 224         }
 225     }
 226     if (interrupt_request & CPU_INTERRUPT_HARD) {
 227         excp_idx = EXCP_IRQ;
 228         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 229         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 230             cs->exception_index = excp_idx;
 231             env->exception.target_el = target_el;
 232             cc->do_interrupt(cs);
 233             ret = true;
 234         }
 235     }
 236     if (interrupt_request & CPU_INTERRUPT_VIRQ) {
 237         excp_idx = EXCP_VIRQ;
 238         target_el = 1;
 239         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 240             cs->exception_index = excp_idx;
 241             env->exception.target_el = target_el;
 242             cc->do_interrupt(cs);
 243             ret = true;
 244         }
 245     }
 246     if (interrupt_request & CPU_INTERRUPT_VFIQ) {
 247         excp_idx = EXCP_VFIQ;
 248         target_el = 1;
 249         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 250             cs->exception_index = excp_idx;
 251             env->exception.target_el = target_el;
 252             cc->do_interrupt(cs);
 253             ret = true;
 254         }
 255     }
 256
 257     return ret;
 258 }
 259
 260 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 261 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 262 {
 263     CPUClass *cc = CPU_GET_CLASS(cs);
 264     ARMCPU *cpu = ARM_CPU(cs);
 265     CPUARMState *env = &cpu->env;
 266     bool ret = false;
 267
 268
 269     if (interrupt_request & CPU_INTERRUPT_FIQ
 270         && !(env->daif & PSTATE_F)) {
 271         cs->exception_index = EXCP_FIQ;
 272         cc->do_interrupt(cs);
 273         ret = true;
 274     }
 275     /* ARMv7-M interrupt return works by loading a magic value
 276      * into the PC.  On real hardware the load causes the
 277      * return to occur.  The qemu implementation performs the
 278      * jump normally, then does the exception return when the
 279      * CPU tries to execute code at the magic address.
 280      * This will cause the magic PC value to be pushed to
 281      * the stack if an interrupt occurred at the wrong time.
 282      * We avoid this by disabling interrupts when
 283      * pc contains a magic address.
 284      */
 285     if (interrupt_request & CPU_INTERRUPT_HARD
 286         && !(env->daif & PSTATE_I)
 287         && (env->regs[15] < 0xfffffff0)) {
 288         cs->exception_index = EXCP_IRQ;
 289         cc->do_interrupt(cs);
 290         ret = true;
 291     }
 292     return ret;
 293 }
 294 #endif
 295
 296 #ifndef CONFIG_USER_ONLY
 297 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 298 {
 299     ARMCPU *cpu = opaque;
 300     CPUARMState *env = &cpu->env;
 301     CPUState *cs = CPU(cpu);
 302     static const int mask[] = {
 303         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 304         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 305         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 306         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 307     };
 308
 309     switch (irq) {
 310     case ARM_CPU_VIRQ:
 311     case ARM_CPU_VFIQ:
 312         if (!arm_feature(env, ARM_FEATURE_EL2)) {
 313             hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
 314                      __func__, irq);
 315         }
 316         /* fall through */
 317     case ARM_CPU_IRQ:
 318     case ARM_CPU_FIQ:
 319         if (level) {
 320             cpu_interrupt(cs, mask[irq]);
 321         } else {
 322             cpu_reset_interrupt(cs, mask[irq]);
 323         }
 324         break;
 325     default:
 326         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 327     }
 328 }
 329
 330 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 331 {
 332 #ifdef CONFIG_KVM
 333     ARMCPU *cpu = opaque;
 334     CPUState *cs = CPU(cpu);
 335     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 336
 337     switch (irq) {
 338     case ARM_CPU_IRQ:
 339         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 340         break;
 341     case ARM_CPU_FIQ:
 342         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 343         break;
 344     default:
 345         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 346     }
 347     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 348     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 349 #endif
 350 }
 351
 352 static bool arm_cpu_is_big_endian(CPUState *cs)
 353 {
 354     ARMCPU *cpu = ARM_CPU(cs);
 355     CPUARMState *env = &cpu->env;
 356     int cur_el;
 357
 358     cpu_synchronize_state(cs);
 359
 360     /* In 32bit guest endianness is determined by looking at CPSR's E bit */
 361     if (!is_a64(env)) {
 362         return (env->uncached_cpsr & CPSR_E) ? 1 : 0;
 363     }
 364
 365     cur_el = arm_current_el(env);
 366
 367     if (cur_el == 0) {
 368         return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
 369     }
 370
 371     return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
 372 }
 373
 374 #endif
 375
 376 static inline void set_feature(CPUARMState *env, int feature)
 377 {
 378     env->features |= 1ULL << feature;
 379 }
 380
 381 static inline void unset_feature(CPUARMState *env, int feature)
 382 {
 383     env->features &= ~(1ULL << feature);
 384 }
 385
 386 static void arm_cpu_initfn(Object *obj)
 387 {
 388     CPUState *cs = CPU(obj);
 389     ARMCPU *cpu = ARM_CPU(obj);
 390     static bool inited;
 391
 392     cs->env_ptr = &cpu->env;
 393     cpu_exec_init(&cpu->env);
 394     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 395                                          g_free, g_free);
 396
 397 #ifndef CONFIG_USER_ONLY
 398     /* Our inbound IRQ and FIQ lines */
 399     if (kvm_enabled()) {
 400         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 401          * the same interface as non-KVM CPUs.
 402          */
 403         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 404     } else {
 405         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 406     }
 407
 408     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 409                                                 arm_gt_ptimer_cb, cpu);
 410     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 411                                                 arm_gt_vtimer_cb, cpu);
 412     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 413                        ARRAY_SIZE(cpu->gt_timer_outputs));
 414 #endif
 415
 416     /* DTB consumers generally don't in fact care what the 'compatible'
 417      * string is, so always provide some string and trust that a hypothetical
 418      * picky DTB consumer will also provide a helpful error message.
 419      */
 420     cpu->dtb_compatible = "qemu,unknown";
 421     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 422     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 423
 424     if (tcg_enabled()) {
 425         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 426         if (!inited) {
 427             inited = true;
 428             arm_translate_init();
 429         }
 430     }
 431 }
 432
 433 static Property arm_cpu_reset_cbar_property =
 434             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 435
 436 static Property arm_cpu_reset_hivecs_property =
 437             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 438
 439 static Property arm_cpu_rvbar_property =
 440             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 441
 442 static Property arm_cpu_has_el3_property =
 443             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 444
 445 static void arm_cpu_post_init(Object *obj)
 446 {
 447     ARMCPU *cpu = ARM_CPU(obj);
 448
 449     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 450         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 451         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 452                                  &error_abort);
 453     }
 454
 455     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 456         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 457                                  &error_abort);
 458     }
 459
 460     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 461         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 462                                  &error_abort);
 463     }
 464
 465     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 466         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
 467          * prevent "has_el3" from existing on CPUs which cannot support EL3.
 468          */
 469         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
 470                                  &error_abort);
 471     }
 472 }
 473
 474 static void arm_cpu_finalizefn(Object *obj)
 475 {
 476     ARMCPU *cpu = ARM_CPU(obj);
 477     g_hash_table_destroy(cpu->cp_regs);
 478 }
 479
 480 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 481 {
 482     CPUState *cs = CPU(dev);
 483     ARMCPU *cpu = ARM_CPU(dev);
 484     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 485     CPUARMState *env = &cpu->env;
 486
 487     /* Some features automatically imply others: */
 488     if (arm_feature(env, ARM_FEATURE_V8)) {
 489         set_feature(env, ARM_FEATURE_V7);
 490         set_feature(env, ARM_FEATURE_ARM_DIV);
 491         set_feature(env, ARM_FEATURE_LPAE);
 492     }
 493     if (arm_feature(env, ARM_FEATURE_V7)) {
 494         set_feature(env, ARM_FEATURE_VAPA);
 495         set_feature(env, ARM_FEATURE_THUMB2);
 496         set_feature(env, ARM_FEATURE_MPIDR);
 497         if (!arm_feature(env, ARM_FEATURE_M)) {
 498             set_feature(env, ARM_FEATURE_V6K);
 499         } else {
 500             set_feature(env, ARM_FEATURE_V6);
 501         }
 502     }
 503     if (arm_feature(env, ARM_FEATURE_V6K)) {
 504         set_feature(env, ARM_FEATURE_V6);
 505         set_feature(env, ARM_FEATURE_MVFR);
 506     }
 507     if (arm_feature(env, ARM_FEATURE_V6)) {
 508         set_feature(env, ARM_FEATURE_V5);
 509         if (!arm_feature(env, ARM_FEATURE_M)) {
 510             set_feature(env, ARM_FEATURE_AUXCR);
 511         }
 512     }
 513     if (arm_feature(env, ARM_FEATURE_V5)) {
 514         set_feature(env, ARM_FEATURE_V4T);
 515     }
 516     if (arm_feature(env, ARM_FEATURE_M)) {
 517         set_feature(env, ARM_FEATURE_THUMB_DIV);
 518     }
 519     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 520         set_feature(env, ARM_FEATURE_THUMB_DIV);
 521     }
 522     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 523         set_feature(env, ARM_FEATURE_VFP3);
 524         set_feature(env, ARM_FEATURE_VFP_FP16);
 525     }
 526     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 527         set_feature(env, ARM_FEATURE_VFP);
 528     }
 529     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 530         set_feature(env, ARM_FEATURE_V7MP);
 531         set_feature(env, ARM_FEATURE_PXN);
 532     }
 533     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 534         set_feature(env, ARM_FEATURE_CBAR);
 535     }
 536
 537     if (cpu->reset_hivecs) {
 538             cpu->reset_sctlr |= (1 << 13);
 539     }
 540
 541     if (!cpu->has_el3) {
 542         /* If the has_el3 CPU property is disabled then we need to disable the
 543          * feature.
 544          */
 545         unset_feature(env, ARM_FEATURE_EL3);
 546
 547         /* Disable the security extension feature bits in the processor feature
 548          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
 549          */
 550         cpu->id_pfr1 &= ~0xf0;
 551         cpu->id_aa64pfr0 &= ~0xf000;
 552     }
 553
 554     register_cp_regs_for_features(cpu);
 555     arm_cpu_register_gdb_regs_for_features(cpu);
 556
 557     init_cpreg_list(cpu);
 558
 559     qemu_init_vcpu(cs);
 560     cpu_reset(cs);
 561
 562     acc->parent_realize(dev, errp);
 563 }
 564
 565 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 566 {
 567     ObjectClass *oc;
 568     char *typename;
 569     char **cpuname;
 570
 571     if (!cpu_model) {
 572         return NULL;
 573     }
 574
 575     cpuname = g_strsplit(cpu_model, ",", 1);
 576     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
 577     oc = object_class_by_name(typename);
 578     g_strfreev(cpuname);
 579     g_free(typename);
 580     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 581         object_class_is_abstract(oc)) {
 582         return NULL;
 583     }
 584     return oc;
 585 }
 586
 587 /* CPU models. These are not needed for the AArch64 linux-user build. */
 588 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 589
 590 static void arm926_initfn(Object *obj)
 591 {
 592     ARMCPU *cpu = ARM_CPU(obj);
 593
 594     cpu->dtb_compatible = "arm,arm926";
 595     set_feature(&cpu->env, ARM_FEATURE_V5);
 596     set_feature(&cpu->env, ARM_FEATURE_VFP);
 597     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 598     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 599     cpu->midr = 0x41069265;
 600     cpu->reset_fpsid = 0x41011090;
 601     cpu->ctr = 0x1dd20d2;
 602     cpu->reset_sctlr = 0x00090078;
 603 }
 604
 605 static void arm946_initfn(Object *obj)
 606 {
 607     ARMCPU *cpu = ARM_CPU(obj);
 608
 609     cpu->dtb_compatible = "arm,arm946";
 610     set_feature(&cpu->env, ARM_FEATURE_V5);
 611     set_feature(&cpu->env, ARM_FEATURE_MPU);
 612     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 613     cpu->midr = 0x41059461;
 614     cpu->ctr = 0x0f004006;
 615     cpu->reset_sctlr = 0x00000078;
 616 }
 617
 618 static void arm1026_initfn(Object *obj)
 619 {
 620     ARMCPU *cpu = ARM_CPU(obj);
 621
 622     cpu->dtb_compatible = "arm,arm1026";
 623     set_feature(&cpu->env, ARM_FEATURE_V5);
 624     set_feature(&cpu->env, ARM_FEATURE_VFP);
 625     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 626     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 627     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 628     cpu->midr = 0x4106a262;
 629     cpu->reset_fpsid = 0x410110a0;
 630     cpu->ctr = 0x1dd20d2;
 631     cpu->reset_sctlr = 0x00090078;
 632     cpu->reset_auxcr = 1;
 633     {
 634         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 635         ARMCPRegInfo ifar = {
 636             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 637             .access = PL1_RW,
 638             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 639             .resetvalue = 0
 640         };
 641         define_one_arm_cp_reg(cpu, &ifar);
 642     }
 643 }
 644
 645 static void arm1136_r2_initfn(Object *obj)
 646 {
 647     ARMCPU *cpu = ARM_CPU(obj);
 648     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 649      * older core than plain "arm1136". In particular this does not
 650      * have the v6K features.
 651      * These ID register values are correct for 1136 but may be wrong
 652      * for 1136_r2 (in particular r0p2 does not actually implement most
 653      * of the ID registers).
 654      */
 655
 656     cpu->dtb_compatible = "arm,arm1136";
 657     set_feature(&cpu->env, ARM_FEATURE_V6);
 658     set_feature(&cpu->env, ARM_FEATURE_VFP);
 659     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 660     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 661     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 662     cpu->midr = 0x4107b362;
 663     cpu->reset_fpsid = 0x410120b4;
 664     cpu->mvfr0 = 0x11111111;
 665     cpu->mvfr1 = 0x00000000;
 666     cpu->ctr = 0x1dd20d2;
 667     cpu->reset_sctlr = 0x00050078;
 668     cpu->id_pfr0 = 0x111;
 669     cpu->id_pfr1 = 0x1;
 670     cpu->id_dfr0 = 0x2;
 671     cpu->id_afr0 = 0x3;
 672     cpu->id_mmfr0 = 0x01130003;
 673     cpu->id_mmfr1 = 0x10030302;
 674     cpu->id_mmfr2 = 0x01222110;
 675     cpu->id_isar0 = 0x00140011;
 676     cpu->id_isar1 = 0x12002111;
 677     cpu->id_isar2 = 0x11231111;
 678     cpu->id_isar3 = 0x01102131;
 679     cpu->id_isar4 = 0x141;
 680     cpu->reset_auxcr = 7;
 681 }
 682
 683 static void arm1136_initfn(Object *obj)
 684 {
 685     ARMCPU *cpu = ARM_CPU(obj);
 686
 687     cpu->dtb_compatible = "arm,arm1136";
 688     set_feature(&cpu->env, ARM_FEATURE_V6K);
 689     set_feature(&cpu->env, ARM_FEATURE_V6);
 690     set_feature(&cpu->env, ARM_FEATURE_VFP);
 691     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 692     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 693     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 694     cpu->midr = 0x4117b363;
 695     cpu->reset_fpsid = 0x410120b4;
 696     cpu->mvfr0 = 0x11111111;
 697     cpu->mvfr1 = 0x00000000;
 698     cpu->ctr = 0x1dd20d2;
 699     cpu->reset_sctlr = 0x00050078;
 700     cpu->id_pfr0 = 0x111;
 701     cpu->id_pfr1 = 0x1;
 702     cpu->id_dfr0 = 0x2;
 703     cpu->id_afr0 = 0x3;
 704     cpu->id_mmfr0 = 0x01130003;
 705     cpu->id_mmfr1 = 0x10030302;
 706     cpu->id_mmfr2 = 0x01222110;
 707     cpu->id_isar0 = 0x00140011;
 708     cpu->id_isar1 = 0x12002111;
 709     cpu->id_isar2 = 0x11231111;
 710     cpu->id_isar3 = 0x01102131;
 711     cpu->id_isar4 = 0x141;
 712     cpu->reset_auxcr = 7;
 713 }
 714
 715 static void arm1176_initfn(Object *obj)
 716 {
 717     ARMCPU *cpu = ARM_CPU(obj);
 718
 719     cpu->dtb_compatible = "arm,arm1176";
 720     set_feature(&cpu->env, ARM_FEATURE_V6K);
 721     set_feature(&cpu->env, ARM_FEATURE_VFP);
 722     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 723     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 724     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 725     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 726     set_feature(&cpu->env, ARM_FEATURE_EL3);
 727     cpu->midr = 0x410fb767;
 728     cpu->reset_fpsid = 0x410120b5;
 729     cpu->mvfr0 = 0x11111111;
 730     cpu->mvfr1 = 0x00000000;
 731     cpu->ctr = 0x1dd20d2;
 732     cpu->reset_sctlr = 0x00050078;
 733     cpu->id_pfr0 = 0x111;
 734     cpu->id_pfr1 = 0x11;
 735     cpu->id_dfr0 = 0x33;
 736     cpu->id_afr0 = 0;
 737     cpu->id_mmfr0 = 0x01130003;
 738     cpu->id_mmfr1 = 0x10030302;
 739     cpu->id_mmfr2 = 0x01222100;
 740     cpu->id_isar0 = 0x0140011;
 741     cpu->id_isar1 = 0x12002111;
 742     cpu->id_isar2 = 0x11231121;
 743     cpu->id_isar3 = 0x01102131;
 744     cpu->id_isar4 = 0x01141;
 745     cpu->reset_auxcr = 7;
 746 }
 747
 748 static void arm11mpcore_initfn(Object *obj)
 749 {
 750     ARMCPU *cpu = ARM_CPU(obj);
 751
 752     cpu->dtb_compatible = "arm,arm11mpcore";
 753     set_feature(&cpu->env, ARM_FEATURE_V6K);
 754     set_feature(&cpu->env, ARM_FEATURE_VFP);
 755     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 756     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 757     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 758     cpu->midr = 0x410fb022;
 759     cpu->reset_fpsid = 0x410120b4;
 760     cpu->mvfr0 = 0x11111111;
 761     cpu->mvfr1 = 0x00000000;
 762     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 763     cpu->id_pfr0 = 0x111;
 764     cpu->id_pfr1 = 0x1;
 765     cpu->id_dfr0 = 0;
 766     cpu->id_afr0 = 0x2;
 767     cpu->id_mmfr0 = 0x01100103;
 768     cpu->id_mmfr1 = 0x10020302;
 769     cpu->id_mmfr2 = 0x01222000;
 770     cpu->id_isar0 = 0x00100011;
 771     cpu->id_isar1 = 0x12002111;
 772     cpu->id_isar2 = 0x11221011;
 773     cpu->id_isar3 = 0x01102131;
 774     cpu->id_isar4 = 0x141;
 775     cpu->reset_auxcr = 1;
 776 }
 777
 778 static void cortex_m3_initfn(Object *obj)
 779 {
 780     ARMCPU *cpu = ARM_CPU(obj);
 781     set_feature(&cpu->env, ARM_FEATURE_V7);
 782     set_feature(&cpu->env, ARM_FEATURE_M);
 783     cpu->midr = 0x410fc231;
 784 }
 785
 786 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 787 {
 788     CPUClass *cc = CPU_CLASS(oc);
 789
 790 #ifndef CONFIG_USER_ONLY
 791     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 792 #endif
 793
 794     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
 795 }
 796
 797 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 798     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 799       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 800     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 801       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 802     REGINFO_SENTINEL
 803 };
 804
 805 static void cortex_a8_initfn(Object *obj)
 806 {
 807     ARMCPU *cpu = ARM_CPU(obj);
 808
 809     cpu->dtb_compatible = "arm,cortex-a8";
 810     set_feature(&cpu->env, ARM_FEATURE_V7);
 811     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 812     set_feature(&cpu->env, ARM_FEATURE_NEON);
 813     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 814     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 815     set_feature(&cpu->env, ARM_FEATURE_EL3);
 816     cpu->midr = 0x410fc080;
 817     cpu->reset_fpsid = 0x410330c0;
 818     cpu->mvfr0 = 0x11110222;
 819     cpu->mvfr1 = 0x00011100;
 820     cpu->ctr = 0x82048004;
 821     cpu->reset_sctlr = 0x00c50078;
 822     cpu->id_pfr0 = 0x1031;
 823     cpu->id_pfr1 = 0x11;
 824     cpu->id_dfr0 = 0x400;
 825     cpu->id_afr0 = 0;
 826     cpu->id_mmfr0 = 0x31100003;
 827     cpu->id_mmfr1 = 0x20000000;
 828     cpu->id_mmfr2 = 0x01202000;
 829     cpu->id_mmfr3 = 0x11;
 830     cpu->id_isar0 = 0x00101111;
 831     cpu->id_isar1 = 0x12112111;
 832     cpu->id_isar2 = 0x21232031;
 833     cpu->id_isar3 = 0x11112131;
 834     cpu->id_isar4 = 0x00111142;
 835     cpu->dbgdidr = 0x15141000;
 836     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 837     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 838     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 839     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 840     cpu->reset_auxcr = 2;
 841     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 842 }
 843
 844 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 845     /* power_control should be set to maximum latency. Again,
 846      * default to 0 and set by private hook
 847      */
 848     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 849       .access = PL1_RW, .resetvalue = 0,
 850       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 851     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 852       .access = PL1_RW, .resetvalue = 0,
 853       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 854     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 855       .access = PL1_RW, .resetvalue = 0,
 856       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 857     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 858       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 859     /* TLB lockdown control */
 860     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 861       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 862     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 863       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 864     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 865       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 866     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 867       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 868     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 869       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 870     REGINFO_SENTINEL
 871 };
 872
 873 static void cortex_a9_initfn(Object *obj)
 874 {
 875     ARMCPU *cpu = ARM_CPU(obj);
 876
 877     cpu->dtb_compatible = "arm,cortex-a9";
 878     set_feature(&cpu->env, ARM_FEATURE_V7);
 879     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 880     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 881     set_feature(&cpu->env, ARM_FEATURE_NEON);
 882     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 883     set_feature(&cpu->env, ARM_FEATURE_EL3);
 884     /* Note that A9 supports the MP extensions even for
 885      * A9UP and single-core A9MP (which are both different
 886      * and valid configurations; we don't model A9UP).
 887      */
 888     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 889     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 890     cpu->midr = 0x410fc090;
 891     cpu->reset_fpsid = 0x41033090;
 892     cpu->mvfr0 = 0x11110222;
 893     cpu->mvfr1 = 0x01111111;
 894     cpu->ctr = 0x80038003;
 895     cpu->reset_sctlr = 0x00c50078;
 896     cpu->id_pfr0 = 0x1031;
 897     cpu->id_pfr1 = 0x11;
 898     cpu->id_dfr0 = 0x000;
 899     cpu->id_afr0 = 0;
 900     cpu->id_mmfr0 = 0x00100103;
 901     cpu->id_mmfr1 = 0x20000000;
 902     cpu->id_mmfr2 = 0x01230000;
 903     cpu->id_mmfr3 = 0x00002111;
 904     cpu->id_isar0 = 0x00101111;
 905     cpu->id_isar1 = 0x13112111;
 906     cpu->id_isar2 = 0x21232041;
 907     cpu->id_isar3 = 0x11112131;
 908     cpu->id_isar4 = 0x00111142;
 909     cpu->dbgdidr = 0x35141000;
 910     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 911     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
 912     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
 913     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 914 }
 915
 916 #ifndef CONFIG_USER_ONLY
 917 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 918 {
 919     /* Linux wants the number of processors from here.
 920      * Might as well set the interrupt-controller bit too.
 921      */
 922     return ((smp_cpus - 1) << 24) | (1 << 23);
 923 }
 924 #endif
 925
 926 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 927 #ifndef CONFIG_USER_ONLY
 928     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 929       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 930       .writefn = arm_cp_write_ignore, },
 931 #endif
 932     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 933       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 934     REGINFO_SENTINEL
 935 };
 936
 937 static void cortex_a15_initfn(Object *obj)
 938 {
 939     ARMCPU *cpu = ARM_CPU(obj);
 940
 941     cpu->dtb_compatible = "arm,cortex-a15";
 942     set_feature(&cpu->env, ARM_FEATURE_V7);
 943     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 944     set_feature(&cpu->env, ARM_FEATURE_NEON);
 945     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 946     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 947     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 948     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 949     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 950     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 951     set_feature(&cpu->env, ARM_FEATURE_EL3);
 952     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 953     cpu->midr = 0x412fc0f1;
 954     cpu->reset_fpsid = 0x410430f0;
 955     cpu->mvfr0 = 0x10110222;
 956     cpu->mvfr1 = 0x11111111;
 957     cpu->ctr = 0x8444c004;
 958     cpu->reset_sctlr = 0x00c50078;
 959     cpu->id_pfr0 = 0x00001131;
 960     cpu->id_pfr1 = 0x00011011;
 961     cpu->id_dfr0 = 0x02010555;
 962     cpu->id_afr0 = 0x00000000;
 963     cpu->id_mmfr0 = 0x10201105;
 964     cpu->id_mmfr1 = 0x20000000;
 965     cpu->id_mmfr2 = 0x01240000;
 966     cpu->id_mmfr3 = 0x02102211;
 967     cpu->id_isar0 = 0x02101110;
 968     cpu->id_isar1 = 0x13112111;
 969     cpu->id_isar2 = 0x21232041;
 970     cpu->id_isar3 = 0x11112131;
 971     cpu->id_isar4 = 0x10011142;
 972     cpu->dbgdidr = 0x3515f021;
 973     cpu->clidr = 0x0a200023;
 974     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 975     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 976     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 977     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 978 }
 979
 980 static void ti925t_initfn(Object *obj)
 981 {
 982     ARMCPU *cpu = ARM_CPU(obj);
 983     set_feature(&cpu->env, ARM_FEATURE_V4T);
 984     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 985     cpu->midr = ARM_CPUID_TI925T;
 986     cpu->ctr = 0x5109149;
 987     cpu->reset_sctlr = 0x00000070;
 988 }
 989
 990 static void sa1100_initfn(Object *obj)
 991 {
 992     ARMCPU *cpu = ARM_CPU(obj);
 993
 994     cpu->dtb_compatible = "intel,sa1100";
 995     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 996     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 997     cpu->midr = 0x4401A11B;
 998     cpu->reset_sctlr = 0x00000070;
 999 }
1000
1001 static void sa1110_initfn(Object *obj)
1002 {
1003     ARMCPU *cpu = ARM_CPU(obj);
1004     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1005     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1006     cpu->midr = 0x6901B119;
1007     cpu->reset_sctlr = 0x00000070;
1008 }
1009
1010 static void pxa250_initfn(Object *obj)
1011 {
1012     ARMCPU *cpu = ARM_CPU(obj);
1013
1014     cpu->dtb_compatible = "marvell,xscale";
1015     set_feature(&cpu->env, ARM_FEATURE_V5);
1016     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1017     cpu->midr = 0x69052100;
1018     cpu->ctr = 0xd172172;
1019     cpu->reset_sctlr = 0x00000078;
1020 }
1021
1022 static void pxa255_initfn(Object *obj)
1023 {
1024     ARMCPU *cpu = ARM_CPU(obj);
1025
1026     cpu->dtb_compatible = "marvell,xscale";
1027     set_feature(&cpu->env, ARM_FEATURE_V5);
1028     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1029     cpu->midr = 0x69052d00;
1030     cpu->ctr = 0xd172172;
1031     cpu->reset_sctlr = 0x00000078;
1032 }
1033
1034 static void pxa260_initfn(Object *obj)
1035 {
1036     ARMCPU *cpu = ARM_CPU(obj);
1037
1038     cpu->dtb_compatible = "marvell,xscale";
1039     set_feature(&cpu->env, ARM_FEATURE_V5);
1040     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1041     cpu->midr = 0x69052903;
1042     cpu->ctr = 0xd172172;
1043     cpu->reset_sctlr = 0x00000078;
1044 }
1045
1046 static void pxa261_initfn(Object *obj)
1047 {
1048     ARMCPU *cpu = ARM_CPU(obj);
1049
1050     cpu->dtb_compatible = "marvell,xscale";
1051     set_feature(&cpu->env, ARM_FEATURE_V5);
1052     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1053     cpu->midr = 0x69052d05;
1054     cpu->ctr = 0xd172172;
1055     cpu->reset_sctlr = 0x00000078;
1056 }
1057
1058 static void pxa262_initfn(Object *obj)
1059 {
1060     ARMCPU *cpu = ARM_CPU(obj);
1061
1062     cpu->dtb_compatible = "marvell,xscale";
1063     set_feature(&cpu->env, ARM_FEATURE_V5);
1064     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1065     cpu->midr = 0x69052d06;
1066     cpu->ctr = 0xd172172;
1067     cpu->reset_sctlr = 0x00000078;
1068 }
1069
1070 static void pxa270a0_initfn(Object *obj)
1071 {
1072     ARMCPU *cpu = ARM_CPU(obj);
1073
1074     cpu->dtb_compatible = "marvell,xscale";
1075     set_feature(&cpu->env, ARM_FEATURE_V5);
1076     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1077     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1078     cpu->midr = 0x69054110;
1079     cpu->ctr = 0xd172172;
1080     cpu->reset_sctlr = 0x00000078;
1081 }
1082
1083 static void pxa270a1_initfn(Object *obj)
1084 {
1085     ARMCPU *cpu = ARM_CPU(obj);
1086
1087     cpu->dtb_compatible = "marvell,xscale";
1088     set_feature(&cpu->env, ARM_FEATURE_V5);
1089     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1090     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1091     cpu->midr = 0x69054111;
1092     cpu->ctr = 0xd172172;
1093     cpu->reset_sctlr = 0x00000078;
1094 }
1095
1096 static void pxa270b0_initfn(Object *obj)
1097 {
1098     ARMCPU *cpu = ARM_CPU(obj);
1099
1100     cpu->dtb_compatible = "marvell,xscale";
1101     set_feature(&cpu->env, ARM_FEATURE_V5);
1102     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1103     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1104     cpu->midr = 0x69054112;
1105     cpu->ctr = 0xd172172;
1106     cpu->reset_sctlr = 0x00000078;
1107 }
1108
1109 static void pxa270b1_initfn(Object *obj)
1110 {
1111     ARMCPU *cpu = ARM_CPU(obj);
1112
1113     cpu->dtb_compatible = "marvell,xscale";
1114     set_feature(&cpu->env, ARM_FEATURE_V5);
1115     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1116     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1117     cpu->midr = 0x69054113;
1118     cpu->ctr = 0xd172172;
1119     cpu->reset_sctlr = 0x00000078;
1120 }
1121
1122 static void pxa270c0_initfn(Object *obj)
1123 {
1124     ARMCPU *cpu = ARM_CPU(obj);
1125
1126     cpu->dtb_compatible = "marvell,xscale";
1127     set_feature(&cpu->env, ARM_FEATURE_V5);
1128     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1129     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1130     cpu->midr = 0x69054114;
1131     cpu->ctr = 0xd172172;
1132     cpu->reset_sctlr = 0x00000078;
1133 }
1134
1135 static void pxa270c5_initfn(Object *obj)
1136 {
1137     ARMCPU *cpu = ARM_CPU(obj);
1138
1139     cpu->dtb_compatible = "marvell,xscale";
1140     set_feature(&cpu->env, ARM_FEATURE_V5);
1141     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1142     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1143     cpu->midr = 0x69054117;
1144     cpu->ctr = 0xd172172;
1145     cpu->reset_sctlr = 0x00000078;
1146 }
1147
1148 #ifdef CONFIG_USER_ONLY
1149 static void arm_any_initfn(Object *obj)
1150 {
1151     ARMCPU *cpu = ARM_CPU(obj);
1152     set_feature(&cpu->env, ARM_FEATURE_V8);
1153     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1154     set_feature(&cpu->env, ARM_FEATURE_NEON);
1155     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1156     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1157     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1158     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1159     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1160     set_feature(&cpu->env, ARM_FEATURE_CRC);
1161     cpu->midr = 0xffffffff;
1162 }
1163 #endif
1164
1165 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1166
1167 typedef struct ARMCPUInfo {
1168     const char *name;
1169     void (*initfn)(Object *obj);
1170     void (*class_init)(ObjectClass *oc, void *data);
1171 } ARMCPUInfo;
1172
1173 static const ARMCPUInfo arm_cpus[] = {
1174 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1175     { .name = "arm926",      .initfn = arm926_initfn },
1176     { .name = "arm946",      .initfn = arm946_initfn },
1177     { .name = "arm1026",     .initfn = arm1026_initfn },
1178     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1179      * older core than plain "arm1136". In particular this does not
1180      * have the v6K features.
1181      */
1182     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1183     { .name = "arm1136",     .initfn = arm1136_initfn },
1184     { .name = "arm1176",     .initfn = arm1176_initfn },
1185     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1186     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1187                              .class_init = arm_v7m_class_init },
1188     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1189     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1190     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1191     { .name = "ti925t",      .initfn = ti925t_initfn },
1192     { .name = "sa1100",      .initfn = sa1100_initfn },
1193     { .name = "sa1110",      .initfn = sa1110_initfn },
1194     { .name = "pxa250",      .initfn = pxa250_initfn },
1195     { .name = "pxa255",      .initfn = pxa255_initfn },
1196     { .name = "pxa260",      .initfn = pxa260_initfn },
1197     { .name = "pxa261",      .initfn = pxa261_initfn },
1198     { .name = "pxa262",      .initfn = pxa262_initfn },
1199     /* "pxa270" is an alias for "pxa270-a0" */
1200     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1201     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1202     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1203     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1204     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1205     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1206     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1207 #ifdef CONFIG_USER_ONLY
1208     { .name = "any",         .initfn = arm_any_initfn },
1209 #endif
1210 #endif
1211     { .name = NULL }
1212 };
1213
1214 static Property arm_cpu_properties[] = {
1215     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1216     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1217     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1218     DEFINE_PROP_END_OF_LIST()
1219 };
1220
1221 #ifdef CONFIG_USER_ONLY
1222 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
1223                                     int mmu_idx)
1224 {
1225     ARMCPU *cpu = ARM_CPU(cs);
1226     CPUARMState *env = &cpu->env;
1227
1228     env->exception.vaddress = address;
1229     if (rw == 2) {
1230         cs->exception_index = EXCP_PREFETCH_ABORT;
1231     } else {
1232         cs->exception_index = EXCP_DATA_ABORT;
1233     }
1234     return 1;
1235 }
1236 #endif
1237
1238 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1239 {
1240     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1241     CPUClass *cc = CPU_CLASS(acc);
1242     DeviceClass *dc = DEVICE_CLASS(oc);
1243
1244     acc->parent_realize = dc->realize;
1245     dc->realize = arm_cpu_realizefn;
1246     dc->props = arm_cpu_properties;
1247
1248     acc->parent_reset = cc->reset;
1249     cc->reset = arm_cpu_reset;
1250
1251     cc->class_by_name = arm_cpu_class_by_name;
1252     cc->has_work = arm_cpu_has_work;
1253     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1254     cc->dump_state = arm_cpu_dump_state;
1255     cc->set_pc = arm_cpu_set_pc;
1256     cc->gdb_read_register = arm_cpu_gdb_read_register;
1257     cc->gdb_write_register = arm_cpu_gdb_write_register;
1258 #ifdef CONFIG_USER_ONLY
1259     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1260 #else
1261     cc->do_interrupt = arm_cpu_do_interrupt;
1262     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1263     cc->vmsd = &vmstate_arm_cpu;
1264     cc->virtio_is_big_endian = arm_cpu_is_big_endian;
1265 #endif
1266     cc->gdb_num_core_regs = 26;
1267     cc->gdb_core_xml_file = "arm-core.xml";
1268     cc->gdb_stop_before_watchpoint = true;
1269     cc->debug_excp_handler = arm_debug_excp_handler;
1270 }
1271
1272 static void cpu_register(const ARMCPUInfo *info)
1273 {
1274     TypeInfo type_info = {
1275         .parent = TYPE_ARM_CPU,
1276         .instance_size = sizeof(ARMCPU),
1277         .instance_init = info->initfn,
1278         .class_size = sizeof(ARMCPUClass),
1279         .class_init = info->class_init,
1280     };
1281
1282     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1283     type_register(&type_info);
1284     g_free((void *)type_info.name);
1285 }
1286
1287 static const TypeInfo arm_cpu_type_info = {
1288     .name = TYPE_ARM_CPU,
1289     .parent = TYPE_CPU,
1290     .instance_size = sizeof(ARMCPU),
1291     .instance_init = arm_cpu_initfn,
1292     .instance_post_init = arm_cpu_post_init,
1293     .instance_finalize = arm_cpu_finalizefn,
1294     .abstract = true,
1295     .class_size = sizeof(ARMCPUClass),
1296     .class_init = arm_cpu_class_init,
1297 };
1298
1299 static void arm_cpu_register_types(void)
1300 {
1301     const ARMCPUInfo *info = arm_cpus;
1302
1303     type_register_static(&arm_cpu_type_info);
1304
1305     while (info->name) {
1306         cpu_register(info);
1307         info++;
1308     }
1309 }
1310
1311 type_init(arm_cpu_register_types)