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target/ppc: cpu_init: Move e300 SPR registration into a function
[qemu.git] / target / ppc / cpu_init.c
blob62eec9e6f0652c933e88da15a162f23fff3919a9
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/dis-asm.h"
23 #include "exec/gdbstub.h"
24 #include "kvm_ppc.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/tcg.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qemu/qemu-print.h"
34 #include "qapi/error.h"
35 #include "qapi/qmp/qnull.h"
36 #include "qapi/visitor.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ppc/ppc.h"
39 #include "mmu-book3s-v3.h"
40 #include "qemu/cutils.h"
41 #include "disas/capstone.h"
42 #include "fpu/softfloat.h"
43 #include "qapi/qapi-commands-machine-target.h"
44
45 #include "helper_regs.h"
46 #include "internal.h"
47 #include "spr_tcg.h"
48 #include "power8-pmu.h"
49
50 /* #define PPC_DEBUG_SPR */
51 /* #define USE_APPLE_GDB */
52
53 static inline void vscr_init(CPUPPCState *env, uint32_t val)
54 {
55 /* Altivec always uses round-to-nearest */
56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
57 ppc_store_vscr(env, val);
58 }
59
60 /**
61 * _spr_register
62 *
63 * Register an SPR with all the callbacks required for tcg,
64 * and the ID number for KVM.
65 *
66 * The reason for the conditional compilation is that the tcg functions
67 * may be compiled out, and the system kvm header may not be available
68 * for supplying the ID numbers. This is ugly, but the best we can do.
69 */
70
71 #ifdef CONFIG_TCG
72 # define USR_ARG(X) X,
73 # ifdef CONFIG_USER_ONLY
74 # define SYS_ARG(X)
75 # else
76 # define SYS_ARG(X) X,
77 # endif
78 #else
79 # define USR_ARG(X)
80 # define SYS_ARG(X)
81 #endif
82 #ifdef CONFIG_KVM
83 # define KVM_ARG(X) X,
84 #else
85 # define KVM_ARG(X)
86 #endif
87
88 typedef void spr_callback(DisasContext *, int, int);
89
90 static void _spr_register(CPUPPCState *env, int num, const char *name,
91 USR_ARG(spr_callback *uea_read)
92 USR_ARG(spr_callback *uea_write)
93 SYS_ARG(spr_callback *oea_read)
94 SYS_ARG(spr_callback *oea_write)
95 SYS_ARG(spr_callback *hea_read)
96 SYS_ARG(spr_callback *hea_write)
97 KVM_ARG(uint64_t one_reg_id)
98 target_ulong initial_value)
99 {
100 ppc_spr_t *spr = &env->spr_cb[num];
101
102 /* No SPR should be registered twice. */
103 assert(spr->name == NULL);
104 assert(name != NULL);
105
106 spr->name = name;
107 spr->default_value = initial_value;
108 env->spr[num] = initial_value;
109
110 #ifdef CONFIG_TCG
111 spr->uea_read = uea_read;
112 spr->uea_write = uea_write;
113 # ifndef CONFIG_USER_ONLY
114 spr->oea_read = oea_read;
115 spr->oea_write = oea_write;
116 spr->hea_read = hea_read;
117 spr->hea_write = hea_write;
118 # endif
119 #endif
120 #ifdef CONFIG_KVM
121 spr->one_reg_id = one_reg_id;
122 #endif
123 }
124
125 /* spr_register_kvm_hv passes all required arguments. */
126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
127 oea_read, oea_write, hea_read, hea_write, \
128 one_reg_id, initial_value) \
129 _spr_register(env, num, name, \
130 USR_ARG(uea_read) USR_ARG(uea_write) \
131 SYS_ARG(oea_read) SYS_ARG(oea_write) \
132 SYS_ARG(hea_read) SYS_ARG(hea_write) \
133 KVM_ARG(one_reg_id) initial_value)
134
135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */
136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
137 oea_read, oea_write, one_reg_id, ival) \
138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
139 oea_write, oea_read, oea_write, one_reg_id, ival)
140
141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */
142 #define spr_register_hv(env, num, name, uea_read, uea_write, \
143 oea_read, oea_write, hea_read, hea_write, ival) \
144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
145 oea_write, hea_read, hea_write, 0, ival)
146
147 #define spr_register(env, num, name, uea_read, uea_write, \
148 oea_read, oea_write, ival) \
149 spr_register_kvm(env, num, name, uea_read, uea_write, \
150 oea_read, oea_write, 0, ival)
151
152 /* Generic PowerPC SPRs */
153 static void register_generic_sprs(PowerPCCPU *cpu)
154 {
155 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
156 CPUPPCState *env = &cpu->env;
157
158 /* Integer processing */
159 spr_register(env, SPR_XER, "XER",
160 &spr_read_xer, &spr_write_xer,
161 &spr_read_xer, &spr_write_xer,
162 0x00000000);
163 /* Branch control */
164 spr_register(env, SPR_LR, "LR",
165 &spr_read_lr, &spr_write_lr,
166 &spr_read_lr, &spr_write_lr,
167 0x00000000);
168 spr_register(env, SPR_CTR, "CTR",
169 &spr_read_ctr, &spr_write_ctr,
170 &spr_read_ctr, &spr_write_ctr,
171 0x00000000);
172 /* Interrupt processing */
173 spr_register(env, SPR_SRR0, "SRR0",
174 SPR_NOACCESS, SPR_NOACCESS,
175 &spr_read_generic, &spr_write_generic,
176 0x00000000);
177 spr_register(env, SPR_SRR1, "SRR1",
178 SPR_NOACCESS, SPR_NOACCESS,
179 &spr_read_generic, &spr_write_generic,
180 0x00000000);
181 /* Processor control */
182 spr_register(env, SPR_SPRG0, "SPRG0",
183 SPR_NOACCESS, SPR_NOACCESS,
184 &spr_read_generic, &spr_write_generic,
185 0x00000000);
186 spr_register(env, SPR_SPRG1, "SPRG1",
187 SPR_NOACCESS, SPR_NOACCESS,
188 &spr_read_generic, &spr_write_generic,
189 0x00000000);
190 spr_register(env, SPR_SPRG2, "SPRG2",
191 SPR_NOACCESS, SPR_NOACCESS,
192 &spr_read_generic, &spr_write_generic,
193 0x00000000);
194 spr_register(env, SPR_SPRG3, "SPRG3",
195 SPR_NOACCESS, SPR_NOACCESS,
196 &spr_read_generic, &spr_write_generic,
197 0x00000000);
198
199 spr_register(env, SPR_PVR, "PVR",
200 /* Linux permits userspace to read PVR */
201 #if defined(CONFIG_LINUX_USER)
202 &spr_read_generic,
203 #else
204 SPR_NOACCESS,
205 #endif
206 SPR_NOACCESS,
207 &spr_read_generic, SPR_NOACCESS,
208 pcc->pvr);
209
210 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
211 if (pcc->svr != POWERPC_SVR_NONE) {
212 if (pcc->svr & POWERPC_SVR_E500) {
213 spr_register(env, SPR_E500_SVR, "SVR",
214 SPR_NOACCESS, SPR_NOACCESS,
215 &spr_read_generic, SPR_NOACCESS,
216 pcc->svr & ~POWERPC_SVR_E500);
217 } else {
218 spr_register(env, SPR_SVR, "SVR",
219 SPR_NOACCESS, SPR_NOACCESS,
220 &spr_read_generic, SPR_NOACCESS,
221 pcc->svr);
222 }
223 }
224
225 /* Time base */
226 spr_register(env, SPR_VTBL, "TBL",
227 &spr_read_tbl, SPR_NOACCESS,
228 &spr_read_tbl, SPR_NOACCESS,
229 0x00000000);
230 spr_register(env, SPR_TBL, "TBL",
231 &spr_read_tbl, SPR_NOACCESS,
232 &spr_read_tbl, &spr_write_tbl,
233 0x00000000);
234 spr_register(env, SPR_VTBU, "TBU",
235 &spr_read_tbu, SPR_NOACCESS,
236 &spr_read_tbu, SPR_NOACCESS,
237 0x00000000);
238 spr_register(env, SPR_TBU, "TBU",
239 &spr_read_tbu, SPR_NOACCESS,
240 &spr_read_tbu, &spr_write_tbu,
241 0x00000000);
242 }
243
244 /* SPR common to all non-embedded PowerPC, including 601 */
245 static void register_ne_601_sprs(CPUPPCState *env)
246 {
247 /* Exception processing */
248 spr_register_kvm(env, SPR_DSISR, "DSISR",
249 SPR_NOACCESS, SPR_NOACCESS,
250 &spr_read_generic, &spr_write_generic,
251 KVM_REG_PPC_DSISR, 0x00000000);
252 spr_register_kvm(env, SPR_DAR, "DAR",
253 SPR_NOACCESS, SPR_NOACCESS,
254 &spr_read_generic, &spr_write_generic,
255 KVM_REG_PPC_DAR, 0x00000000);
256 /* Timer */
257 spr_register(env, SPR_DECR, "DECR",
258 SPR_NOACCESS, SPR_NOACCESS,
259 &spr_read_decr, &spr_write_decr,
260 0x00000000);
261 }
262
263 /* Storage Description Register 1 */
264 static void register_sdr1_sprs(CPUPPCState *env)
265 {
266 #ifndef CONFIG_USER_ONLY
267 if (env->has_hv_mode) {
268 /*
269 * SDR1 is a hypervisor resource on CPUs which have a
270 * hypervisor mode
271 */
272 spr_register_hv(env, SPR_SDR1, "SDR1",
273 SPR_NOACCESS, SPR_NOACCESS,
274 SPR_NOACCESS, SPR_NOACCESS,
275 &spr_read_generic, &spr_write_sdr1,
276 0x00000000);
277 } else {
278 spr_register(env, SPR_SDR1, "SDR1",
279 SPR_NOACCESS, SPR_NOACCESS,
280 &spr_read_generic, &spr_write_sdr1,
281 0x00000000);
282 }
283 #endif
284 }
285
286 /* BATs 0-3 */
287 static void register_low_BATs(CPUPPCState *env)
288 {
289 #if !defined(CONFIG_USER_ONLY)
290 spr_register(env, SPR_IBAT0U, "IBAT0U",
291 SPR_NOACCESS, SPR_NOACCESS,
292 &spr_read_ibat, &spr_write_ibatu,
293 0x00000000);
294 spr_register(env, SPR_IBAT0L, "IBAT0L",
295 SPR_NOACCESS, SPR_NOACCESS,
296 &spr_read_ibat, &spr_write_ibatl,
297 0x00000000);
298 spr_register(env, SPR_IBAT1U, "IBAT1U",
299 SPR_NOACCESS, SPR_NOACCESS,
300 &spr_read_ibat, &spr_write_ibatu,
301 0x00000000);
302 spr_register(env, SPR_IBAT1L, "IBAT1L",
303 SPR_NOACCESS, SPR_NOACCESS,
304 &spr_read_ibat, &spr_write_ibatl,
305 0x00000000);
306 spr_register(env, SPR_IBAT2U, "IBAT2U",
307 SPR_NOACCESS, SPR_NOACCESS,
308 &spr_read_ibat, &spr_write_ibatu,
309 0x00000000);
310 spr_register(env, SPR_IBAT2L, "IBAT2L",
311 SPR_NOACCESS, SPR_NOACCESS,
312 &spr_read_ibat, &spr_write_ibatl,
313 0x00000000);
314 spr_register(env, SPR_IBAT3U, "IBAT3U",
315 SPR_NOACCESS, SPR_NOACCESS,
316 &spr_read_ibat, &spr_write_ibatu,
317 0x00000000);
318 spr_register(env, SPR_IBAT3L, "IBAT3L",
319 SPR_NOACCESS, SPR_NOACCESS,
320 &spr_read_ibat, &spr_write_ibatl,
321 0x00000000);
322 spr_register(env, SPR_DBAT0U, "DBAT0U",
323 SPR_NOACCESS, SPR_NOACCESS,
324 &spr_read_dbat, &spr_write_dbatu,
325 0x00000000);
326 spr_register(env, SPR_DBAT0L, "DBAT0L",
327 SPR_NOACCESS, SPR_NOACCESS,
328 &spr_read_dbat, &spr_write_dbatl,
329 0x00000000);
330 spr_register(env, SPR_DBAT1U, "DBAT1U",
331 SPR_NOACCESS, SPR_NOACCESS,
332 &spr_read_dbat, &spr_write_dbatu,
333 0x00000000);
334 spr_register(env, SPR_DBAT1L, "DBAT1L",
335 SPR_NOACCESS, SPR_NOACCESS,
336 &spr_read_dbat, &spr_write_dbatl,
337 0x00000000);
338 spr_register(env, SPR_DBAT2U, "DBAT2U",
339 SPR_NOACCESS, SPR_NOACCESS,
340 &spr_read_dbat, &spr_write_dbatu,
341 0x00000000);
342 spr_register(env, SPR_DBAT2L, "DBAT2L",
343 SPR_NOACCESS, SPR_NOACCESS,
344 &spr_read_dbat, &spr_write_dbatl,
345 0x00000000);
346 spr_register(env, SPR_DBAT3U, "DBAT3U",
347 SPR_NOACCESS, SPR_NOACCESS,
348 &spr_read_dbat, &spr_write_dbatu,
349 0x00000000);
350 spr_register(env, SPR_DBAT3L, "DBAT3L",
351 SPR_NOACCESS, SPR_NOACCESS,
352 &spr_read_dbat, &spr_write_dbatl,
353 0x00000000);
354 env->nb_BATs += 4;
355 #endif
356 }
357
358 /* BATs 4-7 */
359 static void register_high_BATs(CPUPPCState *env)
360 {
361 #if !defined(CONFIG_USER_ONLY)
362 spr_register(env, SPR_IBAT4U, "IBAT4U",
363 SPR_NOACCESS, SPR_NOACCESS,
364 &spr_read_ibat_h, &spr_write_ibatu_h,
365 0x00000000);
366 spr_register(env, SPR_IBAT4L, "IBAT4L",
367 SPR_NOACCESS, SPR_NOACCESS,
368 &spr_read_ibat_h, &spr_write_ibatl_h,
369 0x00000000);
370 spr_register(env, SPR_IBAT5U, "IBAT5U",
371 SPR_NOACCESS, SPR_NOACCESS,
372 &spr_read_ibat_h, &spr_write_ibatu_h,
373 0x00000000);
374 spr_register(env, SPR_IBAT5L, "IBAT5L",
375 SPR_NOACCESS, SPR_NOACCESS,
376 &spr_read_ibat_h, &spr_write_ibatl_h,
377 0x00000000);
378 spr_register(env, SPR_IBAT6U, "IBAT6U",
379 SPR_NOACCESS, SPR_NOACCESS,
380 &spr_read_ibat_h, &spr_write_ibatu_h,
381 0x00000000);
382 spr_register(env, SPR_IBAT6L, "IBAT6L",
383 SPR_NOACCESS, SPR_NOACCESS,
384 &spr_read_ibat_h, &spr_write_ibatl_h,
385 0x00000000);
386 spr_register(env, SPR_IBAT7U, "IBAT7U",
387 SPR_NOACCESS, SPR_NOACCESS,
388 &spr_read_ibat_h, &spr_write_ibatu_h,
389 0x00000000);
390 spr_register(env, SPR_IBAT7L, "IBAT7L",
391 SPR_NOACCESS, SPR_NOACCESS,
392 &spr_read_ibat_h, &spr_write_ibatl_h,
393 0x00000000);
394 spr_register(env, SPR_DBAT4U, "DBAT4U",
395 SPR_NOACCESS, SPR_NOACCESS,
396 &spr_read_dbat_h, &spr_write_dbatu_h,
397 0x00000000);
398 spr_register(env, SPR_DBAT4L, "DBAT4L",
399 SPR_NOACCESS, SPR_NOACCESS,
400 &spr_read_dbat_h, &spr_write_dbatl_h,
401 0x00000000);
402 spr_register(env, SPR_DBAT5U, "DBAT5U",
403 SPR_NOACCESS, SPR_NOACCESS,
404 &spr_read_dbat_h, &spr_write_dbatu_h,
405 0x00000000);
406 spr_register(env, SPR_DBAT5L, "DBAT5L",
407 SPR_NOACCESS, SPR_NOACCESS,
408 &spr_read_dbat_h, &spr_write_dbatl_h,
409 0x00000000);
410 spr_register(env, SPR_DBAT6U, "DBAT6U",
411 SPR_NOACCESS, SPR_NOACCESS,
412 &spr_read_dbat_h, &spr_write_dbatu_h,
413 0x00000000);
414 spr_register(env, SPR_DBAT6L, "DBAT6L",
415 SPR_NOACCESS, SPR_NOACCESS,
416 &spr_read_dbat_h, &spr_write_dbatl_h,
417 0x00000000);
418 spr_register(env, SPR_DBAT7U, "DBAT7U",
419 SPR_NOACCESS, SPR_NOACCESS,
420 &spr_read_dbat_h, &spr_write_dbatu_h,
421 0x00000000);
422 spr_register(env, SPR_DBAT7L, "DBAT7L",
423 SPR_NOACCESS, SPR_NOACCESS,
424 &spr_read_dbat_h, &spr_write_dbatl_h,
425 0x00000000);
426 env->nb_BATs += 4;
427 #endif
428 }
429
430 /* Softare table search registers */
431 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
432 {
433 #if !defined(CONFIG_USER_ONLY)
434 env->nb_tlb = nb_tlbs;
435 env->nb_ways = nb_ways;
436 env->id_tlbs = 1;
437 env->tlb_type = TLB_6XX;
438 spr_register(env, SPR_DMISS, "DMISS",
439 SPR_NOACCESS, SPR_NOACCESS,
440 &spr_read_generic, SPR_NOACCESS,
441 0x00000000);
442 spr_register(env, SPR_DCMP, "DCMP",
443 SPR_NOACCESS, SPR_NOACCESS,
444 &spr_read_generic, SPR_NOACCESS,
445 0x00000000);
446 spr_register(env, SPR_HASH1, "HASH1",
447 SPR_NOACCESS, SPR_NOACCESS,
448 &spr_read_generic, SPR_NOACCESS,
449 0x00000000);
450 spr_register(env, SPR_HASH2, "HASH2",
451 SPR_NOACCESS, SPR_NOACCESS,
452 &spr_read_generic, SPR_NOACCESS,
453 0x00000000);
454 spr_register(env, SPR_IMISS, "IMISS",
455 SPR_NOACCESS, SPR_NOACCESS,
456 &spr_read_generic, SPR_NOACCESS,
457 0x00000000);
458 spr_register(env, SPR_ICMP, "ICMP",
459 SPR_NOACCESS, SPR_NOACCESS,
460 &spr_read_generic, SPR_NOACCESS,
461 0x00000000);
462 spr_register(env, SPR_RPA, "RPA",
463 SPR_NOACCESS, SPR_NOACCESS,
464 &spr_read_generic, &spr_write_generic,
465 0x00000000);
466 #endif
467 }
468
469 static void register_745_sprs(CPUPPCState *env)
470 {
471 /* SGPRs */
472 spr_register(env, SPR_SPRG4, "SPRG4",
473 SPR_NOACCESS, SPR_NOACCESS,
474 &spr_read_generic, &spr_write_generic,
475 0x00000000);
476 spr_register(env, SPR_SPRG5, "SPRG5",
477 SPR_NOACCESS, SPR_NOACCESS,
478 &spr_read_generic, &spr_write_generic,
479 0x00000000);
480 spr_register(env, SPR_SPRG6, "SPRG6",
481 SPR_NOACCESS, SPR_NOACCESS,
482 &spr_read_generic, &spr_write_generic,
483 0x00000000);
484 spr_register(env, SPR_SPRG7, "SPRG7",
485 SPR_NOACCESS, SPR_NOACCESS,
486 &spr_read_generic, &spr_write_generic,
487 0x00000000);
488
489 /* Hardware implementation registers */
490 spr_register(env, SPR_HID0, "HID0",
491 SPR_NOACCESS, SPR_NOACCESS,
492 &spr_read_generic, &spr_write_generic,
493 0x00000000);
494
495 spr_register(env, SPR_HID1, "HID1",
496 SPR_NOACCESS, SPR_NOACCESS,
497 &spr_read_generic, &spr_write_generic,
498 0x00000000);
499
500 spr_register(env, SPR_HID2, "HID2",
501 SPR_NOACCESS, SPR_NOACCESS,
502 &spr_read_generic, &spr_write_generic,
503 0x00000000);
504 }
505
506 static void register_755_sprs(CPUPPCState *env)
507 {
508 /* L2 cache control */
509 spr_register(env, SPR_L2CR, "L2CR",
510 SPR_NOACCESS, SPR_NOACCESS,
511 &spr_read_generic, spr_access_nop,
512 0x00000000);
513
514 spr_register(env, SPR_L2PMCR, "L2PMCR",
515 SPR_NOACCESS, SPR_NOACCESS,
516 &spr_read_generic, &spr_write_generic,
517 0x00000000);
518 }
519
520 /* SPR common to all 7xx PowerPC implementations */
521 static void register_7xx_sprs(CPUPPCState *env)
522 {
523 /* Breakpoints */
524 spr_register_kvm(env, SPR_DABR, "DABR",
525 SPR_NOACCESS, SPR_NOACCESS,
526 &spr_read_generic, &spr_write_generic,
527 KVM_REG_PPC_DABR, 0x00000000);
528
529 spr_register(env, SPR_IABR, "IABR",
530 SPR_NOACCESS, SPR_NOACCESS,
531 &spr_read_generic, &spr_write_generic,
532 0x00000000);
533 /* Cache management */
534 spr_register(env, SPR_ICTC, "ICTC",
535 SPR_NOACCESS, SPR_NOACCESS,
536 &spr_read_generic, &spr_write_generic,
537 0x00000000);
538 /* Performance monitors */
539 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
540 SPR_NOACCESS, SPR_NOACCESS,
541 &spr_read_generic, &spr_write_generic,
542 0x00000000);
543
544 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
545 SPR_NOACCESS, SPR_NOACCESS,
546 &spr_read_generic, &spr_write_generic,
547 0x00000000);
548
549 spr_register(env, SPR_7XX_PMC1, "PMC1",
550 SPR_NOACCESS, SPR_NOACCESS,
551 &spr_read_generic, &spr_write_generic,
552 0x00000000);
553
554 spr_register(env, SPR_7XX_PMC2, "PMC2",
555 SPR_NOACCESS, SPR_NOACCESS,
556 &spr_read_generic, &spr_write_generic,
557 0x00000000);
558
559 spr_register(env, SPR_7XX_PMC3, "PMC3",
560 SPR_NOACCESS, SPR_NOACCESS,
561 &spr_read_generic, &spr_write_generic,
562 0x00000000);
563
564 spr_register(env, SPR_7XX_PMC4, "PMC4",
565 SPR_NOACCESS, SPR_NOACCESS,
566 &spr_read_generic, &spr_write_generic,
567 0x00000000);
568
569 spr_register(env, SPR_7XX_SIAR, "SIAR",
570 SPR_NOACCESS, SPR_NOACCESS,
571 &spr_read_generic, SPR_NOACCESS,
572 0x00000000);
573
574 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
575 &spr_read_ureg, SPR_NOACCESS,
576 &spr_read_ureg, SPR_NOACCESS,
577 0x00000000);
578
579 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
580 &spr_read_ureg, SPR_NOACCESS,
581 &spr_read_ureg, SPR_NOACCESS,
582 0x00000000);
583
584 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
585 &spr_read_ureg, SPR_NOACCESS,
586 &spr_read_ureg, SPR_NOACCESS,
587 0x00000000);
588
589 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
590 &spr_read_ureg, SPR_NOACCESS,
591 &spr_read_ureg, SPR_NOACCESS,
592 0x00000000);
593
594 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
595 &spr_read_ureg, SPR_NOACCESS,
596 &spr_read_ureg, SPR_NOACCESS,
597 0x00000000);
598
599 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
600 &spr_read_ureg, SPR_NOACCESS,
601 &spr_read_ureg, SPR_NOACCESS,
602 0x00000000);
603
604 spr_register(env, SPR_7XX_USIAR, "USIAR",
605 &spr_read_ureg, SPR_NOACCESS,
606 &spr_read_ureg, SPR_NOACCESS,
607 0x00000000);
608 /* External access control */
609 spr_register(env, SPR_EAR, "EAR",
610 SPR_NOACCESS, SPR_NOACCESS,
611 &spr_read_generic, &spr_write_generic,
612 0x00000000);
613
614 /* Hardware implementation registers */
615 spr_register(env, SPR_HID0, "HID0",
616 SPR_NOACCESS, SPR_NOACCESS,
617 &spr_read_generic, &spr_write_generic,
618 0x00000000);
619
620 spr_register(env, SPR_HID1, "HID1",
621 SPR_NOACCESS, SPR_NOACCESS,
622 &spr_read_generic, &spr_write_generic,
623 0x00000000);
624 }
625
626 #ifdef TARGET_PPC64
627 static void register_amr_sprs(CPUPPCState *env)
628 {
629 #ifndef CONFIG_USER_ONLY
630 /*
631 * Virtual Page Class Key protection
632 *
633 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
634 * userspace accessible, 29 is privileged. So we only need to set
635 * the kvm ONE_REG id on one of them, we use 29
636 */
637 spr_register(env, SPR_UAMR, "UAMR",
638 &spr_read_generic, &spr_write_amr,
639 &spr_read_generic, &spr_write_amr,
640 0);
641 spr_register_kvm_hv(env, SPR_AMR, "AMR",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_generic, &spr_write_amr,
644 &spr_read_generic, &spr_write_generic,
645 KVM_REG_PPC_AMR, 0);
646 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_uamor,
649 &spr_read_generic, &spr_write_generic,
650 KVM_REG_PPC_UAMOR, 0);
651 spr_register_hv(env, SPR_AMOR, "AMOR",
652 SPR_NOACCESS, SPR_NOACCESS,
653 SPR_NOACCESS, SPR_NOACCESS,
654 &spr_read_generic, &spr_write_generic,
655 0);
656 #endif /* !CONFIG_USER_ONLY */
657 }
658
659 static void register_iamr_sprs(CPUPPCState *env)
660 {
661 #ifndef CONFIG_USER_ONLY
662 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
663 SPR_NOACCESS, SPR_NOACCESS,
664 &spr_read_generic, &spr_write_iamr,
665 &spr_read_generic, &spr_write_generic,
666 KVM_REG_PPC_IAMR, 0);
667 #endif /* !CONFIG_USER_ONLY */
668 }
669 #endif /* TARGET_PPC64 */
670
671 static void register_thrm_sprs(CPUPPCState *env)
672 {
673 /* Thermal management */
674 spr_register(env, SPR_THRM1, "THRM1",
675 SPR_NOACCESS, SPR_NOACCESS,
676 &spr_read_thrm, &spr_write_generic,
677 0x00000000);
678
679 spr_register(env, SPR_THRM2, "THRM2",
680 SPR_NOACCESS, SPR_NOACCESS,
681 &spr_read_thrm, &spr_write_generic,
682 0x00000000);
683
684 spr_register(env, SPR_THRM3, "THRM3",
685 SPR_NOACCESS, SPR_NOACCESS,
686 &spr_read_thrm, &spr_write_generic,
687 0x00000000);
688 }
689
690 /* SPR specific to PowerPC 604 implementation */
691 static void register_604_sprs(CPUPPCState *env)
692 {
693 /* Processor identification */
694 spr_register(env, SPR_PIR, "PIR",
695 SPR_NOACCESS, SPR_NOACCESS,
696 &spr_read_generic, &spr_write_pir,
697 0x00000000);
698 /* Breakpoints */
699 spr_register(env, SPR_IABR, "IABR",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_generic, &spr_write_generic,
702 0x00000000);
703
704 spr_register_kvm(env, SPR_DABR, "DABR",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_generic, &spr_write_generic,
707 KVM_REG_PPC_DABR, 0x00000000);
708 /* Performance counters */
709 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_generic, &spr_write_generic,
712 0x00000000);
713
714 spr_register(env, SPR_7XX_PMC1, "PMC1",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_generic, &spr_write_generic,
717 0x00000000);
718
719 spr_register(env, SPR_7XX_PMC2, "PMC2",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_generic, &spr_write_generic,
722 0x00000000);
723
724 spr_register(env, SPR_7XX_SIAR, "SIAR",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_generic, SPR_NOACCESS,
727 0x00000000);
728
729 spr_register(env, SPR_SDA, "SDA",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_generic, SPR_NOACCESS,
732 0x00000000);
733 /* External access control */
734 spr_register(env, SPR_EAR, "EAR",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_generic, &spr_write_generic,
737 0x00000000);
738
739 /* Hardware implementation registers */
740 spr_register(env, SPR_HID0, "HID0",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_generic, &spr_write_generic,
743 0x00000000);
744 }
745
746 /* SPR specific to PowerPC 603 implementation */
747 static void register_603_sprs(CPUPPCState *env)
748 {
749 /* External access control */
750 spr_register(env, SPR_EAR, "EAR",
751 SPR_NOACCESS, SPR_NOACCESS,
752 &spr_read_generic, &spr_write_generic,
753 0x00000000);
754 /* Breakpoints */
755 spr_register(env, SPR_IABR, "IABR",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_generic, &spr_write_generic,
758 0x00000000);
759
760 spr_register(env, SPR_HID0, "HID0",
761 SPR_NOACCESS, SPR_NOACCESS,
762 &spr_read_generic, &spr_write_generic,
763 0x00000000);
764
765 spr_register(env, SPR_HID1, "HID1",
766 SPR_NOACCESS, SPR_NOACCESS,
767 &spr_read_generic, &spr_write_generic,
768 0x00000000);
769 }
770
771 static void register_e300_sprs(CPUPPCState *env)
772 {
773 /* hardware implementation registers */
774 spr_register(env, SPR_HID2, "HID2",
775 SPR_NOACCESS, SPR_NOACCESS,
776 &spr_read_generic, &spr_write_generic,
777 0x00000000);
778 /* Breakpoints */
779 spr_register(env, SPR_DABR, "DABR",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_generic, &spr_write_generic,
782 0x00000000);
783
784 spr_register(env, SPR_DABR2, "DABR2",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_generic, &spr_write_generic,
787 0x00000000);
788
789 spr_register(env, SPR_IABR2, "IABR2",
790 SPR_NOACCESS, SPR_NOACCESS,
791 &spr_read_generic, &spr_write_generic,
792 0x00000000);
793
794 spr_register(env, SPR_IBCR, "IBCR",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_generic, &spr_write_generic,
797 0x00000000);
798
799 spr_register(env, SPR_DBCR, "DBCR",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_generic, &spr_write_generic,
802 0x00000000);
803 }
804
805 /* SPR specific to PowerPC G2 implementation */
806 static void register_G2_sprs(CPUPPCState *env)
807 {
808 /* Memory base address */
809 /* MBAR */
810 spr_register(env, SPR_MBAR, "MBAR",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_generic, &spr_write_generic,
813 0x00000000);
814 /* Exception processing */
815 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
816 SPR_NOACCESS, SPR_NOACCESS,
817 &spr_read_generic, &spr_write_generic,
818 0x00000000);
819 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
820 SPR_NOACCESS, SPR_NOACCESS,
821 &spr_read_generic, &spr_write_generic,
822 0x00000000);
823 /* Breakpoints */
824 spr_register(env, SPR_DABR, "DABR",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_generic, &spr_write_generic,
827 0x00000000);
828
829 spr_register(env, SPR_DABR2, "DABR2",
830 SPR_NOACCESS, SPR_NOACCESS,
831 &spr_read_generic, &spr_write_generic,
832 0x00000000);
833
834 spr_register(env, SPR_IABR, "IABR",
835 SPR_NOACCESS, SPR_NOACCESS,
836 &spr_read_generic, &spr_write_generic,
837 0x00000000);
838
839 spr_register(env, SPR_IABR2, "IABR2",
840 SPR_NOACCESS, SPR_NOACCESS,
841 &spr_read_generic, &spr_write_generic,
842 0x00000000);
843
844 spr_register(env, SPR_IBCR, "IBCR",
845 SPR_NOACCESS, SPR_NOACCESS,
846 &spr_read_generic, &spr_write_generic,
847 0x00000000);
848
849 spr_register(env, SPR_DBCR, "DBCR",
850 SPR_NOACCESS, SPR_NOACCESS,
851 &spr_read_generic, &spr_write_generic,
852 0x00000000);
853
854 /* External access control */
855 spr_register(env, SPR_EAR, "EAR",
856 SPR_NOACCESS, SPR_NOACCESS,
857 &spr_read_generic, &spr_write_generic,
858 0x00000000);
859 /* Hardware implementation register */
860 spr_register(env, SPR_HID0, "HID0",
861 SPR_NOACCESS, SPR_NOACCESS,
862 &spr_read_generic, &spr_write_generic,
863 0x00000000);
864
865 spr_register(env, SPR_HID1, "HID1",
866 SPR_NOACCESS, SPR_NOACCESS,
867 &spr_read_generic, &spr_write_generic,
868 0x00000000);
869
870 spr_register(env, SPR_HID2, "HID2",
871 SPR_NOACCESS, SPR_NOACCESS,
872 &spr_read_generic, &spr_write_generic,
873 0x00000000);
874
875 /* SGPRs */
876 spr_register(env, SPR_SPRG4, "SPRG4",
877 SPR_NOACCESS, SPR_NOACCESS,
878 &spr_read_generic, &spr_write_generic,
879 0x00000000);
880 spr_register(env, SPR_SPRG5, "SPRG5",
881 SPR_NOACCESS, SPR_NOACCESS,
882 &spr_read_generic, &spr_write_generic,
883 0x00000000);
884 spr_register(env, SPR_SPRG6, "SPRG6",
885 SPR_NOACCESS, SPR_NOACCESS,
886 &spr_read_generic, &spr_write_generic,
887 0x00000000);
888 spr_register(env, SPR_SPRG7, "SPRG7",
889 SPR_NOACCESS, SPR_NOACCESS,
890 &spr_read_generic, &spr_write_generic,
891 0x00000000);
892 }
893
894 static void register_74xx_sprs(CPUPPCState *env)
895 {
896 /* Breakpoints */
897 spr_register_kvm(env, SPR_DABR, "DABR",
898 SPR_NOACCESS, SPR_NOACCESS,
899 &spr_read_generic, &spr_write_generic,
900 KVM_REG_PPC_DABR, 0x00000000);
901
902 spr_register(env, SPR_IABR, "IABR",
903 SPR_NOACCESS, SPR_NOACCESS,
904 &spr_read_generic, &spr_write_generic,
905 0x00000000);
906 /* Cache management */
907 spr_register(env, SPR_ICTC, "ICTC",
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_generic, &spr_write_generic,
910 0x00000000);
911 /* Performance monitors */
912 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, &spr_write_generic,
915 0x00000000);
916
917 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
918 SPR_NOACCESS, SPR_NOACCESS,
919 &spr_read_generic, &spr_write_generic,
920 0x00000000);
921
922 spr_register(env, SPR_7XX_PMC1, "PMC1",
923 SPR_NOACCESS, SPR_NOACCESS,
924 &spr_read_generic, &spr_write_generic,
925 0x00000000);
926
927 spr_register(env, SPR_7XX_PMC2, "PMC2",
928 SPR_NOACCESS, SPR_NOACCESS,
929 &spr_read_generic, &spr_write_generic,
930 0x00000000);
931
932 spr_register(env, SPR_7XX_PMC3, "PMC3",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, &spr_write_generic,
935 0x00000000);
936
937 spr_register(env, SPR_7XX_PMC4, "PMC4",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_generic, &spr_write_generic,
940 0x00000000);
941
942 spr_register(env, SPR_7XX_SIAR, "SIAR",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, SPR_NOACCESS,
945 0x00000000);
946
947 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
948 &spr_read_ureg, SPR_NOACCESS,
949 &spr_read_ureg, SPR_NOACCESS,
950 0x00000000);
951
952 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
953 &spr_read_ureg, SPR_NOACCESS,
954 &spr_read_ureg, SPR_NOACCESS,
955 0x00000000);
956
957 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
958 &spr_read_ureg, SPR_NOACCESS,
959 &spr_read_ureg, SPR_NOACCESS,
960 0x00000000);
961
962 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
963 &spr_read_ureg, SPR_NOACCESS,
964 &spr_read_ureg, SPR_NOACCESS,
965 0x00000000);
966
967 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
968 &spr_read_ureg, SPR_NOACCESS,
969 &spr_read_ureg, SPR_NOACCESS,
970 0x00000000);
971
972 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
973 &spr_read_ureg, SPR_NOACCESS,
974 &spr_read_ureg, SPR_NOACCESS,
975 0x00000000);
976
977 spr_register(env, SPR_7XX_USIAR, "USIAR",
978 &spr_read_ureg, SPR_NOACCESS,
979 &spr_read_ureg, SPR_NOACCESS,
980 0x00000000);
981 /* External access control */
982 spr_register(env, SPR_EAR, "EAR",
983 SPR_NOACCESS, SPR_NOACCESS,
984 &spr_read_generic, &spr_write_generic,
985 0x00000000);
986
987 /* Processor identification */
988 spr_register(env, SPR_PIR, "PIR",
989 SPR_NOACCESS, SPR_NOACCESS,
990 &spr_read_generic, &spr_write_pir,
991 0x00000000);
992
993 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
994 SPR_NOACCESS, SPR_NOACCESS,
995 &spr_read_generic, &spr_write_generic,
996 0x00000000);
997
998 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
999 &spr_read_ureg, SPR_NOACCESS,
1000 &spr_read_ureg, SPR_NOACCESS,
1001 0x00000000);
1002
1003 spr_register(env, SPR_BAMR, "BAMR",
1004 SPR_NOACCESS, SPR_NOACCESS,
1005 &spr_read_generic, &spr_write_generic,
1006 0x00000000);
1007
1008 spr_register(env, SPR_MSSCR0, "MSSCR0",
1009 SPR_NOACCESS, SPR_NOACCESS,
1010 &spr_read_generic, &spr_write_generic,
1011 0x00000000);
1012 /* Hardware implementation registers */
1013 spr_register(env, SPR_HID0, "HID0",
1014 SPR_NOACCESS, SPR_NOACCESS,
1015 &spr_read_generic, &spr_write_generic,
1016 0x00000000);
1017
1018 spr_register(env, SPR_HID1, "HID1",
1019 SPR_NOACCESS, SPR_NOACCESS,
1020 &spr_read_generic, &spr_write_generic,
1021 0x00000000);
1022 /* Altivec */
1023 spr_register(env, SPR_VRSAVE, "VRSAVE",
1024 &spr_read_generic, &spr_write_generic,
1025 &spr_read_generic, &spr_write_generic,
1026 0x00000000);
1027
1028 spr_register(env, SPR_L2CR, "L2CR",
1029 SPR_NOACCESS, SPR_NOACCESS,
1030 &spr_read_generic, spr_access_nop,
1031 0x00000000);
1032 }
1033
1034 static void register_l3_ctrl(CPUPPCState *env)
1035 {
1036 /* L3CR */
1037 spr_register(env, SPR_L3CR, "L3CR",
1038 SPR_NOACCESS, SPR_NOACCESS,
1039 &spr_read_generic, &spr_write_generic,
1040 0x00000000);
1041 /* L3ITCR0 */
1042 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
1046 /* L3PM */
1047 spr_register(env, SPR_L3PM, "L3PM",
1048 SPR_NOACCESS, SPR_NOACCESS,
1049 &spr_read_generic, &spr_write_generic,
1050 0x00000000);
1051 }
1052
1053 static void register_usprg3_sprs(CPUPPCState *env)
1054 {
1055 spr_register(env, SPR_USPRG3, "USPRG3",
1056 &spr_read_ureg, SPR_NOACCESS,
1057 &spr_read_ureg, SPR_NOACCESS,
1058 0x00000000);
1059 }
1060
1061 static void register_usprgh_sprs(CPUPPCState *env)
1062 {
1063 spr_register(env, SPR_USPRG4, "USPRG4",
1064 &spr_read_ureg, SPR_NOACCESS,
1065 &spr_read_ureg, SPR_NOACCESS,
1066 0x00000000);
1067 spr_register(env, SPR_USPRG5, "USPRG5",
1068 &spr_read_ureg, SPR_NOACCESS,
1069 &spr_read_ureg, SPR_NOACCESS,
1070 0x00000000);
1071 spr_register(env, SPR_USPRG6, "USPRG6",
1072 &spr_read_ureg, SPR_NOACCESS,
1073 &spr_read_ureg, SPR_NOACCESS,
1074 0x00000000);
1075 spr_register(env, SPR_USPRG7, "USPRG7",
1076 &spr_read_ureg, SPR_NOACCESS,
1077 &spr_read_ureg, SPR_NOACCESS,
1078 0x00000000);
1079 }
1080
1081 /* PowerPC BookE SPR */
1082 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
1083 {
1084 const char *ivor_names[64] = {
1085 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1086 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1087 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1088 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1089 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1090 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1091 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1092 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1093 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1094 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1095 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1096 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1097 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1098 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1099 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1100 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1101 };
1102 #define SPR_BOOKE_IVORxx (-1)
1103 int ivor_sprn[64] = {
1104 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1105 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1106 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1107 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1108 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1109 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1110 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1111 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1112 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1113 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1114 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1115 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1116 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1117 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1118 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1119 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1120 };
1121 int i;
1122
1123 /* Interrupt processing */
1124 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1125 SPR_NOACCESS, SPR_NOACCESS,
1126 &spr_read_generic, &spr_write_generic,
1127 0x00000000);
1128 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1129 SPR_NOACCESS, SPR_NOACCESS,
1130 &spr_read_generic, &spr_write_generic,
1131 0x00000000);
1132 /* Debug */
1133 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1134 SPR_NOACCESS, SPR_NOACCESS,
1135 &spr_read_generic, &spr_write_generic,
1136 0x00000000);
1137
1138 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1139 SPR_NOACCESS, SPR_NOACCESS,
1140 &spr_read_generic, &spr_write_generic,
1141 0x00000000);
1142
1143 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1144 SPR_NOACCESS, SPR_NOACCESS,
1145 &spr_read_generic, &spr_write_generic,
1146 0x00000000);
1147
1148 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1149 SPR_NOACCESS, SPR_NOACCESS,
1150 &spr_read_generic, &spr_write_generic,
1151 0x00000000);
1152
1153 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1154 SPR_NOACCESS, SPR_NOACCESS,
1155 &spr_read_generic, &spr_write_40x_dbcr0,
1156 0x00000000);
1157
1158 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1159 SPR_NOACCESS, SPR_NOACCESS,
1160 &spr_read_generic, &spr_write_generic,
1161 0x00000000);
1162
1163 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1168 SPR_NOACCESS, SPR_NOACCESS,
1169 &spr_read_generic, &spr_write_generic,
1170 0x00000000);
1171 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1172 SPR_NOACCESS, SPR_NOACCESS,
1173 &spr_read_generic, &spr_write_generic,
1174 0x00000000);
1175
1176 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1177 SPR_NOACCESS, SPR_NOACCESS,
1178 &spr_read_generic, &spr_write_clear,
1179 0x00000000);
1180 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1181 SPR_NOACCESS, SPR_NOACCESS,
1182 &spr_read_generic, &spr_write_generic,
1183 0x00000000);
1184 spr_register(env, SPR_BOOKE_ESR, "ESR",
1185 SPR_NOACCESS, SPR_NOACCESS,
1186 &spr_read_generic, &spr_write_generic,
1187 0x00000000);
1188 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1189 SPR_NOACCESS, SPR_NOACCESS,
1190 &spr_read_generic, &spr_write_excp_prefix,
1191 0x00000000);
1192 /* Exception vectors */
1193 for (i = 0; i < 64; i++) {
1194 if (ivor_mask & (1ULL << i)) {
1195 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1196 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1197 exit(1);
1198 }
1199 spr_register(env, ivor_sprn[i], ivor_names[i],
1200 SPR_NOACCESS, SPR_NOACCESS,
1201 &spr_read_generic, &spr_write_excp_vector,
1202 0x00000000);
1203 }
1204 }
1205 spr_register(env, SPR_BOOKE_PID, "PID",
1206 SPR_NOACCESS, SPR_NOACCESS,
1207 &spr_read_generic, &spr_write_booke_pid,
1208 0x00000000);
1209 spr_register(env, SPR_BOOKE_TCR, "TCR",
1210 SPR_NOACCESS, SPR_NOACCESS,
1211 &spr_read_generic, &spr_write_booke_tcr,
1212 0x00000000);
1213 spr_register(env, SPR_BOOKE_TSR, "TSR",
1214 SPR_NOACCESS, SPR_NOACCESS,
1215 &spr_read_generic, &spr_write_booke_tsr,
1216 0x00000000);
1217 /* Timer */
1218 spr_register(env, SPR_DECR, "DECR",
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_decr, &spr_write_decr,
1221 0x00000000);
1222 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1223 SPR_NOACCESS, SPR_NOACCESS,
1224 SPR_NOACCESS, &spr_write_generic,
1225 0x00000000);
1226 /* SPRGs */
1227 spr_register(env, SPR_USPRG0, "USPRG0",
1228 &spr_read_generic, &spr_write_generic,
1229 &spr_read_generic, &spr_write_generic,
1230 0x00000000);
1231 spr_register(env, SPR_SPRG4, "SPRG4",
1232 SPR_NOACCESS, SPR_NOACCESS,
1233 &spr_read_generic, &spr_write_generic,
1234 0x00000000);
1235 spr_register(env, SPR_SPRG5, "SPRG5",
1236 SPR_NOACCESS, SPR_NOACCESS,
1237 &spr_read_generic, &spr_write_generic,
1238 0x00000000);
1239 spr_register(env, SPR_SPRG6, "SPRG6",
1240 SPR_NOACCESS, SPR_NOACCESS,
1241 &spr_read_generic, &spr_write_generic,
1242 0x00000000);
1243 spr_register(env, SPR_SPRG7, "SPRG7",
1244 SPR_NOACCESS, SPR_NOACCESS,
1245 &spr_read_generic, &spr_write_generic,
1246 0x00000000);
1247 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
1248 SPR_NOACCESS, SPR_NOACCESS,
1249 &spr_read_generic, &spr_write_generic,
1250 0x00000000);
1251 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
1252 SPR_NOACCESS, SPR_NOACCESS,
1253 &spr_read_generic, &spr_write_generic,
1254 0x00000000);
1255 }
1256
1257 #if !defined(CONFIG_USER_ONLY)
1258 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
1259 uint32_t maxsize, uint32_t flags,
1260 uint32_t nentries)
1261 {
1262 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1263 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1264 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1265 flags | nentries;
1266 }
1267 #endif /* !CONFIG_USER_ONLY */
1268
1269 /* BookE 2.06 storage control registers */
1270 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
1271 uint32_t *tlbncfg, uint32_t mmucfg)
1272 {
1273 #if !defined(CONFIG_USER_ONLY)
1274 const char *mas_names[8] = {
1275 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1276 };
1277 int mas_sprn[8] = {
1278 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1279 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1280 };
1281 int i;
1282
1283 /* TLB assist registers */
1284 for (i = 0; i < 8; i++) {
1285 if (mas_mask & (1 << i)) {
1286 spr_register(env, mas_sprn[i], mas_names[i],
1287 SPR_NOACCESS, SPR_NOACCESS,
1288 &spr_read_generic,
1289 (i == 2 && (env->insns_flags & PPC_64B))
1290 ? &spr_write_generic : &spr_write_generic32,
1291 0x00000000);
1292 }
1293 }
1294 if (env->nb_pids > 1) {
1295 spr_register(env, SPR_BOOKE_PID1, "PID1",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_booke_pid,
1298 0x00000000);
1299 }
1300 if (env->nb_pids > 2) {
1301 spr_register(env, SPR_BOOKE_PID2, "PID2",
1302 SPR_NOACCESS, SPR_NOACCESS,
1303 &spr_read_generic, &spr_write_booke_pid,
1304 0x00000000);
1305 }
1306
1307 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
1308 SPR_NOACCESS, SPR_NOACCESS,
1309 &spr_read_generic, &spr_write_eplc,
1310 0x00000000);
1311 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_generic, &spr_write_epsc,
1314 0x00000000);
1315
1316 spr_register(env, SPR_MMUCFG, "MMUCFG",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_generic, SPR_NOACCESS,
1319 mmucfg);
1320 switch (env->nb_ways) {
1321 case 4:
1322 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1323 SPR_NOACCESS, SPR_NOACCESS,
1324 &spr_read_generic, SPR_NOACCESS,
1325 tlbncfg[3]);
1326 /* Fallthru */
1327 case 3:
1328 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1329 SPR_NOACCESS, SPR_NOACCESS,
1330 &spr_read_generic, SPR_NOACCESS,
1331 tlbncfg[2]);
1332 /* Fallthru */
1333 case 2:
1334 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, SPR_NOACCESS,
1337 tlbncfg[1]);
1338 /* Fallthru */
1339 case 1:
1340 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1341 SPR_NOACCESS, SPR_NOACCESS,
1342 &spr_read_generic, SPR_NOACCESS,
1343 tlbncfg[0]);
1344 /* Fallthru */
1345 case 0:
1346 default:
1347 break;
1348 }
1349 #endif
1350 }
1351
1352 /* SPR specific to PowerPC 440 implementation */
1353 static void register_440_sprs(CPUPPCState *env)
1354 {
1355 /* Cache control */
1356 spr_register(env, SPR_440_DNV0, "DNV0",
1357 SPR_NOACCESS, SPR_NOACCESS,
1358 &spr_read_generic, &spr_write_generic,
1359 0x00000000);
1360
1361 spr_register(env, SPR_440_DNV1, "DNV1",
1362 SPR_NOACCESS, SPR_NOACCESS,
1363 &spr_read_generic, &spr_write_generic,
1364 0x00000000);
1365
1366 spr_register(env, SPR_440_DNV2, "DNV2",
1367 SPR_NOACCESS, SPR_NOACCESS,
1368 &spr_read_generic, &spr_write_generic,
1369 0x00000000);
1370
1371 spr_register(env, SPR_440_DNV3, "DNV3",
1372 SPR_NOACCESS, SPR_NOACCESS,
1373 &spr_read_generic, &spr_write_generic,
1374 0x00000000);
1375
1376 spr_register(env, SPR_440_DTV0, "DTV0",
1377 SPR_NOACCESS, SPR_NOACCESS,
1378 &spr_read_generic, &spr_write_generic,
1379 0x00000000);
1380
1381 spr_register(env, SPR_440_DTV1, "DTV1",
1382 SPR_NOACCESS, SPR_NOACCESS,
1383 &spr_read_generic, &spr_write_generic,
1384 0x00000000);
1385
1386 spr_register(env, SPR_440_DTV2, "DTV2",
1387 SPR_NOACCESS, SPR_NOACCESS,
1388 &spr_read_generic, &spr_write_generic,
1389 0x00000000);
1390
1391 spr_register(env, SPR_440_DTV3, "DTV3",
1392 SPR_NOACCESS, SPR_NOACCESS,
1393 &spr_read_generic, &spr_write_generic,
1394 0x00000000);
1395
1396 spr_register(env, SPR_440_DVLIM, "DVLIM",
1397 SPR_NOACCESS, SPR_NOACCESS,
1398 &spr_read_generic, &spr_write_generic,
1399 0x00000000);
1400
1401 spr_register(env, SPR_440_INV0, "INV0",
1402 SPR_NOACCESS, SPR_NOACCESS,
1403 &spr_read_generic, &spr_write_generic,
1404 0x00000000);
1405
1406 spr_register(env, SPR_440_INV1, "INV1",
1407 SPR_NOACCESS, SPR_NOACCESS,
1408 &spr_read_generic, &spr_write_generic,
1409 0x00000000);
1410
1411 spr_register(env, SPR_440_INV2, "INV2",
1412 SPR_NOACCESS, SPR_NOACCESS,
1413 &spr_read_generic, &spr_write_generic,
1414 0x00000000);
1415
1416 spr_register(env, SPR_440_INV3, "INV3",
1417 SPR_NOACCESS, SPR_NOACCESS,
1418 &spr_read_generic, &spr_write_generic,
1419 0x00000000);
1420
1421 spr_register(env, SPR_440_ITV0, "ITV0",
1422 SPR_NOACCESS, SPR_NOACCESS,
1423 &spr_read_generic, &spr_write_generic,
1424 0x00000000);
1425
1426 spr_register(env, SPR_440_ITV1, "ITV1",
1427 SPR_NOACCESS, SPR_NOACCESS,
1428 &spr_read_generic, &spr_write_generic,
1429 0x00000000);
1430
1431 spr_register(env, SPR_440_ITV2, "ITV2",
1432 SPR_NOACCESS, SPR_NOACCESS,
1433 &spr_read_generic, &spr_write_generic,
1434 0x00000000);
1435
1436 spr_register(env, SPR_440_ITV3, "ITV3",
1437 SPR_NOACCESS, SPR_NOACCESS,
1438 &spr_read_generic, &spr_write_generic,
1439 0x00000000);
1440
1441 spr_register(env, SPR_440_IVLIM, "IVLIM",
1442 SPR_NOACCESS, SPR_NOACCESS,
1443 &spr_read_generic, &spr_write_generic,
1444 0x00000000);
1445 /* Cache debug */
1446 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1447 SPR_NOACCESS, SPR_NOACCESS,
1448 &spr_read_generic, SPR_NOACCESS,
1449 0x00000000);
1450
1451 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1452 SPR_NOACCESS, SPR_NOACCESS,
1453 &spr_read_generic, SPR_NOACCESS,
1454 0x00000000);
1455
1456 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1457 SPR_NOACCESS, SPR_NOACCESS,
1458 &spr_read_generic, SPR_NOACCESS,
1459 0x00000000);
1460
1461 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1462 SPR_NOACCESS, SPR_NOACCESS,
1463 &spr_read_generic, SPR_NOACCESS,
1464 0x00000000);
1465
1466 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1467 SPR_NOACCESS, SPR_NOACCESS,
1468 &spr_read_generic, SPR_NOACCESS,
1469 0x00000000);
1470
1471 spr_register(env, SPR_440_DBDR, "DBDR",
1472 SPR_NOACCESS, SPR_NOACCESS,
1473 &spr_read_generic, &spr_write_generic,
1474 0x00000000);
1475 /* Processor control */
1476 spr_register(env, SPR_4xx_CCR0, "CCR0",
1477 SPR_NOACCESS, SPR_NOACCESS,
1478 &spr_read_generic, &spr_write_generic,
1479 0x00000000);
1480 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1481 SPR_NOACCESS, SPR_NOACCESS,
1482 &spr_read_generic, SPR_NOACCESS,
1483 0x00000000);
1484 /* Storage control */
1485 spr_register(env, SPR_440_MMUCR, "MMUCR",
1486 SPR_NOACCESS, SPR_NOACCESS,
1487 &spr_read_generic, &spr_write_generic,
1488 0x00000000);
1489
1490 /* Processor identification */
1491 spr_register(env, SPR_BOOKE_PIR, "PIR",
1492 SPR_NOACCESS, SPR_NOACCESS,
1493 &spr_read_generic, &spr_write_pir,
1494 0x00000000);
1495
1496 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1497 SPR_NOACCESS, SPR_NOACCESS,
1498 &spr_read_generic, &spr_write_generic,
1499 0x00000000);
1500
1501 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1502 SPR_NOACCESS, SPR_NOACCESS,
1503 &spr_read_generic, &spr_write_generic,
1504 0x00000000);
1505
1506 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1507 SPR_NOACCESS, SPR_NOACCESS,
1508 &spr_read_generic, &spr_write_generic,
1509 0x00000000);
1510
1511 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1512 SPR_NOACCESS, SPR_NOACCESS,
1513 &spr_read_generic, &spr_write_generic,
1514 0x00000000);
1515 }
1516
1517 /* SPR shared between PowerPC 40x implementations */
1518 static void register_40x_sprs(CPUPPCState *env)
1519 {
1520 /* Cache */
1521 /* not emulated, as QEMU do not emulate caches */
1522 spr_register(env, SPR_40x_DCCR, "DCCR",
1523 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, &spr_write_generic,
1525 0x00000000);
1526 /* not emulated, as QEMU do not emulate caches */
1527 spr_register(env, SPR_40x_ICCR, "ICCR",
1528 SPR_NOACCESS, SPR_NOACCESS,
1529 &spr_read_generic, &spr_write_generic,
1530 0x00000000);
1531 /* not emulated, as QEMU do not emulate caches */
1532 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1533 SPR_NOACCESS, SPR_NOACCESS,
1534 &spr_read_generic, SPR_NOACCESS,
1535 0x00000000);
1536 /* Exception */
1537 spr_register(env, SPR_40x_DEAR, "DEAR",
1538 SPR_NOACCESS, SPR_NOACCESS,
1539 &spr_read_generic, &spr_write_generic,
1540 0x00000000);
1541 spr_register(env, SPR_40x_ESR, "ESR",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 &spr_read_generic, &spr_write_generic,
1544 0x00000000);
1545 spr_register(env, SPR_40x_EVPR, "EVPR",
1546 SPR_NOACCESS, SPR_NOACCESS,
1547 &spr_read_generic, &spr_write_excp_prefix,
1548 0x00000000);
1549 spr_register(env, SPR_40x_SRR2, "SRR2",
1550 &spr_read_generic, &spr_write_generic,
1551 &spr_read_generic, &spr_write_generic,
1552 0x00000000);
1553 spr_register(env, SPR_40x_SRR3, "SRR3",
1554 &spr_read_generic, &spr_write_generic,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557 /* Timers */
1558 spr_register(env, SPR_40x_PIT, "PIT",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_40x_pit, &spr_write_40x_pit,
1561 0x00000000);
1562 spr_register(env, SPR_40x_TCR, "TCR",
1563 SPR_NOACCESS, SPR_NOACCESS,
1564 &spr_read_generic, &spr_write_40x_tcr,
1565 0x00000000);
1566 spr_register(env, SPR_40x_TSR, "TSR",
1567 SPR_NOACCESS, SPR_NOACCESS,
1568 &spr_read_generic, &spr_write_40x_tsr,
1569 0x00000000);
1570 }
1571
1572 /* SPR specific to PowerPC 405 implementation */
1573 static void register_405_sprs(CPUPPCState *env)
1574 {
1575 /* MMU */
1576 spr_register(env, SPR_40x_PID, "PID",
1577 SPR_NOACCESS, SPR_NOACCESS,
1578 &spr_read_generic, &spr_write_40x_pid,
1579 0x00000000);
1580 spr_register(env, SPR_4xx_CCR0, "CCR0",
1581 SPR_NOACCESS, SPR_NOACCESS,
1582 &spr_read_generic, &spr_write_generic,
1583 0x00700000);
1584 /* Debug interface */
1585 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1586 SPR_NOACCESS, SPR_NOACCESS,
1587 &spr_read_generic, &spr_write_40x_dbcr0,
1588 0x00000000);
1589
1590 spr_register(env, SPR_405_DBCR1, "DBCR1",
1591 SPR_NOACCESS, SPR_NOACCESS,
1592 &spr_read_generic, &spr_write_generic,
1593 0x00000000);
1594
1595 spr_register(env, SPR_40x_DBSR, "DBSR",
1596 SPR_NOACCESS, SPR_NOACCESS,
1597 &spr_read_generic, &spr_write_clear,
1598 /* Last reset was system reset */
1599 0x00000300);
1600
1601 spr_register(env, SPR_40x_DAC1, "DAC1",
1602 SPR_NOACCESS, SPR_NOACCESS,
1603 &spr_read_generic, &spr_write_generic,
1604 0x00000000);
1605 spr_register(env, SPR_40x_DAC2, "DAC2",
1606 SPR_NOACCESS, SPR_NOACCESS,
1607 &spr_read_generic, &spr_write_generic,
1608 0x00000000);
1609
1610 spr_register(env, SPR_405_DVC1, "DVC1",
1611 SPR_NOACCESS, SPR_NOACCESS,
1612 &spr_read_generic, &spr_write_generic,
1613 0x00000000);
1614
1615 spr_register(env, SPR_405_DVC2, "DVC2",
1616 SPR_NOACCESS, SPR_NOACCESS,
1617 &spr_read_generic, &spr_write_generic,
1618 0x00000000);
1619
1620 spr_register(env, SPR_40x_IAC1, "IAC1",
1621 SPR_NOACCESS, SPR_NOACCESS,
1622 &spr_read_generic, &spr_write_generic,
1623 0x00000000);
1624 spr_register(env, SPR_40x_IAC2, "IAC2",
1625 SPR_NOACCESS, SPR_NOACCESS,
1626 &spr_read_generic, &spr_write_generic,
1627 0x00000000);
1628
1629 spr_register(env, SPR_405_IAC3, "IAC3",
1630 SPR_NOACCESS, SPR_NOACCESS,
1631 &spr_read_generic, &spr_write_generic,
1632 0x00000000);
1633
1634 spr_register(env, SPR_405_IAC4, "IAC4",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, &spr_write_generic,
1637 0x00000000);
1638 /* Storage control */
1639 spr_register(env, SPR_405_SLER, "SLER",
1640 SPR_NOACCESS, SPR_NOACCESS,
1641 &spr_read_generic, &spr_write_40x_sler,
1642 0x00000000);
1643 spr_register(env, SPR_40x_ZPR, "ZPR",
1644 SPR_NOACCESS, SPR_NOACCESS,
1645 &spr_read_generic, &spr_write_generic,
1646 0x00000000);
1647
1648 spr_register(env, SPR_405_SU0R, "SU0R",
1649 SPR_NOACCESS, SPR_NOACCESS,
1650 &spr_read_generic, &spr_write_generic,
1651 0x00000000);
1652 /* SPRG */
1653 spr_register(env, SPR_USPRG0, "USPRG0",
1654 &spr_read_ureg, SPR_NOACCESS,
1655 &spr_read_ureg, SPR_NOACCESS,
1656 0x00000000);
1657 spr_register(env, SPR_SPRG4, "SPRG4",
1658 SPR_NOACCESS, SPR_NOACCESS,
1659 &spr_read_generic, &spr_write_generic,
1660 0x00000000);
1661 spr_register(env, SPR_SPRG5, "SPRG5",
1662 SPR_NOACCESS, SPR_NOACCESS,
1663 spr_read_generic, &spr_write_generic,
1664 0x00000000);
1665 spr_register(env, SPR_SPRG6, "SPRG6",
1666 SPR_NOACCESS, SPR_NOACCESS,
1667 spr_read_generic, &spr_write_generic,
1668 0x00000000);
1669 spr_register(env, SPR_SPRG7, "SPRG7",
1670 SPR_NOACCESS, SPR_NOACCESS,
1671 spr_read_generic, &spr_write_generic,
1672 0x00000000);
1673
1674 /* Bus access control */
1675 /* not emulated, as QEMU never does speculative access */
1676 spr_register(env, SPR_40x_SGR, "SGR",
1677 SPR_NOACCESS, SPR_NOACCESS,
1678 &spr_read_generic, &spr_write_generic,
1679 0xFFFFFFFF);
1680 /* not emulated, as QEMU do not emulate caches */
1681 spr_register(env, SPR_40x_DCWR, "DCWR",
1682 SPR_NOACCESS, SPR_NOACCESS,
1683 &spr_read_generic, &spr_write_generic,
1684 0x00000000);
1685 }
1686
1687
1688 static void register_5xx_8xx_sprs(CPUPPCState *env)
1689 {
1690 /* Exception processing */
1691 spr_register_kvm(env, SPR_DSISR, "DSISR",
1692 SPR_NOACCESS, SPR_NOACCESS,
1693 &spr_read_generic, &spr_write_generic,
1694 KVM_REG_PPC_DSISR, 0x00000000);
1695 spr_register_kvm(env, SPR_DAR, "DAR",
1696 SPR_NOACCESS, SPR_NOACCESS,
1697 &spr_read_generic, &spr_write_generic,
1698 KVM_REG_PPC_DAR, 0x00000000);
1699 /* Timer */
1700 spr_register(env, SPR_DECR, "DECR",
1701 SPR_NOACCESS, SPR_NOACCESS,
1702 &spr_read_decr, &spr_write_decr,
1703 0x00000000);
1704
1705 spr_register(env, SPR_MPC_EIE, "EIE",
1706 SPR_NOACCESS, SPR_NOACCESS,
1707 &spr_read_generic, &spr_write_generic,
1708 0x00000000);
1709
1710 spr_register(env, SPR_MPC_EID, "EID",
1711 SPR_NOACCESS, SPR_NOACCESS,
1712 &spr_read_generic, &spr_write_generic,
1713 0x00000000);
1714
1715 spr_register(env, SPR_MPC_NRI, "NRI",
1716 SPR_NOACCESS, SPR_NOACCESS,
1717 &spr_read_generic, &spr_write_generic,
1718 0x00000000);
1719
1720 spr_register(env, SPR_MPC_CMPA, "CMPA",
1721 SPR_NOACCESS, SPR_NOACCESS,
1722 &spr_read_generic, &spr_write_generic,
1723 0x00000000);
1724
1725 spr_register(env, SPR_MPC_CMPB, "CMPB",
1726 SPR_NOACCESS, SPR_NOACCESS,
1727 &spr_read_generic, &spr_write_generic,
1728 0x00000000);
1729
1730 spr_register(env, SPR_MPC_CMPC, "CMPC",
1731 SPR_NOACCESS, SPR_NOACCESS,
1732 &spr_read_generic, &spr_write_generic,
1733 0x00000000);
1734
1735 spr_register(env, SPR_MPC_CMPD, "CMPD",
1736 SPR_NOACCESS, SPR_NOACCESS,
1737 &spr_read_generic, &spr_write_generic,
1738 0x00000000);
1739
1740 spr_register(env, SPR_MPC_ECR, "ECR",
1741 SPR_NOACCESS, SPR_NOACCESS,
1742 &spr_read_generic, &spr_write_generic,
1743 0x00000000);
1744
1745 spr_register(env, SPR_MPC_DER, "DER",
1746 SPR_NOACCESS, SPR_NOACCESS,
1747 &spr_read_generic, &spr_write_generic,
1748 0x00000000);
1749
1750 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1751 SPR_NOACCESS, SPR_NOACCESS,
1752 &spr_read_generic, &spr_write_generic,
1753 0x00000000);
1754
1755 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1756 SPR_NOACCESS, SPR_NOACCESS,
1757 &spr_read_generic, &spr_write_generic,
1758 0x00000000);
1759
1760 spr_register(env, SPR_MPC_CMPE, "CMPE",
1761 SPR_NOACCESS, SPR_NOACCESS,
1762 &spr_read_generic, &spr_write_generic,
1763 0x00000000);
1764
1765 spr_register(env, SPR_MPC_CMPF, "CMPF",
1766 SPR_NOACCESS, SPR_NOACCESS,
1767 &spr_read_generic, &spr_write_generic,
1768 0x00000000);
1769
1770 spr_register(env, SPR_MPC_CMPG, "CMPG",
1771 SPR_NOACCESS, SPR_NOACCESS,
1772 &spr_read_generic, &spr_write_generic,
1773 0x00000000);
1774
1775 spr_register(env, SPR_MPC_CMPH, "CMPH",
1776 SPR_NOACCESS, SPR_NOACCESS,
1777 &spr_read_generic, &spr_write_generic,
1778 0x00000000);
1779
1780 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1781 SPR_NOACCESS, SPR_NOACCESS,
1782 &spr_read_generic, &spr_write_generic,
1783 0x00000000);
1784
1785 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1786 SPR_NOACCESS, SPR_NOACCESS,
1787 &spr_read_generic, &spr_write_generic,
1788 0x00000000);
1789
1790 spr_register(env, SPR_MPC_BAR, "BAR",
1791 SPR_NOACCESS, SPR_NOACCESS,
1792 &spr_read_generic, &spr_write_generic,
1793 0x00000000);
1794
1795 spr_register(env, SPR_MPC_DPDR, "DPDR",
1796 SPR_NOACCESS, SPR_NOACCESS,
1797 &spr_read_generic, &spr_write_generic,
1798 0x00000000);
1799
1800 spr_register(env, SPR_MPC_IMMR, "IMMR",
1801 SPR_NOACCESS, SPR_NOACCESS,
1802 &spr_read_generic, &spr_write_generic,
1803 0x00000000);
1804 }
1805
1806 static void register_5xx_sprs(CPUPPCState *env)
1807 {
1808 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1809 SPR_NOACCESS, SPR_NOACCESS,
1810 &spr_read_generic, &spr_write_generic,
1811 0x00000000);
1812
1813 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1814 SPR_NOACCESS, SPR_NOACCESS,
1815 &spr_read_generic, &spr_write_generic,
1816 0x00000000);
1817
1818 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_generic,
1821 0x00000000);
1822
1823 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, &spr_write_generic,
1826 0x00000000);
1827
1828 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1829 SPR_NOACCESS, SPR_NOACCESS,
1830 &spr_read_generic, &spr_write_generic,
1831 0x00000000);
1832
1833 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1834 SPR_NOACCESS, SPR_NOACCESS,
1835 &spr_read_generic, &spr_write_generic,
1836 0x00000000);
1837
1838 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1839 SPR_NOACCESS, SPR_NOACCESS,
1840 &spr_read_generic, &spr_write_generic,
1841 0x00000000);
1842
1843 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1844 SPR_NOACCESS, SPR_NOACCESS,
1845 &spr_read_generic, &spr_write_generic,
1846 0x00000000);
1847
1848 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1849 SPR_NOACCESS, SPR_NOACCESS,
1850 &spr_read_generic, &spr_write_generic,
1851 0x00000000);
1852
1853 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1854 SPR_NOACCESS, SPR_NOACCESS,
1855 &spr_read_generic, &spr_write_generic,
1856 0x00000000);
1857
1858 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1859 SPR_NOACCESS, SPR_NOACCESS,
1860 &spr_read_generic, &spr_write_generic,
1861 0x00000000);
1862
1863 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1864 SPR_NOACCESS, SPR_NOACCESS,
1865 &spr_read_generic, &spr_write_generic,
1866 0x00000000);
1867
1868 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, &spr_write_generic,
1871 0x00000000);
1872
1873 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1874 SPR_NOACCESS, SPR_NOACCESS,
1875 &spr_read_generic, &spr_write_generic,
1876 0x00000000);
1877
1878 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_generic,
1881 0x00000000);
1882
1883 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, &spr_write_generic,
1886 0x00000000);
1887
1888 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1889 SPR_NOACCESS, SPR_NOACCESS,
1890 &spr_read_generic, &spr_write_generic,
1891 0x00000000);
1892
1893 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1894 SPR_NOACCESS, SPR_NOACCESS,
1895 &spr_read_generic, &spr_write_generic,
1896 0x00000000);
1897
1898 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_generic,
1901 0x00000000);
1902
1903 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1904 SPR_NOACCESS, SPR_NOACCESS,
1905 &spr_read_generic, &spr_write_generic,
1906 0x00000000);
1907
1908 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, &spr_write_generic,
1911 0x00000000);
1912 }
1913
1914 static void register_8xx_sprs(CPUPPCState *env)
1915 {
1916
1917 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1918 SPR_NOACCESS, SPR_NOACCESS,
1919 &spr_read_generic, &spr_write_generic,
1920 0x00000000);
1921
1922 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1923 SPR_NOACCESS, SPR_NOACCESS,
1924 &spr_read_generic, &spr_write_generic,
1925 0x00000000);
1926
1927 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1928 SPR_NOACCESS, SPR_NOACCESS,
1929 &spr_read_generic, &spr_write_generic,
1930 0x00000000);
1931
1932 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1933 SPR_NOACCESS, SPR_NOACCESS,
1934 &spr_read_generic, &spr_write_generic,
1935 0x00000000);
1936
1937 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1938 SPR_NOACCESS, SPR_NOACCESS,
1939 &spr_read_generic, &spr_write_generic,
1940 0x00000000);
1941
1942 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
1943 SPR_NOACCESS, SPR_NOACCESS,
1944 &spr_read_generic, &spr_write_generic,
1945 0x00000000);
1946
1947 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 &spr_read_generic, &spr_write_generic,
1950 0x00000000);
1951
1952 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
1953 SPR_NOACCESS, SPR_NOACCESS,
1954 &spr_read_generic, &spr_write_generic,
1955 0x00000000);
1956
1957 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
1958 SPR_NOACCESS, SPR_NOACCESS,
1959 &spr_read_generic, &spr_write_generic,
1960 0x00000000);
1961
1962 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
1963 SPR_NOACCESS, SPR_NOACCESS,
1964 &spr_read_generic, &spr_write_generic,
1965 0x00000000);
1966
1967 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
1968 SPR_NOACCESS, SPR_NOACCESS,
1969 &spr_read_generic, &spr_write_generic,
1970 0x00000000);
1971
1972 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
1973 SPR_NOACCESS, SPR_NOACCESS,
1974 &spr_read_generic, &spr_write_generic,
1975 0x00000000);
1976
1977 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
1978 SPR_NOACCESS, SPR_NOACCESS,
1979 &spr_read_generic, &spr_write_generic,
1980 0x00000000);
1981
1982 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
1983 SPR_NOACCESS, SPR_NOACCESS,
1984 &spr_read_generic, &spr_write_generic,
1985 0x00000000);
1986
1987 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
1988 SPR_NOACCESS, SPR_NOACCESS,
1989 &spr_read_generic, &spr_write_generic,
1990 0x00000000);
1991
1992 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_generic, &spr_write_generic,
1995 0x00000000);
1996
1997 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
1998 SPR_NOACCESS, SPR_NOACCESS,
1999 &spr_read_generic, &spr_write_generic,
2000 0x00000000);
2001
2002 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2003 SPR_NOACCESS, SPR_NOACCESS,
2004 &spr_read_generic, &spr_write_generic,
2005 0x00000000);
2006
2007 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2008 SPR_NOACCESS, SPR_NOACCESS,
2009 &spr_read_generic, &spr_write_generic,
2010 0x00000000);
2011
2012 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2013 SPR_NOACCESS, SPR_NOACCESS,
2014 &spr_read_generic, &spr_write_generic,
2015 0x00000000);
2016
2017 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, &spr_write_generic,
2020 0x00000000);
2021
2022 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2023 SPR_NOACCESS, SPR_NOACCESS,
2024 &spr_read_generic, &spr_write_generic,
2025 0x00000000);
2026
2027 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2028 SPR_NOACCESS, SPR_NOACCESS,
2029 &spr_read_generic, &spr_write_generic,
2030 0x00000000);
2031
2032 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2033 SPR_NOACCESS, SPR_NOACCESS,
2034 &spr_read_generic, &spr_write_generic,
2035 0x00000000);
2036
2037 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2038 SPR_NOACCESS, SPR_NOACCESS,
2039 &spr_read_generic, &spr_write_generic,
2040 0x00000000);
2041 }
2042
2043 /*
2044 * AMR => SPR 29 (Power 2.04)
2045 * CTRL => SPR 136 (Power 2.04)
2046 * CTRL => SPR 152 (Power 2.04)
2047 * SCOMC => SPR 276 (64 bits ?)
2048 * SCOMD => SPR 277 (64 bits ?)
2049 * TBU40 => SPR 286 (Power 2.04 hypv)
2050 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2051 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2052 * HDSISR => SPR 306 (Power 2.04 hypv)
2053 * HDAR => SPR 307 (Power 2.04 hypv)
2054 * PURR => SPR 309 (Power 2.04 hypv)
2055 * HDEC => SPR 310 (Power 2.04 hypv)
2056 * HIOR => SPR 311 (hypv)
2057 * RMOR => SPR 312 (970)
2058 * HRMOR => SPR 313 (Power 2.04 hypv)
2059 * HSRR0 => SPR 314 (Power 2.04 hypv)
2060 * HSRR1 => SPR 315 (Power 2.04 hypv)
2061 * LPIDR => SPR 317 (970)
2062 * EPR => SPR 702 (Power 2.04 emb)
2063 * perf => 768-783 (Power 2.04)
2064 * perf => 784-799 (Power 2.04)
2065 * PPR => SPR 896 (Power 2.04)
2066 * DABRX => 1015 (Power 2.04 hypv)
2067 * FPECR => SPR 1022 (?)
2068 * ... and more (thermal management, performance counters, ...)
2069 */
2070
2071 /*****************************************************************************/
2072 /* Exception vectors models */
2073 static void init_excp_4xx_softmmu(CPUPPCState *env)
2074 {
2075 #if !defined(CONFIG_USER_ONLY)
2076 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2077 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2078 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2079 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2080 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2081 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2082 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2083 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2084 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2085 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2086 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2087 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2088 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2089 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2090 env->ivor_mask = 0x0000FFF0UL;
2091 env->ivpr_mask = 0xFFFF0000UL;
2092 /* Hardware reset vector */
2093 env->hreset_vector = 0xFFFFFFFCUL;
2094 #endif
2095 }
2096
2097 static void init_excp_MPC5xx(CPUPPCState *env)
2098 {
2099 #if !defined(CONFIG_USER_ONLY)
2100 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2101 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2102 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2103 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2104 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2105 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2106 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2107 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2108 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2109 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2110 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2111 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2112 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2113 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2114 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2115 env->ivor_mask = 0x0000FFF0UL;
2116 env->ivpr_mask = 0xFFFF0000UL;
2117 /* Hardware reset vector */
2118 env->hreset_vector = 0x00000100UL;
2119 #endif
2120 }
2121
2122 static void init_excp_MPC8xx(CPUPPCState *env)
2123 {
2124 #if !defined(CONFIG_USER_ONLY)
2125 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2126 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2127 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2128 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2129 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2130 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2131 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2132 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2133 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2134 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2135 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2136 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2137 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2138 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2139 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2140 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2141 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2142 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2143 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2144 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2145 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2146 env->ivor_mask = 0x0000FFF0UL;
2147 env->ivpr_mask = 0xFFFF0000UL;
2148 /* Hardware reset vector */
2149 env->hreset_vector = 0x00000100UL;
2150 #endif
2151 }
2152
2153 static void init_excp_G2(CPUPPCState *env)
2154 {
2155 #if !defined(CONFIG_USER_ONLY)
2156 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2157 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2158 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2159 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2160 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2161 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2162 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2163 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2164 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2165 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2166 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2167 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2168 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2169 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2170 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2171 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2172 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2173 /* Hardware reset vector */
2174 env->hreset_vector = 0x00000100UL;
2175 #endif
2176 }
2177
2178 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2179 {
2180 #if !defined(CONFIG_USER_ONLY)
2181 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2182 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2183 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2184 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2185 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2186 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2187 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2188 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2189 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2190 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2191 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2192 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2193 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2194 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2195 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2196 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2197 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2198 /*
2199 * These two are the same IVOR as POWERPC_EXCP_VPU and
2200 * POWERPC_EXCP_VPUA. We deal with that when dispatching at
2201 * powerpc_excp().
2202 */
2203 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2204 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2205
2206 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2207 env->ivor_mask = 0x0000FFF7UL;
2208 env->ivpr_mask = ivpr_mask;
2209 /* Hardware reset vector */
2210 env->hreset_vector = 0xFFFFFFFCUL;
2211 #endif
2212 }
2213
2214 static void init_excp_BookE(CPUPPCState *env)
2215 {
2216 #if !defined(CONFIG_USER_ONLY)
2217 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2218 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2219 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2220 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2221 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2222 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2223 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2224 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2225 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2226 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2227 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2228 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2229 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2230 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2231 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2232 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2233 env->ivor_mask = 0x0000FFF0UL;
2234 env->ivpr_mask = 0xFFFF0000UL;
2235 /* Hardware reset vector */
2236 env->hreset_vector = 0xFFFFFFFCUL;
2237 #endif
2238 }
2239
2240 static void init_excp_603(CPUPPCState *env)
2241 {
2242 #if !defined(CONFIG_USER_ONLY)
2243 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2244 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2245 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2246 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2247 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2248 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2249 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2250 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2251 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2252 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2253 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2254 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2255 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2256 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2257 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2258 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2259 /* Hardware reset vector */
2260 env->hreset_vector = 0x00000100UL;
2261 #endif
2262 }
2263
2264 static void init_excp_604(CPUPPCState *env)
2265 {
2266 #if !defined(CONFIG_USER_ONLY)
2267 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2268 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2269 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2270 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2271 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2272 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2273 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2274 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2275 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2276 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2277 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2278 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2279 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2280 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2281 /* Hardware reset vector */
2282 env->hreset_vector = 0x00000100UL;
2283 #endif
2284 }
2285
2286 static void init_excp_7x0(CPUPPCState *env)
2287 {
2288 #if !defined(CONFIG_USER_ONLY)
2289 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2290 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2291 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2292 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2293 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2294 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2295 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2296 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2297 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2298 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2299 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2300 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2301 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2302 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2303 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2304 /* Hardware reset vector */
2305 env->hreset_vector = 0x00000100UL;
2306 #endif
2307 }
2308
2309 static void init_excp_750cl(CPUPPCState *env)
2310 {
2311 #if !defined(CONFIG_USER_ONLY)
2312 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2313 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2314 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2315 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2316 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2317 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2318 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2319 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2320 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2321 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2322 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2323 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2324 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2325 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2326 /* Hardware reset vector */
2327 env->hreset_vector = 0x00000100UL;
2328 #endif
2329 }
2330
2331 static void init_excp_750cx(CPUPPCState *env)
2332 {
2333 #if !defined(CONFIG_USER_ONLY)
2334 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2335 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2336 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2337 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2338 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2339 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2340 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2341 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2342 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2343 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2344 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2345 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2346 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2347 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2348 /* Hardware reset vector */
2349 env->hreset_vector = 0x00000100UL;
2350 #endif
2351 }
2352
2353 /* XXX: Check if this is correct */
2354 static void init_excp_7x5(CPUPPCState *env)
2355 {
2356 #if !defined(CONFIG_USER_ONLY)
2357 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2358 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2359 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2360 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2361 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2362 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2363 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2364 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2365 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2366 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2367 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2368 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2369 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2370 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2371 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2372 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2373 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2374 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2375 /* Hardware reset vector */
2376 env->hreset_vector = 0x00000100UL;
2377 #endif
2378 }
2379
2380 static void init_excp_7400(CPUPPCState *env)
2381 {
2382 #if !defined(CONFIG_USER_ONLY)
2383 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2384 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2385 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2386 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2387 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2388 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2389 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2390 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2391 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2392 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2393 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2394 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2395 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2396 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2397 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2398 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2399 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2400 /* Hardware reset vector */
2401 env->hreset_vector = 0x00000100UL;
2402 #endif
2403 }
2404
2405 static void init_excp_7450(CPUPPCState *env)
2406 {
2407 #if !defined(CONFIG_USER_ONLY)
2408 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2409 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2410 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2411 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2412 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2413 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2414 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2415 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2416 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2417 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2418 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2419 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2420 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2421 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2422 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2423 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2424 /* Hardware reset vector */
2425 env->hreset_vector = 0x00000100UL;
2426 #endif
2427 }
2428
2429 #if defined(TARGET_PPC64)
2430 static void init_excp_970(CPUPPCState *env)
2431 {
2432 #if !defined(CONFIG_USER_ONLY)
2433 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2434 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2435 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2436 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2437 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2438 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2439 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2440 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2441 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2442 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2443 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2444 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2445 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2446 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2447 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2448 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2449 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2450 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2451 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2452 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2453 /* Hardware reset vector */
2454 env->hreset_vector = 0x0000000000000100ULL;
2455 #endif
2456 }
2457
2458 static void init_excp_POWER7(CPUPPCState *env)
2459 {
2460 #if !defined(CONFIG_USER_ONLY)
2461 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2462 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2463 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2464 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2465 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2466 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2467 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2468 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2469 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2470 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2471 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2472 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2473 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2474 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2475 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2476 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2477 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2478 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2479 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2480 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2481 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
2482 /* Hardware reset vector */
2483 env->hreset_vector = 0x0000000000000100ULL;
2484 #endif
2485 }
2486
2487 static void init_excp_POWER8(CPUPPCState *env)
2488 {
2489 init_excp_POWER7(env);
2490
2491 #if !defined(CONFIG_USER_ONLY)
2492 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2493 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2494 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2495 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2496 #endif
2497 }
2498
2499 static void init_excp_POWER9(CPUPPCState *env)
2500 {
2501 init_excp_POWER8(env);
2502
2503 #if !defined(CONFIG_USER_ONLY)
2504 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
2505 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2506 #endif
2507 }
2508
2509 static void init_excp_POWER10(CPUPPCState *env)
2510 {
2511 init_excp_POWER9(env);
2512 }
2513
2514 #endif
2515
2516 /*****************************************************************************/
2517 /* Power management enable checks */
2518 static int check_pow_none(CPUPPCState *env)
2519 {
2520 return 0;
2521 }
2522
2523 static int check_pow_nocheck(CPUPPCState *env)
2524 {
2525 return 1;
2526 }
2527
2528 static int check_pow_hid0(CPUPPCState *env)
2529 {
2530 if (env->spr[SPR_HID0] & 0x00E00000) {
2531 return 1;
2532 }
2533
2534 return 0;
2535 }
2536
2537 static int check_pow_hid0_74xx(CPUPPCState *env)
2538 {
2539 if (env->spr[SPR_HID0] & 0x00600000) {
2540 return 1;
2541 }
2542
2543 return 0;
2544 }
2545
2546 /*****************************************************************************/
2547 /* PowerPC implementations definitions */
2548
2549 #define POWERPC_FAMILY(_name) \
2550 static void \
2551 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
2552 \
2553 static const TypeInfo \
2554 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
2555 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
2556 .parent = TYPE_POWERPC_CPU, \
2557 .abstract = true, \
2558 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
2559 }; \
2560 \
2561 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
2562 { \
2563 type_register_static( \
2564 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
2565 } \
2566 \
2567 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
2568 \
2569 static void glue(glue(ppc_, _name), _cpu_family_class_init)
2570
2571 static void init_proc_405(CPUPPCState *env)
2572 {
2573 register_40x_sprs(env);
2574 register_405_sprs(env);
2575 register_usprgh_sprs(env);
2576
2577 /* Memory management */
2578 #if !defined(CONFIG_USER_ONLY)
2579 env->nb_tlb = 64;
2580 env->nb_ways = 1;
2581 env->id_tlbs = 0;
2582 env->tlb_type = TLB_EMB;
2583 #endif
2584 init_excp_4xx_softmmu(env);
2585 env->dcache_line_size = 32;
2586 env->icache_line_size = 32;
2587 /* Allocate hardware IRQ controller */
2588 ppc40x_irq_init(env_archcpu(env));
2589
2590 SET_FIT_PERIOD(8, 12, 16, 20);
2591 SET_WDT_PERIOD(16, 20, 24, 28);
2592 }
2593
2594 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
2595 {
2596 DeviceClass *dc = DEVICE_CLASS(oc);
2597 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2598
2599 dc->desc = "PowerPC 405";
2600 pcc->init_proc = init_proc_405;
2601 pcc->check_pow = check_pow_nocheck;
2602 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2603 PPC_DCR | PPC_WRTEE |
2604 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2605 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2606 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2607 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2608 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
2609 pcc->msr_mask = (1ull << MSR_WE) |
2610 (1ull << MSR_CE) |
2611 (1ull << MSR_EE) |
2612 (1ull << MSR_PR) |
2613 (1ull << MSR_FP) |
2614 (1ull << MSR_ME) |
2615 (1ull << MSR_DWE) |
2616 (1ull << MSR_DE) |
2617 (1ull << MSR_IR) |
2618 (1ull << MSR_DR);
2619 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
2620 pcc->excp_model = POWERPC_EXCP_40x;
2621 pcc->bus_model = PPC_FLAGS_INPUT_405;
2622 pcc->bfd_mach = bfd_mach_ppc_403;
2623 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2624 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2625 }
2626
2627 static void init_proc_440EP(CPUPPCState *env)
2628 {
2629 register_BookE_sprs(env, 0x000000000000FFFFULL);
2630 register_440_sprs(env);
2631 register_usprgh_sprs(env);
2632
2633 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2634 SPR_NOACCESS, SPR_NOACCESS,
2635 &spr_read_generic, &spr_write_generic,
2636 0x00000000);
2637 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2638 SPR_NOACCESS, SPR_NOACCESS,
2639 &spr_read_generic, &spr_write_generic,
2640 0x00000000);
2641 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2642 SPR_NOACCESS, SPR_NOACCESS,
2643 &spr_read_generic, &spr_write_generic,
2644 0x00000000);
2645
2646 spr_register(env, SPR_440_CCR1, "CCR1",
2647 SPR_NOACCESS, SPR_NOACCESS,
2648 &spr_read_generic, &spr_write_generic,
2649 0x00000000);
2650 /* Memory management */
2651 #if !defined(CONFIG_USER_ONLY)
2652 env->nb_tlb = 64;
2653 env->nb_ways = 1;
2654 env->id_tlbs = 0;
2655 env->tlb_type = TLB_EMB;
2656 #endif
2657 init_excp_BookE(env);
2658 env->dcache_line_size = 32;
2659 env->icache_line_size = 32;
2660 ppc40x_irq_init(env_archcpu(env));
2661
2662 SET_FIT_PERIOD(12, 16, 20, 24);
2663 SET_WDT_PERIOD(20, 24, 28, 32);
2664 }
2665
2666 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
2667 {
2668 DeviceClass *dc = DEVICE_CLASS(oc);
2669 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2670
2671 dc->desc = "PowerPC 440 EP";
2672 pcc->init_proc = init_proc_440EP;
2673 pcc->check_pow = check_pow_nocheck;
2674 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2675 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2676 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2677 PPC_FLOAT_STFIWX |
2678 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2679 PPC_CACHE | PPC_CACHE_ICBI |
2680 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2681 PPC_MEM_TLBSYNC | PPC_MFTB |
2682 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2683 PPC_440_SPEC;
2684 pcc->msr_mask = (1ull << MSR_POW) |
2685 (1ull << MSR_CE) |
2686 (1ull << MSR_EE) |
2687 (1ull << MSR_PR) |
2688 (1ull << MSR_FP) |
2689 (1ull << MSR_ME) |
2690 (1ull << MSR_FE0) |
2691 (1ull << MSR_DWE) |
2692 (1ull << MSR_DE) |
2693 (1ull << MSR_FE1) |
2694 (1ull << MSR_IR) |
2695 (1ull << MSR_DR);
2696 pcc->mmu_model = POWERPC_MMU_BOOKE;
2697 pcc->excp_model = POWERPC_EXCP_BOOKE;
2698 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2699 pcc->bfd_mach = bfd_mach_ppc_403;
2700 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2701 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2702 }
2703
2704 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
2705 {
2706 DeviceClass *dc = DEVICE_CLASS(oc);
2707 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2708
2709 dc->desc = "PowerPC 460 EX";
2710 pcc->init_proc = init_proc_440EP;
2711 pcc->check_pow = check_pow_nocheck;
2712 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2713 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2714 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2715 PPC_FLOAT_STFIWX |
2716 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
2717 PPC_CACHE | PPC_CACHE_ICBI |
2718 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2719 PPC_MEM_TLBSYNC | PPC_MFTB |
2720 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2721 PPC_440_SPEC;
2722 pcc->msr_mask = (1ull << MSR_POW) |
2723 (1ull << MSR_CE) |
2724 (1ull << MSR_EE) |
2725 (1ull << MSR_PR) |
2726 (1ull << MSR_FP) |
2727 (1ull << MSR_ME) |
2728 (1ull << MSR_FE0) |
2729 (1ull << MSR_DWE) |
2730 (1ull << MSR_DE) |
2731 (1ull << MSR_FE1) |
2732 (1ull << MSR_IR) |
2733 (1ull << MSR_DR);
2734 pcc->mmu_model = POWERPC_MMU_BOOKE;
2735 pcc->excp_model = POWERPC_EXCP_BOOKE;
2736 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2737 pcc->bfd_mach = bfd_mach_ppc_403;
2738 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2739 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2740 }
2741
2742 static void init_proc_440GP(CPUPPCState *env)
2743 {
2744 register_BookE_sprs(env, 0x000000000000FFFFULL);
2745 register_440_sprs(env);
2746 register_usprgh_sprs(env);
2747
2748 /* Memory management */
2749 #if !defined(CONFIG_USER_ONLY)
2750 env->nb_tlb = 64;
2751 env->nb_ways = 1;
2752 env->id_tlbs = 0;
2753 env->tlb_type = TLB_EMB;
2754 #endif
2755 init_excp_BookE(env);
2756 env->dcache_line_size = 32;
2757 env->icache_line_size = 32;
2758 /* XXX: TODO: allocate internal IRQ controller */
2759
2760 SET_FIT_PERIOD(12, 16, 20, 24);
2761 SET_WDT_PERIOD(20, 24, 28, 32);
2762 }
2763
2764 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
2765 {
2766 DeviceClass *dc = DEVICE_CLASS(oc);
2767 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2768
2769 dc->desc = "PowerPC 440 GP";
2770 pcc->init_proc = init_proc_440GP;
2771 pcc->check_pow = check_pow_nocheck;
2772 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2773 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
2774 PPC_CACHE | PPC_CACHE_ICBI |
2775 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2776 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
2777 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2778 PPC_440_SPEC;
2779 pcc->msr_mask = (1ull << MSR_POW) |
2780 (1ull << MSR_CE) |
2781 (1ull << MSR_EE) |
2782 (1ull << MSR_PR) |
2783 (1ull << MSR_FP) |
2784 (1ull << MSR_ME) |
2785 (1ull << MSR_FE0) |
2786 (1ull << MSR_DWE) |
2787 (1ull << MSR_DE) |
2788 (1ull << MSR_FE1) |
2789 (1ull << MSR_IR) |
2790 (1ull << MSR_DR);
2791 pcc->mmu_model = POWERPC_MMU_BOOKE;
2792 pcc->excp_model = POWERPC_EXCP_BOOKE;
2793 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2794 pcc->bfd_mach = bfd_mach_ppc_403;
2795 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2796 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2797 }
2798
2799 static void init_proc_440x5(CPUPPCState *env)
2800 {
2801 register_BookE_sprs(env, 0x000000000000FFFFULL);
2802 register_440_sprs(env);
2803 register_usprgh_sprs(env);
2804
2805 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2806 SPR_NOACCESS, SPR_NOACCESS,
2807 &spr_read_generic, &spr_write_generic,
2808 0x00000000);
2809 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2810 SPR_NOACCESS, SPR_NOACCESS,
2811 &spr_read_generic, &spr_write_generic,
2812 0x00000000);
2813 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2814 SPR_NOACCESS, SPR_NOACCESS,
2815 &spr_read_generic, &spr_write_generic,
2816 0x00000000);
2817
2818 spr_register(env, SPR_440_CCR1, "CCR1",
2819 SPR_NOACCESS, SPR_NOACCESS,
2820 &spr_read_generic, &spr_write_generic,
2821 0x00000000);
2822 /* Memory management */
2823 #if !defined(CONFIG_USER_ONLY)
2824 env->nb_tlb = 64;
2825 env->nb_ways = 1;
2826 env->id_tlbs = 0;
2827 env->tlb_type = TLB_EMB;
2828 #endif
2829 init_excp_BookE(env);
2830 env->dcache_line_size = 32;
2831 env->icache_line_size = 32;
2832 ppc40x_irq_init(env_archcpu(env));
2833
2834 SET_FIT_PERIOD(12, 16, 20, 24);
2835 SET_WDT_PERIOD(20, 24, 28, 32);
2836 }
2837
2838 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
2839 {
2840 DeviceClass *dc = DEVICE_CLASS(oc);
2841 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2842
2843 dc->desc = "PowerPC 440x5";
2844 pcc->init_proc = init_proc_440x5;
2845 pcc->check_pow = check_pow_nocheck;
2846 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2847 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2848 PPC_CACHE | PPC_CACHE_ICBI |
2849 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2850 PPC_MEM_TLBSYNC | PPC_MFTB |
2851 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2852 PPC_440_SPEC;
2853 pcc->msr_mask = (1ull << MSR_POW) |
2854 (1ull << MSR_CE) |
2855 (1ull << MSR_EE) |
2856 (1ull << MSR_PR) |
2857 (1ull << MSR_FP) |
2858 (1ull << MSR_ME) |
2859 (1ull << MSR_FE0) |
2860 (1ull << MSR_DWE) |
2861 (1ull << MSR_DE) |
2862 (1ull << MSR_FE1) |
2863 (1ull << MSR_IR) |
2864 (1ull << MSR_DR);
2865 pcc->mmu_model = POWERPC_MMU_BOOKE;
2866 pcc->excp_model = POWERPC_EXCP_BOOKE;
2867 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2868 pcc->bfd_mach = bfd_mach_ppc_403;
2869 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2870 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2871 }
2872
2873 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
2874 {
2875 DeviceClass *dc = DEVICE_CLASS(oc);
2876 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2877
2878 dc->desc = "PowerPC 440x5 with double precision FPU";
2879 pcc->init_proc = init_proc_440x5;
2880 pcc->check_pow = check_pow_nocheck;
2881 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2882 PPC_FLOAT | PPC_FLOAT_FSQRT |
2883 PPC_FLOAT_STFIWX |
2884 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2885 PPC_CACHE | PPC_CACHE_ICBI |
2886 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2887 PPC_MEM_TLBSYNC | PPC_MFTB |
2888 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2889 PPC_440_SPEC;
2890 pcc->insns_flags2 = PPC2_FP_CVT_S64;
2891 pcc->msr_mask = (1ull << MSR_POW) |
2892 (1ull << MSR_CE) |
2893 (1ull << MSR_EE) |
2894 (1ull << MSR_PR) |
2895 (1ull << MSR_FP) |
2896 (1ull << MSR_ME) |
2897 (1ull << MSR_FE0) |
2898 (1ull << MSR_DWE) |
2899 (1ull << MSR_DE) |
2900 (1ull << MSR_FE1) |
2901 (1ull << MSR_IR) |
2902 (1ull << MSR_DR);
2903 pcc->mmu_model = POWERPC_MMU_BOOKE;
2904 pcc->excp_model = POWERPC_EXCP_BOOKE;
2905 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2906 pcc->bfd_mach = bfd_mach_ppc_403;
2907 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2908 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2909 }
2910
2911 static void init_proc_MPC5xx(CPUPPCState *env)
2912 {
2913 register_5xx_8xx_sprs(env);
2914 register_5xx_sprs(env);
2915 init_excp_MPC5xx(env);
2916 env->dcache_line_size = 32;
2917 env->icache_line_size = 32;
2918 /* XXX: TODO: allocate internal IRQ controller */
2919 }
2920
2921 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
2922 {
2923 DeviceClass *dc = DEVICE_CLASS(oc);
2924 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2925
2926 dc->desc = "Freescale 5xx cores (aka RCPU)";
2927 pcc->init_proc = init_proc_MPC5xx;
2928 pcc->check_pow = check_pow_none;
2929 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2930 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2931 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
2932 PPC_MFTB;
2933 pcc->msr_mask = (1ull << MSR_ILE) |
2934 (1ull << MSR_EE) |
2935 (1ull << MSR_PR) |
2936 (1ull << MSR_FP) |
2937 (1ull << MSR_ME) |
2938 (1ull << MSR_FE0) |
2939 (1ull << MSR_SE) |
2940 (1ull << MSR_DE) |
2941 (1ull << MSR_FE1) |
2942 (1ull << MSR_EP) |
2943 (1ull << MSR_RI) |
2944 (1ull << MSR_LE);
2945 pcc->mmu_model = POWERPC_MMU_REAL;
2946 pcc->excp_model = POWERPC_EXCP_6xx;
2947 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2948 pcc->bfd_mach = bfd_mach_ppc_505;
2949 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2950 POWERPC_FLAG_BUS_CLK;
2951 }
2952
2953 static void init_proc_MPC8xx(CPUPPCState *env)
2954 {
2955 register_5xx_8xx_sprs(env);
2956 register_8xx_sprs(env);
2957 init_excp_MPC8xx(env);
2958 env->dcache_line_size = 32;
2959 env->icache_line_size = 32;
2960 /* XXX: TODO: allocate internal IRQ controller */
2961 }
2962
2963 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
2964 {
2965 DeviceClass *dc = DEVICE_CLASS(oc);
2966 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2967
2968 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
2969 pcc->init_proc = init_proc_MPC8xx;
2970 pcc->check_pow = check_pow_none;
2971 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2972 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2973 PPC_CACHE_ICBI | PPC_MFTB;
2974 pcc->msr_mask = (1ull << MSR_ILE) |
2975 (1ull << MSR_EE) |
2976 (1ull << MSR_PR) |
2977 (1ull << MSR_FP) |
2978 (1ull << MSR_ME) |
2979 (1ull << MSR_SE) |
2980 (1ull << MSR_DE) |
2981 (1ull << MSR_EP) |
2982 (1ull << MSR_IR) |
2983 (1ull << MSR_DR) |
2984 (1ull << MSR_RI) |
2985 (1ull << MSR_LE);
2986 pcc->mmu_model = POWERPC_MMU_MPC8xx;
2987 pcc->excp_model = POWERPC_EXCP_6xx;
2988 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2989 pcc->bfd_mach = bfd_mach_ppc_860;
2990 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2991 POWERPC_FLAG_BUS_CLK;
2992 }
2993
2994 /* Freescale 82xx cores (aka PowerQUICC-II) */
2995
2996 static void init_proc_G2(CPUPPCState *env)
2997 {
2998 register_ne_601_sprs(env);
2999 register_sdr1_sprs(env);
3000 register_G2_sprs(env);
3001
3002 /* Memory management */
3003 register_low_BATs(env);
3004 register_high_BATs(env);
3005 register_6xx_7xx_soft_tlb(env, 64, 2);
3006 init_excp_G2(env);
3007 env->dcache_line_size = 32;
3008 env->icache_line_size = 32;
3009 /* Allocate hardware IRQ controller */
3010 ppc6xx_irq_init(env_archcpu(env));
3011 }
3012
3013 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
3014 {
3015 DeviceClass *dc = DEVICE_CLASS(oc);
3016 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3017
3018 dc->desc = "PowerPC G2";
3019 pcc->init_proc = init_proc_G2;
3020 pcc->check_pow = check_pow_hid0;
3021 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3022 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3023 PPC_FLOAT_STFIWX |
3024 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3025 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3026 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3027 PPC_SEGMENT | PPC_EXTERN;
3028 pcc->msr_mask = (1ull << MSR_POW) |
3029 (1ull << MSR_TGPR) |
3030 (1ull << MSR_EE) |
3031 (1ull << MSR_PR) |
3032 (1ull << MSR_FP) |
3033 (1ull << MSR_ME) |
3034 (1ull << MSR_FE0) |
3035 (1ull << MSR_SE) |
3036 (1ull << MSR_DE) |
3037 (1ull << MSR_FE1) |
3038 (1ull << MSR_AL) |
3039 (1ull << MSR_EP) |
3040 (1ull << MSR_IR) |
3041 (1ull << MSR_DR) |
3042 (1ull << MSR_RI);
3043 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3044 pcc->excp_model = POWERPC_EXCP_6xx;
3045 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3046 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3047 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3048 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3049 }
3050
3051 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
3052 {
3053 DeviceClass *dc = DEVICE_CLASS(oc);
3054 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3055
3056 dc->desc = "PowerPC G2LE";
3057 pcc->init_proc = init_proc_G2;
3058 pcc->check_pow = check_pow_hid0;
3059 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3060 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3061 PPC_FLOAT_STFIWX |
3062 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3063 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3064 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3065 PPC_SEGMENT | PPC_EXTERN;
3066 pcc->msr_mask = (1ull << MSR_POW) |
3067 (1ull << MSR_TGPR) |
3068 (1ull << MSR_ILE) |
3069 (1ull << MSR_EE) |
3070 (1ull << MSR_PR) |
3071 (1ull << MSR_FP) |
3072 (1ull << MSR_ME) |
3073 (1ull << MSR_FE0) |
3074 (1ull << MSR_SE) |
3075 (1ull << MSR_DE) |
3076 (1ull << MSR_FE1) |
3077 (1ull << MSR_AL) |
3078 (1ull << MSR_EP) |
3079 (1ull << MSR_IR) |
3080 (1ull << MSR_DR) |
3081 (1ull << MSR_RI) |
3082 (1ull << MSR_LE);
3083 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3084 pcc->excp_model = POWERPC_EXCP_6xx;
3085 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3086 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3087 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3088 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3089 }
3090
3091 static void init_proc_e200(CPUPPCState *env)
3092 {
3093 register_BookE_sprs(env, 0x000000070000FFFFULL);
3094
3095 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
3096 &spr_read_spefscr, &spr_write_spefscr,
3097 &spr_read_spefscr, &spr_write_spefscr,
3098 0x00000000);
3099 /* Memory management */
3100 register_BookE206_sprs(env, 0x0000005D, NULL, 0);
3101 register_usprgh_sprs(env);
3102
3103 spr_register(env, SPR_HID0, "HID0",
3104 SPR_NOACCESS, SPR_NOACCESS,
3105 &spr_read_generic, &spr_write_generic,
3106 0x00000000);
3107
3108 spr_register(env, SPR_HID1, "HID1",
3109 SPR_NOACCESS, SPR_NOACCESS,
3110 &spr_read_generic, &spr_write_generic,
3111 0x00000000);
3112
3113 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
3114 SPR_NOACCESS, SPR_NOACCESS,
3115 &spr_read_generic, &spr_write_generic,
3116 0x00000000);
3117
3118 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3119 SPR_NOACCESS, SPR_NOACCESS,
3120 &spr_read_generic, &spr_write_generic,
3121 0x00000000);
3122
3123 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
3124 SPR_NOACCESS, SPR_NOACCESS,
3125 &spr_read_generic, &spr_write_generic,
3126 0x00000000);
3127
3128 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
3129 SPR_NOACCESS, SPR_NOACCESS,
3130 &spr_read_generic, &spr_write_generic,
3131 0x00000000);
3132
3133 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
3134 SPR_NOACCESS, SPR_NOACCESS,
3135 &spr_read_generic, &spr_write_generic,
3136 0x00000000);
3137
3138 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3139 &spr_read_generic, SPR_NOACCESS,
3140 &spr_read_generic, SPR_NOACCESS,
3141 0x00000000);
3142
3143 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3144 SPR_NOACCESS, SPR_NOACCESS,
3145 &spr_read_generic, &spr_write_generic,
3146 0x00000000);
3147
3148 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
3149 SPR_NOACCESS, SPR_NOACCESS,
3150 &spr_read_generic, &spr_write_generic,
3151 0x00000000);
3152
3153 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
3154 SPR_NOACCESS, SPR_NOACCESS,
3155 &spr_read_generic, &spr_write_generic,
3156 0x00000000);
3157
3158 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
3159 SPR_NOACCESS, SPR_NOACCESS,
3160 &spr_read_generic, &spr_write_generic,
3161 0x00000000);
3162
3163 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3164 SPR_NOACCESS, SPR_NOACCESS,
3165 &spr_read_generic, &spr_write_generic,
3166 0x00000000);
3167
3168 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3169 SPR_NOACCESS, SPR_NOACCESS,
3170 &spr_read_generic, &spr_write_generic,
3171 0x00000000);
3172
3173 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
3174 SPR_NOACCESS, SPR_NOACCESS,
3175 &spr_read_generic, &spr_write_generic,
3176 0x00000000); /* TOFIX */
3177 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
3178 SPR_NOACCESS, SPR_NOACCESS,
3179 &spr_read_generic, &spr_write_generic,
3180 0x00000000);
3181 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
3182 SPR_NOACCESS, SPR_NOACCESS,
3183 &spr_read_generic, &spr_write_generic,
3184 0x00000000);
3185 #if !defined(CONFIG_USER_ONLY)
3186 env->nb_tlb = 64;
3187 env->nb_ways = 1;
3188 env->id_tlbs = 0;
3189 env->tlb_type = TLB_EMB;
3190 #endif
3191 init_excp_e200(env, 0xFFFF0000UL);
3192 env->dcache_line_size = 32;
3193 env->icache_line_size = 32;
3194 /* XXX: TODO: allocate internal IRQ controller */
3195 }
3196
3197 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
3198 {
3199 DeviceClass *dc = DEVICE_CLASS(oc);
3200 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3201
3202 dc->desc = "e200 core";
3203 pcc->init_proc = init_proc_e200;
3204 pcc->check_pow = check_pow_hid0;
3205 /*
3206 * XXX: unimplemented instructions:
3207 * dcblc
3208 * dcbtlst
3209 * dcbtstls
3210 * icblc
3211 * icbtls
3212 * tlbivax
3213 * all SPE multiply-accumulate instructions
3214 */
3215 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3216 PPC_SPE | PPC_SPE_SINGLE |
3217 PPC_WRTEE | PPC_RFDI |
3218 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3219 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3220 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
3221 PPC_BOOKE;
3222 pcc->msr_mask = (1ull << MSR_UCLE) |
3223 (1ull << MSR_SPE) |
3224 (1ull << MSR_POW) |
3225 (1ull << MSR_CE) |
3226 (1ull << MSR_EE) |
3227 (1ull << MSR_PR) |
3228 (1ull << MSR_FP) |
3229 (1ull << MSR_ME) |
3230 (1ull << MSR_FE0) |
3231 (1ull << MSR_DWE) |
3232 (1ull << MSR_DE) |
3233 (1ull << MSR_FE1) |
3234 (1ull << MSR_IR) |
3235 (1ull << MSR_DR);
3236 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3237 pcc->excp_model = POWERPC_EXCP_BOOKE;
3238 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3239 pcc->bfd_mach = bfd_mach_ppc_860;
3240 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3241 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3242 POWERPC_FLAG_BUS_CLK;
3243 }
3244
3245 static void init_proc_e300(CPUPPCState *env)
3246 {
3247 register_ne_601_sprs(env);
3248 register_sdr1_sprs(env);
3249 register_603_sprs(env);
3250 register_e300_sprs(env);
3251
3252 /* Memory management */
3253 register_low_BATs(env);
3254 register_high_BATs(env);
3255 register_6xx_7xx_soft_tlb(env, 64, 2);
3256 init_excp_603(env);
3257 env->dcache_line_size = 32;
3258 env->icache_line_size = 32;
3259 /* Allocate hardware IRQ controller */
3260 ppc6xx_irq_init(env_archcpu(env));
3261 }
3262
3263 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
3264 {
3265 DeviceClass *dc = DEVICE_CLASS(oc);
3266 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3267
3268 dc->desc = "e300 core";
3269 pcc->init_proc = init_proc_e300;
3270 pcc->check_pow = check_pow_hid0;
3271 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3272 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3273 PPC_FLOAT_STFIWX |
3274 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3275 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3276 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3277 PPC_SEGMENT | PPC_EXTERN;
3278 pcc->msr_mask = (1ull << MSR_POW) |
3279 (1ull << MSR_TGPR) |
3280 (1ull << MSR_ILE) |
3281 (1ull << MSR_EE) |
3282 (1ull << MSR_PR) |
3283 (1ull << MSR_FP) |
3284 (1ull << MSR_ME) |
3285 (1ull << MSR_FE0) |
3286 (1ull << MSR_SE) |
3287 (1ull << MSR_DE) |
3288 (1ull << MSR_FE1) |
3289 (1ull << MSR_AL) |
3290 (1ull << MSR_EP) |
3291 (1ull << MSR_IR) |
3292 (1ull << MSR_DR) |
3293 (1ull << MSR_RI) |
3294 (1ull << MSR_LE);
3295 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3296 pcc->excp_model = POWERPC_EXCP_6xx;
3297 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3298 pcc->bfd_mach = bfd_mach_ppc_603;
3299 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3300 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3301 }
3302
3303 enum fsl_e500_version {
3304 fsl_e500v1,
3305 fsl_e500v2,
3306 fsl_e500mc,
3307 fsl_e5500,
3308 fsl_e6500,
3309 };
3310
3311 static void init_proc_e500(CPUPPCState *env, int version)
3312 {
3313 uint32_t tlbncfg[2];
3314 uint64_t ivor_mask;
3315 uint64_t ivpr_mask = 0xFFFF0000ULL;
3316 uint32_t l1cfg0 = 0x3800 /* 8 ways */
3317 | 0x0020; /* 32 kb */
3318 uint32_t l1cfg1 = 0x3800 /* 8 ways */
3319 | 0x0020; /* 32 kb */
3320 uint32_t mmucfg = 0;
3321 #if !defined(CONFIG_USER_ONLY)
3322 int i;
3323 #endif
3324
3325 /*
3326 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
3327 * complain when accessing them.
3328 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
3329 */
3330 switch (version) {
3331 case fsl_e500v1:
3332 case fsl_e500v2:
3333 default:
3334 ivor_mask = 0x0000000F0000FFFFULL;
3335 break;
3336 case fsl_e500mc:
3337 case fsl_e5500:
3338 ivor_mask = 0x000003FE0000FFFFULL;
3339 break;
3340 case fsl_e6500:
3341 ivor_mask = 0x000003FF0000FFFFULL;
3342 break;
3343 }
3344 register_BookE_sprs(env, ivor_mask);
3345 register_usprg3_sprs(env);
3346 /* Processor identification */
3347 spr_register(env, SPR_BOOKE_PIR, "PIR",
3348 SPR_NOACCESS, SPR_NOACCESS,
3349 &spr_read_generic, &spr_write_pir,
3350 0x00000000);
3351
3352 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
3353 &spr_read_spefscr, &spr_write_spefscr,
3354 &spr_read_spefscr, &spr_write_spefscr,
3355 0x00000000);
3356 #if !defined(CONFIG_USER_ONLY)
3357 /* Memory management */
3358 env->nb_pids = 3;
3359 env->nb_ways = 2;
3360 env->id_tlbs = 0;
3361 switch (version) {
3362 case fsl_e500v1:
3363 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
3364 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
3365 break;
3366 case fsl_e500v2:
3367 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
3368 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
3369 break;
3370 case fsl_e500mc:
3371 case fsl_e5500:
3372 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
3373 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
3374 break;
3375 case fsl_e6500:
3376 mmucfg = 0x6510B45;
3377 env->nb_pids = 1;
3378 tlbncfg[0] = 0x08052400;
3379 tlbncfg[1] = 0x40028040;
3380 break;
3381 default:
3382 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
3383 env->spr[SPR_PVR]);
3384 }
3385 #endif
3386 /* Cache sizes */
3387 switch (version) {
3388 case fsl_e500v1:
3389 case fsl_e500v2:
3390 env->dcache_line_size = 32;
3391 env->icache_line_size = 32;
3392 break;
3393 case fsl_e500mc:
3394 case fsl_e5500:
3395 env->dcache_line_size = 64;
3396 env->icache_line_size = 64;
3397 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
3398 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
3399 break;
3400 case fsl_e6500:
3401 env->dcache_line_size = 32;
3402 env->icache_line_size = 32;
3403 l1cfg0 |= 0x0F83820;
3404 l1cfg1 |= 0x0B83820;
3405 break;
3406 default:
3407 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
3408 env->spr[SPR_PVR]);
3409 }
3410 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
3411 register_usprgh_sprs(env);
3412
3413 spr_register(env, SPR_HID0, "HID0",
3414 SPR_NOACCESS, SPR_NOACCESS,
3415 &spr_read_generic, &spr_write_generic,
3416 0x00000000);
3417
3418 spr_register(env, SPR_HID1, "HID1",
3419 SPR_NOACCESS, SPR_NOACCESS,
3420 &spr_read_generic, &spr_write_generic,
3421 0x00000000);
3422
3423 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
3424 SPR_NOACCESS, SPR_NOACCESS,
3425 &spr_read_generic, &spr_write_generic,
3426 0x00000000);
3427
3428 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
3429 SPR_NOACCESS, SPR_NOACCESS,
3430 &spr_read_generic, &spr_write_generic,
3431 0x00000000);
3432
3433 spr_register(env, SPR_Exxx_MCAR, "MCAR",
3434 SPR_NOACCESS, SPR_NOACCESS,
3435 &spr_read_generic, &spr_write_generic,
3436 0x00000000);
3437
3438 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3439 SPR_NOACCESS, SPR_NOACCESS,
3440 &spr_read_generic, &spr_write_generic,
3441 0x00000000);
3442
3443 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
3444 SPR_NOACCESS, SPR_NOACCESS,
3445 &spr_read_generic, &spr_write_generic,
3446 0x00000000);
3447
3448 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3449 SPR_NOACCESS, SPR_NOACCESS,
3450 &spr_read_generic, &spr_write_generic,
3451 0x00000000);
3452
3453 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3454 &spr_read_generic, SPR_NOACCESS,
3455 &spr_read_generic, SPR_NOACCESS,
3456 l1cfg0);
3457 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
3458 &spr_read_generic, SPR_NOACCESS,
3459 &spr_read_generic, SPR_NOACCESS,
3460 l1cfg1);
3461 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3462 SPR_NOACCESS, SPR_NOACCESS,
3463 &spr_read_generic, &spr_write_e500_l1csr0,
3464 0x00000000);
3465 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
3466 SPR_NOACCESS, SPR_NOACCESS,
3467 &spr_read_generic, &spr_write_e500_l1csr1,
3468 0x00000000);
3469 if (version != fsl_e500v1 && version != fsl_e500v2) {
3470 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
3471 SPR_NOACCESS, SPR_NOACCESS,
3472 &spr_read_generic, &spr_write_e500_l2csr0,
3473 0x00000000);
3474 }
3475 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3476 SPR_NOACCESS, SPR_NOACCESS,
3477 &spr_read_generic, &spr_write_generic,
3478 0x00000000);
3479 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3480 SPR_NOACCESS, SPR_NOACCESS,
3481 &spr_read_generic, &spr_write_generic,
3482 0x00000000);
3483 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
3484 SPR_NOACCESS, SPR_NOACCESS,
3485 &spr_read_generic, &spr_write_booke206_mmucsr0,
3486 0x00000000);
3487 spr_register(env, SPR_BOOKE_EPR, "EPR",
3488 SPR_NOACCESS, SPR_NOACCESS,
3489 &spr_read_generic, SPR_NOACCESS,
3490 0x00000000);
3491 /* XXX better abstract into Emb.xxx features */
3492 if ((version == fsl_e5500) || (version == fsl_e6500)) {
3493 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
3494 SPR_NOACCESS, SPR_NOACCESS,
3495 &spr_read_generic, &spr_write_generic,
3496 0x00000000);
3497 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
3498 SPR_NOACCESS, SPR_NOACCESS,
3499 &spr_read_mas73, &spr_write_mas73,
3500 0x00000000);
3501 ivpr_mask = (target_ulong)~0xFFFFULL;
3502 }
3503
3504 if (version == fsl_e6500) {
3505 /* Thread identification */
3506 spr_register(env, SPR_TIR, "TIR",
3507 SPR_NOACCESS, SPR_NOACCESS,
3508 &spr_read_generic, SPR_NOACCESS,
3509 0x00000000);
3510 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
3511 SPR_NOACCESS, SPR_NOACCESS,
3512 &spr_read_generic, SPR_NOACCESS,
3513 0x00000004);
3514 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
3515 SPR_NOACCESS, SPR_NOACCESS,
3516 &spr_read_generic, SPR_NOACCESS,
3517 0x7FFFFFFC);
3518 }
3519
3520 #if !defined(CONFIG_USER_ONLY)
3521 env->nb_tlb = 0;
3522 env->tlb_type = TLB_MAS;
3523 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
3524 env->nb_tlb += booke206_tlb_size(env, i);
3525 }
3526 #endif
3527
3528 init_excp_e200(env, ivpr_mask);
3529 /* Allocate hardware IRQ controller */
3530 ppce500_irq_init(env_archcpu(env));
3531 }
3532
3533 static void init_proc_e500v1(CPUPPCState *env)
3534 {
3535 init_proc_e500(env, fsl_e500v1);
3536 }
3537
3538 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
3539 {
3540 DeviceClass *dc = DEVICE_CLASS(oc);
3541 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3542
3543 dc->desc = "e500v1 core";
3544 pcc->init_proc = init_proc_e500v1;
3545 pcc->check_pow = check_pow_hid0;
3546 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3547 PPC_SPE | PPC_SPE_SINGLE |
3548 PPC_WRTEE | PPC_RFDI |
3549 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3550 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3551 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3552 pcc->insns_flags2 = PPC2_BOOKE206;
3553 pcc->msr_mask = (1ull << MSR_UCLE) |
3554 (1ull << MSR_SPE) |
3555 (1ull << MSR_POW) |
3556 (1ull << MSR_CE) |
3557 (1ull << MSR_EE) |
3558 (1ull << MSR_PR) |
3559 (1ull << MSR_FP) |
3560 (1ull << MSR_ME) |
3561 (1ull << MSR_FE0) |
3562 (1ull << MSR_DWE) |
3563 (1ull << MSR_DE) |
3564 (1ull << MSR_FE1) |
3565 (1ull << MSR_IR) |
3566 (1ull << MSR_DR);
3567 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3568 pcc->excp_model = POWERPC_EXCP_BOOKE;
3569 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3570 pcc->bfd_mach = bfd_mach_ppc_860;
3571 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3572 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3573 POWERPC_FLAG_BUS_CLK;
3574 }
3575
3576 static void init_proc_e500v2(CPUPPCState *env)
3577 {
3578 init_proc_e500(env, fsl_e500v2);
3579 }
3580
3581 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
3582 {
3583 DeviceClass *dc = DEVICE_CLASS(oc);
3584 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3585
3586 dc->desc = "e500v2 core";
3587 pcc->init_proc = init_proc_e500v2;
3588 pcc->check_pow = check_pow_hid0;
3589 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3590 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
3591 PPC_WRTEE | PPC_RFDI |
3592 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3593 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3594 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3595 pcc->insns_flags2 = PPC2_BOOKE206;
3596 pcc->msr_mask = (1ull << MSR_UCLE) |
3597 (1ull << MSR_SPE) |
3598 (1ull << MSR_POW) |
3599 (1ull << MSR_CE) |
3600 (1ull << MSR_EE) |
3601 (1ull << MSR_PR) |
3602 (1ull << MSR_FP) |
3603 (1ull << MSR_ME) |
3604 (1ull << MSR_FE0) |
3605 (1ull << MSR_DWE) |
3606 (1ull << MSR_DE) |
3607 (1ull << MSR_FE1) |
3608 (1ull << MSR_IR) |
3609 (1ull << MSR_DR);
3610 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3611 pcc->excp_model = POWERPC_EXCP_BOOKE;
3612 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3613 pcc->bfd_mach = bfd_mach_ppc_860;
3614 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3615 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3616 POWERPC_FLAG_BUS_CLK;
3617 }
3618
3619 static void init_proc_e500mc(CPUPPCState *env)
3620 {
3621 init_proc_e500(env, fsl_e500mc);
3622 }
3623
3624 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
3625 {
3626 DeviceClass *dc = DEVICE_CLASS(oc);
3627 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3628
3629 dc->desc = "e500mc core";
3630 pcc->init_proc = init_proc_e500mc;
3631 pcc->check_pow = check_pow_none;
3632 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3633 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3634 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3635 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3636 PPC_FLOAT | PPC_FLOAT_FRES |
3637 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3638 PPC_FLOAT_STFIWX | PPC_WAIT |
3639 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3640 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
3641 pcc->msr_mask = (1ull << MSR_GS) |
3642 (1ull << MSR_UCLE) |
3643 (1ull << MSR_CE) |
3644 (1ull << MSR_EE) |
3645 (1ull << MSR_PR) |
3646 (1ull << MSR_FP) |
3647 (1ull << MSR_ME) |
3648 (1ull << MSR_FE0) |
3649 (1ull << MSR_DE) |
3650 (1ull << MSR_FE1) |
3651 (1ull << MSR_IR) |
3652 (1ull << MSR_DR) |
3653 (1ull << MSR_PX) |
3654 (1ull << MSR_RI);
3655 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3656 pcc->excp_model = POWERPC_EXCP_BOOKE;
3657 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3658 /* FIXME: figure out the correct flag for e500mc */
3659 pcc->bfd_mach = bfd_mach_ppc_e500;
3660 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3661 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3662 }
3663
3664 #ifdef TARGET_PPC64
3665 static void init_proc_e5500(CPUPPCState *env)
3666 {
3667 init_proc_e500(env, fsl_e5500);
3668 }
3669
3670 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
3671 {
3672 DeviceClass *dc = DEVICE_CLASS(oc);
3673 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3674
3675 dc->desc = "e5500 core";
3676 pcc->init_proc = init_proc_e5500;
3677 pcc->check_pow = check_pow_none;
3678 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3679 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3680 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3681 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3682 PPC_FLOAT | PPC_FLOAT_FRES |
3683 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3684 PPC_FLOAT_STFIWX | PPC_WAIT |
3685 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3686 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
3687 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3688 PPC2_FP_CVT_S64;
3689 pcc->msr_mask = (1ull << MSR_CM) |
3690 (1ull << MSR_GS) |
3691 (1ull << MSR_UCLE) |
3692 (1ull << MSR_CE) |
3693 (1ull << MSR_EE) |
3694 (1ull << MSR_PR) |
3695 (1ull << MSR_FP) |
3696 (1ull << MSR_ME) |
3697 (1ull << MSR_FE0) |
3698 (1ull << MSR_DE) |
3699 (1ull << MSR_FE1) |
3700 (1ull << MSR_IR) |
3701 (1ull << MSR_DR) |
3702 (1ull << MSR_PX) |
3703 (1ull << MSR_RI);
3704 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3705 pcc->excp_model = POWERPC_EXCP_BOOKE;
3706 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3707 /* FIXME: figure out the correct flag for e5500 */
3708 pcc->bfd_mach = bfd_mach_ppc_e500;
3709 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3710 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3711 }
3712
3713 static void init_proc_e6500(CPUPPCState *env)
3714 {
3715 init_proc_e500(env, fsl_e6500);
3716 }
3717
3718 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
3719 {
3720 DeviceClass *dc = DEVICE_CLASS(oc);
3721 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3722
3723 dc->desc = "e6500 core";
3724 pcc->init_proc = init_proc_e6500;
3725 pcc->check_pow = check_pow_none;
3726 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3727 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3728 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3729 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3730 PPC_FLOAT | PPC_FLOAT_FRES |
3731 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3732 PPC_FLOAT_STFIWX | PPC_WAIT |
3733 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3734 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
3735 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3736 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
3737 pcc->msr_mask = (1ull << MSR_CM) |
3738 (1ull << MSR_GS) |
3739 (1ull << MSR_UCLE) |
3740 (1ull << MSR_CE) |
3741 (1ull << MSR_EE) |
3742 (1ull << MSR_PR) |
3743 (1ull << MSR_FP) |
3744 (1ull << MSR_ME) |
3745 (1ull << MSR_FE0) |
3746 (1ull << MSR_DE) |
3747 (1ull << MSR_FE1) |
3748 (1ull << MSR_IS) |
3749 (1ull << MSR_DS) |
3750 (1ull << MSR_PX) |
3751 (1ull << MSR_RI) |
3752 (1ull << MSR_VR);
3753 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3754 pcc->excp_model = POWERPC_EXCP_BOOKE;
3755 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3756 pcc->bfd_mach = bfd_mach_ppc_e500;
3757 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3758 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
3759 }
3760
3761 #endif
3762
3763 /* Non-embedded PowerPC */
3764 static void init_proc_603(CPUPPCState *env)
3765 {
3766 register_ne_601_sprs(env);
3767 register_sdr1_sprs(env);
3768 register_603_sprs(env);
3769
3770 /* Memory management */
3771 register_low_BATs(env);
3772 register_6xx_7xx_soft_tlb(env, 64, 2);
3773 init_excp_603(env);
3774 env->dcache_line_size = 32;
3775 env->icache_line_size = 32;
3776 /* Allocate hardware IRQ controller */
3777 ppc6xx_irq_init(env_archcpu(env));
3778 }
3779
3780 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
3781 {
3782 DeviceClass *dc = DEVICE_CLASS(oc);
3783 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3784
3785 dc->desc = "PowerPC 603";
3786 pcc->init_proc = init_proc_603;
3787 pcc->check_pow = check_pow_hid0;
3788 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3789 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3790 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3791 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3792 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3793 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3794 PPC_SEGMENT | PPC_EXTERN;
3795 pcc->msr_mask = (1ull << MSR_POW) |
3796 (1ull << MSR_TGPR) |
3797 (1ull << MSR_ILE) |
3798 (1ull << MSR_EE) |
3799 (1ull << MSR_PR) |
3800 (1ull << MSR_FP) |
3801 (1ull << MSR_ME) |
3802 (1ull << MSR_FE0) |
3803 (1ull << MSR_SE) |
3804 (1ull << MSR_DE) |
3805 (1ull << MSR_FE1) |
3806 (1ull << MSR_EP) |
3807 (1ull << MSR_IR) |
3808 (1ull << MSR_DR) |
3809 (1ull << MSR_RI) |
3810 (1ull << MSR_LE);
3811 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3812 pcc->excp_model = POWERPC_EXCP_6xx;
3813 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3814 pcc->bfd_mach = bfd_mach_ppc_603;
3815 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3816 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3817 }
3818
3819 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
3820 {
3821 DeviceClass *dc = DEVICE_CLASS(oc);
3822 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3823
3824 dc->desc = "PowerPC 603e";
3825 pcc->init_proc = init_proc_603;
3826 pcc->check_pow = check_pow_hid0;
3827 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3828 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3829 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3830 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3831 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3832 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3833 PPC_SEGMENT | PPC_EXTERN;
3834 pcc->msr_mask = (1ull << MSR_POW) |
3835 (1ull << MSR_TGPR) |
3836 (1ull << MSR_ILE) |
3837 (1ull << MSR_EE) |
3838 (1ull << MSR_PR) |
3839 (1ull << MSR_FP) |
3840 (1ull << MSR_ME) |
3841 (1ull << MSR_FE0) |
3842 (1ull << MSR_SE) |
3843 (1ull << MSR_DE) |
3844 (1ull << MSR_FE1) |
3845 (1ull << MSR_EP) |
3846 (1ull << MSR_IR) |
3847 (1ull << MSR_DR) |
3848 (1ull << MSR_RI) |
3849 (1ull << MSR_LE);
3850 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3851 pcc->excp_model = POWERPC_EXCP_6xx;
3852 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3853 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3854 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3855 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3856 }
3857
3858 static void init_proc_604(CPUPPCState *env)
3859 {
3860 register_ne_601_sprs(env);
3861 register_sdr1_sprs(env);
3862 register_604_sprs(env);
3863
3864 /* Memory management */
3865 register_low_BATs(env);
3866 init_excp_604(env);
3867 env->dcache_line_size = 32;
3868 env->icache_line_size = 32;
3869 /* Allocate hardware IRQ controller */
3870 ppc6xx_irq_init(env_archcpu(env));
3871 }
3872
3873 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
3874 {
3875 DeviceClass *dc = DEVICE_CLASS(oc);
3876 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3877
3878 dc->desc = "PowerPC 604";
3879 pcc->init_proc = init_proc_604;
3880 pcc->check_pow = check_pow_nocheck;
3881 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3882 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3883 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3884 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3885 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3886 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3887 PPC_SEGMENT | PPC_EXTERN;
3888 pcc->msr_mask = (1ull << MSR_POW) |
3889 (1ull << MSR_ILE) |
3890 (1ull << MSR_EE) |
3891 (1ull << MSR_PR) |
3892 (1ull << MSR_FP) |
3893 (1ull << MSR_ME) |
3894 (1ull << MSR_FE0) |
3895 (1ull << MSR_SE) |
3896 (1ull << MSR_DE) |
3897 (1ull << MSR_FE1) |
3898 (1ull << MSR_EP) |
3899 (1ull << MSR_IR) |
3900 (1ull << MSR_DR) |
3901 (1ull << MSR_PMM) |
3902 (1ull << MSR_RI) |
3903 (1ull << MSR_LE);
3904 pcc->mmu_model = POWERPC_MMU_32B;
3905 pcc->excp_model = POWERPC_EXCP_6xx;
3906 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3907 pcc->bfd_mach = bfd_mach_ppc_604;
3908 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3909 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3910 }
3911
3912 static void init_proc_604E(CPUPPCState *env)
3913 {
3914 register_ne_601_sprs(env);
3915 register_sdr1_sprs(env);
3916 register_604_sprs(env);
3917
3918 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
3919 SPR_NOACCESS, SPR_NOACCESS,
3920 &spr_read_generic, &spr_write_generic,
3921 0x00000000);
3922
3923 spr_register(env, SPR_7XX_PMC3, "PMC3",
3924 SPR_NOACCESS, SPR_NOACCESS,
3925 &spr_read_generic, &spr_write_generic,
3926 0x00000000);
3927
3928 spr_register(env, SPR_7XX_PMC4, "PMC4",
3929 SPR_NOACCESS, SPR_NOACCESS,
3930 &spr_read_generic, &spr_write_generic,
3931 0x00000000);
3932 /* Hardware implementation registers */
3933 spr_register(env, SPR_HID1, "HID1",
3934 SPR_NOACCESS, SPR_NOACCESS,
3935 &spr_read_generic, &spr_write_generic,
3936 0x00000000);
3937 /* Memory management */
3938 register_low_BATs(env);
3939 init_excp_604(env);
3940 env->dcache_line_size = 32;
3941 env->icache_line_size = 32;
3942 /* Allocate hardware IRQ controller */
3943 ppc6xx_irq_init(env_archcpu(env));
3944 }
3945
3946 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
3947 {
3948 DeviceClass *dc = DEVICE_CLASS(oc);
3949 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3950
3951 dc->desc = "PowerPC 604E";
3952 pcc->init_proc = init_proc_604E;
3953 pcc->check_pow = check_pow_nocheck;
3954 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3955 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3956 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3957 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3958 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3959 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3960 PPC_SEGMENT | PPC_EXTERN;
3961 pcc->msr_mask = (1ull << MSR_POW) |
3962 (1ull << MSR_ILE) |
3963 (1ull << MSR_EE) |
3964 (1ull << MSR_PR) |
3965 (1ull << MSR_FP) |
3966 (1ull << MSR_ME) |
3967 (1ull << MSR_FE0) |
3968 (1ull << MSR_SE) |
3969 (1ull << MSR_DE) |
3970 (1ull << MSR_FE1) |
3971 (1ull << MSR_EP) |
3972 (1ull << MSR_IR) |
3973 (1ull << MSR_DR) |
3974 (1ull << MSR_PMM) |
3975 (1ull << MSR_RI) |
3976 (1ull << MSR_LE);
3977 pcc->mmu_model = POWERPC_MMU_32B;
3978 pcc->excp_model = POWERPC_EXCP_6xx;
3979 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3980 pcc->bfd_mach = bfd_mach_ppc_604;
3981 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3982 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3983 }
3984
3985 static void init_proc_740(CPUPPCState *env)
3986 {
3987 register_ne_601_sprs(env);
3988 register_sdr1_sprs(env);
3989 register_7xx_sprs(env);
3990 /* Thermal management */
3991 register_thrm_sprs(env);
3992
3993 /* Memory management */
3994 register_low_BATs(env);
3995 init_excp_7x0(env);
3996 env->dcache_line_size = 32;
3997 env->icache_line_size = 32;
3998 /* Allocate hardware IRQ controller */
3999 ppc6xx_irq_init(env_archcpu(env));
4000 }
4001
4002 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
4003 {
4004 DeviceClass *dc = DEVICE_CLASS(oc);
4005 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4006
4007 dc->desc = "PowerPC 740";
4008 pcc->init_proc = init_proc_740;
4009 pcc->check_pow = check_pow_hid0;
4010 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4011 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4012 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4013 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4014 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4015 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4016 PPC_SEGMENT | PPC_EXTERN;
4017 pcc->msr_mask = (1ull << MSR_POW) |
4018 (1ull << MSR_ILE) |
4019 (1ull << MSR_EE) |
4020 (1ull << MSR_PR) |
4021 (1ull << MSR_FP) |
4022 (1ull << MSR_ME) |
4023 (1ull << MSR_FE0) |
4024 (1ull << MSR_SE) |
4025 (1ull << MSR_DE) |
4026 (1ull << MSR_FE1) |
4027 (1ull << MSR_EP) |
4028 (1ull << MSR_IR) |
4029 (1ull << MSR_DR) |
4030 (1ull << MSR_PMM) |
4031 (1ull << MSR_RI) |
4032 (1ull << MSR_LE);
4033 pcc->mmu_model = POWERPC_MMU_32B;
4034 pcc->excp_model = POWERPC_EXCP_7xx;
4035 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4036 pcc->bfd_mach = bfd_mach_ppc_750;
4037 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4038 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4039 }
4040
4041 static void init_proc_750(CPUPPCState *env)
4042 {
4043 register_ne_601_sprs(env);
4044 register_sdr1_sprs(env);
4045 register_7xx_sprs(env);
4046
4047 spr_register(env, SPR_L2CR, "L2CR",
4048 SPR_NOACCESS, SPR_NOACCESS,
4049 &spr_read_generic, spr_access_nop,
4050 0x00000000);
4051 /* Thermal management */
4052 register_thrm_sprs(env);
4053
4054 /* Memory management */
4055 register_low_BATs(env);
4056 /*
4057 * XXX: high BATs are also present but are known to be bugged on
4058 * die version 1.x
4059 */
4060 init_excp_7x0(env);
4061 env->dcache_line_size = 32;
4062 env->icache_line_size = 32;
4063 /* Allocate hardware IRQ controller */
4064 ppc6xx_irq_init(env_archcpu(env));
4065 }
4066
4067 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
4068 {
4069 DeviceClass *dc = DEVICE_CLASS(oc);
4070 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4071
4072 dc->desc = "PowerPC 750";
4073 pcc->init_proc = init_proc_750;
4074 pcc->check_pow = check_pow_hid0;
4075 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4076 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4077 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4078 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4079 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4080 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4081 PPC_SEGMENT | PPC_EXTERN;
4082 pcc->msr_mask = (1ull << MSR_POW) |
4083 (1ull << MSR_ILE) |
4084 (1ull << MSR_EE) |
4085 (1ull << MSR_PR) |
4086 (1ull << MSR_FP) |
4087 (1ull << MSR_ME) |
4088 (1ull << MSR_FE0) |
4089 (1ull << MSR_SE) |
4090 (1ull << MSR_DE) |
4091 (1ull << MSR_FE1) |
4092 (1ull << MSR_EP) |
4093 (1ull << MSR_IR) |
4094 (1ull << MSR_DR) |
4095 (1ull << MSR_PMM) |
4096 (1ull << MSR_RI) |
4097 (1ull << MSR_LE);
4098 pcc->mmu_model = POWERPC_MMU_32B;
4099 pcc->excp_model = POWERPC_EXCP_7xx;
4100 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4101 pcc->bfd_mach = bfd_mach_ppc_750;
4102 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4103 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4104 }
4105
4106 static void init_proc_750cl(CPUPPCState *env)
4107 {
4108 register_ne_601_sprs(env);
4109 register_sdr1_sprs(env);
4110 register_7xx_sprs(env);
4111
4112 spr_register(env, SPR_L2CR, "L2CR",
4113 SPR_NOACCESS, SPR_NOACCESS,
4114 &spr_read_generic, spr_access_nop,
4115 0x00000000);
4116 /* Thermal management */
4117 /* Those registers are fake on 750CL */
4118 spr_register(env, SPR_THRM1, "THRM1",
4119 SPR_NOACCESS, SPR_NOACCESS,
4120 &spr_read_generic, &spr_write_generic,
4121 0x00000000);
4122 spr_register(env, SPR_THRM2, "THRM2",
4123 SPR_NOACCESS, SPR_NOACCESS,
4124 &spr_read_generic, &spr_write_generic,
4125 0x00000000);
4126 spr_register(env, SPR_THRM3, "THRM3",
4127 SPR_NOACCESS, SPR_NOACCESS,
4128 &spr_read_generic, &spr_write_generic,
4129 0x00000000);
4130
4131 spr_register(env, SPR_750_TDCL, "TDCL",
4132 SPR_NOACCESS, SPR_NOACCESS,
4133 &spr_read_generic, &spr_write_generic,
4134 0x00000000);
4135 spr_register(env, SPR_750_TDCH, "TDCH",
4136 SPR_NOACCESS, SPR_NOACCESS,
4137 &spr_read_generic, &spr_write_generic,
4138 0x00000000);
4139 /* DMA */
4140 spr_register(env, SPR_750_WPAR, "WPAR",
4141 SPR_NOACCESS, SPR_NOACCESS,
4142 &spr_read_generic, &spr_write_generic,
4143 0x00000000);
4144 spr_register(env, SPR_750_DMAL, "DMAL",
4145 SPR_NOACCESS, SPR_NOACCESS,
4146 &spr_read_generic, &spr_write_generic,
4147 0x00000000);
4148 spr_register(env, SPR_750_DMAU, "DMAU",
4149 SPR_NOACCESS, SPR_NOACCESS,
4150 &spr_read_generic, &spr_write_generic,
4151 0x00000000);
4152 /* Hardware implementation registers */
4153 spr_register(env, SPR_750CL_HID2, "HID2",
4154 SPR_NOACCESS, SPR_NOACCESS,
4155 &spr_read_generic, &spr_write_generic,
4156 0x00000000);
4157
4158 spr_register(env, SPR_750CL_HID4, "HID4",
4159 SPR_NOACCESS, SPR_NOACCESS,
4160 &spr_read_generic, &spr_write_generic,
4161 0x00000000);
4162 /* Quantization registers */
4163 spr_register(env, SPR_750_GQR0, "GQR0",
4164 SPR_NOACCESS, SPR_NOACCESS,
4165 &spr_read_generic, &spr_write_generic,
4166 0x00000000);
4167
4168 spr_register(env, SPR_750_GQR1, "GQR1",
4169 SPR_NOACCESS, SPR_NOACCESS,
4170 &spr_read_generic, &spr_write_generic,
4171 0x00000000);
4172
4173 spr_register(env, SPR_750_GQR2, "GQR2",
4174 SPR_NOACCESS, SPR_NOACCESS,
4175 &spr_read_generic, &spr_write_generic,
4176 0x00000000);
4177
4178 spr_register(env, SPR_750_GQR3, "GQR3",
4179 SPR_NOACCESS, SPR_NOACCESS,
4180 &spr_read_generic, &spr_write_generic,
4181 0x00000000);
4182
4183 spr_register(env, SPR_750_GQR4, "GQR4",
4184 SPR_NOACCESS, SPR_NOACCESS,
4185 &spr_read_generic, &spr_write_generic,
4186 0x00000000);
4187
4188 spr_register(env, SPR_750_GQR5, "GQR5",
4189 SPR_NOACCESS, SPR_NOACCESS,
4190 &spr_read_generic, &spr_write_generic,
4191 0x00000000);
4192
4193 spr_register(env, SPR_750_GQR6, "GQR6",
4194 SPR_NOACCESS, SPR_NOACCESS,
4195 &spr_read_generic, &spr_write_generic,
4196 0x00000000);
4197
4198 spr_register(env, SPR_750_GQR7, "GQR7",
4199 SPR_NOACCESS, SPR_NOACCESS,
4200 &spr_read_generic, &spr_write_generic,
4201 0x00000000);
4202 /* Memory management */
4203 register_low_BATs(env);
4204 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4205 register_high_BATs(env);
4206 init_excp_750cl(env);
4207 env->dcache_line_size = 32;
4208 env->icache_line_size = 32;
4209 /* Allocate hardware IRQ controller */
4210 ppc6xx_irq_init(env_archcpu(env));
4211 }
4212
4213 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
4214 {
4215 DeviceClass *dc = DEVICE_CLASS(oc);
4216 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4217
4218 dc->desc = "PowerPC 750 CL";
4219 pcc->init_proc = init_proc_750cl;
4220 pcc->check_pow = check_pow_hid0;
4221 /*
4222 * XXX: not implemented:
4223 * cache lock instructions:
4224 * dcbz_l
4225 * floating point paired instructions
4226 * psq_lux
4227 * psq_lx
4228 * psq_stux
4229 * psq_stx
4230 * ps_abs
4231 * ps_add
4232 * ps_cmpo0
4233 * ps_cmpo1
4234 * ps_cmpu0
4235 * ps_cmpu1
4236 * ps_div
4237 * ps_madd
4238 * ps_madds0
4239 * ps_madds1
4240 * ps_merge00
4241 * ps_merge01
4242 * ps_merge10
4243 * ps_merge11
4244 * ps_mr
4245 * ps_msub
4246 * ps_mul
4247 * ps_muls0
4248 * ps_muls1
4249 * ps_nabs
4250 * ps_neg
4251 * ps_nmadd
4252 * ps_nmsub
4253 * ps_res
4254 * ps_rsqrte
4255 * ps_sel
4256 * ps_sub
4257 * ps_sum0
4258 * ps_sum1
4259 */
4260 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4261 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4262 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4263 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4264 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4265 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4266 PPC_SEGMENT | PPC_EXTERN;
4267 pcc->msr_mask = (1ull << MSR_POW) |
4268 (1ull << MSR_ILE) |
4269 (1ull << MSR_EE) |
4270 (1ull << MSR_PR) |
4271 (1ull << MSR_FP) |
4272 (1ull << MSR_ME) |
4273 (1ull << MSR_FE0) |
4274 (1ull << MSR_SE) |
4275 (1ull << MSR_DE) |
4276 (1ull << MSR_FE1) |
4277 (1ull << MSR_EP) |
4278 (1ull << MSR_IR) |
4279 (1ull << MSR_DR) |
4280 (1ull << MSR_PMM) |
4281 (1ull << MSR_RI) |
4282 (1ull << MSR_LE);
4283 pcc->mmu_model = POWERPC_MMU_32B;
4284 pcc->excp_model = POWERPC_EXCP_7xx;
4285 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4286 pcc->bfd_mach = bfd_mach_ppc_750;
4287 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4288 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4289 }
4290
4291 static void init_proc_750cx(CPUPPCState *env)
4292 {
4293 register_ne_601_sprs(env);
4294 register_sdr1_sprs(env);
4295 register_7xx_sprs(env);
4296
4297 spr_register(env, SPR_L2CR, "L2CR",
4298 SPR_NOACCESS, SPR_NOACCESS,
4299 &spr_read_generic, spr_access_nop,
4300 0x00000000);
4301 /* Thermal management */
4302 register_thrm_sprs(env);
4303
4304 spr_register(env, SPR_SDA, "SDA",
4305 SPR_NOACCESS, SPR_NOACCESS,
4306 &spr_read_generic, &spr_write_generic,
4307 0x00000000);
4308
4309 /* Memory management */
4310 register_low_BATs(env);
4311 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
4312 register_high_BATs(env);
4313 init_excp_750cx(env);
4314 env->dcache_line_size = 32;
4315 env->icache_line_size = 32;
4316 /* Allocate hardware IRQ controller */
4317 ppc6xx_irq_init(env_archcpu(env));
4318 }
4319
4320 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
4321 {
4322 DeviceClass *dc = DEVICE_CLASS(oc);
4323 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4324
4325 dc->desc = "PowerPC 750CX";
4326 pcc->init_proc = init_proc_750cx;
4327 pcc->check_pow = check_pow_hid0;
4328 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4329 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4330 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4331 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4332 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4333 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4334 PPC_SEGMENT | PPC_EXTERN;
4335 pcc->msr_mask = (1ull << MSR_POW) |
4336 (1ull << MSR_ILE) |
4337 (1ull << MSR_EE) |
4338 (1ull << MSR_PR) |
4339 (1ull << MSR_FP) |
4340 (1ull << MSR_ME) |
4341 (1ull << MSR_FE0) |
4342 (1ull << MSR_SE) |
4343 (1ull << MSR_DE) |
4344 (1ull << MSR_FE1) |
4345 (1ull << MSR_EP) |
4346 (1ull << MSR_IR) |
4347 (1ull << MSR_DR) |
4348 (1ull << MSR_PMM) |
4349 (1ull << MSR_RI) |
4350 (1ull << MSR_LE);
4351 pcc->mmu_model = POWERPC_MMU_32B;
4352 pcc->excp_model = POWERPC_EXCP_7xx;
4353 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4354 pcc->bfd_mach = bfd_mach_ppc_750;
4355 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4356 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4357 }
4358
4359 static void init_proc_750fx(CPUPPCState *env)
4360 {
4361 register_ne_601_sprs(env);
4362 register_sdr1_sprs(env);
4363 register_7xx_sprs(env);
4364
4365 spr_register(env, SPR_L2CR, "L2CR",
4366 SPR_NOACCESS, SPR_NOACCESS,
4367 &spr_read_generic, spr_access_nop,
4368 0x00000000);
4369 /* Thermal management */
4370 register_thrm_sprs(env);
4371
4372 spr_register(env, SPR_750_THRM4, "THRM4",
4373 SPR_NOACCESS, SPR_NOACCESS,
4374 &spr_read_generic, &spr_write_generic,
4375 0x00000000);
4376 /* Hardware implementation registers */
4377 spr_register(env, SPR_750FX_HID2, "HID2",
4378 SPR_NOACCESS, SPR_NOACCESS,
4379 &spr_read_generic, &spr_write_generic,
4380 0x00000000);
4381 /* Memory management */
4382 register_low_BATs(env);
4383 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4384 register_high_BATs(env);
4385 init_excp_7x0(env);
4386 env->dcache_line_size = 32;
4387 env->icache_line_size = 32;
4388 /* Allocate hardware IRQ controller */
4389 ppc6xx_irq_init(env_archcpu(env));
4390 }
4391
4392 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
4393 {
4394 DeviceClass *dc = DEVICE_CLASS(oc);
4395 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4396
4397 dc->desc = "PowerPC 750FX";
4398 pcc->init_proc = init_proc_750fx;
4399 pcc->check_pow = check_pow_hid0;
4400 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4401 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4402 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4403 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4404 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4405 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4406 PPC_SEGMENT | PPC_EXTERN;
4407 pcc->msr_mask = (1ull << MSR_POW) |
4408 (1ull << MSR_ILE) |
4409 (1ull << MSR_EE) |
4410 (1ull << MSR_PR) |
4411 (1ull << MSR_FP) |
4412 (1ull << MSR_ME) |
4413 (1ull << MSR_FE0) |
4414 (1ull << MSR_SE) |
4415 (1ull << MSR_DE) |
4416 (1ull << MSR_FE1) |
4417 (1ull << MSR_EP) |
4418 (1ull << MSR_IR) |
4419 (1ull << MSR_DR) |
4420 (1ull << MSR_PMM) |
4421 (1ull << MSR_RI) |
4422 (1ull << MSR_LE);
4423 pcc->mmu_model = POWERPC_MMU_32B;
4424 pcc->excp_model = POWERPC_EXCP_7xx;
4425 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4426 pcc->bfd_mach = bfd_mach_ppc_750;
4427 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4428 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4429 }
4430
4431 static void init_proc_750gx(CPUPPCState *env)
4432 {
4433 register_ne_601_sprs(env);
4434 register_sdr1_sprs(env);
4435 register_7xx_sprs(env);
4436
4437 spr_register(env, SPR_L2CR, "L2CR",
4438 SPR_NOACCESS, SPR_NOACCESS,
4439 &spr_read_generic, spr_access_nop,
4440 0x00000000);
4441 /* Thermal management */
4442 register_thrm_sprs(env);
4443
4444 spr_register(env, SPR_750_THRM4, "THRM4",
4445 SPR_NOACCESS, SPR_NOACCESS,
4446 &spr_read_generic, &spr_write_generic,
4447 0x00000000);
4448 /* Hardware implementation registers */
4449 spr_register(env, SPR_750FX_HID2, "HID2",
4450 SPR_NOACCESS, SPR_NOACCESS,
4451 &spr_read_generic, &spr_write_generic,
4452 0x00000000);
4453 /* Memory management */
4454 register_low_BATs(env);
4455 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4456 register_high_BATs(env);
4457 init_excp_7x0(env);
4458 env->dcache_line_size = 32;
4459 env->icache_line_size = 32;
4460 /* Allocate hardware IRQ controller */
4461 ppc6xx_irq_init(env_archcpu(env));
4462 }
4463
4464 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
4465 {
4466 DeviceClass *dc = DEVICE_CLASS(oc);
4467 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4468
4469 dc->desc = "PowerPC 750GX";
4470 pcc->init_proc = init_proc_750gx;
4471 pcc->check_pow = check_pow_hid0;
4472 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4473 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4474 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4475 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4476 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4477 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4478 PPC_SEGMENT | PPC_EXTERN;
4479 pcc->msr_mask = (1ull << MSR_POW) |
4480 (1ull << MSR_ILE) |
4481 (1ull << MSR_EE) |
4482 (1ull << MSR_PR) |
4483 (1ull << MSR_FP) |
4484 (1ull << MSR_ME) |
4485 (1ull << MSR_FE0) |
4486 (1ull << MSR_SE) |
4487 (1ull << MSR_DE) |
4488 (1ull << MSR_FE1) |
4489 (1ull << MSR_EP) |
4490 (1ull << MSR_IR) |
4491 (1ull << MSR_DR) |
4492 (1ull << MSR_PMM) |
4493 (1ull << MSR_RI) |
4494 (1ull << MSR_LE);
4495 pcc->mmu_model = POWERPC_MMU_32B;
4496 pcc->excp_model = POWERPC_EXCP_7xx;
4497 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4498 pcc->bfd_mach = bfd_mach_ppc_750;
4499 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4500 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4501 }
4502
4503 static void init_proc_745(CPUPPCState *env)
4504 {
4505 register_ne_601_sprs(env);
4506 register_sdr1_sprs(env);
4507 register_7xx_sprs(env);
4508 register_745_sprs(env);
4509 /* Thermal management */
4510 register_thrm_sprs(env);
4511
4512 /* Memory management */
4513 register_low_BATs(env);
4514 register_high_BATs(env);
4515 register_6xx_7xx_soft_tlb(env, 64, 2);
4516 init_excp_7x5(env);
4517 env->dcache_line_size = 32;
4518 env->icache_line_size = 32;
4519 /* Allocate hardware IRQ controller */
4520 ppc6xx_irq_init(env_archcpu(env));
4521 }
4522
4523 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
4524 {
4525 DeviceClass *dc = DEVICE_CLASS(oc);
4526 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4527
4528 dc->desc = "PowerPC 745";
4529 pcc->init_proc = init_proc_745;
4530 pcc->check_pow = check_pow_hid0;
4531 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4532 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4533 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4534 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4535 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4536 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4537 PPC_SEGMENT | PPC_EXTERN;
4538 pcc->msr_mask = (1ull << MSR_POW) |
4539 (1ull << MSR_ILE) |
4540 (1ull << MSR_EE) |
4541 (1ull << MSR_PR) |
4542 (1ull << MSR_FP) |
4543 (1ull << MSR_ME) |
4544 (1ull << MSR_FE0) |
4545 (1ull << MSR_SE) |
4546 (1ull << MSR_DE) |
4547 (1ull << MSR_FE1) |
4548 (1ull << MSR_EP) |
4549 (1ull << MSR_IR) |
4550 (1ull << MSR_DR) |
4551 (1ull << MSR_PMM) |
4552 (1ull << MSR_RI) |
4553 (1ull << MSR_LE);
4554 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4555 pcc->excp_model = POWERPC_EXCP_7xx;
4556 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4557 pcc->bfd_mach = bfd_mach_ppc_750;
4558 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4559 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4560 }
4561
4562 static void init_proc_755(CPUPPCState *env)
4563 {
4564 register_ne_601_sprs(env);
4565 register_sdr1_sprs(env);
4566 register_7xx_sprs(env);
4567 register_745_sprs(env);
4568 register_755_sprs(env);
4569
4570 /* Thermal management */
4571 register_thrm_sprs(env);
4572
4573 /* Memory management */
4574 register_low_BATs(env);
4575 register_high_BATs(env);
4576 register_6xx_7xx_soft_tlb(env, 64, 2);
4577 init_excp_7x5(env);
4578 env->dcache_line_size = 32;
4579 env->icache_line_size = 32;
4580 /* Allocate hardware IRQ controller */
4581 ppc6xx_irq_init(env_archcpu(env));
4582 }
4583
4584 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
4585 {
4586 DeviceClass *dc = DEVICE_CLASS(oc);
4587 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4588
4589 dc->desc = "PowerPC 755";
4590 pcc->init_proc = init_proc_755;
4591 pcc->check_pow = check_pow_hid0;
4592 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4593 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4594 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4595 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4596 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4597 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4598 PPC_SEGMENT | PPC_EXTERN;
4599 pcc->msr_mask = (1ull << MSR_POW) |
4600 (1ull << MSR_ILE) |
4601 (1ull << MSR_EE) |
4602 (1ull << MSR_PR) |
4603 (1ull << MSR_FP) |
4604 (1ull << MSR_ME) |
4605 (1ull << MSR_FE0) |
4606 (1ull << MSR_SE) |
4607 (1ull << MSR_DE) |
4608 (1ull << MSR_FE1) |
4609 (1ull << MSR_EP) |
4610 (1ull << MSR_IR) |
4611 (1ull << MSR_DR) |
4612 (1ull << MSR_PMM) |
4613 (1ull << MSR_RI) |
4614 (1ull << MSR_LE);
4615 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4616 pcc->excp_model = POWERPC_EXCP_7xx;
4617 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4618 pcc->bfd_mach = bfd_mach_ppc_750;
4619 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4620 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4621 }
4622
4623 static void init_proc_7400(CPUPPCState *env)
4624 {
4625 register_ne_601_sprs(env);
4626 register_sdr1_sprs(env);
4627 register_74xx_sprs(env);
4628 vscr_init(env, 0x00010000);
4629
4630 spr_register(env, SPR_UBAMR, "UBAMR",
4631 &spr_read_ureg, SPR_NOACCESS,
4632 &spr_read_ureg, SPR_NOACCESS,
4633 0x00000000);
4634
4635 spr_register(env, SPR_MSSCR1, "MSSCR1",
4636 SPR_NOACCESS, SPR_NOACCESS,
4637 &spr_read_generic, &spr_write_generic,
4638 0x00000000);
4639 /* Thermal management */
4640 register_thrm_sprs(env);
4641 /* Memory management */
4642 register_low_BATs(env);
4643 init_excp_7400(env);
4644 env->dcache_line_size = 32;
4645 env->icache_line_size = 32;
4646 /* Allocate hardware IRQ controller */
4647 ppc6xx_irq_init(env_archcpu(env));
4648 }
4649
4650 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
4651 {
4652 DeviceClass *dc = DEVICE_CLASS(oc);
4653 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4654
4655 dc->desc = "PowerPC 7400 (aka G4)";
4656 pcc->init_proc = init_proc_7400;
4657 pcc->check_pow = check_pow_hid0;
4658 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4659 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4660 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4661 PPC_FLOAT_STFIWX |
4662 PPC_CACHE | PPC_CACHE_ICBI |
4663 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4664 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4665 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4666 PPC_MEM_TLBIA |
4667 PPC_SEGMENT | PPC_EXTERN |
4668 PPC_ALTIVEC;
4669 pcc->msr_mask = (1ull << MSR_VR) |
4670 (1ull << MSR_POW) |
4671 (1ull << MSR_ILE) |
4672 (1ull << MSR_EE) |
4673 (1ull << MSR_PR) |
4674 (1ull << MSR_FP) |
4675 (1ull << MSR_ME) |
4676 (1ull << MSR_FE0) |
4677 (1ull << MSR_SE) |
4678 (1ull << MSR_DE) |
4679 (1ull << MSR_FE1) |
4680 (1ull << MSR_EP) |
4681 (1ull << MSR_IR) |
4682 (1ull << MSR_DR) |
4683 (1ull << MSR_PMM) |
4684 (1ull << MSR_RI) |
4685 (1ull << MSR_LE);
4686 pcc->mmu_model = POWERPC_MMU_32B;
4687 pcc->excp_model = POWERPC_EXCP_74xx;
4688 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4689 pcc->bfd_mach = bfd_mach_ppc_7400;
4690 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4691 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4692 POWERPC_FLAG_BUS_CLK;
4693 }
4694
4695 static void init_proc_7410(CPUPPCState *env)
4696 {
4697 register_ne_601_sprs(env);
4698 register_sdr1_sprs(env);
4699 register_74xx_sprs(env);
4700 vscr_init(env, 0x00010000);
4701
4702 spr_register(env, SPR_UBAMR, "UBAMR",
4703 &spr_read_ureg, SPR_NOACCESS,
4704 &spr_read_ureg, SPR_NOACCESS,
4705 0x00000000);
4706 /* Thermal management */
4707 register_thrm_sprs(env);
4708 /* L2PMCR */
4709
4710 spr_register(env, SPR_L2PMCR, "L2PMCR",
4711 SPR_NOACCESS, SPR_NOACCESS,
4712 &spr_read_generic, &spr_write_generic,
4713 0x00000000);
4714 /* LDSTDB */
4715
4716 spr_register(env, SPR_LDSTDB, "LDSTDB",
4717 SPR_NOACCESS, SPR_NOACCESS,
4718 &spr_read_generic, &spr_write_generic,
4719 0x00000000);
4720 /* Memory management */
4721 register_low_BATs(env);
4722 init_excp_7400(env);
4723 env->dcache_line_size = 32;
4724 env->icache_line_size = 32;
4725 /* Allocate hardware IRQ controller */
4726 ppc6xx_irq_init(env_archcpu(env));
4727 }
4728
4729 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
4730 {
4731 DeviceClass *dc = DEVICE_CLASS(oc);
4732 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4733
4734 dc->desc = "PowerPC 7410 (aka G4)";
4735 pcc->init_proc = init_proc_7410;
4736 pcc->check_pow = check_pow_hid0;
4737 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4738 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4739 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4740 PPC_FLOAT_STFIWX |
4741 PPC_CACHE | PPC_CACHE_ICBI |
4742 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4743 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4744 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4745 PPC_MEM_TLBIA |
4746 PPC_SEGMENT | PPC_EXTERN |
4747 PPC_ALTIVEC;
4748 pcc->msr_mask = (1ull << MSR_VR) |
4749 (1ull << MSR_POW) |
4750 (1ull << MSR_ILE) |
4751 (1ull << MSR_EE) |
4752 (1ull << MSR_PR) |
4753 (1ull << MSR_FP) |
4754 (1ull << MSR_ME) |
4755 (1ull << MSR_FE0) |
4756 (1ull << MSR_SE) |
4757 (1ull << MSR_DE) |
4758 (1ull << MSR_FE1) |
4759 (1ull << MSR_EP) |
4760 (1ull << MSR_IR) |
4761 (1ull << MSR_DR) |
4762 (1ull << MSR_PMM) |
4763 (1ull << MSR_RI) |
4764 (1ull << MSR_LE);
4765 pcc->mmu_model = POWERPC_MMU_32B;
4766 pcc->excp_model = POWERPC_EXCP_74xx;
4767 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4768 pcc->bfd_mach = bfd_mach_ppc_7400;
4769 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4770 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4771 POWERPC_FLAG_BUS_CLK;
4772 }
4773
4774 static void init_proc_7440(CPUPPCState *env)
4775 {
4776 register_ne_601_sprs(env);
4777 register_sdr1_sprs(env);
4778 register_74xx_sprs(env);
4779 vscr_init(env, 0x00010000);
4780
4781 spr_register(env, SPR_UBAMR, "UBAMR",
4782 &spr_read_ureg, SPR_NOACCESS,
4783 &spr_read_ureg, SPR_NOACCESS,
4784 0x00000000);
4785 /* LDSTCR */
4786 spr_register(env, SPR_LDSTCR, "LDSTCR",
4787 SPR_NOACCESS, SPR_NOACCESS,
4788 &spr_read_generic, &spr_write_generic,
4789 0x00000000);
4790 /* ICTRL */
4791 spr_register(env, SPR_ICTRL, "ICTRL",
4792 SPR_NOACCESS, SPR_NOACCESS,
4793 &spr_read_generic, &spr_write_generic,
4794 0x00000000);
4795 /* MSSSR0 */
4796 spr_register(env, SPR_MSSSR0, "MSSSR0",
4797 SPR_NOACCESS, SPR_NOACCESS,
4798 &spr_read_generic, &spr_write_generic,
4799 0x00000000);
4800 /* PMC */
4801 spr_register(env, SPR_7XX_PMC5, "PMC5",
4802 SPR_NOACCESS, SPR_NOACCESS,
4803 &spr_read_generic, &spr_write_generic,
4804 0x00000000);
4805
4806 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4807 &spr_read_ureg, SPR_NOACCESS,
4808 &spr_read_ureg, SPR_NOACCESS,
4809 0x00000000);
4810
4811 spr_register(env, SPR_7XX_PMC6, "PMC6",
4812 SPR_NOACCESS, SPR_NOACCESS,
4813 &spr_read_generic, &spr_write_generic,
4814 0x00000000);
4815
4816 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4817 &spr_read_ureg, SPR_NOACCESS,
4818 &spr_read_ureg, SPR_NOACCESS,
4819 0x00000000);
4820 /* Memory management */
4821 register_low_BATs(env);
4822 init_excp_7450(env);
4823 env->dcache_line_size = 32;
4824 env->icache_line_size = 32;
4825 /* Allocate hardware IRQ controller */
4826 ppc6xx_irq_init(env_archcpu(env));
4827 }
4828
4829 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
4830 {
4831 DeviceClass *dc = DEVICE_CLASS(oc);
4832 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4833
4834 dc->desc = "PowerPC 7440 (aka G4)";
4835 pcc->init_proc = init_proc_7440;
4836 pcc->check_pow = check_pow_hid0_74xx;
4837 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4838 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4839 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4840 PPC_FLOAT_STFIWX |
4841 PPC_CACHE | PPC_CACHE_ICBI |
4842 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4843 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4844 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4845 PPC_MEM_TLBIA |
4846 PPC_SEGMENT | PPC_EXTERN |
4847 PPC_ALTIVEC;
4848 pcc->msr_mask = (1ull << MSR_VR) |
4849 (1ull << MSR_POW) |
4850 (1ull << MSR_ILE) |
4851 (1ull << MSR_EE) |
4852 (1ull << MSR_PR) |
4853 (1ull << MSR_FP) |
4854 (1ull << MSR_ME) |
4855 (1ull << MSR_FE0) |
4856 (1ull << MSR_SE) |
4857 (1ull << MSR_DE) |
4858 (1ull << MSR_FE1) |
4859 (1ull << MSR_EP) |
4860 (1ull << MSR_IR) |
4861 (1ull << MSR_DR) |
4862 (1ull << MSR_PMM) |
4863 (1ull << MSR_RI) |
4864 (1ull << MSR_LE);
4865 pcc->mmu_model = POWERPC_MMU_32B;
4866 pcc->excp_model = POWERPC_EXCP_74xx;
4867 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4868 pcc->bfd_mach = bfd_mach_ppc_7400;
4869 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4870 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4871 POWERPC_FLAG_BUS_CLK;
4872 }
4873
4874 static void init_proc_7450(CPUPPCState *env)
4875 {
4876 register_ne_601_sprs(env);
4877 register_sdr1_sprs(env);
4878 register_74xx_sprs(env);
4879 vscr_init(env, 0x00010000);
4880 /* Level 3 cache control */
4881 register_l3_ctrl(env);
4882 /* L3ITCR1 */
4883 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4884 SPR_NOACCESS, SPR_NOACCESS,
4885 &spr_read_generic, &spr_write_generic,
4886 0x00000000);
4887 /* L3ITCR2 */
4888 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4889 SPR_NOACCESS, SPR_NOACCESS,
4890 &spr_read_generic, &spr_write_generic,
4891 0x00000000);
4892 /* L3ITCR3 */
4893 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4894 SPR_NOACCESS, SPR_NOACCESS,
4895 &spr_read_generic, &spr_write_generic,
4896 0x00000000);
4897 /* L3OHCR */
4898 spr_register(env, SPR_L3OHCR, "L3OHCR",
4899 SPR_NOACCESS, SPR_NOACCESS,
4900 &spr_read_generic, &spr_write_generic,
4901 0x00000000);
4902
4903 spr_register(env, SPR_UBAMR, "UBAMR",
4904 &spr_read_ureg, SPR_NOACCESS,
4905 &spr_read_ureg, SPR_NOACCESS,
4906 0x00000000);
4907 /* LDSTCR */
4908 spr_register(env, SPR_LDSTCR, "LDSTCR",
4909 SPR_NOACCESS, SPR_NOACCESS,
4910 &spr_read_generic, &spr_write_generic,
4911 0x00000000);
4912 /* ICTRL */
4913 spr_register(env, SPR_ICTRL, "ICTRL",
4914 SPR_NOACCESS, SPR_NOACCESS,
4915 &spr_read_generic, &spr_write_generic,
4916 0x00000000);
4917 /* MSSSR0 */
4918 spr_register(env, SPR_MSSSR0, "MSSSR0",
4919 SPR_NOACCESS, SPR_NOACCESS,
4920 &spr_read_generic, &spr_write_generic,
4921 0x00000000);
4922 /* PMC */
4923 spr_register(env, SPR_7XX_PMC5, "PMC5",
4924 SPR_NOACCESS, SPR_NOACCESS,
4925 &spr_read_generic, &spr_write_generic,
4926 0x00000000);
4927
4928 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4929 &spr_read_ureg, SPR_NOACCESS,
4930 &spr_read_ureg, SPR_NOACCESS,
4931 0x00000000);
4932
4933 spr_register(env, SPR_7XX_PMC6, "PMC6",
4934 SPR_NOACCESS, SPR_NOACCESS,
4935 &spr_read_generic, &spr_write_generic,
4936 0x00000000);
4937
4938 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4939 &spr_read_ureg, SPR_NOACCESS,
4940 &spr_read_ureg, SPR_NOACCESS,
4941 0x00000000);
4942 /* Memory management */
4943 register_low_BATs(env);
4944 init_excp_7450(env);
4945 env->dcache_line_size = 32;
4946 env->icache_line_size = 32;
4947 /* Allocate hardware IRQ controller */
4948 ppc6xx_irq_init(env_archcpu(env));
4949 }
4950
4951 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
4952 {
4953 DeviceClass *dc = DEVICE_CLASS(oc);
4954 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4955
4956 dc->desc = "PowerPC 7450 (aka G4)";
4957 pcc->init_proc = init_proc_7450;
4958 pcc->check_pow = check_pow_hid0_74xx;
4959 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4960 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4961 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4962 PPC_FLOAT_STFIWX |
4963 PPC_CACHE | PPC_CACHE_ICBI |
4964 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4965 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4966 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4967 PPC_MEM_TLBIA |
4968 PPC_SEGMENT | PPC_EXTERN |
4969 PPC_ALTIVEC;
4970 pcc->msr_mask = (1ull << MSR_VR) |
4971 (1ull << MSR_POW) |
4972 (1ull << MSR_ILE) |
4973 (1ull << MSR_EE) |
4974 (1ull << MSR_PR) |
4975 (1ull << MSR_FP) |
4976 (1ull << MSR_ME) |
4977 (1ull << MSR_FE0) |
4978 (1ull << MSR_SE) |
4979 (1ull << MSR_DE) |
4980 (1ull << MSR_FE1) |
4981 (1ull << MSR_EP) |
4982 (1ull << MSR_IR) |
4983 (1ull << MSR_DR) |
4984 (1ull << MSR_PMM) |
4985 (1ull << MSR_RI) |
4986 (1ull << MSR_LE);
4987 pcc->mmu_model = POWERPC_MMU_32B;
4988 pcc->excp_model = POWERPC_EXCP_74xx;
4989 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4990 pcc->bfd_mach = bfd_mach_ppc_7400;
4991 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4992 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4993 POWERPC_FLAG_BUS_CLK;
4994 }
4995
4996 static void init_proc_7445(CPUPPCState *env)
4997 {
4998 register_ne_601_sprs(env);
4999 register_sdr1_sprs(env);
5000 register_74xx_sprs(env);
5001 vscr_init(env, 0x00010000);
5002 /* LDSTCR */
5003 spr_register(env, SPR_LDSTCR, "LDSTCR",
5004 SPR_NOACCESS, SPR_NOACCESS,
5005 &spr_read_generic, &spr_write_generic,
5006 0x00000000);
5007 /* ICTRL */
5008 spr_register(env, SPR_ICTRL, "ICTRL",
5009 SPR_NOACCESS, SPR_NOACCESS,
5010 &spr_read_generic, &spr_write_generic,
5011 0x00000000);
5012 /* MSSSR0 */
5013 spr_register(env, SPR_MSSSR0, "MSSSR0",
5014 SPR_NOACCESS, SPR_NOACCESS,
5015 &spr_read_generic, &spr_write_generic,
5016 0x00000000);
5017 /* PMC */
5018 spr_register(env, SPR_7XX_PMC5, "PMC5",
5019 SPR_NOACCESS, SPR_NOACCESS,
5020 &spr_read_generic, &spr_write_generic,
5021 0x00000000);
5022
5023 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5024 &spr_read_ureg, SPR_NOACCESS,
5025 &spr_read_ureg, SPR_NOACCESS,
5026 0x00000000);
5027
5028 spr_register(env, SPR_7XX_PMC6, "PMC6",
5029 SPR_NOACCESS, SPR_NOACCESS,
5030 &spr_read_generic, &spr_write_generic,
5031 0x00000000);
5032
5033 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5034 &spr_read_ureg, SPR_NOACCESS,
5035 &spr_read_ureg, SPR_NOACCESS,
5036 0x00000000);
5037 /* SPRGs */
5038 spr_register(env, SPR_SPRG4, "SPRG4",
5039 SPR_NOACCESS, SPR_NOACCESS,
5040 &spr_read_generic, &spr_write_generic,
5041 0x00000000);
5042 spr_register(env, SPR_USPRG4, "USPRG4",
5043 &spr_read_ureg, SPR_NOACCESS,
5044 &spr_read_ureg, SPR_NOACCESS,
5045 0x00000000);
5046 spr_register(env, SPR_SPRG5, "SPRG5",
5047 SPR_NOACCESS, SPR_NOACCESS,
5048 &spr_read_generic, &spr_write_generic,
5049 0x00000000);
5050 spr_register(env, SPR_USPRG5, "USPRG5",
5051 &spr_read_ureg, SPR_NOACCESS,
5052 &spr_read_ureg, SPR_NOACCESS,
5053 0x00000000);
5054 spr_register(env, SPR_SPRG6, "SPRG6",
5055 SPR_NOACCESS, SPR_NOACCESS,
5056 &spr_read_generic, &spr_write_generic,
5057 0x00000000);
5058 spr_register(env, SPR_USPRG6, "USPRG6",
5059 &spr_read_ureg, SPR_NOACCESS,
5060 &spr_read_ureg, SPR_NOACCESS,
5061 0x00000000);
5062 spr_register(env, SPR_SPRG7, "SPRG7",
5063 SPR_NOACCESS, SPR_NOACCESS,
5064 &spr_read_generic, &spr_write_generic,
5065 0x00000000);
5066 spr_register(env, SPR_USPRG7, "USPRG7",
5067 &spr_read_ureg, SPR_NOACCESS,
5068 &spr_read_ureg, SPR_NOACCESS,
5069 0x00000000);
5070 /* Memory management */
5071 register_low_BATs(env);
5072 register_high_BATs(env);
5073 init_excp_7450(env);
5074 env->dcache_line_size = 32;
5075 env->icache_line_size = 32;
5076 /* Allocate hardware IRQ controller */
5077 ppc6xx_irq_init(env_archcpu(env));
5078 }
5079
5080 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
5081 {
5082 DeviceClass *dc = DEVICE_CLASS(oc);
5083 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5084
5085 dc->desc = "PowerPC 7445 (aka G4)";
5086 pcc->init_proc = init_proc_7445;
5087 pcc->check_pow = check_pow_hid0_74xx;
5088 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5089 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5090 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5091 PPC_FLOAT_STFIWX |
5092 PPC_CACHE | PPC_CACHE_ICBI |
5093 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5094 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5095 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5096 PPC_MEM_TLBIA |
5097 PPC_SEGMENT | PPC_EXTERN |
5098 PPC_ALTIVEC;
5099 pcc->msr_mask = (1ull << MSR_VR) |
5100 (1ull << MSR_POW) |
5101 (1ull << MSR_ILE) |
5102 (1ull << MSR_EE) |
5103 (1ull << MSR_PR) |
5104 (1ull << MSR_FP) |
5105 (1ull << MSR_ME) |
5106 (1ull << MSR_FE0) |
5107 (1ull << MSR_SE) |
5108 (1ull << MSR_DE) |
5109 (1ull << MSR_FE1) |
5110 (1ull << MSR_EP) |
5111 (1ull << MSR_IR) |
5112 (1ull << MSR_DR) |
5113 (1ull << MSR_PMM) |
5114 (1ull << MSR_RI) |
5115 (1ull << MSR_LE);
5116 pcc->mmu_model = POWERPC_MMU_32B;
5117 pcc->excp_model = POWERPC_EXCP_74xx;
5118 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5119 pcc->bfd_mach = bfd_mach_ppc_7400;
5120 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5121 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5122 POWERPC_FLAG_BUS_CLK;
5123 }
5124
5125 static void init_proc_7455(CPUPPCState *env)
5126 {
5127 register_ne_601_sprs(env);
5128 register_sdr1_sprs(env);
5129 register_74xx_sprs(env);
5130 vscr_init(env, 0x00010000);
5131 /* Level 3 cache control */
5132 register_l3_ctrl(env);
5133 /* LDSTCR */
5134 spr_register(env, SPR_LDSTCR, "LDSTCR",
5135 SPR_NOACCESS, SPR_NOACCESS,
5136 &spr_read_generic, &spr_write_generic,
5137 0x00000000);
5138 /* ICTRL */
5139 spr_register(env, SPR_ICTRL, "ICTRL",
5140 SPR_NOACCESS, SPR_NOACCESS,
5141 &spr_read_generic, &spr_write_generic,
5142 0x00000000);
5143 /* MSSSR0 */
5144 spr_register(env, SPR_MSSSR0, "MSSSR0",
5145 SPR_NOACCESS, SPR_NOACCESS,
5146 &spr_read_generic, &spr_write_generic,
5147 0x00000000);
5148 /* PMC */
5149 spr_register(env, SPR_7XX_PMC5, "PMC5",
5150 SPR_NOACCESS, SPR_NOACCESS,
5151 &spr_read_generic, &spr_write_generic,
5152 0x00000000);
5153
5154 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5155 &spr_read_ureg, SPR_NOACCESS,
5156 &spr_read_ureg, SPR_NOACCESS,
5157 0x00000000);
5158
5159 spr_register(env, SPR_7XX_PMC6, "PMC6",
5160 SPR_NOACCESS, SPR_NOACCESS,
5161 &spr_read_generic, &spr_write_generic,
5162 0x00000000);
5163
5164 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5165 &spr_read_ureg, SPR_NOACCESS,
5166 &spr_read_ureg, SPR_NOACCESS,
5167 0x00000000);
5168 /* SPRGs */
5169 spr_register(env, SPR_SPRG4, "SPRG4",
5170 SPR_NOACCESS, SPR_NOACCESS,
5171 &spr_read_generic, &spr_write_generic,
5172 0x00000000);
5173 spr_register(env, SPR_USPRG4, "USPRG4",
5174 &spr_read_ureg, SPR_NOACCESS,
5175 &spr_read_ureg, SPR_NOACCESS,
5176 0x00000000);
5177 spr_register(env, SPR_SPRG5, "SPRG5",
5178 SPR_NOACCESS, SPR_NOACCESS,
5179 &spr_read_generic, &spr_write_generic,
5180 0x00000000);
5181 spr_register(env, SPR_USPRG5, "USPRG5",
5182 &spr_read_ureg, SPR_NOACCESS,
5183 &spr_read_ureg, SPR_NOACCESS,
5184 0x00000000);
5185 spr_register(env, SPR_SPRG6, "SPRG6",
5186 SPR_NOACCESS, SPR_NOACCESS,
5187 &spr_read_generic, &spr_write_generic,
5188 0x00000000);
5189 spr_register(env, SPR_USPRG6, "USPRG6",
5190 &spr_read_ureg, SPR_NOACCESS,
5191 &spr_read_ureg, SPR_NOACCESS,
5192 0x00000000);
5193 spr_register(env, SPR_SPRG7, "SPRG7",
5194 SPR_NOACCESS, SPR_NOACCESS,
5195 &spr_read_generic, &spr_write_generic,
5196 0x00000000);
5197 spr_register(env, SPR_USPRG7, "USPRG7",
5198 &spr_read_ureg, SPR_NOACCESS,
5199 &spr_read_ureg, SPR_NOACCESS,
5200 0x00000000);
5201 /* Memory management */
5202 register_low_BATs(env);
5203 register_high_BATs(env);
5204 init_excp_7450(env);
5205 env->dcache_line_size = 32;
5206 env->icache_line_size = 32;
5207 /* Allocate hardware IRQ controller */
5208 ppc6xx_irq_init(env_archcpu(env));
5209 }
5210
5211 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
5212 {
5213 DeviceClass *dc = DEVICE_CLASS(oc);
5214 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5215
5216 dc->desc = "PowerPC 7455 (aka G4)";
5217 pcc->init_proc = init_proc_7455;
5218 pcc->check_pow = check_pow_hid0_74xx;
5219 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5220 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5221 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5222 PPC_FLOAT_STFIWX |
5223 PPC_CACHE | PPC_CACHE_ICBI |
5224 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5225 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5226 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5227 PPC_MEM_TLBIA |
5228 PPC_SEGMENT | PPC_EXTERN |
5229 PPC_ALTIVEC;
5230 pcc->msr_mask = (1ull << MSR_VR) |
5231 (1ull << MSR_POW) |
5232 (1ull << MSR_ILE) |
5233 (1ull << MSR_EE) |
5234 (1ull << MSR_PR) |
5235 (1ull << MSR_FP) |
5236 (1ull << MSR_ME) |
5237 (1ull << MSR_FE0) |
5238 (1ull << MSR_SE) |
5239 (1ull << MSR_DE) |
5240 (1ull << MSR_FE1) |
5241 (1ull << MSR_EP) |
5242 (1ull << MSR_IR) |
5243 (1ull << MSR_DR) |
5244 (1ull << MSR_PMM) |
5245 (1ull << MSR_RI) |
5246 (1ull << MSR_LE);
5247 pcc->mmu_model = POWERPC_MMU_32B;
5248 pcc->excp_model = POWERPC_EXCP_74xx;
5249 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5250 pcc->bfd_mach = bfd_mach_ppc_7400;
5251 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5252 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5253 POWERPC_FLAG_BUS_CLK;
5254 }
5255
5256 static void init_proc_7457(CPUPPCState *env)
5257 {
5258 register_ne_601_sprs(env);
5259 register_sdr1_sprs(env);
5260 register_74xx_sprs(env);
5261 vscr_init(env, 0x00010000);
5262 /* Level 3 cache control */
5263 register_l3_ctrl(env);
5264 /* L3ITCR1 */
5265 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5266 SPR_NOACCESS, SPR_NOACCESS,
5267 &spr_read_generic, &spr_write_generic,
5268 0x00000000);
5269 /* L3ITCR2 */
5270 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5271 SPR_NOACCESS, SPR_NOACCESS,
5272 &spr_read_generic, &spr_write_generic,
5273 0x00000000);
5274 /* L3ITCR3 */
5275 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5276 SPR_NOACCESS, SPR_NOACCESS,
5277 &spr_read_generic, &spr_write_generic,
5278 0x00000000);
5279 /* L3OHCR */
5280 spr_register(env, SPR_L3OHCR, "L3OHCR",
5281 SPR_NOACCESS, SPR_NOACCESS,
5282 &spr_read_generic, &spr_write_generic,
5283 0x00000000);
5284 /* LDSTCR */
5285 spr_register(env, SPR_LDSTCR, "LDSTCR",
5286 SPR_NOACCESS, SPR_NOACCESS,
5287 &spr_read_generic, &spr_write_generic,
5288 0x00000000);
5289 /* ICTRL */
5290 spr_register(env, SPR_ICTRL, "ICTRL",
5291 SPR_NOACCESS, SPR_NOACCESS,
5292 &spr_read_generic, &spr_write_generic,
5293 0x00000000);
5294 /* MSSSR0 */
5295 spr_register(env, SPR_MSSSR0, "MSSSR0",
5296 SPR_NOACCESS, SPR_NOACCESS,
5297 &spr_read_generic, &spr_write_generic,
5298 0x00000000);
5299 /* PMC */
5300 spr_register(env, SPR_7XX_PMC5, "PMC5",
5301 SPR_NOACCESS, SPR_NOACCESS,
5302 &spr_read_generic, &spr_write_generic,
5303 0x00000000);
5304
5305 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5306 &spr_read_ureg, SPR_NOACCESS,
5307 &spr_read_ureg, SPR_NOACCESS,
5308 0x00000000);
5309
5310 spr_register(env, SPR_7XX_PMC6, "PMC6",
5311 SPR_NOACCESS, SPR_NOACCESS,
5312 &spr_read_generic, &spr_write_generic,
5313 0x00000000);
5314
5315 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5316 &spr_read_ureg, SPR_NOACCESS,
5317 &spr_read_ureg, SPR_NOACCESS,
5318 0x00000000);
5319 /* SPRGs */
5320 spr_register(env, SPR_SPRG4, "SPRG4",
5321 SPR_NOACCESS, SPR_NOACCESS,
5322 &spr_read_generic, &spr_write_generic,
5323 0x00000000);
5324 spr_register(env, SPR_USPRG4, "USPRG4",
5325 &spr_read_ureg, SPR_NOACCESS,
5326 &spr_read_ureg, SPR_NOACCESS,
5327 0x00000000);
5328 spr_register(env, SPR_SPRG5, "SPRG5",
5329 SPR_NOACCESS, SPR_NOACCESS,
5330 &spr_read_generic, &spr_write_generic,
5331 0x00000000);
5332 spr_register(env, SPR_USPRG5, "USPRG5",
5333 &spr_read_ureg, SPR_NOACCESS,
5334 &spr_read_ureg, SPR_NOACCESS,
5335 0x00000000);
5336 spr_register(env, SPR_SPRG6, "SPRG6",
5337 SPR_NOACCESS, SPR_NOACCESS,
5338 &spr_read_generic, &spr_write_generic,
5339 0x00000000);
5340 spr_register(env, SPR_USPRG6, "USPRG6",
5341 &spr_read_ureg, SPR_NOACCESS,
5342 &spr_read_ureg, SPR_NOACCESS,
5343 0x00000000);
5344 spr_register(env, SPR_SPRG7, "SPRG7",
5345 SPR_NOACCESS, SPR_NOACCESS,
5346 &spr_read_generic, &spr_write_generic,
5347 0x00000000);
5348 spr_register(env, SPR_USPRG7, "USPRG7",
5349 &spr_read_ureg, SPR_NOACCESS,
5350 &spr_read_ureg, SPR_NOACCESS,
5351 0x00000000);
5352 /* Memory management */
5353 register_low_BATs(env);
5354 register_high_BATs(env);
5355 init_excp_7450(env);
5356 env->dcache_line_size = 32;
5357 env->icache_line_size = 32;
5358 /* Allocate hardware IRQ controller */
5359 ppc6xx_irq_init(env_archcpu(env));
5360 }
5361
5362 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
5363 {
5364 DeviceClass *dc = DEVICE_CLASS(oc);
5365 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5366
5367 dc->desc = "PowerPC 7457 (aka G4)";
5368 pcc->init_proc = init_proc_7457;
5369 pcc->check_pow = check_pow_hid0_74xx;
5370 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5371 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5372 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5373 PPC_FLOAT_STFIWX |
5374 PPC_CACHE | PPC_CACHE_ICBI |
5375 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5376 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5377 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5378 PPC_MEM_TLBIA |
5379 PPC_SEGMENT | PPC_EXTERN |
5380 PPC_ALTIVEC;
5381 pcc->msr_mask = (1ull << MSR_VR) |
5382 (1ull << MSR_POW) |
5383 (1ull << MSR_ILE) |
5384 (1ull << MSR_EE) |
5385 (1ull << MSR_PR) |
5386 (1ull << MSR_FP) |
5387 (1ull << MSR_ME) |
5388 (1ull << MSR_FE0) |
5389 (1ull << MSR_SE) |
5390 (1ull << MSR_DE) |
5391 (1ull << MSR_FE1) |
5392 (1ull << MSR_EP) |
5393 (1ull << MSR_IR) |
5394 (1ull << MSR_DR) |
5395 (1ull << MSR_PMM) |
5396 (1ull << MSR_RI) |
5397 (1ull << MSR_LE);
5398 pcc->mmu_model = POWERPC_MMU_32B;
5399 pcc->excp_model = POWERPC_EXCP_74xx;
5400 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5401 pcc->bfd_mach = bfd_mach_ppc_7400;
5402 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5403 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5404 POWERPC_FLAG_BUS_CLK;
5405 }
5406
5407 static void init_proc_e600(CPUPPCState *env)
5408 {
5409 register_ne_601_sprs(env);
5410 register_sdr1_sprs(env);
5411 register_74xx_sprs(env);
5412 vscr_init(env, 0x00010000);
5413
5414 spr_register(env, SPR_UBAMR, "UBAMR",
5415 &spr_read_ureg, SPR_NOACCESS,
5416 &spr_read_ureg, SPR_NOACCESS,
5417 0x00000000);
5418
5419 spr_register(env, SPR_LDSTCR, "LDSTCR",
5420 SPR_NOACCESS, SPR_NOACCESS,
5421 &spr_read_generic, &spr_write_generic,
5422 0x00000000);
5423
5424 spr_register(env, SPR_ICTRL, "ICTRL",
5425 SPR_NOACCESS, SPR_NOACCESS,
5426 &spr_read_generic, &spr_write_generic,
5427 0x00000000);
5428
5429 spr_register(env, SPR_MSSSR0, "MSSSR0",
5430 SPR_NOACCESS, SPR_NOACCESS,
5431 &spr_read_generic, &spr_write_generic,
5432 0x00000000);
5433
5434 spr_register(env, SPR_7XX_PMC5, "PMC5",
5435 SPR_NOACCESS, SPR_NOACCESS,
5436 &spr_read_generic, &spr_write_generic,
5437 0x00000000);
5438
5439 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5440 &spr_read_ureg, SPR_NOACCESS,
5441 &spr_read_ureg, SPR_NOACCESS,
5442 0x00000000);
5443
5444 spr_register(env, SPR_7XX_PMC6, "PMC6",
5445 SPR_NOACCESS, SPR_NOACCESS,
5446 &spr_read_generic, &spr_write_generic,
5447 0x00000000);
5448
5449 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5450 &spr_read_ureg, SPR_NOACCESS,
5451 &spr_read_ureg, SPR_NOACCESS,
5452 0x00000000);
5453 /* SPRGs */
5454 spr_register(env, SPR_SPRG4, "SPRG4",
5455 SPR_NOACCESS, SPR_NOACCESS,
5456 &spr_read_generic, &spr_write_generic,
5457 0x00000000);
5458 spr_register(env, SPR_USPRG4, "USPRG4",
5459 &spr_read_ureg, SPR_NOACCESS,
5460 &spr_read_ureg, SPR_NOACCESS,
5461 0x00000000);
5462 spr_register(env, SPR_SPRG5, "SPRG5",
5463 SPR_NOACCESS, SPR_NOACCESS,
5464 &spr_read_generic, &spr_write_generic,
5465 0x00000000);
5466 spr_register(env, SPR_USPRG5, "USPRG5",
5467 &spr_read_ureg, SPR_NOACCESS,
5468 &spr_read_ureg, SPR_NOACCESS,
5469 0x00000000);
5470 spr_register(env, SPR_SPRG6, "SPRG6",
5471 SPR_NOACCESS, SPR_NOACCESS,
5472 &spr_read_generic, &spr_write_generic,
5473 0x00000000);
5474 spr_register(env, SPR_USPRG6, "USPRG6",
5475 &spr_read_ureg, SPR_NOACCESS,
5476 &spr_read_ureg, SPR_NOACCESS,
5477 0x00000000);
5478 spr_register(env, SPR_SPRG7, "SPRG7",
5479 SPR_NOACCESS, SPR_NOACCESS,
5480 &spr_read_generic, &spr_write_generic,
5481 0x00000000);
5482 spr_register(env, SPR_USPRG7, "USPRG7",
5483 &spr_read_ureg, SPR_NOACCESS,
5484 &spr_read_ureg, SPR_NOACCESS,
5485 0x00000000);
5486 /* Memory management */
5487 register_low_BATs(env);
5488 register_high_BATs(env);
5489 init_excp_7450(env);
5490 env->dcache_line_size = 32;
5491 env->icache_line_size = 32;
5492 /* Allocate hardware IRQ controller */
5493 ppc6xx_irq_init(env_archcpu(env));
5494 }
5495
5496 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
5497 {
5498 DeviceClass *dc = DEVICE_CLASS(oc);
5499 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5500
5501 dc->desc = "PowerPC e600";
5502 pcc->init_proc = init_proc_e600;
5503 pcc->check_pow = check_pow_hid0_74xx;
5504 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5505 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5506 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5507 PPC_FLOAT_STFIWX |
5508 PPC_CACHE | PPC_CACHE_ICBI |
5509 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5510 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5511 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5512 PPC_MEM_TLBIA |
5513 PPC_SEGMENT | PPC_EXTERN |
5514 PPC_ALTIVEC;
5515 pcc->insns_flags2 = PPC_NONE;
5516 pcc->msr_mask = (1ull << MSR_VR) |
5517 (1ull << MSR_POW) |
5518 (1ull << MSR_ILE) |
5519 (1ull << MSR_EE) |
5520 (1ull << MSR_PR) |
5521 (1ull << MSR_FP) |
5522 (1ull << MSR_ME) |
5523 (1ull << MSR_FE0) |
5524 (1ull << MSR_SE) |
5525 (1ull << MSR_DE) |
5526 (1ull << MSR_FE1) |
5527 (1ull << MSR_EP) |
5528 (1ull << MSR_IR) |
5529 (1ull << MSR_DR) |
5530 (1ull << MSR_PMM) |
5531 (1ull << MSR_RI) |
5532 (1ull << MSR_LE);
5533 pcc->mmu_model = POWERPC_MMU_32B;
5534 pcc->excp_model = POWERPC_EXCP_74xx;
5535 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5536 pcc->bfd_mach = bfd_mach_ppc_7400;
5537 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5538 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5539 POWERPC_FLAG_BUS_CLK;
5540 }
5541
5542 #if defined(TARGET_PPC64)
5543 #if defined(CONFIG_USER_ONLY)
5544 #define POWERPC970_HID5_INIT 0x00000080
5545 #else
5546 #define POWERPC970_HID5_INIT 0x00000000
5547 #endif
5548
5549 static int check_pow_970(CPUPPCState *env)
5550 {
5551 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
5552 return 1;
5553 }
5554
5555 return 0;
5556 }
5557
5558 static void register_970_hid_sprs(CPUPPCState *env)
5559 {
5560 /* Hardware implementation registers */
5561 spr_register(env, SPR_HID0, "HID0",
5562 SPR_NOACCESS, SPR_NOACCESS,
5563 &spr_read_generic, &spr_write_clear,
5564 0x60000000);
5565 spr_register(env, SPR_HID1, "HID1",
5566 SPR_NOACCESS, SPR_NOACCESS,
5567 &spr_read_generic, &spr_write_generic,
5568 0x00000000);
5569 spr_register(env, SPR_970_HID5, "HID5",
5570 SPR_NOACCESS, SPR_NOACCESS,
5571 &spr_read_generic, &spr_write_generic,
5572 POWERPC970_HID5_INIT);
5573 }
5574
5575 static void register_970_hior_sprs(CPUPPCState *env)
5576 {
5577 spr_register(env, SPR_HIOR, "SPR_HIOR",
5578 SPR_NOACCESS, SPR_NOACCESS,
5579 &spr_read_hior, &spr_write_hior,
5580 0x00000000);
5581 }
5582
5583 static void register_book3s_ctrl_sprs(CPUPPCState *env)
5584 {
5585 spr_register(env, SPR_CTRL, "SPR_CTRL",
5586 SPR_NOACCESS, SPR_NOACCESS,
5587 SPR_NOACCESS, &spr_write_CTRL,
5588 0x00000000);
5589 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
5590 &spr_read_ureg, SPR_NOACCESS,
5591 &spr_read_ureg, SPR_NOACCESS,
5592 0x00000000);
5593 }
5594
5595 static void register_book3s_altivec_sprs(CPUPPCState *env)
5596 {
5597 if (!(env->insns_flags & PPC_ALTIVEC)) {
5598 return;
5599 }
5600
5601 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
5602 &spr_read_generic, &spr_write_generic,
5603 &spr_read_generic, &spr_write_generic,
5604 KVM_REG_PPC_VRSAVE, 0x00000000);
5605
5606 }
5607
5608 static void register_book3s_dbg_sprs(CPUPPCState *env)
5609 {
5610 /*
5611 * TODO: different specs define different scopes for these,
5612 * will have to address this:
5613 * 970: super/write and super/read
5614 * powerisa 2.03..2.04: hypv/write and super/read.
5615 * powerisa 2.05 and newer: hypv/write and hypv/read.
5616 */
5617 spr_register_kvm(env, SPR_DABR, "DABR",
5618 SPR_NOACCESS, SPR_NOACCESS,
5619 &spr_read_generic, &spr_write_generic,
5620 KVM_REG_PPC_DABR, 0x00000000);
5621 spr_register_kvm(env, SPR_DABRX, "DABRX",
5622 SPR_NOACCESS, SPR_NOACCESS,
5623 &spr_read_generic, &spr_write_generic,
5624 KVM_REG_PPC_DABRX, 0x00000000);
5625 }
5626
5627 static void register_book3s_207_dbg_sprs(CPUPPCState *env)
5628 {
5629 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
5630 SPR_NOACCESS, SPR_NOACCESS,
5631 SPR_NOACCESS, SPR_NOACCESS,
5632 &spr_read_generic, &spr_write_generic,
5633 KVM_REG_PPC_DAWR, 0x00000000);
5634 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
5635 SPR_NOACCESS, SPR_NOACCESS,
5636 SPR_NOACCESS, SPR_NOACCESS,
5637 &spr_read_generic, &spr_write_generic,
5638 KVM_REG_PPC_DAWRX, 0x00000000);
5639 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
5640 SPR_NOACCESS, SPR_NOACCESS,
5641 SPR_NOACCESS, SPR_NOACCESS,
5642 &spr_read_generic, &spr_write_generic,
5643 KVM_REG_PPC_CIABR, 0x00000000);
5644 }
5645
5646 static void register_970_dbg_sprs(CPUPPCState *env)
5647 {
5648 /* Breakpoints */
5649 spr_register(env, SPR_IABR, "IABR",
5650 SPR_NOACCESS, SPR_NOACCESS,
5651 &spr_read_generic, &spr_write_generic,
5652 0x00000000);
5653 }
5654
5655 static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
5656 {
5657 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
5658 SPR_NOACCESS, SPR_NOACCESS,
5659 &spr_read_generic, &spr_write_MMCR0,
5660 KVM_REG_PPC_MMCR0, 0x80000000);
5661 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
5662 SPR_NOACCESS, SPR_NOACCESS,
5663 &spr_read_generic, &spr_write_MMCR1,
5664 KVM_REG_PPC_MMCR1, 0x00000000);
5665 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
5666 SPR_NOACCESS, SPR_NOACCESS,
5667 &spr_read_generic, &spr_write_generic,
5668 KVM_REG_PPC_MMCRA, 0x00000000);
5669 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
5670 SPR_NOACCESS, SPR_NOACCESS,
5671 &spr_read_PMC, &spr_write_PMC,
5672 KVM_REG_PPC_PMC1, 0x00000000);
5673 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
5674 SPR_NOACCESS, SPR_NOACCESS,
5675 &spr_read_PMC, &spr_write_PMC,
5676 KVM_REG_PPC_PMC2, 0x00000000);
5677 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
5678 SPR_NOACCESS, SPR_NOACCESS,
5679 &spr_read_PMC, &spr_write_PMC,
5680 KVM_REG_PPC_PMC3, 0x00000000);
5681 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
5682 SPR_NOACCESS, SPR_NOACCESS,
5683 &spr_read_PMC, &spr_write_PMC,
5684 KVM_REG_PPC_PMC4, 0x00000000);
5685 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
5686 SPR_NOACCESS, SPR_NOACCESS,
5687 &spr_read_PMC, &spr_write_PMC,
5688 KVM_REG_PPC_PMC5, 0x00000000);
5689 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
5690 SPR_NOACCESS, SPR_NOACCESS,
5691 &spr_read_PMC, &spr_write_PMC,
5692 KVM_REG_PPC_PMC6, 0x00000000);
5693 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
5694 SPR_NOACCESS, SPR_NOACCESS,
5695 &spr_read_generic, &spr_write_generic,
5696 KVM_REG_PPC_SIAR, 0x00000000);
5697 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
5698 SPR_NOACCESS, SPR_NOACCESS,
5699 &spr_read_generic, &spr_write_generic,
5700 KVM_REG_PPC_SDAR, 0x00000000);
5701 }
5702
5703 static void register_book3s_pmu_user_sprs(CPUPPCState *env)
5704 {
5705 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
5706 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg,
5707 &spr_read_ureg, &spr_write_ureg,
5708 0x80000000);
5709 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
5710 &spr_read_ureg, SPR_NOACCESS,
5711 &spr_read_ureg, &spr_write_ureg,
5712 0x00000000);
5713 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
5714 &spr_read_ureg, SPR_NOACCESS,
5715 &spr_read_ureg, &spr_write_ureg,
5716 0x00000000);
5717 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
5718 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5719 &spr_read_ureg, &spr_write_ureg,
5720 0x00000000);
5721 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
5722 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5723 &spr_read_ureg, &spr_write_ureg,
5724 0x00000000);
5725 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
5726 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5727 &spr_read_ureg, &spr_write_ureg,
5728 0x00000000);
5729 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
5730 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5731 &spr_read_ureg, &spr_write_ureg,
5732 0x00000000);
5733 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
5734 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5735 &spr_read_ureg, &spr_write_ureg,
5736 0x00000000);
5737 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
5738 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5739 &spr_read_ureg, &spr_write_ureg,
5740 0x00000000);
5741 spr_register(env, SPR_POWER_USIAR, "USIAR",
5742 &spr_read_ureg, SPR_NOACCESS,
5743 &spr_read_ureg, &spr_write_ureg,
5744 0x00000000);
5745 spr_register(env, SPR_POWER_USDAR, "USDAR",
5746 &spr_read_ureg, SPR_NOACCESS,
5747 &spr_read_ureg, &spr_write_ureg,
5748 0x00000000);
5749 }
5750
5751 static void register_970_pmu_sup_sprs(CPUPPCState *env)
5752 {
5753 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
5754 SPR_NOACCESS, SPR_NOACCESS,
5755 &spr_read_generic, &spr_write_generic,
5756 KVM_REG_PPC_PMC7, 0x00000000);
5757 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
5758 SPR_NOACCESS, SPR_NOACCESS,
5759 &spr_read_generic, &spr_write_generic,
5760 KVM_REG_PPC_PMC8, 0x00000000);
5761 }
5762
5763 static void register_970_pmu_user_sprs(CPUPPCState *env)
5764 {
5765 spr_register(env, SPR_970_UPMC7, "UPMC7",
5766 &spr_read_ureg, SPR_NOACCESS,
5767 &spr_read_ureg, &spr_write_ureg,
5768 0x00000000);
5769 spr_register(env, SPR_970_UPMC8, "UPMC8",
5770 &spr_read_ureg, SPR_NOACCESS,
5771 &spr_read_ureg, &spr_write_ureg,
5772 0x00000000);
5773 }
5774
5775 static void register_power8_pmu_sup_sprs(CPUPPCState *env)
5776 {
5777 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
5778 SPR_NOACCESS, SPR_NOACCESS,
5779 &spr_read_generic, &spr_write_generic,
5780 KVM_REG_PPC_MMCR2, 0x00000000);
5781 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
5782 SPR_NOACCESS, SPR_NOACCESS,
5783 &spr_read_generic, &spr_write_generic,
5784 KVM_REG_PPC_MMCRS, 0x00000000);
5785 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
5786 SPR_NOACCESS, SPR_NOACCESS,
5787 &spr_read_generic, &spr_write_generic,
5788 KVM_REG_PPC_SIER, 0x00000000);
5789 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
5790 SPR_NOACCESS, SPR_NOACCESS,
5791 &spr_read_generic, &spr_write_generic,
5792 KVM_REG_PPC_SPMC1, 0x00000000);
5793 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
5794 SPR_NOACCESS, SPR_NOACCESS,
5795 &spr_read_generic, &spr_write_generic,
5796 KVM_REG_PPC_SPMC2, 0x00000000);
5797 spr_register_kvm(env, SPR_TACR, "TACR",
5798 SPR_NOACCESS, SPR_NOACCESS,
5799 &spr_read_generic, &spr_write_generic,
5800 KVM_REG_PPC_TACR, 0x00000000);
5801 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
5802 SPR_NOACCESS, SPR_NOACCESS,
5803 &spr_read_generic, &spr_write_generic,
5804 KVM_REG_PPC_TCSCR, 0x00000000);
5805 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
5806 SPR_NOACCESS, SPR_NOACCESS,
5807 &spr_read_generic, &spr_write_generic,
5808 KVM_REG_PPC_CSIGR, 0x00000000);
5809 }
5810
5811 static void register_power8_pmu_user_sprs(CPUPPCState *env)
5812 {
5813 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
5814 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg,
5815 &spr_read_ureg, &spr_write_ureg,
5816 0x00000000);
5817 spr_register(env, SPR_POWER_USIER, "USIER",
5818 &spr_read_generic, SPR_NOACCESS,
5819 &spr_read_generic, &spr_write_generic,
5820 0x00000000);
5821 }
5822
5823 static void register_power5p_ear_sprs(CPUPPCState *env)
5824 {
5825 /* External access control */
5826 spr_register(env, SPR_EAR, "EAR",
5827 SPR_NOACCESS, SPR_NOACCESS,
5828 &spr_read_generic, &spr_write_generic,
5829 0x00000000);
5830 }
5831
5832 static void register_power5p_tb_sprs(CPUPPCState *env)
5833 {
5834 /* TBU40 (High 40 bits of the Timebase register */
5835 spr_register_hv(env, SPR_TBU40, "TBU40",
5836 SPR_NOACCESS, SPR_NOACCESS,
5837 SPR_NOACCESS, SPR_NOACCESS,
5838 SPR_NOACCESS, &spr_write_tbu40,
5839 0x00000000);
5840 }
5841
5842 static void register_970_lpar_sprs(CPUPPCState *env)
5843 {
5844 #if !defined(CONFIG_USER_ONLY)
5845 /*
5846 * PPC970: HID4 covers things later controlled by the LPCR and
5847 * RMOR in later CPUs, but with a different encoding. We only
5848 * support the 970 in "Apple mode" which has all hypervisor
5849 * facilities disabled by strapping, so we can basically just
5850 * ignore it
5851 */
5852 spr_register(env, SPR_970_HID4, "HID4",
5853 SPR_NOACCESS, SPR_NOACCESS,
5854 &spr_read_generic, &spr_write_generic,
5855 0x00000000);
5856 #endif
5857 }
5858
5859 static void register_power5p_lpar_sprs(CPUPPCState *env)
5860 {
5861 #if !defined(CONFIG_USER_ONLY)
5862 /* Logical partitionning */
5863 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
5864 SPR_NOACCESS, SPR_NOACCESS,
5865 SPR_NOACCESS, SPR_NOACCESS,
5866 &spr_read_generic, &spr_write_lpcr,
5867 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
5868 spr_register_hv(env, SPR_HDEC, "HDEC",
5869 SPR_NOACCESS, SPR_NOACCESS,
5870 SPR_NOACCESS, SPR_NOACCESS,
5871 &spr_read_hdecr, &spr_write_hdecr, 0);
5872 #endif
5873 }
5874
5875 static void register_book3s_ids_sprs(CPUPPCState *env)
5876 {
5877 /* FIXME: Will need to deal with thread vs core only SPRs */
5878
5879 /* Processor identification */
5880 spr_register_hv(env, SPR_PIR, "PIR",
5881 SPR_NOACCESS, SPR_NOACCESS,
5882 &spr_read_generic, SPR_NOACCESS,
5883 &spr_read_generic, NULL,
5884 0x00000000);
5885 spr_register_hv(env, SPR_HID0, "HID0",
5886 SPR_NOACCESS, SPR_NOACCESS,
5887 SPR_NOACCESS, SPR_NOACCESS,
5888 &spr_read_generic, &spr_write_generic,
5889 0x00000000);
5890 spr_register_hv(env, SPR_TSCR, "TSCR",
5891 SPR_NOACCESS, SPR_NOACCESS,
5892 SPR_NOACCESS, SPR_NOACCESS,
5893 &spr_read_generic, &spr_write_generic,
5894 0x00000000);
5895 spr_register_hv(env, SPR_HMER, "HMER",
5896 SPR_NOACCESS, SPR_NOACCESS,
5897 SPR_NOACCESS, SPR_NOACCESS,
5898 &spr_read_generic, &spr_write_hmer,
5899 0x00000000);
5900 spr_register_hv(env, SPR_HMEER, "HMEER",
5901 SPR_NOACCESS, SPR_NOACCESS,
5902 SPR_NOACCESS, SPR_NOACCESS,
5903 &spr_read_generic, &spr_write_generic,
5904 0x00000000);
5905 spr_register_hv(env, SPR_TFMR, "TFMR",
5906 SPR_NOACCESS, SPR_NOACCESS,
5907 SPR_NOACCESS, SPR_NOACCESS,
5908 &spr_read_generic, &spr_write_generic,
5909 0x00000000);
5910 spr_register_hv(env, SPR_LPIDR, "LPIDR",
5911 SPR_NOACCESS, SPR_NOACCESS,
5912 SPR_NOACCESS, SPR_NOACCESS,
5913 &spr_read_generic, &spr_write_lpidr,
5914 0x00000000);
5915 spr_register_hv(env, SPR_HFSCR, "HFSCR",
5916 SPR_NOACCESS, SPR_NOACCESS,
5917 SPR_NOACCESS, SPR_NOACCESS,
5918 &spr_read_generic, &spr_write_generic,
5919 0x00000000);
5920 spr_register_hv(env, SPR_MMCRC, "MMCRC",
5921 SPR_NOACCESS, SPR_NOACCESS,
5922 SPR_NOACCESS, SPR_NOACCESS,
5923 &spr_read_generic, &spr_write_generic,
5924 0x00000000);
5925 spr_register_hv(env, SPR_MMCRH, "MMCRH",
5926 SPR_NOACCESS, SPR_NOACCESS,
5927 SPR_NOACCESS, SPR_NOACCESS,
5928 &spr_read_generic, &spr_write_generic,
5929 0x00000000);
5930 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
5931 SPR_NOACCESS, SPR_NOACCESS,
5932 SPR_NOACCESS, SPR_NOACCESS,
5933 &spr_read_generic, &spr_write_generic,
5934 0x00000000);
5935 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
5936 SPR_NOACCESS, SPR_NOACCESS,
5937 SPR_NOACCESS, SPR_NOACCESS,
5938 &spr_read_generic, &spr_write_generic,
5939 0x00000000);
5940 spr_register_hv(env, SPR_HSRR0, "HSRR0",
5941 SPR_NOACCESS, SPR_NOACCESS,
5942 SPR_NOACCESS, SPR_NOACCESS,
5943 &spr_read_generic, &spr_write_generic,
5944 0x00000000);
5945 spr_register_hv(env, SPR_HSRR1, "HSRR1",
5946 SPR_NOACCESS, SPR_NOACCESS,
5947 SPR_NOACCESS, SPR_NOACCESS,
5948 &spr_read_generic, &spr_write_generic,
5949 0x00000000);
5950 spr_register_hv(env, SPR_HDAR, "HDAR",
5951 SPR_NOACCESS, SPR_NOACCESS,
5952 SPR_NOACCESS, SPR_NOACCESS,
5953 &spr_read_generic, &spr_write_generic,
5954 0x00000000);
5955 spr_register_hv(env, SPR_HDSISR, "HDSISR",
5956 SPR_NOACCESS, SPR_NOACCESS,
5957 SPR_NOACCESS, SPR_NOACCESS,
5958 &spr_read_generic, &spr_write_generic,
5959 0x00000000);
5960 spr_register_hv(env, SPR_HRMOR, "HRMOR",
5961 SPR_NOACCESS, SPR_NOACCESS,
5962 SPR_NOACCESS, SPR_NOACCESS,
5963 &spr_read_generic, &spr_write_generic,
5964 0x00000000);
5965 }
5966
5967 static void register_rmor_sprs(CPUPPCState *env)
5968 {
5969 spr_register_hv(env, SPR_RMOR, "RMOR",
5970 SPR_NOACCESS, SPR_NOACCESS,
5971 SPR_NOACCESS, SPR_NOACCESS,
5972 &spr_read_generic, &spr_write_generic,
5973 0x00000000);
5974 }
5975
5976 static void register_power8_ids_sprs(CPUPPCState *env)
5977 {
5978 /* Thread identification */
5979 spr_register(env, SPR_TIR, "TIR",
5980 SPR_NOACCESS, SPR_NOACCESS,
5981 &spr_read_generic, SPR_NOACCESS,
5982 0x00000000);
5983 }
5984
5985 static void register_book3s_purr_sprs(CPUPPCState *env)
5986 {
5987 #if !defined(CONFIG_USER_ONLY)
5988 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
5989 spr_register_kvm_hv(env, SPR_PURR, "PURR",
5990 &spr_read_purr, SPR_NOACCESS,
5991 &spr_read_purr, SPR_NOACCESS,
5992 &spr_read_purr, &spr_write_purr,
5993 KVM_REG_PPC_PURR, 0x00000000);
5994 spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
5995 &spr_read_purr, SPR_NOACCESS,
5996 &spr_read_purr, SPR_NOACCESS,
5997 &spr_read_purr, &spr_write_purr,
5998 KVM_REG_PPC_SPURR, 0x00000000);
5999 #endif
6000 }
6001
6002 static void register_power6_dbg_sprs(CPUPPCState *env)
6003 {
6004 #if !defined(CONFIG_USER_ONLY)
6005 spr_register(env, SPR_CFAR, "SPR_CFAR",
6006 SPR_NOACCESS, SPR_NOACCESS,
6007 &spr_read_cfar, &spr_write_cfar,
6008 0x00000000);
6009 #endif
6010 }
6011
6012 static void register_power5p_common_sprs(CPUPPCState *env)
6013 {
6014 spr_register_kvm(env, SPR_PPR, "PPR",
6015 &spr_read_generic, &spr_write_generic,
6016 &spr_read_generic, &spr_write_generic,
6017 KVM_REG_PPC_PPR, 0x00000000);
6018 }
6019
6020 static void register_power6_common_sprs(CPUPPCState *env)
6021 {
6022 #if !defined(CONFIG_USER_ONLY)
6023 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
6024 SPR_NOACCESS, SPR_NOACCESS,
6025 &spr_read_generic, &spr_write_generic,
6026 KVM_REG_PPC_DSCR, 0x00000000);
6027 #endif
6028 /*
6029 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
6030 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
6031 */
6032 spr_register_hv(env, SPR_PCR, "PCR",
6033 SPR_NOACCESS, SPR_NOACCESS,
6034 SPR_NOACCESS, SPR_NOACCESS,
6035 &spr_read_generic, &spr_write_pcr,
6036 0x00000000);
6037 }
6038
6039 static void register_power8_tce_address_control_sprs(CPUPPCState *env)
6040 {
6041 spr_register_kvm(env, SPR_TAR, "TAR",
6042 &spr_read_tar, &spr_write_tar,
6043 &spr_read_generic, &spr_write_generic,
6044 KVM_REG_PPC_TAR, 0x00000000);
6045 }
6046
6047 static void register_power8_tm_sprs(CPUPPCState *env)
6048 {
6049 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
6050 &spr_read_tm, &spr_write_tm,
6051 &spr_read_tm, &spr_write_tm,
6052 KVM_REG_PPC_TFHAR, 0x00000000);
6053 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
6054 &spr_read_tm, &spr_write_tm,
6055 &spr_read_tm, &spr_write_tm,
6056 KVM_REG_PPC_TFIAR, 0x00000000);
6057 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
6058 &spr_read_tm, &spr_write_tm,
6059 &spr_read_tm, &spr_write_tm,
6060 KVM_REG_PPC_TEXASR, 0x00000000);
6061 spr_register(env, SPR_TEXASRU, "TEXASRU",
6062 &spr_read_tm_upper32, &spr_write_tm_upper32,
6063 &spr_read_tm_upper32, &spr_write_tm_upper32,
6064 0x00000000);
6065 }
6066
6067 static void register_power8_ebb_sprs(CPUPPCState *env)
6068 {
6069 spr_register(env, SPR_BESCRS, "BESCRS",
6070 &spr_read_ebb, &spr_write_ebb,
6071 &spr_read_generic, &spr_write_generic,
6072 0x00000000);
6073 spr_register(env, SPR_BESCRSU, "BESCRSU",
6074 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
6075 &spr_read_prev_upper32, &spr_write_prev_upper32,
6076 0x00000000);
6077 spr_register(env, SPR_BESCRR, "BESCRR",
6078 &spr_read_ebb, &spr_write_ebb,
6079 &spr_read_generic, &spr_write_generic,
6080 0x00000000);
6081 spr_register(env, SPR_BESCRRU, "BESCRRU",
6082 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
6083 &spr_read_prev_upper32, &spr_write_prev_upper32,
6084 0x00000000);
6085 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
6086 &spr_read_ebb, &spr_write_ebb,
6087 &spr_read_generic, &spr_write_generic,
6088 KVM_REG_PPC_EBBHR, 0x00000000);
6089 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
6090 &spr_read_ebb, &spr_write_ebb,
6091 &spr_read_generic, &spr_write_generic,
6092 KVM_REG_PPC_EBBRR, 0x00000000);
6093 spr_register_kvm(env, SPR_BESCR, "BESCR",
6094 &spr_read_ebb, &spr_write_ebb,
6095 &spr_read_generic, &spr_write_generic,
6096 KVM_REG_PPC_BESCR, 0x00000000);
6097 }
6098
6099 /* Virtual Time Base */
6100 static void register_vtb_sprs(CPUPPCState *env)
6101 {
6102 spr_register_kvm_hv(env, SPR_VTB, "VTB",
6103 SPR_NOACCESS, SPR_NOACCESS,
6104 &spr_read_vtb, SPR_NOACCESS,
6105 &spr_read_vtb, &spr_write_vtb,
6106 KVM_REG_PPC_VTB, 0x00000000);
6107 }
6108
6109 static void register_power8_fscr_sprs(CPUPPCState *env)
6110 {
6111 #if defined(CONFIG_USER_ONLY)
6112 target_ulong initval = 1ULL << FSCR_TAR;
6113 #else
6114 target_ulong initval = 0;
6115 #endif
6116 spr_register_kvm(env, SPR_FSCR, "FSCR",
6117 SPR_NOACCESS, SPR_NOACCESS,
6118 &spr_read_generic, &spr_write_generic,
6119 KVM_REG_PPC_FSCR, initval);
6120 }
6121
6122 static void register_power8_pspb_sprs(CPUPPCState *env)
6123 {
6124 spr_register_kvm(env, SPR_PSPB, "PSPB",
6125 SPR_NOACCESS, SPR_NOACCESS,
6126 &spr_read_generic, &spr_write_generic32,
6127 KVM_REG_PPC_PSPB, 0);
6128 }
6129
6130 static void register_power8_dpdes_sprs(CPUPPCState *env)
6131 {
6132 #if !defined(CONFIG_USER_ONLY)
6133 /* Directed Privileged Door-bell Exception State, used for IPI */
6134 spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
6135 SPR_NOACCESS, SPR_NOACCESS,
6136 &spr_read_dpdes, SPR_NOACCESS,
6137 &spr_read_dpdes, &spr_write_dpdes,
6138 KVM_REG_PPC_DPDES, 0x00000000);
6139 #endif
6140 }
6141
6142 static void register_power8_ic_sprs(CPUPPCState *env)
6143 {
6144 #if !defined(CONFIG_USER_ONLY)
6145 spr_register_hv(env, SPR_IC, "IC",
6146 SPR_NOACCESS, SPR_NOACCESS,
6147 &spr_read_generic, SPR_NOACCESS,
6148 &spr_read_generic, &spr_write_generic,
6149 0);
6150 #endif
6151 }
6152
6153 static void register_power8_book4_sprs(CPUPPCState *env)
6154 {
6155 /* Add a number of P8 book4 registers */
6156 #if !defined(CONFIG_USER_ONLY)
6157 spr_register_kvm(env, SPR_ACOP, "ACOP",
6158 SPR_NOACCESS, SPR_NOACCESS,
6159 &spr_read_generic, &spr_write_generic,
6160 KVM_REG_PPC_ACOP, 0);
6161 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
6162 SPR_NOACCESS, SPR_NOACCESS,
6163 &spr_read_generic, &spr_write_pidr,
6164 KVM_REG_PPC_PID, 0);
6165 spr_register_kvm(env, SPR_WORT, "WORT",
6166 SPR_NOACCESS, SPR_NOACCESS,
6167 &spr_read_generic, &spr_write_generic,
6168 KVM_REG_PPC_WORT, 0);
6169 #endif
6170 }
6171
6172 static void register_power7_book4_sprs(CPUPPCState *env)
6173 {
6174 /* Add a number of P7 book4 registers */
6175 #if !defined(CONFIG_USER_ONLY)
6176 spr_register_kvm(env, SPR_ACOP, "ACOP",
6177 SPR_NOACCESS, SPR_NOACCESS,
6178 &spr_read_generic, &spr_write_generic,
6179 KVM_REG_PPC_ACOP, 0);
6180 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
6181 SPR_NOACCESS, SPR_NOACCESS,
6182 &spr_read_generic, &spr_write_generic,
6183 KVM_REG_PPC_PID, 0);
6184 #endif
6185 }
6186
6187 static void register_power8_rpr_sprs(CPUPPCState *env)
6188 {
6189 #if !defined(CONFIG_USER_ONLY)
6190 spr_register_hv(env, SPR_RPR, "RPR",
6191 SPR_NOACCESS, SPR_NOACCESS,
6192 SPR_NOACCESS, SPR_NOACCESS,
6193 &spr_read_generic, &spr_write_generic,
6194 0x00000103070F1F3F);
6195 #endif
6196 }
6197
6198 static void register_power9_mmu_sprs(CPUPPCState *env)
6199 {
6200 #if !defined(CONFIG_USER_ONLY)
6201 /* Partition Table Control */
6202 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
6203 SPR_NOACCESS, SPR_NOACCESS,
6204 SPR_NOACCESS, SPR_NOACCESS,
6205 &spr_read_generic, &spr_write_ptcr,
6206 KVM_REG_PPC_PTCR, 0x00000000);
6207 /* Address Segment Descriptor Register */
6208 spr_register_hv(env, SPR_ASDR, "ASDR",
6209 SPR_NOACCESS, SPR_NOACCESS,
6210 SPR_NOACCESS, SPR_NOACCESS,
6211 &spr_read_generic, &spr_write_generic,
6212 0x0000000000000000);
6213 #endif
6214 }
6215
6216 /*
6217 * Initialize PMU counter overflow timers for Power8 and
6218 * newer Power chips when using TCG.
6219 */
6220 static void init_tcg_pmu_power8(CPUPPCState *env)
6221 {
6222 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
6223 /* Init PMU overflow timers */
6224 if (!kvm_enabled()) {
6225 cpu_ppc_pmu_init(env);
6226 }
6227 #endif
6228 }
6229
6230 static void init_proc_book3s_common(CPUPPCState *env)
6231 {
6232 register_ne_601_sprs(env);
6233 register_usprg3_sprs(env);
6234 register_book3s_altivec_sprs(env);
6235 register_book3s_pmu_sup_sprs(env);
6236 register_book3s_pmu_user_sprs(env);
6237 register_book3s_ctrl_sprs(env);
6238 /*
6239 * Can't find information on what this should be on reset. This
6240 * value is the one used by 74xx processors.
6241 */
6242 vscr_init(env, 0x00010000);
6243 }
6244
6245 static void init_proc_970(CPUPPCState *env)
6246 {
6247 /* Common Registers */
6248 init_proc_book3s_common(env);
6249 register_sdr1_sprs(env);
6250 register_book3s_dbg_sprs(env);
6251
6252 /* 970 Specific Registers */
6253 register_970_hid_sprs(env);
6254 register_970_hior_sprs(env);
6255 register_low_BATs(env);
6256 register_970_pmu_sup_sprs(env);
6257 register_970_pmu_user_sprs(env);
6258 register_970_lpar_sprs(env);
6259 register_970_dbg_sprs(env);
6260
6261 /* env variables */
6262 env->dcache_line_size = 128;
6263 env->icache_line_size = 128;
6264
6265 /* Allocate hardware IRQ controller */
6266 init_excp_970(env);
6267 ppc970_irq_init(env_archcpu(env));
6268 }
6269
6270 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
6271 {
6272 DeviceClass *dc = DEVICE_CLASS(oc);
6273 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6274
6275 dc->desc = "PowerPC 970";
6276 pcc->init_proc = init_proc_970;
6277 pcc->check_pow = check_pow_970;
6278 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6279 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6280 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6281 PPC_FLOAT_STFIWX |
6282 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6283 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6284 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6285 PPC_64B | PPC_ALTIVEC |
6286 PPC_SEGMENT_64B | PPC_SLBI;
6287 pcc->insns_flags2 = PPC2_FP_CVT_S64;
6288 pcc->msr_mask = (1ull << MSR_SF) |
6289 (1ull << MSR_VR) |
6290 (1ull << MSR_POW) |
6291 (1ull << MSR_EE) |
6292 (1ull << MSR_PR) |
6293 (1ull << MSR_FP) |
6294 (1ull << MSR_ME) |
6295 (1ull << MSR_FE0) |
6296 (1ull << MSR_SE) |
6297 (1ull << MSR_DE) |
6298 (1ull << MSR_FE1) |
6299 (1ull << MSR_IR) |
6300 (1ull << MSR_DR) |
6301 (1ull << MSR_PMM) |
6302 (1ull << MSR_RI);
6303 pcc->mmu_model = POWERPC_MMU_64B;
6304 #if defined(CONFIG_SOFTMMU)
6305 pcc->hash64_opts = &ppc_hash64_opts_basic;
6306 #endif
6307 pcc->excp_model = POWERPC_EXCP_970;
6308 pcc->bus_model = PPC_FLAGS_INPUT_970;
6309 pcc->bfd_mach = bfd_mach_ppc64;
6310 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6311 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6312 POWERPC_FLAG_BUS_CLK;
6313 pcc->l1_dcache_size = 0x8000;
6314 pcc->l1_icache_size = 0x10000;
6315 }
6316
6317 static void init_proc_power5plus(CPUPPCState *env)
6318 {
6319 /* Common Registers */
6320 init_proc_book3s_common(env);
6321 register_sdr1_sprs(env);
6322 register_book3s_dbg_sprs(env);
6323
6324 /* POWER5+ Specific Registers */
6325 register_970_hid_sprs(env);
6326 register_970_hior_sprs(env);
6327 register_low_BATs(env);
6328 register_970_pmu_sup_sprs(env);
6329 register_970_pmu_user_sprs(env);
6330 register_power5p_common_sprs(env);
6331 register_power5p_lpar_sprs(env);
6332 register_power5p_ear_sprs(env);
6333 register_power5p_tb_sprs(env);
6334
6335 /* env variables */
6336 env->dcache_line_size = 128;
6337 env->icache_line_size = 128;
6338
6339 /* Allocate hardware IRQ controller */
6340 init_excp_970(env);
6341 ppc970_irq_init(env_archcpu(env));
6342 }
6343
6344 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
6345 {
6346 DeviceClass *dc = DEVICE_CLASS(oc);
6347 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6348
6349 dc->fw_name = "PowerPC,POWER5";
6350 dc->desc = "POWER5+";
6351 pcc->init_proc = init_proc_power5plus;
6352 pcc->check_pow = check_pow_970;
6353 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6354 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6355 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6356 PPC_FLOAT_STFIWX |
6357 PPC_FLOAT_EXT |
6358 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6359 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6360 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6361 PPC_64B |
6362 PPC_POPCNTB |
6363 PPC_SEGMENT_64B | PPC_SLBI;
6364 pcc->insns_flags2 = PPC2_FP_CVT_S64;
6365 pcc->msr_mask = (1ull << MSR_SF) |
6366 (1ull << MSR_VR) |
6367 (1ull << MSR_POW) |
6368 (1ull << MSR_EE) |
6369 (1ull << MSR_PR) |
6370 (1ull << MSR_FP) |
6371 (1ull << MSR_ME) |
6372 (1ull << MSR_FE0) |
6373 (1ull << MSR_SE) |
6374 (1ull << MSR_DE) |
6375 (1ull << MSR_FE1) |
6376 (1ull << MSR_IR) |
6377 (1ull << MSR_DR) |
6378 (1ull << MSR_PMM) |
6379 (1ull << MSR_RI);
6380 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
6381 LPCR_RMI | LPCR_HDICE;
6382 pcc->mmu_model = POWERPC_MMU_2_03;
6383 #if defined(CONFIG_SOFTMMU)
6384 pcc->hash64_opts = &ppc_hash64_opts_basic;
6385 pcc->lrg_decr_bits = 32;
6386 #endif
6387 pcc->excp_model = POWERPC_EXCP_970;
6388 pcc->bus_model = PPC_FLAGS_INPUT_970;
6389 pcc->bfd_mach = bfd_mach_ppc64;
6390 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6391 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6392 POWERPC_FLAG_BUS_CLK;
6393 pcc->l1_dcache_size = 0x8000;
6394 pcc->l1_icache_size = 0x10000;
6395 }
6396
6397 static void init_proc_POWER7(CPUPPCState *env)
6398 {
6399 /* Common Registers */
6400 init_proc_book3s_common(env);
6401 register_sdr1_sprs(env);
6402 register_book3s_dbg_sprs(env);
6403
6404 /* POWER7 Specific Registers */
6405 register_book3s_ids_sprs(env);
6406 register_rmor_sprs(env);
6407 register_amr_sprs(env);
6408 register_book3s_purr_sprs(env);
6409 register_power5p_common_sprs(env);
6410 register_power5p_lpar_sprs(env);
6411 register_power5p_ear_sprs(env);
6412 register_power5p_tb_sprs(env);
6413 register_power6_common_sprs(env);
6414 register_power6_dbg_sprs(env);
6415 register_power7_book4_sprs(env);
6416
6417 /* env variables */
6418 env->dcache_line_size = 128;
6419 env->icache_line_size = 128;
6420
6421 /* Allocate hardware IRQ controller */
6422 init_excp_POWER7(env);
6423 ppcPOWER7_irq_init(env_archcpu(env));
6424 }
6425
6426 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
6427 {
6428 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
6429 return true;
6430 }
6431 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
6432 return true;
6433 }
6434 return false;
6435 }
6436
6437 static bool cpu_has_work_POWER7(CPUState *cs)
6438 {
6439 PowerPCCPU *cpu = POWERPC_CPU(cs);
6440 CPUPPCState *env = &cpu->env;
6441
6442 if (cs->halted) {
6443 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6444 return false;
6445 }
6446 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6447 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
6448 return true;
6449 }
6450 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6451 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
6452 return true;
6453 }
6454 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
6455 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
6456 return true;
6457 }
6458 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
6459 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
6460 return true;
6461 }
6462 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6463 return true;
6464 }
6465 return false;
6466 } else {
6467 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
6468 }
6469 }
6470
6471 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
6472 {
6473 DeviceClass *dc = DEVICE_CLASS(oc);
6474 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6475 CPUClass *cc = CPU_CLASS(oc);
6476
6477 dc->fw_name = "PowerPC,POWER7";
6478 dc->desc = "POWER7";
6479 pcc->pvr_match = ppc_pvr_match_power7;
6480 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
6481 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6482 pcc->init_proc = init_proc_POWER7;
6483 pcc->check_pow = check_pow_nocheck;
6484 cc->has_work = cpu_has_work_POWER7;
6485 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6486 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6487 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6488 PPC_FLOAT_FRSQRTES |
6489 PPC_FLOAT_STFIWX |
6490 PPC_FLOAT_EXT |
6491 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6492 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6493 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6494 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6495 PPC_SEGMENT_64B | PPC_SLBI |
6496 PPC_POPCNTB | PPC_POPCNTWD |
6497 PPC_CILDST;
6498 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
6499 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6500 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6501 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
6502 PPC2_PM_ISA206;
6503 pcc->msr_mask = (1ull << MSR_SF) |
6504 (1ull << MSR_VR) |
6505 (1ull << MSR_VSX) |
6506 (1ull << MSR_EE) |
6507 (1ull << MSR_PR) |
6508 (1ull << MSR_FP) |
6509 (1ull << MSR_ME) |
6510 (1ull << MSR_FE0) |
6511 (1ull << MSR_SE) |
6512 (1ull << MSR_DE) |
6513 (1ull << MSR_FE1) |
6514 (1ull << MSR_IR) |
6515 (1ull << MSR_DR) |
6516 (1ull << MSR_PMM) |
6517 (1ull << MSR_RI) |
6518 (1ull << MSR_LE);
6519 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
6520 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6521 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
6522 LPCR_MER | LPCR_TC |
6523 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
6524 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
6525 pcc->mmu_model = POWERPC_MMU_2_06;
6526 #if defined(CONFIG_SOFTMMU)
6527 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6528 pcc->lrg_decr_bits = 32;
6529 #endif
6530 pcc->excp_model = POWERPC_EXCP_POWER7;
6531 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6532 pcc->bfd_mach = bfd_mach_ppc64;
6533 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6534 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6535 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6536 POWERPC_FLAG_VSX;
6537 pcc->l1_dcache_size = 0x8000;
6538 pcc->l1_icache_size = 0x8000;
6539 }
6540
6541 static void init_proc_POWER8(CPUPPCState *env)
6542 {
6543 /* Common Registers */
6544 init_proc_book3s_common(env);
6545 register_sdr1_sprs(env);
6546 register_book3s_207_dbg_sprs(env);
6547
6548 /* Common TCG PMU */
6549 init_tcg_pmu_power8(env);
6550
6551 /* POWER8 Specific Registers */
6552 register_book3s_ids_sprs(env);
6553 register_rmor_sprs(env);
6554 register_amr_sprs(env);
6555 register_iamr_sprs(env);
6556 register_book3s_purr_sprs(env);
6557 register_power5p_common_sprs(env);
6558 register_power5p_lpar_sprs(env);
6559 register_power5p_ear_sprs(env);
6560 register_power5p_tb_sprs(env);
6561 register_power6_common_sprs(env);
6562 register_power6_dbg_sprs(env);
6563 register_power8_tce_address_control_sprs(env);
6564 register_power8_ids_sprs(env);
6565 register_power8_ebb_sprs(env);
6566 register_power8_fscr_sprs(env);
6567 register_power8_pmu_sup_sprs(env);
6568 register_power8_pmu_user_sprs(env);
6569 register_power8_tm_sprs(env);
6570 register_power8_pspb_sprs(env);
6571 register_power8_dpdes_sprs(env);
6572 register_vtb_sprs(env);
6573 register_power8_ic_sprs(env);
6574 register_power8_book4_sprs(env);
6575 register_power8_rpr_sprs(env);
6576
6577 /* env variables */
6578 env->dcache_line_size = 128;
6579 env->icache_line_size = 128;
6580
6581 /* Allocate hardware IRQ controller */
6582 init_excp_POWER8(env);
6583 ppcPOWER7_irq_init(env_archcpu(env));
6584 }
6585
6586 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
6587 {
6588 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
6589 return true;
6590 }
6591 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
6592 return true;
6593 }
6594 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
6595 return true;
6596 }
6597 return false;
6598 }
6599
6600 static bool cpu_has_work_POWER8(CPUState *cs)
6601 {
6602 PowerPCCPU *cpu = POWERPC_CPU(cs);
6603 CPUPPCState *env = &cpu->env;
6604
6605 if (cs->halted) {
6606 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6607 return false;
6608 }
6609 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6610 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
6611 return true;
6612 }
6613 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6614 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
6615 return true;
6616 }
6617 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
6618 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
6619 return true;
6620 }
6621 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
6622 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
6623 return true;
6624 }
6625 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6626 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
6627 return true;
6628 }
6629 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6630 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
6631 return true;
6632 }
6633 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6634 return true;
6635 }
6636 return false;
6637 } else {
6638 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
6639 }
6640 }
6641
6642 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
6643 {
6644 DeviceClass *dc = DEVICE_CLASS(oc);
6645 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6646 CPUClass *cc = CPU_CLASS(oc);
6647
6648 dc->fw_name = "PowerPC,POWER8";
6649 dc->desc = "POWER8";
6650 pcc->pvr_match = ppc_pvr_match_power8;
6651 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6652 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6653 pcc->init_proc = init_proc_POWER8;
6654 pcc->check_pow = check_pow_nocheck;
6655 cc->has_work = cpu_has_work_POWER8;
6656 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6657 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6658 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6659 PPC_FLOAT_FRSQRTES |
6660 PPC_FLOAT_STFIWX |
6661 PPC_FLOAT_EXT |
6662 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6663 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6664 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6665 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6666 PPC_SEGMENT_64B | PPC_SLBI |
6667 PPC_POPCNTB | PPC_POPCNTWD |
6668 PPC_CILDST;
6669 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6670 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6671 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6672 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6673 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6674 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6675 PPC2_TM | PPC2_PM_ISA206;
6676 pcc->msr_mask = (1ull << MSR_SF) |
6677 (1ull << MSR_HV) |
6678 (1ull << MSR_TM) |
6679 (1ull << MSR_VR) |
6680 (1ull << MSR_VSX) |
6681 (1ull << MSR_EE) |
6682 (1ull << MSR_PR) |
6683 (1ull << MSR_FP) |
6684 (1ull << MSR_ME) |
6685 (1ull << MSR_FE0) |
6686 (1ull << MSR_SE) |
6687 (1ull << MSR_DE) |
6688 (1ull << MSR_FE1) |
6689 (1ull << MSR_IR) |
6690 (1ull << MSR_DR) |
6691 (1ull << MSR_PMM) |
6692 (1ull << MSR_RI) |
6693 (1ull << MSR_TS0) |
6694 (1ull << MSR_TS1) |
6695 (1ull << MSR_LE);
6696 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
6697 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6698 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
6699 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
6700 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
6701 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
6702 LPCR_P8_PECE3 | LPCR_P8_PECE4;
6703 pcc->mmu_model = POWERPC_MMU_2_07;
6704 #if defined(CONFIG_SOFTMMU)
6705 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6706 pcc->lrg_decr_bits = 32;
6707 pcc->n_host_threads = 8;
6708 #endif
6709 pcc->excp_model = POWERPC_EXCP_POWER8;
6710 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6711 pcc->bfd_mach = bfd_mach_ppc64;
6712 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6713 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6714 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6715 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
6716 pcc->l1_dcache_size = 0x8000;
6717 pcc->l1_icache_size = 0x8000;
6718 }
6719
6720 #ifdef CONFIG_SOFTMMU
6721 /*
6722 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6723 * Encoded as array of int_32s in the form:
6724 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6725 * x -> AP encoding
6726 * y -> radix mode supported page size (encoded as a shift)
6727 */
6728 static struct ppc_radix_page_info POWER9_radix_page_info = {
6729 .count = 4,
6730 .entries = {
6731 0x0000000c, /* 4K - enc: 0x0 */
6732 0xa0000010, /* 64K - enc: 0x5 */
6733 0x20000015, /* 2M - enc: 0x1 */
6734 0x4000001e /* 1G - enc: 0x2 */
6735 }
6736 };
6737 #endif /* CONFIG_SOFTMMU */
6738
6739 static void init_proc_POWER9(CPUPPCState *env)
6740 {
6741 /* Common Registers */
6742 init_proc_book3s_common(env);
6743 register_book3s_207_dbg_sprs(env);
6744
6745 /* Common TCG PMU */
6746 init_tcg_pmu_power8(env);
6747
6748 /* POWER8 Specific Registers */
6749 register_book3s_ids_sprs(env);
6750 register_amr_sprs(env);
6751 register_iamr_sprs(env);
6752 register_book3s_purr_sprs(env);
6753 register_power5p_common_sprs(env);
6754 register_power5p_lpar_sprs(env);
6755 register_power5p_ear_sprs(env);
6756 register_power5p_tb_sprs(env);
6757 register_power6_common_sprs(env);
6758 register_power6_dbg_sprs(env);
6759 register_power8_tce_address_control_sprs(env);
6760 register_power8_ids_sprs(env);
6761 register_power8_ebb_sprs(env);
6762 register_power8_fscr_sprs(env);
6763 register_power8_pmu_sup_sprs(env);
6764 register_power8_pmu_user_sprs(env);
6765 register_power8_tm_sprs(env);
6766 register_power8_pspb_sprs(env);
6767 register_power8_dpdes_sprs(env);
6768 register_vtb_sprs(env);
6769 register_power8_ic_sprs(env);
6770 register_power8_book4_sprs(env);
6771 register_power8_rpr_sprs(env);
6772 register_power9_mmu_sprs(env);
6773
6774 /* POWER9 Specific registers */
6775 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
6776 spr_read_generic, spr_write_generic,
6777 KVM_REG_PPC_TIDR, 0);
6778
6779 /* FIXME: Filter fields properly based on privilege level */
6780 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6781 spr_read_generic, spr_write_generic,
6782 KVM_REG_PPC_PSSCR, 0);
6783
6784 /* env variables */
6785 env->dcache_line_size = 128;
6786 env->icache_line_size = 128;
6787
6788 /* Allocate hardware IRQ controller */
6789 init_excp_POWER9(env);
6790 ppcPOWER9_irq_init(env_archcpu(env));
6791 }
6792
6793 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
6794 {
6795 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
6796 return true;
6797 }
6798 return false;
6799 }
6800
6801 static bool cpu_has_work_POWER9(CPUState *cs)
6802 {
6803 PowerPCCPU *cpu = POWERPC_CPU(cs);
6804 CPUPPCState *env = &cpu->env;
6805
6806 if (cs->halted) {
6807 uint64_t psscr = env->spr[SPR_PSSCR];
6808
6809 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6810 return false;
6811 }
6812
6813 /* If EC is clear, just return true on any pending interrupt */
6814 if (!(psscr & PSSCR_EC)) {
6815 return true;
6816 }
6817 /* External Exception */
6818 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6819 (env->spr[SPR_LPCR] & LPCR_EEE)) {
6820 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
6821 if (heic == 0 || !msr_hv || msr_pr) {
6822 return true;
6823 }
6824 }
6825 /* Decrementer Exception */
6826 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6827 (env->spr[SPR_LPCR] & LPCR_DEE)) {
6828 return true;
6829 }
6830 /* Machine Check or Hypervisor Maintenance Exception */
6831 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
6832 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
6833 return true;
6834 }
6835 /* Privileged Doorbell Exception */
6836 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6837 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
6838 return true;
6839 }
6840 /* Hypervisor Doorbell Exception */
6841 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6842 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
6843 return true;
6844 }
6845 /* Hypervisor virtualization exception */
6846 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
6847 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
6848 return true;
6849 }
6850 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6851 return true;
6852 }
6853 return false;
6854 } else {
6855 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
6856 }
6857 }
6858
6859 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
6860 {
6861 DeviceClass *dc = DEVICE_CLASS(oc);
6862 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6863 CPUClass *cc = CPU_CLASS(oc);
6864
6865 dc->fw_name = "PowerPC,POWER9";
6866 dc->desc = "POWER9";
6867 pcc->pvr_match = ppc_pvr_match_power9;
6868 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
6869 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
6870 PCR_COMPAT_2_05;
6871 pcc->init_proc = init_proc_POWER9;
6872 pcc->check_pow = check_pow_nocheck;
6873 cc->has_work = cpu_has_work_POWER9;
6874 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6875 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6876 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6877 PPC_FLOAT_FRSQRTES |
6878 PPC_FLOAT_STFIWX |
6879 PPC_FLOAT_EXT |
6880 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6881 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6882 PPC_MEM_TLBSYNC |
6883 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6884 PPC_SEGMENT_64B | PPC_SLBI |
6885 PPC_POPCNTB | PPC_POPCNTWD |
6886 PPC_CILDST;
6887 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6888 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6889 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6890 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6891 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6892 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6893 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
6894 pcc->msr_mask = (1ull << MSR_SF) |
6895 (1ull << MSR_HV) |
6896 (1ull << MSR_TM) |
6897 (1ull << MSR_VR) |
6898 (1ull << MSR_VSX) |
6899 (1ull << MSR_EE) |
6900 (1ull << MSR_PR) |
6901 (1ull << MSR_FP) |
6902 (1ull << MSR_ME) |
6903 (1ull << MSR_FE0) |
6904 (1ull << MSR_SE) |
6905 (1ull << MSR_DE) |
6906 (1ull << MSR_FE1) |
6907 (1ull << MSR_IR) |
6908 (1ull << MSR_DR) |
6909 (1ull << MSR_PMM) |
6910 (1ull << MSR_RI) |
6911 (1ull << MSR_LE);
6912 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
6913 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
6914 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
6915 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
6916 LPCR_DEE | LPCR_OEE))
6917 | LPCR_MER | LPCR_GTSE | LPCR_TC |
6918 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
6919 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6920 pcc->mmu_model = POWERPC_MMU_3_00;
6921 #if defined(CONFIG_SOFTMMU)
6922 /* segment page size remain the same */
6923 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6924 pcc->radix_page_info = &POWER9_radix_page_info;
6925 pcc->lrg_decr_bits = 56;
6926 pcc->n_host_threads = 4;
6927 #endif
6928 pcc->excp_model = POWERPC_EXCP_POWER9;
6929 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6930 pcc->bfd_mach = bfd_mach_ppc64;
6931 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6932 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6933 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6934 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
6935 pcc->l1_dcache_size = 0x8000;
6936 pcc->l1_icache_size = 0x8000;
6937 }
6938
6939 #ifdef CONFIG_SOFTMMU
6940 /*
6941 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6942 * Encoded as array of int_32s in the form:
6943 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6944 * x -> AP encoding
6945 * y -> radix mode supported page size (encoded as a shift)
6946 */
6947 static struct ppc_radix_page_info POWER10_radix_page_info = {
6948 .count = 4,
6949 .entries = {
6950 0x0000000c, /* 4K - enc: 0x0 */
6951 0xa0000010, /* 64K - enc: 0x5 */
6952 0x20000015, /* 2M - enc: 0x1 */
6953 0x4000001e /* 1G - enc: 0x2 */
6954 }
6955 };
6956 #endif /* CONFIG_SOFTMMU */
6957
6958 static void init_proc_POWER10(CPUPPCState *env)
6959 {
6960 /* Common Registers */
6961 init_proc_book3s_common(env);
6962 register_book3s_207_dbg_sprs(env);
6963
6964 /* Common TCG PMU */
6965 init_tcg_pmu_power8(env);
6966
6967 /* POWER8 Specific Registers */
6968 register_book3s_ids_sprs(env);
6969 register_amr_sprs(env);
6970 register_iamr_sprs(env);
6971 register_book3s_purr_sprs(env);
6972 register_power5p_common_sprs(env);
6973 register_power5p_lpar_sprs(env);
6974 register_power5p_ear_sprs(env);
6975 register_power6_common_sprs(env);
6976 register_power6_dbg_sprs(env);
6977 register_power8_tce_address_control_sprs(env);
6978 register_power8_ids_sprs(env);
6979 register_power8_ebb_sprs(env);
6980 register_power8_fscr_sprs(env);
6981 register_power8_pmu_sup_sprs(env);
6982 register_power8_pmu_user_sprs(env);
6983 register_power8_tm_sprs(env);
6984 register_power8_pspb_sprs(env);
6985 register_vtb_sprs(env);
6986 register_power8_ic_sprs(env);
6987 register_power8_book4_sprs(env);
6988 register_power8_rpr_sprs(env);
6989 register_power9_mmu_sprs(env);
6990
6991 /* FIXME: Filter fields properly based on privilege level */
6992 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6993 spr_read_generic, spr_write_generic,
6994 KVM_REG_PPC_PSSCR, 0);
6995
6996 /* env variables */
6997 env->dcache_line_size = 128;
6998 env->icache_line_size = 128;
6999
7000 /* Allocate hardware IRQ controller */
7001 init_excp_POWER10(env);
7002 ppcPOWER9_irq_init(env_archcpu(env));
7003 }
7004
7005 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
7006 {
7007 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
7008 return true;
7009 }
7010 return false;
7011 }
7012
7013 static bool cpu_has_work_POWER10(CPUState *cs)
7014 {
7015 PowerPCCPU *cpu = POWERPC_CPU(cs);
7016 CPUPPCState *env = &cpu->env;
7017
7018 if (cs->halted) {
7019 uint64_t psscr = env->spr[SPR_PSSCR];
7020
7021 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7022 return false;
7023 }
7024
7025 /* If EC is clear, just return true on any pending interrupt */
7026 if (!(psscr & PSSCR_EC)) {
7027 return true;
7028 }
7029 /* External Exception */
7030 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7031 (env->spr[SPR_LPCR] & LPCR_EEE)) {
7032 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
7033 if (heic == 0 || !msr_hv || msr_pr) {
7034 return true;
7035 }
7036 }
7037 /* Decrementer Exception */
7038 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7039 (env->spr[SPR_LPCR] & LPCR_DEE)) {
7040 return true;
7041 }
7042 /* Machine Check or Hypervisor Maintenance Exception */
7043 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
7044 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
7045 return true;
7046 }
7047 /* Privileged Doorbell Exception */
7048 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
7049 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
7050 return true;
7051 }
7052 /* Hypervisor Doorbell Exception */
7053 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
7054 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
7055 return true;
7056 }
7057 /* Hypervisor virtualization exception */
7058 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
7059 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
7060 return true;
7061 }
7062 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7063 return true;
7064 }
7065 return false;
7066 } else {
7067 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7068 }
7069 }
7070
7071 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
7072 {
7073 DeviceClass *dc = DEVICE_CLASS(oc);
7074 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7075 CPUClass *cc = CPU_CLASS(oc);
7076
7077 dc->fw_name = "PowerPC,POWER10";
7078 dc->desc = "POWER10";
7079 pcc->pvr_match = ppc_pvr_match_power10;
7080 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
7081 PCR_COMPAT_3_00;
7082 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
7083 PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7084 pcc->init_proc = init_proc_POWER10;
7085 pcc->check_pow = check_pow_nocheck;
7086 cc->has_work = cpu_has_work_POWER10;
7087 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7088 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7089 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7090 PPC_FLOAT_FRSQRTES |
7091 PPC_FLOAT_STFIWX |
7092 PPC_FLOAT_EXT |
7093 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7094 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7095 PPC_MEM_TLBSYNC |
7096 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7097 PPC_SEGMENT_64B | PPC_SLBI |
7098 PPC_POPCNTB | PPC_POPCNTWD |
7099 PPC_CILDST;
7100 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
7101 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7102 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7103 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
7104 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
7105 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
7106 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
7107 pcc->msr_mask = (1ull << MSR_SF) |
7108 (1ull << MSR_HV) |
7109 (1ull << MSR_TM) |
7110 (1ull << MSR_VR) |
7111 (1ull << MSR_VSX) |
7112 (1ull << MSR_EE) |
7113 (1ull << MSR_PR) |
7114 (1ull << MSR_FP) |
7115 (1ull << MSR_ME) |
7116 (1ull << MSR_FE0) |
7117 (1ull << MSR_SE) |
7118 (1ull << MSR_DE) |
7119 (1ull << MSR_FE1) |
7120 (1ull << MSR_IR) |
7121 (1ull << MSR_DR) |
7122 (1ull << MSR_PMM) |
7123 (1ull << MSR_RI) |
7124 (1ull << MSR_LE);
7125 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
7126 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
7127 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
7128 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
7129 LPCR_DEE | LPCR_OEE))
7130 | LPCR_MER | LPCR_GTSE | LPCR_TC |
7131 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
7132 /* DD2 adds an extra HAIL bit */
7133 pcc->lpcr_mask |= LPCR_HAIL;
7134
7135 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
7136 pcc->mmu_model = POWERPC_MMU_3_00;
7137 #if defined(CONFIG_SOFTMMU)
7138 /* segment page size remain the same */
7139 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7140 pcc->radix_page_info = &POWER10_radix_page_info;
7141 pcc->lrg_decr_bits = 56;
7142 #endif
7143 pcc->excp_model = POWERPC_EXCP_POWER10;
7144 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
7145 pcc->bfd_mach = bfd_mach_ppc64;
7146 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7147 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7148 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7149 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
7150 pcc->l1_dcache_size = 0x8000;
7151 pcc->l1_icache_size = 0x8000;
7152 }
7153
7154 #if !defined(CONFIG_USER_ONLY)
7155 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
7156 {
7157 CPUPPCState *env = &cpu->env;
7158
7159 cpu->vhyp = vhyp;
7160
7161 /*
7162 * With a virtual hypervisor mode we never allow the CPU to go
7163 * hypervisor mode itself
7164 */
7165 env->msr_mask &= ~MSR_HVB;
7166 }
7167
7168 #endif /* !defined(CONFIG_USER_ONLY) */
7169
7170 #endif /* defined(TARGET_PPC64) */
7171
7172 /*****************************************************************************/
7173 /* Generic CPU instantiation routine */
7174 static void init_ppc_proc(PowerPCCPU *cpu)
7175 {
7176 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7177 CPUPPCState *env = &cpu->env;
7178 #if !defined(CONFIG_USER_ONLY)
7179 int i;
7180
7181 env->irq_inputs = NULL;
7182 /* Set all exception vectors to an invalid address */
7183 for (i = 0; i < POWERPC_EXCP_NB; i++) {
7184 env->excp_vectors[i] = (target_ulong)(-1ULL);
7185 }
7186 env->ivor_mask = 0x00000000;
7187 env->ivpr_mask = 0x00000000;
7188 /* Default MMU definitions */
7189 env->nb_BATs = 0;
7190 env->nb_tlb = 0;
7191 env->nb_ways = 0;
7192 env->tlb_type = TLB_NONE;
7193 #endif
7194 /* Register SPR common to all PowerPC implementations */
7195 register_generic_sprs(cpu);
7196
7197 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
7198 (*pcc->init_proc)(env);
7199
7200 #if !defined(CONFIG_USER_ONLY)
7201 ppc_gdb_gen_spr_xml(cpu);
7202 #endif
7203
7204 /* MSR bits & flags consistency checks */
7205 if (env->msr_mask & (1 << 25)) {
7206 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7207 case POWERPC_FLAG_SPE:
7208 case POWERPC_FLAG_VRE:
7209 break;
7210 default:
7211 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7212 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7213 exit(1);
7214 }
7215 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7216 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7217 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7218 exit(1);
7219 }
7220 if (env->msr_mask & (1 << 17)) {
7221 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7222 case POWERPC_FLAG_TGPR:
7223 case POWERPC_FLAG_CE:
7224 break;
7225 default:
7226 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7227 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
7228 exit(1);
7229 }
7230 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7231 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7232 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
7233 exit(1);
7234 }
7235 if (env->msr_mask & (1 << 10)) {
7236 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7237 POWERPC_FLAG_UBLE)) {
7238 case POWERPC_FLAG_SE:
7239 case POWERPC_FLAG_DWE:
7240 case POWERPC_FLAG_UBLE:
7241 break;
7242 default:
7243 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7244 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
7245 "POWERPC_FLAG_UBLE\n");
7246 exit(1);
7247 }
7248 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7249 POWERPC_FLAG_UBLE)) {
7250 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7251 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
7252 "POWERPC_FLAG_UBLE\n");
7253 exit(1);
7254 }
7255 if (env->msr_mask & (1 << 9)) {
7256 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7257 case POWERPC_FLAG_BE:
7258 case POWERPC_FLAG_DE:
7259 break;
7260 default:
7261 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7262 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
7263 exit(1);
7264 }
7265 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7266 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7267 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
7268 exit(1);
7269 }
7270 if (env->msr_mask & (1 << 2)) {
7271 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7272 case POWERPC_FLAG_PX:
7273 case POWERPC_FLAG_PMM:
7274 break;
7275 default:
7276 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7277 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
7278 exit(1);
7279 }
7280 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7281 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7282 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
7283 exit(1);
7284 }
7285 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) {
7286 fprintf(stderr, "PowerPC flags inconsistency\n"
7287 "Should define the time-base and decrementer clock source\n");
7288 exit(1);
7289 }
7290 /* Allocate TLBs buffer when needed */
7291 #if !defined(CONFIG_USER_ONLY)
7292 if (env->nb_tlb != 0) {
7293 int nb_tlb = env->nb_tlb;
7294 if (env->id_tlbs != 0) {
7295 nb_tlb *= 2;
7296 }
7297 switch (env->tlb_type) {
7298 case TLB_6XX:
7299 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
7300 break;
7301 case TLB_EMB:
7302 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
7303 break;
7304 case TLB_MAS:
7305 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
7306 break;
7307 }
7308 /* Pre-compute some useful values */
7309 env->tlb_per_way = env->nb_tlb / env->nb_ways;
7310 }
7311 if (env->irq_inputs == NULL) {
7312 warn_report("no internal IRQ controller registered."
7313 " Attempt QEMU to crash very soon !");
7314 }
7315 #endif
7316 if (env->check_pow == NULL) {
7317 warn_report("no power management check handler registered."
7318 " Attempt QEMU to crash very soon !");
7319 }
7320 }
7321
7322
7323 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
7324 {
7325 CPUState *cs = CPU(dev);
7326 PowerPCCPU *cpu = POWERPC_CPU(dev);
7327 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7328 Error *local_err = NULL;
7329
7330 cpu_exec_realizefn(cs, &local_err);
7331 if (local_err != NULL) {
7332 error_propagate(errp, local_err);
7333 return;
7334 }
7335 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
7336 cpu->vcpu_id = cs->cpu_index;
7337 }
7338
7339 if (tcg_enabled()) {
7340 if (ppc_fixup_cpu(cpu) != 0) {
7341 error_setg(errp, "Unable to emulate selected CPU with TCG");
7342 goto unrealize;
7343 }
7344 }
7345
7346 create_ppc_opcodes(cpu, &local_err);
7347 if (local_err != NULL) {
7348 error_propagate(errp, local_err);
7349 goto unrealize;
7350 }
7351 init_ppc_proc(cpu);
7352
7353 ppc_gdb_init(cs, pcc);
7354 qemu_init_vcpu(cs);
7355
7356 pcc->parent_realize(dev, errp);
7357
7358 return;
7359
7360 unrealize:
7361 cpu_exec_unrealizefn(cs);
7362 }
7363
7364 static void ppc_cpu_unrealize(DeviceState *dev)
7365 {
7366 PowerPCCPU *cpu = POWERPC_CPU(dev);
7367 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7368
7369 pcc->parent_unrealize(dev);
7370
7371 cpu_remove_sync(CPU(cpu));
7372
7373 destroy_ppc_opcodes(cpu);
7374 }
7375
7376 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
7377 {
7378 ObjectClass *oc = (ObjectClass *)a;
7379 uint32_t pvr = *(uint32_t *)b;
7380 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
7381
7382 /* -cpu host does a PVR lookup during construction */
7383 if (unlikely(strcmp(object_class_get_name(oc),
7384 TYPE_HOST_POWERPC_CPU) == 0)) {
7385 return -1;
7386 }
7387
7388 return pcc->pvr == pvr ? 0 : -1;
7389 }
7390
7391 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
7392 {
7393 GSList *list, *item;
7394 PowerPCCPUClass *pcc = NULL;
7395
7396 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7397 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
7398 if (item != NULL) {
7399 pcc = POWERPC_CPU_CLASS(item->data);
7400 }
7401 g_slist_free(list);
7402
7403 return pcc;
7404 }
7405
7406 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
7407 {
7408 ObjectClass *oc = (ObjectClass *)a;
7409 uint32_t pvr = *(uint32_t *)b;
7410 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
7411
7412 /* -cpu host does a PVR lookup during construction */
7413 if (unlikely(strcmp(object_class_get_name(oc),
7414 TYPE_HOST_POWERPC_CPU) == 0)) {
7415 return -1;
7416 }
7417
7418 if (pcc->pvr_match(pcc, pvr)) {
7419 return 0;
7420 }
7421
7422 return -1;
7423 }
7424
7425 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
7426 {
7427 GSList *list, *item;
7428 PowerPCCPUClass *pcc = NULL;
7429
7430 list = object_class_get_list(TYPE_POWERPC_CPU, true);
7431 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
7432 if (item != NULL) {
7433 pcc = POWERPC_CPU_CLASS(item->data);
7434 }
7435 g_slist_free(list);
7436
7437 return pcc;
7438 }
7439
7440 static const char *ppc_cpu_lookup_alias(const char *alias)
7441 {
7442 int ai;
7443
7444 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
7445 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
7446 return ppc_cpu_aliases[ai].model;
7447 }
7448 }
7449
7450 return NULL;
7451 }
7452
7453 static ObjectClass *ppc_cpu_class_by_name(const char *name)
7454 {
7455 char *cpu_model, *typename;
7456 ObjectClass *oc;
7457 const char *p;
7458 unsigned long pvr;
7459
7460 /*
7461 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
7462 * 0x prefix if present)
7463 */
7464 if (!qemu_strtoul(name, &p, 16, &pvr)) {
7465 int len = p - name;
7466 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
7467 if ((len == 8) && (*p == '\0')) {
7468 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
7469 }
7470 }
7471
7472 cpu_model = g_ascii_strdown(name, -1);
7473 p = ppc_cpu_lookup_alias(cpu_model);
7474 if (p) {
7475 g_free(cpu_model);
7476 cpu_model = g_strdup(p);
7477 }
7478
7479 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
7480 oc = object_class_by_name(typename);
7481 g_free(typename);
7482 g_free(cpu_model);
7483
7484 return oc;
7485 }
7486
7487 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
7488 {
7489 ObjectClass *oc = OBJECT_CLASS(pcc);
7490
7491 while (oc && !object_class_is_abstract(oc)) {
7492 oc = object_class_get_parent(oc);
7493 }
7494 assert(oc);
7495
7496 return POWERPC_CPU_CLASS(oc);
7497 }
7498
7499 /* Sort by PVR, ordering special case "host" last. */
7500 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
7501 {
7502 ObjectClass *oc_a = (ObjectClass *)a;
7503 ObjectClass *oc_b = (ObjectClass *)b;
7504 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
7505 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
7506 const char *name_a = object_class_get_name(oc_a);
7507 const char *name_b = object_class_get_name(oc_b);
7508
7509 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
7510 return 1;
7511 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
7512 return -1;
7513 } else {
7514 /* Avoid an integer overflow during subtraction */
7515 if (pcc_a->pvr < pcc_b->pvr) {
7516 return -1;
7517 } else if (pcc_a->pvr > pcc_b->pvr) {
7518 return 1;
7519 } else {
7520 return 0;
7521 }
7522 }
7523 }
7524
7525 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
7526 {
7527 ObjectClass *oc = data;
7528 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7529 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
7530 const char *typename = object_class_get_name(oc);
7531 char *name;
7532 int i;
7533
7534 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
7535 return;
7536 }
7537
7538 name = g_strndup(typename,
7539 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
7540 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
7541 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7542 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7543 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
7544
7545 if (alias_oc != oc) {
7546 continue;
7547 }
7548 /*
7549 * If running with KVM, we might update the family alias later, so
7550 * avoid printing the wrong alias here and use "preferred" instead
7551 */
7552 if (strcmp(alias->alias, family->desc) == 0) {
7553 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
7554 alias->alias, family->desc);
7555 } else {
7556 qemu_printf("PowerPC %-16s (alias for %s)\n",
7557 alias->alias, name);
7558 }
7559 }
7560 g_free(name);
7561 }
7562
7563 void ppc_cpu_list(void)
7564 {
7565 GSList *list;
7566
7567 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7568 list = g_slist_sort(list, ppc_cpu_list_compare);
7569 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
7570 g_slist_free(list);
7571
7572 #ifdef CONFIG_KVM
7573 qemu_printf("\n");
7574 qemu_printf("PowerPC %s\n", "host");
7575 #endif
7576 }
7577
7578 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
7579 {
7580 ObjectClass *oc = data;
7581 CpuDefinitionInfoList **first = user_data;
7582 const char *typename;
7583 CpuDefinitionInfo *info;
7584
7585 typename = object_class_get_name(oc);
7586 info = g_malloc0(sizeof(*info));
7587 info->name = g_strndup(typename,
7588 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
7589
7590 QAPI_LIST_PREPEND(*first, info);
7591 }
7592
7593 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
7594 {
7595 CpuDefinitionInfoList *cpu_list = NULL;
7596 GSList *list;
7597 int i;
7598
7599 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7600 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
7601 g_slist_free(list);
7602
7603 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7604 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7605 ObjectClass *oc;
7606 CpuDefinitionInfo *info;
7607
7608 oc = ppc_cpu_class_by_name(alias->model);
7609 if (oc == NULL) {
7610 continue;
7611 }
7612
7613 info = g_malloc0(sizeof(*info));
7614 info->name = g_strdup(alias->alias);
7615 info->q_typename = g_strdup(object_class_get_name(oc));
7616
7617 QAPI_LIST_PREPEND(cpu_list, info);
7618 }
7619
7620 return cpu_list;
7621 }
7622
7623 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
7624 {
7625 PowerPCCPU *cpu = POWERPC_CPU(cs);
7626
7627 cpu->env.nip = value;
7628 }
7629
7630 static bool ppc_cpu_has_work(CPUState *cs)
7631 {
7632 PowerPCCPU *cpu = POWERPC_CPU(cs);
7633 CPUPPCState *env = &cpu->env;
7634
7635 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7636 }
7637
7638 static void ppc_cpu_reset(DeviceState *dev)
7639 {
7640 CPUState *s = CPU(dev);
7641 PowerPCCPU *cpu = POWERPC_CPU(s);
7642 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7643 CPUPPCState *env = &cpu->env;
7644 target_ulong msr;
7645 int i;
7646
7647 pcc->parent_reset(dev);
7648
7649 msr = (target_ulong)0;
7650 msr |= (target_ulong)MSR_HVB;
7651 msr |= (target_ulong)1 << MSR_EP;
7652 #if defined(DO_SINGLE_STEP) && 0
7653 /* Single step trace mode */
7654 msr |= (target_ulong)1 << MSR_SE;
7655 msr |= (target_ulong)1 << MSR_BE;
7656 #endif
7657 #if defined(CONFIG_USER_ONLY)
7658 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
7659 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
7660 msr |= (target_ulong)1 << MSR_FE1;
7661 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
7662 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
7663 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
7664 msr |= (target_ulong)1 << MSR_PR;
7665 #if defined(TARGET_PPC64)
7666 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
7667 #endif
7668 #if !defined(TARGET_WORDS_BIGENDIAN)
7669 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
7670 if (!((env->msr_mask >> MSR_LE) & 1)) {
7671 fprintf(stderr, "Selected CPU does not support little-endian.\n");
7672 exit(1);
7673 }
7674 #endif
7675 #endif
7676
7677 #if defined(TARGET_PPC64)
7678 if (mmu_is_64bit(env->mmu_model)) {
7679 msr |= (1ULL << MSR_SF);
7680 }
7681 #endif
7682
7683 hreg_store_msr(env, msr, 1);
7684
7685 #if !defined(CONFIG_USER_ONLY)
7686 env->nip = env->hreset_vector | env->excp_prefix;
7687 #if defined(CONFIG_TCG)
7688 if (env->mmu_model != POWERPC_MMU_REAL) {
7689 ppc_tlb_invalidate_all(env);
7690 }
7691 #endif /* CONFIG_TCG */
7692 #endif
7693
7694 pmu_update_summaries(env);
7695 hreg_compute_hflags(env);
7696 env->reserve_addr = (target_ulong)-1ULL;
7697 /* Be sure no exception or interrupt is pending */
7698 env->pending_interrupts = 0;
7699 s->exception_index = POWERPC_EXCP_NONE;
7700 env->error_code = 0;
7701 ppc_irq_reset(cpu);
7702
7703 /* tininess for underflow is detected before rounding */
7704 set_float_detect_tininess(float_tininess_before_rounding,
7705 &env->fp_status);
7706
7707 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
7708 ppc_spr_t *spr = &env->spr_cb[i];
7709
7710 if (!spr->name) {
7711 continue;
7712 }
7713 env->spr[i] = spr->default_value;
7714 }
7715 }
7716
7717 #ifndef CONFIG_USER_ONLY
7718
7719 static bool ppc_cpu_is_big_endian(CPUState *cs)
7720 {
7721 PowerPCCPU *cpu = POWERPC_CPU(cs);
7722 CPUPPCState *env = &cpu->env;
7723
7724 cpu_synchronize_state(cs);
7725
7726 return !msr_le;
7727 }
7728
7729 #ifdef CONFIG_TCG
7730 static void ppc_cpu_exec_enter(CPUState *cs)
7731 {
7732 PowerPCCPU *cpu = POWERPC_CPU(cs);
7733
7734 if (cpu->vhyp) {
7735 PPCVirtualHypervisorClass *vhc =
7736 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7737 vhc->cpu_exec_enter(cpu->vhyp, cpu);
7738 }
7739 }
7740
7741 static void ppc_cpu_exec_exit(CPUState *cs)
7742 {
7743 PowerPCCPU *cpu = POWERPC_CPU(cs);
7744
7745 if (cpu->vhyp) {
7746 PPCVirtualHypervisorClass *vhc =
7747 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7748 vhc->cpu_exec_exit(cpu->vhyp, cpu);
7749 }
7750 }
7751 #endif /* CONFIG_TCG */
7752
7753 #endif /* !CONFIG_USER_ONLY */
7754
7755 static void ppc_cpu_instance_init(Object *obj)
7756 {
7757 PowerPCCPU *cpu = POWERPC_CPU(obj);
7758 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7759 CPUPPCState *env = &cpu->env;
7760
7761 cpu_set_cpustate_pointers(cpu);
7762 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
7763
7764 env->msr_mask = pcc->msr_mask;
7765 env->mmu_model = pcc->mmu_model;
7766 env->excp_model = pcc->excp_model;
7767 env->bus_model = pcc->bus_model;
7768 env->insns_flags = pcc->insns_flags;
7769 env->insns_flags2 = pcc->insns_flags2;
7770 env->flags = pcc->flags;
7771 env->bfd_mach = pcc->bfd_mach;
7772 env->check_pow = pcc->check_pow;
7773
7774 /*
7775 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
7776 * msr_mask. The mask can later be cleared by PAPR mode but the hv
7777 * mode support will remain, thus enforcing that we cannot use
7778 * priv. instructions in guest in PAPR mode. For 970 we currently
7779 * simply don't set HV in msr_mask thus simulating an "Apple mode"
7780 * 970. If we ever want to support 970 HV mode, we'll have to add
7781 * a processor attribute of some sort.
7782 */
7783 #if !defined(CONFIG_USER_ONLY)
7784 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
7785 #endif
7786
7787 ppc_hash64_init(cpu);
7788 }
7789
7790 static void ppc_cpu_instance_finalize(Object *obj)
7791 {
7792 PowerPCCPU *cpu = POWERPC_CPU(obj);
7793
7794 ppc_hash64_finalize(cpu);
7795 }
7796
7797 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
7798 {
7799 return pcc->pvr == pvr;
7800 }
7801
7802 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
7803 {
7804 PowerPCCPU *cpu = POWERPC_CPU(cs);
7805 CPUPPCState *env = &cpu->env;
7806
7807 if ((env->hflags >> MSR_LE) & 1) {
7808 info->endian = BFD_ENDIAN_LITTLE;
7809 }
7810 info->mach = env->bfd_mach;
7811 if (!env->bfd_mach) {
7812 #ifdef TARGET_PPC64
7813 info->mach = bfd_mach_ppc64;
7814 #else
7815 info->mach = bfd_mach_ppc;
7816 #endif
7817 }
7818 info->disassembler_options = (char *)"any";
7819 info->print_insn = print_insn_ppc;
7820
7821 info->cap_arch = CS_ARCH_PPC;
7822 #ifdef TARGET_PPC64
7823 info->cap_mode = CS_MODE_64;
7824 #endif
7825 }
7826
7827 static Property ppc_cpu_properties[] = {
7828 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
7829 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
7830 false),
7831 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
7832 false),
7833 DEFINE_PROP_END_OF_LIST(),
7834 };
7835
7836 #ifndef CONFIG_USER_ONLY
7837 #include "hw/core/sysemu-cpu-ops.h"
7838
7839 static const struct SysemuCPUOps ppc_sysemu_ops = {
7840 .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
7841 .write_elf32_note = ppc32_cpu_write_elf32_note,
7842 .write_elf64_note = ppc64_cpu_write_elf64_note,
7843 .virtio_is_big_endian = ppc_cpu_is_big_endian,
7844 .legacy_vmsd = &vmstate_ppc_cpu,
7845 };
7846 #endif
7847
7848 #ifdef CONFIG_TCG
7849 #include "hw/core/tcg-cpu-ops.h"
7850
7851 static const struct TCGCPUOps ppc_tcg_ops = {
7852 .initialize = ppc_translate_init,
7853
7854 #ifdef CONFIG_USER_ONLY
7855 .record_sigsegv = ppc_cpu_record_sigsegv,
7856 #else
7857 .tlb_fill = ppc_cpu_tlb_fill,
7858 .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
7859 .do_interrupt = ppc_cpu_do_interrupt,
7860 .cpu_exec_enter = ppc_cpu_exec_enter,
7861 .cpu_exec_exit = ppc_cpu_exec_exit,
7862 .do_unaligned_access = ppc_cpu_do_unaligned_access,
7863 #endif /* !CONFIG_USER_ONLY */
7864 };
7865 #endif /* CONFIG_TCG */
7866
7867 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
7868 {
7869 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7870 CPUClass *cc = CPU_CLASS(oc);
7871 DeviceClass *dc = DEVICE_CLASS(oc);
7872
7873 device_class_set_parent_realize(dc, ppc_cpu_realize,
7874 &pcc->parent_realize);
7875 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
7876 &pcc->parent_unrealize);
7877 pcc->pvr_match = ppc_pvr_match_default;
7878 device_class_set_props(dc, ppc_cpu_properties);
7879
7880 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
7881
7882 cc->class_by_name = ppc_cpu_class_by_name;
7883 cc->has_work = ppc_cpu_has_work;
7884 cc->dump_state = ppc_cpu_dump_state;
7885 cc->set_pc = ppc_cpu_set_pc;
7886 cc->gdb_read_register = ppc_cpu_gdb_read_register;
7887 cc->gdb_write_register = ppc_cpu_gdb_write_register;
7888 #ifndef CONFIG_USER_ONLY
7889 cc->sysemu_ops = &ppc_sysemu_ops;
7890 #endif
7891
7892 cc->gdb_num_core_regs = 71;
7893 #ifndef CONFIG_USER_ONLY
7894 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
7895 #endif
7896 #ifdef USE_APPLE_GDB
7897 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
7898 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
7899 cc->gdb_num_core_regs = 71 + 32;
7900 #endif
7901
7902 cc->gdb_arch_name = ppc_gdb_arch_name;
7903 #if defined(TARGET_PPC64)
7904 cc->gdb_core_xml_file = "power64-core.xml";
7905 #else
7906 cc->gdb_core_xml_file = "power-core.xml";
7907 #endif
7908 cc->disas_set_info = ppc_disas_set_info;
7909
7910 dc->fw_name = "PowerPC,UNKNOWN";
7911
7912 #ifdef CONFIG_TCG
7913 cc->tcg_ops = &ppc_tcg_ops;
7914 #endif /* CONFIG_TCG */
7915 }
7916
7917 static const TypeInfo ppc_cpu_type_info = {
7918 .name = TYPE_POWERPC_CPU,
7919 .parent = TYPE_CPU,
7920 .instance_size = sizeof(PowerPCCPU),
7921 .instance_align = __alignof__(PowerPCCPU),
7922 .instance_init = ppc_cpu_instance_init,
7923 .instance_finalize = ppc_cpu_instance_finalize,
7924 .abstract = true,
7925 .class_size = sizeof(PowerPCCPUClass),
7926 .class_init = ppc_cpu_class_init,
7927 };
7928
7929 #ifndef CONFIG_USER_ONLY
7930 static const TypeInfo ppc_vhyp_type_info = {
7931 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
7932 .parent = TYPE_INTERFACE,
7933 .class_size = sizeof(PPCVirtualHypervisorClass),
7934 };
7935 #endif
7936
7937 static void ppc_cpu_register_types(void)
7938 {
7939 type_register_static(&ppc_cpu_type_info);
7940 #ifndef CONFIG_USER_ONLY
7941 type_register_static(&ppc_vhyp_type_info);
7942 #endif
7943 }
7944
7945 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
7946 {
7947 #define RGPL 4
7948 #define RFPL 4
7949
7950 PowerPCCPU *cpu = POWERPC_CPU(cs);
7951 CPUPPCState *env = &cpu->env;
7952 int i;
7953
7954 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7955 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7956 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7957 cs->cpu_index);
7958 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7959 "%08x iidx %d didx %d\n",
7960 env->msr, env->spr[SPR_HID0], env->hflags,
7961 cpu_mmu_index(env, true), cpu_mmu_index(env, false));
7962 #if !defined(NO_TIMER_DUMP)
7963 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7964 #if !defined(CONFIG_USER_ONLY)
7965 " DECR " TARGET_FMT_lu
7966 #endif
7967 "\n",
7968 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7969 #if !defined(CONFIG_USER_ONLY)
7970 , cpu_ppc_load_decr(env)
7971 #endif
7972 );
7973 #endif
7974 for (i = 0; i < 32; i++) {
7975 if ((i & (RGPL - 1)) == 0) {
7976 qemu_fprintf(f, "GPR%02d", i);
7977 }
7978 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7979 if ((i & (RGPL - 1)) == (RGPL - 1)) {
7980 qemu_fprintf(f, "\n");
7981 }
7982 }
7983 qemu_fprintf(f, "CR ");
7984 for (i = 0; i < 8; i++)
7985 qemu_fprintf(f, "%01x", env->crf[i]);
7986 qemu_fprintf(f, " [");
7987 for (i = 0; i < 8; i++) {
7988 char a = '-';
7989 if (env->crf[i] & 0x08) {
7990 a = 'L';
7991 } else if (env->crf[i] & 0x04) {
7992 a = 'G';
7993 } else if (env->crf[i] & 0x02) {
7994 a = 'E';
7995 }
7996 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7997 }
7998 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7999 env->reserve_addr);
8000
8001 if (flags & CPU_DUMP_FPU) {
8002 for (i = 0; i < 32; i++) {
8003 if ((i & (RFPL - 1)) == 0) {
8004 qemu_fprintf(f, "FPR%02d", i);
8005 }
8006 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
8007 if ((i & (RFPL - 1)) == (RFPL - 1)) {
8008 qemu_fprintf(f, "\n");
8009 }
8010 }
8011 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
8012 }
8013
8014 #if !defined(CONFIG_USER_ONLY)
8015 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
8016 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
8017 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
8018 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
8019
8020 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
8021 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
8022 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
8023 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
8024
8025 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
8026 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
8027 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
8028 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
8029
8030 switch (env->excp_model) {
8031 #if defined(TARGET_PPC64)
8032 case POWERPC_EXCP_POWER7:
8033 case POWERPC_EXCP_POWER8:
8034 case POWERPC_EXCP_POWER9:
8035 case POWERPC_EXCP_POWER10:
8036 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
8037 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
8038 break;
8039 #endif
8040 case POWERPC_EXCP_BOOKE:
8041 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
8042 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
8043 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
8044 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
8045
8046 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
8047 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
8048 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
8049 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
8050
8051 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
8052 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
8053 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
8054 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
8055
8056 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
8057 " EPR " TARGET_FMT_lx "\n",
8058 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
8059 env->spr[SPR_BOOKE_EPR]);
8060
8061 /* FSL-specific */
8062 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
8063 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
8064 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
8065 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
8066
8067 /*
8068 * IVORs are left out as they are large and do not change often --
8069 * they can be read with "p $ivor0", "p $ivor1", etc.
8070 */
8071 break;
8072 case POWERPC_EXCP_40x:
8073 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
8074 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
8075 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
8076 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
8077
8078 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx
8079 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
8080 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2],
8081 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]);
8082 break;
8083 default:
8084 break;
8085 }
8086
8087 #if defined(TARGET_PPC64)
8088 if (env->flags & POWERPC_FLAG_CFAR) {
8089 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
8090 }
8091 #endif
8092
8093 if (env->spr_cb[SPR_LPCR].name) {
8094 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
8095 }
8096
8097 switch (env->mmu_model) {
8098 case POWERPC_MMU_32B:
8099 case POWERPC_MMU_SOFT_6xx:
8100 #if defined(TARGET_PPC64)
8101 case POWERPC_MMU_64B:
8102 case POWERPC_MMU_2_03:
8103 case POWERPC_MMU_2_06:
8104 case POWERPC_MMU_2_07:
8105 case POWERPC_MMU_3_00:
8106 #endif
8107 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
8108 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
8109 }
8110 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
8111 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
8112 }
8113 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
8114 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
8115 break;
8116 case POWERPC_MMU_BOOKE206:
8117 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
8118 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
8119 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
8120 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
8121
8122 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
8123 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
8124 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
8125 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
8126
8127 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
8128 " TLB1CFG " TARGET_FMT_lx "\n",
8129 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
8130 env->spr[SPR_BOOKE_TLB1CFG]);
8131 break;
8132 default:
8133 break;
8134 }
8135 #endif
8136
8137 #undef RGPL
8138 #undef RFPL
8139 }
8140 type_init(ppc_cpu_register_types)
QEmu