hw/acpi_ich9.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 /*
  19  *  Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
  20  *                     VA Linux Systems Japan K.K.
  21  *  Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
  22  *
  23  *  This is based on acpi.c.
  24  */
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "qemu-timer.h"
  29 #include "sysemu.h"
  30 #include "acpi.h"
  31 #include "kvm.h"
  32 #include "exec-memory.h"
  33
  34 #include "ich9.h"
  35
  36 //#define DEBUG
  37
  38 #ifdef DEBUG
  39 #define ICH9_DEBUG(fmt, ...) \
  40 do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
  41 #else
  42 #define ICH9_DEBUG(fmt, ...)    do { } while (0)
  43 #endif
  44
  45 static void pm_update_sci(ICH9LPCPMRegs *pm)
  46 {
  47     int sci_level, pm1a_sts;
  48
  49     pm1a_sts = acpi_pm1_evt_get_sts(&pm->acpi_regs);
  50
  51     sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) &
  52                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
  53                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
  54                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
  55                    ACPI_BITMASK_TIMER_ENABLE)) != 0);
  56     qemu_set_irq(pm->irq, sci_level);
  57
  58     /* schedule a timer interruption if needed */
  59     acpi_pm_tmr_update(&pm->acpi_regs,
  60                        (pm->acpi_regs.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
  61                        !(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
  62 }
  63
  64 static void ich9_pm_update_sci_fn(ACPIREGS *regs)
  65 {
  66     ICH9LPCPMRegs *pm = container_of(regs, ICH9LPCPMRegs, acpi_regs);
  67     pm_update_sci(pm);
  68 }
  69
  70 static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width)
  71 {
  72     ICH9LPCPMRegs *pm = opaque;
  73     return acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
  74 }
  75
  76 static void ich9_gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
  77                             unsigned width)
  78 {
  79     ICH9LPCPMRegs *pm = opaque;
  80     acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
  81 }
  82
  83 static const MemoryRegionOps ich9_gpe_ops = {
  84     .read = ich9_gpe_readb,
  85     .write = ich9_gpe_writeb,
  86     .valid.min_access_size = 1,
  87     .valid.max_access_size = 4,
  88     .impl.min_access_size = 1,
  89     .impl.max_access_size = 1,
  90     .endianness = DEVICE_LITTLE_ENDIAN,
  91 };
  92
  93 static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width)
  94 {
  95     ICH9LPCPMRegs *pm = opaque;
  96     switch (addr) {
  97     case 0:
  98         return pm->smi_en;
  99     case 4:
 100         return pm->smi_sts;
 101     default:
 102         return 0;
 103     }
 104 }
 105
 106 static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val,
 107                             unsigned width)
 108 {
 109     ICH9LPCPMRegs *pm = opaque;
 110     switch (addr) {
 111     case 0:
 112         pm->smi_en = val;
 113         break;
 114     }
 115 }
 116
 117 static const MemoryRegionOps ich9_smi_ops = {
 118     .read = ich9_smi_readl,
 119     .write = ich9_smi_writel,
 120     .valid.min_access_size = 4,
 121     .valid.max_access_size = 4,
 122     .endianness = DEVICE_LITTLE_ENDIAN,
 123 };
 124
 125 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base)
 126 {
 127     ICH9_DEBUG("to 0x%x\n", pm_io_base);
 128
 129     assert((pm_io_base & ICH9_PMIO_MASK) == 0);
 130
 131     pm->pm_io_base = pm_io_base;
 132     memory_region_transaction_begin();
 133     memory_region_set_enabled(&pm->io, pm->pm_io_base != 0);
 134     memory_region_set_address(&pm->io, pm->pm_io_base);
 135     memory_region_transaction_commit();
 136 }
 137
 138 static int ich9_pm_post_load(void *opaque, int version_id)
 139 {
 140     ICH9LPCPMRegs *pm = opaque;
 141     uint32_t pm_io_base = pm->pm_io_base;
 142     pm->pm_io_base = 0;
 143     ich9_pm_iospace_update(pm, pm_io_base);
 144     return 0;
 145 }
 146
 147 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 148  {                                                                   \
 149      .name       = (stringify(_field)),                              \
 150      .version_id = 0,                                                \
 151      .num        = ICH9_PMIO_GPE0_LEN,                               \
 152      .info       = &vmstate_info_uint8,                              \
 153      .size       = sizeof(uint8_t),                                  \
 154      .flags      = VMS_ARRAY | VMS_POINTER,                          \
 155      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 156  }
 157
 158 const VMStateDescription vmstate_ich9_pm = {
 159     .name = "ich9_pm",
 160     .version_id = 1,
 161     .minimum_version_id = 1,
 162     .minimum_version_id_old = 1,
 163     .post_load = ich9_pm_post_load,
 164     .fields = (VMStateField[]) {
 165         VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
 166         VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
 167         VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
 168         VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9LPCPMRegs),
 169         VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
 170         VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
 171         VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
 172         VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
 173         VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
 174         VMSTATE_END_OF_LIST()
 175     }
 176 };
 177
 178 static void pm_reset(void *opaque)
 179 {
 180     ICH9LPCPMRegs *pm = opaque;
 181     ich9_pm_iospace_update(pm, 0);
 182
 183     acpi_pm1_evt_reset(&pm->acpi_regs);
 184     acpi_pm1_cnt_reset(&pm->acpi_regs);
 185     acpi_pm_tmr_reset(&pm->acpi_regs);
 186     acpi_gpe_reset(&pm->acpi_regs);
 187
 188     if (kvm_enabled()) {
 189         /* Mark SMM as already inited to prevent SMM from running. KVM does not
 190          * support SMM mode. */
 191         pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
 192     }
 193
 194     pm_update_sci(pm);
 195 }
 196
 197 static void pm_powerdown_req(Notifier *n, void *opaque)
 198 {
 199     ICH9LPCPMRegs *pm = container_of(n, ICH9LPCPMRegs, powerdown_notifier);
 200
 201     acpi_pm1_evt_power_down(&pm->acpi_regs);
 202 }
 203
 204 void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
 205 {
 206     memory_region_init(&pm->io, "ich9-pm", ICH9_PMIO_SIZE);
 207     memory_region_set_enabled(&pm->io, false);
 208     memory_region_add_subregion(get_system_io(), 0, &pm->io);
 209
 210     acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
 211     acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io);
 212     acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io);
 213
 214     acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
 215     memory_region_init_io(&pm->io_gpe, &ich9_gpe_ops, pm, "apci-gpe0",
 216                           ICH9_PMIO_GPE0_LEN);
 217     memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe);
 218
 219     memory_region_init_io(&pm->io_smi, &ich9_smi_ops, pm, "apci-smi",
 220                           8);
 221     memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi);
 222
 223     pm->irq = sci_irq;
 224     qemu_register_reset(pm_reset, pm);
 225     pm->powerdown_notifier.notify = pm_powerdown_req;
 226     qemu_register_powerdown_notifier(&pm->powerdown_notifier);
 227 }