4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 # define PCI_DPRINTF(format, ...) printf(format, __VA_ARGS__)
34 # define PCI_DPRINTF(format, ...) do { } while (0)
41 pci_set_irq_fn set_irq
;
42 pci_map_irq_fn map_irq
;
43 uint32_t config_reg
; /* XXX: suppress */
45 PCIDevice
*devices
[256];
46 PCIDevice
*parent_dev
;
48 /* The bus IRQ state is the logical OR of the connected devices.
49 Keep a count of the number of devices with raised IRQs. */
54 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
56 static struct BusInfo pci_bus_info
= {
58 .size
= sizeof(PCIBus
),
59 .print_dev
= pcibus_dev_print
,
60 .props
= (Property
[]) {
61 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
62 DEFINE_PROP_END_OF_LIST()
66 static void pci_update_mappings(PCIDevice
*d
);
67 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
69 target_phys_addr_t pci_mem_base
;
70 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
71 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
72 static PCIBus
*first_bus
;
74 static const VMStateDescription vmstate_pcibus
= {
77 .minimum_version_id
= 1,
78 .minimum_version_id_old
= 1,
79 .fields
= (VMStateField
[]) {
80 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
81 VMSTATE_INT32_VARRAY(irq_count
, PCIBus
, nirq
),
86 static void pci_bus_reset(void *opaque
)
91 for (i
= 0; i
< bus
->nirq
; i
++) {
92 bus
->irq_count
[i
] = 0;
94 for (i
= 0; i
< 256; i
++) {
96 memset(bus
->devices
[i
]->irq_state
, 0,
97 sizeof(bus
->devices
[i
]->irq_state
));
101 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
102 const char *name
, int devfn_min
)
106 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, parent
, name
);
107 bus
->devfn_min
= devfn_min
;
108 bus
->next
= first_bus
;
110 vmstate_register(nbus
++, &vmstate_pcibus
, bus
);
111 qemu_register_reset(pci_bus_reset
, bus
);
114 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
, int devfn_min
)
118 bus
= qemu_mallocz(sizeof(*bus
));
119 bus
->qbus
.qdev_allocated
= 1;
120 pci_bus_new_inplace(bus
, parent
, name
, devfn_min
);
124 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
125 void *irq_opaque
, int nirq
)
127 bus
->set_irq
= set_irq
;
128 bus
->map_irq
= map_irq
;
129 bus
->irq_opaque
= irq_opaque
;
131 bus
->irq_count
= qemu_mallocz(nirq
* sizeof(bus
->irq_count
[0]));
134 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
135 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
136 void *irq_opaque
, int devfn_min
, int nirq
)
140 bus
= pci_bus_new(parent
, name
, devfn_min
);
141 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
145 static void pci_register_secondary_bus(PCIBus
*bus
,
147 pci_map_irq_fn map_irq
,
150 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, &dev
->qdev
, name
);
151 bus
->map_irq
= map_irq
;
152 bus
->parent_dev
= dev
;
153 bus
->next
= dev
->bus
->next
;
154 dev
->bus
->next
= bus
;
157 int pci_bus_num(PCIBus
*s
)
162 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
164 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
165 uint8_t config
[size
];
168 qemu_get_buffer(f
, config
, size
);
169 for (i
= 0; i
< size
; ++i
)
170 if ((config
[i
] ^ s
->config
[i
]) & s
->cmask
[i
] & ~s
->wmask
[i
])
172 memcpy(s
->config
, config
, size
);
174 pci_update_mappings(s
);
179 /* just put buffer */
180 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
182 const uint8_t *v
= pv
;
183 qemu_put_buffer(f
, v
, size
);
186 static VMStateInfo vmstate_info_pci_config
= {
187 .name
= "pci config",
188 .get
= get_pci_config_device
,
189 .put
= put_pci_config_device
,
192 const VMStateDescription vmstate_pci_device
= {
195 .minimum_version_id
= 1,
196 .minimum_version_id_old
= 1,
197 .fields
= (VMStateField
[]) {
198 VMSTATE_INT32_LE(version_id
, PCIDevice
),
199 VMSTATE_SINGLE(config
, PCIDevice
, 0, vmstate_info_pci_config
,
200 typeof_field(PCIDevice
,config
)),
201 VMSTATE_INT32_ARRAY_V(irq_state
, PCIDevice
, 4, 2),
202 VMSTATE_END_OF_LIST()
206 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
208 vmstate_save_state(f
, &vmstate_pci_device
, s
);
211 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
213 return vmstate_load_state(f
, &vmstate_pci_device
, s
, s
->version_id
);
216 static int pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
220 id
= (void*)(&pci_dev
->config
[PCI_SUBVENDOR_ID
]);
221 id
[0] = cpu_to_le16(pci_default_sub_vendor_id
);
222 id
[1] = cpu_to_le16(pci_default_sub_device_id
);
227 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
229 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
, unsigned *slotp
)
234 unsigned long dom
= 0, bus
= 0;
238 val
= strtoul(p
, &e
, 16);
244 val
= strtoul(p
, &e
, 16);
251 val
= strtoul(p
, &e
, 16);
257 if (dom
> 0xffff || bus
> 0xff || val
> 0x1f)
265 /* Note: QEMU doesn't implement domains other than 0 */
266 if (dom
!= 0 || pci_find_bus(bus
) == NULL
)
275 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
278 /* strip legacy tag */
279 if (!strncmp(addr
, "pci_addr=", 9)) {
282 if (pci_parse_devaddr(addr
, domp
, busp
, slotp
)) {
283 monitor_printf(mon
, "Invalid pci address\n");
289 static PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
)
296 return pci_find_bus(0);
299 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
) < 0) {
304 return pci_find_bus(bus
);
307 static void pci_init_cmask(PCIDevice
*dev
)
309 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
310 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
311 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
312 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
313 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
314 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
315 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
316 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
319 static void pci_init_wmask(PCIDevice
*dev
)
322 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
323 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
324 dev
->wmask
[PCI_COMMAND
] = PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
325 | PCI_COMMAND_MASTER
;
326 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
)
327 dev
->wmask
[i
] = 0xff;
330 /* -1 for devfn means auto assign */
331 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
332 const char *name
, int devfn
,
333 PCIConfigReadFunc
*config_read
,
334 PCIConfigWriteFunc
*config_write
)
337 for(devfn
= bus
->devfn_min
; devfn
< 256; devfn
+= 8) {
338 if (!bus
->devices
[devfn
])
343 } else if (bus
->devices
[devfn
]) {
347 pci_dev
->devfn
= devfn
;
348 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
349 memset(pci_dev
->irq_state
, 0, sizeof(pci_dev
->irq_state
));
350 pci_set_default_subsystem_id(pci_dev
);
351 pci_init_cmask(pci_dev
);
352 pci_init_wmask(pci_dev
);
355 config_read
= pci_default_read_config
;
357 config_write
= pci_default_write_config
;
358 pci_dev
->config_read
= config_read
;
359 pci_dev
->config_write
= config_write
;
360 bus
->devices
[devfn
] = pci_dev
;
361 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, 4);
362 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
366 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
367 int instance_size
, int devfn
,
368 PCIConfigReadFunc
*config_read
,
369 PCIConfigWriteFunc
*config_write
)
373 pci_dev
= qemu_mallocz(instance_size
);
374 pci_dev
= do_pci_register_device(pci_dev
, bus
, name
, devfn
,
375 config_read
, config_write
);
378 static target_phys_addr_t
pci_to_cpu_addr(target_phys_addr_t addr
)
380 return addr
+ pci_mem_base
;
383 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
388 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
389 r
= &pci_dev
->io_regions
[i
];
390 if (!r
->size
|| r
->addr
== -1)
392 if (r
->type
== PCI_ADDRESS_SPACE_IO
) {
393 isa_unassign_ioport(r
->addr
, r
->size
);
395 cpu_register_physical_memory(pci_to_cpu_addr(r
->addr
),
402 static int pci_unregister_device(DeviceState
*dev
)
404 PCIDevice
*pci_dev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
407 if (pci_dev
->unregister
)
408 ret
= pci_dev
->unregister(pci_dev
);
412 pci_unregister_io_regions(pci_dev
);
414 qemu_free_irqs(pci_dev
->irq
);
415 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
419 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
420 uint32_t size
, int type
,
421 PCIMapIORegionFunc
*map_func
)
427 if ((unsigned int)region_num
>= PCI_NUM_REGIONS
)
430 if (size
& (size
-1)) {
431 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
432 "type=0x%x, size=0x%x\n", type
, size
);
436 r
= &pci_dev
->io_regions
[region_num
];
440 r
->map_func
= map_func
;
443 if (region_num
== PCI_ROM_SLOT
) {
445 /* ROM enable bit is writeable */
448 addr
= 0x10 + region_num
* 4;
450 *(uint32_t *)(pci_dev
->config
+ addr
) = cpu_to_le32(type
);
451 *(uint32_t *)(pci_dev
->wmask
+ addr
) = cpu_to_le32(wmask
);
452 *(uint32_t *)(pci_dev
->cmask
+ addr
) = 0xffffffff;
455 static void pci_update_mappings(PCIDevice
*d
)
459 uint32_t last_addr
, new_addr
, config_ofs
;
461 cmd
= le16_to_cpu(*(uint16_t *)(d
->config
+ PCI_COMMAND
));
462 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
463 r
= &d
->io_regions
[i
];
464 if (i
== PCI_ROM_SLOT
) {
467 config_ofs
= 0x10 + i
* 4;
470 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
471 if (cmd
& PCI_COMMAND_IO
) {
472 new_addr
= le32_to_cpu(*(uint32_t *)(d
->config
+
474 new_addr
= new_addr
& ~(r
->size
- 1);
475 last_addr
= new_addr
+ r
->size
- 1;
476 /* NOTE: we have only 64K ioports on PC */
477 if (last_addr
<= new_addr
|| new_addr
== 0 ||
478 last_addr
>= 0x10000) {
485 if (cmd
& PCI_COMMAND_MEMORY
) {
486 new_addr
= le32_to_cpu(*(uint32_t *)(d
->config
+
488 /* the ROM slot has a specific enable bit */
489 if (i
== PCI_ROM_SLOT
&& !(new_addr
& 1))
491 new_addr
= new_addr
& ~(r
->size
- 1);
492 last_addr
= new_addr
+ r
->size
- 1;
493 /* NOTE: we do not support wrapping */
494 /* XXX: as we cannot support really dynamic
495 mappings, we handle specific values as invalid
497 if (last_addr
<= new_addr
|| new_addr
== 0 ||
506 /* now do the real mapping */
507 if (new_addr
!= r
->addr
) {
509 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
511 /* NOTE: specific hack for IDE in PC case:
512 only one byte must be mapped. */
513 class = d
->config
[0x0a] | (d
->config
[0x0b] << 8);
514 if (class == 0x0101 && r
->size
== 4) {
515 isa_unassign_ioport(r
->addr
+ 2, 1);
517 isa_unassign_ioport(r
->addr
, r
->size
);
520 cpu_register_physical_memory(pci_to_cpu_addr(r
->addr
),
523 qemu_unregister_coalesced_mmio(r
->addr
, r
->size
);
528 r
->map_func(d
, i
, r
->addr
, r
->size
, r
->type
);
535 uint32_t pci_default_read_config(PCIDevice
*d
,
536 uint32_t address
, int len
)
543 if (address
<= 0xfc) {
544 val
= le32_to_cpu(*(uint32_t *)(d
->config
+ address
));
549 if (address
<= 0xfe) {
550 val
= le16_to_cpu(*(uint16_t *)(d
->config
+ address
));
555 val
= d
->config
[address
];
561 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
563 uint8_t orig
[PCI_CONFIG_SPACE_SIZE
];
566 /* not efficient, but simple */
567 memcpy(orig
, d
->config
, PCI_CONFIG_SPACE_SIZE
);
568 for(i
= 0; i
< l
&& addr
< PCI_CONFIG_SPACE_SIZE
; val
>>= 8, ++i
, ++addr
) {
569 uint8_t wmask
= d
->wmask
[addr
];
570 d
->config
[addr
] = (d
->config
[addr
] & ~wmask
) | (val
& wmask
);
572 if (memcmp(orig
+ PCI_BASE_ADDRESS_0
, d
->config
+ PCI_BASE_ADDRESS_0
, 24)
573 || ((orig
[PCI_COMMAND
] ^ d
->config
[PCI_COMMAND
])
574 & (PCI_COMMAND_MEMORY
| PCI_COMMAND_IO
)))
575 pci_update_mappings(d
);
578 void pci_data_write(void *opaque
, uint32_t addr
, uint32_t val
, int len
)
582 int config_addr
, bus_num
;
585 PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n",
588 bus_num
= (addr
>> 16) & 0xff;
589 while (s
&& s
->bus_num
!= bus_num
)
593 pci_dev
= s
->devices
[(addr
>> 8) & 0xff];
596 config_addr
= addr
& 0xff;
597 PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
598 pci_dev
->name
, config_addr
, val
, len
);
599 pci_dev
->config_write(pci_dev
, config_addr
, val
, len
);
602 uint32_t pci_data_read(void *opaque
, uint32_t addr
, int len
)
606 int config_addr
, bus_num
;
609 bus_num
= (addr
>> 16) & 0xff;
610 while (s
&& s
->bus_num
!= bus_num
)
614 pci_dev
= s
->devices
[(addr
>> 8) & 0xff];
631 config_addr
= addr
& 0xff;
632 val
= pci_dev
->config_read(pci_dev
, config_addr
, len
);
633 PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
634 pci_dev
->name
, config_addr
, val
, len
);
637 PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n",
643 /***********************************************************/
644 /* generic PCI irq support */
646 /* 0 <= irq_num <= 3. level must be 0 or 1 */
647 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
649 PCIDevice
*pci_dev
= opaque
;
653 change
= level
- pci_dev
->irq_state
[irq_num
];
657 pci_dev
->irq_state
[irq_num
] = level
;
660 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
663 pci_dev
= bus
->parent_dev
;
665 bus
->irq_count
[irq_num
] += change
;
666 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
669 /***********************************************************/
670 /* monitor info on PCI */
677 static const pci_class_desc pci_class_descriptions
[] =
679 { 0x0100, "SCSI controller"},
680 { 0x0101, "IDE controller"},
681 { 0x0102, "Floppy controller"},
682 { 0x0103, "IPI controller"},
683 { 0x0104, "RAID controller"},
684 { 0x0106, "SATA controller"},
685 { 0x0107, "SAS controller"},
686 { 0x0180, "Storage controller"},
687 { 0x0200, "Ethernet controller"},
688 { 0x0201, "Token Ring controller"},
689 { 0x0202, "FDDI controller"},
690 { 0x0203, "ATM controller"},
691 { 0x0280, "Network controller"},
692 { 0x0300, "VGA controller"},
693 { 0x0301, "XGA controller"},
694 { 0x0302, "3D controller"},
695 { 0x0380, "Display controller"},
696 { 0x0400, "Video controller"},
697 { 0x0401, "Audio controller"},
699 { 0x0480, "Multimedia controller"},
700 { 0x0500, "RAM controller"},
701 { 0x0501, "Flash controller"},
702 { 0x0580, "Memory controller"},
703 { 0x0600, "Host bridge"},
704 { 0x0601, "ISA bridge"},
705 { 0x0602, "EISA bridge"},
706 { 0x0603, "MC bridge"},
707 { 0x0604, "PCI bridge"},
708 { 0x0605, "PCMCIA bridge"},
709 { 0x0606, "NUBUS bridge"},
710 { 0x0607, "CARDBUS bridge"},
711 { 0x0608, "RACEWAY bridge"},
713 { 0x0c03, "USB controller"},
717 static void pci_info_device(PCIDevice
*d
)
719 Monitor
*mon
= cur_mon
;
722 const pci_class_desc
*desc
;
724 monitor_printf(mon
, " Bus %2d, device %3d, function %d:\n",
725 d
->bus
->bus_num
, d
->devfn
>> 3, d
->devfn
& 7);
726 class = le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_CLASS_DEVICE
)));
727 monitor_printf(mon
, " ");
728 desc
= pci_class_descriptions
;
729 while (desc
->desc
&& class != desc
->class)
732 monitor_printf(mon
, "%s", desc
->desc
);
734 monitor_printf(mon
, "Class %04x", class);
736 monitor_printf(mon
, ": PCI device %04x:%04x\n",
737 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_VENDOR_ID
))),
738 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_DEVICE_ID
))));
740 if (d
->config
[PCI_INTERRUPT_PIN
] != 0) {
741 monitor_printf(mon
, " IRQ %d.\n",
742 d
->config
[PCI_INTERRUPT_LINE
]);
744 if (class == 0x0604) {
745 monitor_printf(mon
, " BUS %d.\n", d
->config
[0x19]);
747 for(i
= 0;i
< PCI_NUM_REGIONS
; i
++) {
748 r
= &d
->io_regions
[i
];
750 monitor_printf(mon
, " BAR%d: ", i
);
751 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
752 monitor_printf(mon
, "I/O at 0x%04x [0x%04x].\n",
753 r
->addr
, r
->addr
+ r
->size
- 1);
755 monitor_printf(mon
, "32 bit memory at 0x%08x [0x%08x].\n",
756 r
->addr
, r
->addr
+ r
->size
- 1);
760 monitor_printf(mon
, " id \"%s\"\n", d
->qdev
.id
? d
->qdev
.id
: "");
761 if (class == 0x0604 && d
->config
[0x19] != 0) {
762 pci_for_each_device(d
->config
[0x19], pci_info_device
);
766 void pci_for_each_device(int bus_num
, void (*fn
)(PCIDevice
*d
))
768 PCIBus
*bus
= first_bus
;
772 while (bus
&& bus
->bus_num
!= bus_num
)
775 for(devfn
= 0; devfn
< 256; devfn
++) {
776 d
= bus
->devices
[devfn
];
783 void pci_info(Monitor
*mon
)
785 pci_for_each_device(0, pci_info_device
);
788 PCIDevice
*pci_create(const char *name
, const char *devaddr
)
794 bus
= pci_get_bus_devfn(&devfn
, devaddr
);
796 fprintf(stderr
, "Invalid PCI device address %s for device %s\n",
801 dev
= qdev_create(&bus
->qbus
, name
);
802 qdev_prop_set_uint32(dev
, "addr", devfn
);
803 return (PCIDevice
*)dev
;
806 static const char * const pci_nic_models
[] = {
818 static const char * const pci_nic_names
[] = {
830 int pci_nic_supported(const char *model
)
834 for (i
= 0; pci_nic_names
[i
]; i
++)
835 if (strcmp(model
, pci_nic_names
[i
]) == 0)
841 /* Initialize a PCI NIC. */
842 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
843 const char *default_devaddr
)
845 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
850 qemu_check_nic_model_list(nd
, pci_nic_models
, default_model
);
852 for (i
= 0; pci_nic_models
[i
]; i
++) {
853 if (strcmp(nd
->model
, pci_nic_models
[i
]) == 0) {
854 pci_dev
= pci_create(pci_nic_names
[i
], devaddr
);
855 dev
= &pci_dev
->qdev
;
857 dev
->id
= qemu_strdup(nd
->id
);
875 static void pci_bridge_write_config(PCIDevice
*d
,
876 uint32_t address
, uint32_t val
, int len
)
878 PCIBridge
*s
= (PCIBridge
*)d
;
880 pci_default_write_config(d
, address
, val
, len
);
881 s
->bus
.bus_num
= d
->config
[PCI_SECONDARY_BUS
];
884 PCIBus
*pci_find_bus(int bus_num
)
886 PCIBus
*bus
= first_bus
;
888 while (bus
&& bus
->bus_num
!= bus_num
)
894 PCIDevice
*pci_find_device(int bus_num
, int slot
, int function
)
896 PCIBus
*bus
= pci_find_bus(bus_num
);
901 return bus
->devices
[PCI_DEVFN(slot
, function
)];
904 static int pci_bridge_initfn(PCIDevice
*dev
)
906 PCIBridge
*s
= DO_UPCAST(PCIBridge
, dev
, dev
);
908 pci_config_set_vendor_id(s
->dev
.config
, s
->vid
);
909 pci_config_set_device_id(s
->dev
.config
, s
->did
);
911 s
->dev
.config
[0x04] = 0x06; // command = bus master, pci mem
912 s
->dev
.config
[0x05] = 0x00;
913 s
->dev
.config
[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
914 s
->dev
.config
[0x07] = 0x00; // status = fast devsel
915 s
->dev
.config
[0x08] = 0x00; // revision
916 s
->dev
.config
[0x09] = 0x00; // programming i/f
917 pci_config_set_class(s
->dev
.config
, PCI_CLASS_BRIDGE_PCI
);
918 s
->dev
.config
[0x0D] = 0x10; // latency_timer
919 s
->dev
.config
[PCI_HEADER_TYPE
] =
920 PCI_HEADER_TYPE_MULTI_FUNCTION
| PCI_HEADER_TYPE_BRIDGE
; // header_type
921 s
->dev
.config
[0x1E] = 0xa0; // secondary status
925 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, uint16_t vid
, uint16_t did
,
926 pci_map_irq_fn map_irq
, const char *name
)
931 dev
= pci_create_noinit(bus
, devfn
, "pci-bridge");
932 qdev_prop_set_uint32(&dev
->qdev
, "vendorid", vid
);
933 qdev_prop_set_uint32(&dev
->qdev
, "deviceid", did
);
934 qdev_init(&dev
->qdev
);
936 s
= DO_UPCAST(PCIBridge
, dev
, dev
);
937 pci_register_secondary_bus(&s
->bus
, &s
->dev
, map_irq
, name
);
941 static int pci_qdev_init(DeviceState
*qdev
, DeviceInfo
*base
)
943 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
944 PCIDeviceInfo
*info
= container_of(base
, PCIDeviceInfo
, qdev
);
948 bus
= FROM_QBUS(PCIBus
, qdev_get_parent_bus(qdev
));
949 devfn
= pci_dev
->devfn
;
950 pci_dev
= do_pci_register_device(pci_dev
, bus
, base
->name
, devfn
,
951 info
->config_read
, info
->config_write
);
953 return info
->init(pci_dev
);
956 void pci_qdev_register(PCIDeviceInfo
*info
)
958 info
->qdev
.init
= pci_qdev_init
;
959 info
->qdev
.exit
= pci_unregister_device
;
960 info
->qdev
.bus_info
= &pci_bus_info
;
961 qdev_register(&info
->qdev
);
964 void pci_qdev_register_many(PCIDeviceInfo
*info
)
966 while (info
->qdev
.name
) {
967 pci_qdev_register(info
);
972 PCIDevice
*pci_create_noinit(PCIBus
*bus
, int devfn
, const char *name
)
976 dev
= qdev_create(&bus
->qbus
, name
);
977 qdev_prop_set_uint32(dev
, "addr", devfn
);
978 return DO_UPCAST(PCIDevice
, qdev
, dev
);
981 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
983 PCIDevice
*dev
= pci_create_noinit(bus
, devfn
, name
);
984 qdev_init(&dev
->qdev
);
988 static int pci_find_space(PCIDevice
*pdev
, uint8_t size
)
990 int offset
= PCI_CONFIG_HEADER_SIZE
;
992 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
)
995 else if (i
- offset
+ 1 == size
)
1000 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1005 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1008 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1009 prev
= next
+ PCI_CAP_LIST_NEXT
)
1010 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1018 /* Reserve space and add capability to the linked list in pci config space */
1019 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1021 uint8_t offset
= pci_find_space(pdev
, size
);
1022 uint8_t *config
= pdev
->config
+ offset
;
1025 config
[PCI_CAP_LIST_ID
] = cap_id
;
1026 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
1027 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
1028 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
1029 memset(pdev
->used
+ offset
, 0xFF, size
);
1030 /* Make capability read-only by default */
1031 memset(pdev
->wmask
+ offset
, 0, size
);
1032 /* Check capability by default */
1033 memset(pdev
->cmask
+ offset
, 0xFF, size
);
1037 /* Unlink capability from the pci config space. */
1038 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1040 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
1043 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
1044 /* Make capability writeable again */
1045 memset(pdev
->wmask
+ offset
, 0xff, size
);
1046 /* Clear cmask as device-specific registers can't be checked */
1047 memset(pdev
->cmask
+ offset
, 0, size
);
1048 memset(pdev
->used
+ offset
, 0, size
);
1050 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
1051 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
1054 /* Reserve space for capability at a known offset (to call after load). */
1055 void pci_reserve_capability(PCIDevice
*pdev
, uint8_t offset
, uint8_t size
)
1057 memset(pdev
->used
+ offset
, 0xff, size
);
1060 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
1062 return pci_find_capability_list(pdev
, cap_id
, NULL
);
1065 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
1067 PCIDevice
*d
= (PCIDevice
*)dev
;
1068 const pci_class_desc
*desc
;
1073 class = le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_CLASS_DEVICE
)));
1074 desc
= pci_class_descriptions
;
1075 while (desc
->desc
&& class != desc
->class)
1078 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
1080 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
1083 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
1084 "pci id %04x:%04x (sub %04x:%04x)\n",
1086 d
->bus
->bus_num
, d
->devfn
>> 3, d
->devfn
& 7,
1087 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_VENDOR_ID
))),
1088 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_DEVICE_ID
))),
1089 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
))),
1090 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_SUBSYSTEM_ID
))));
1091 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1092 r
= &d
->io_regions
[i
];
1095 monitor_printf(mon
, "%*sbar %d: %s at 0x%x [0x%x]\n", indent
, "",
1096 i
, r
->type
& PCI_ADDRESS_SPACE_IO
? "i/o" : "mem",
1097 r
->addr
, r
->addr
+ r
->size
- 1);
1101 static PCIDeviceInfo bridge_info
= {
1102 .qdev
.name
= "pci-bridge",
1103 .qdev
.size
= sizeof(PCIBridge
),
1104 .init
= pci_bridge_initfn
,
1105 .config_write
= pci_bridge_write_config
,
1106 .qdev
.props
= (Property
[]) {
1107 DEFINE_PROP_HEX32("vendorid", PCIBridge
, vid
, 0),
1108 DEFINE_PROP_HEX32("deviceid", PCIBridge
, did
, 0),
1109 DEFINE_PROP_END_OF_LIST(),
1113 static void pci_register_devices(void)
1115 pci_qdev_register(&bridge_info
);
1118 device_init(pci_register_devices
)