target-s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22 #ifndef CPU_S390X_H
  23 #define CPU_S390X_H
  24
  25 #include "config.h"
  26 #include "qemu-common.h"
  27
  28 #define TARGET_LONG_BITS 64
  29
  30 #define ELF_MACHINE     EM_S390
  31 #define ELF_MACHINE_UNAME "S390X"
  32
  33 #define CPUArchState struct CPUS390XState
  34
  35 #include "exec/cpu-defs.h"
  36 #define TARGET_PAGE_BITS 12
  37
  38 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  39 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  40
  41 #include "exec/cpu-all.h"
  42
  43 #include "fpu/softfloat.h"
  44
  45 #define NB_MMU_MODES 3
  46
  47 #define MMU_MODE0_SUFFIX _primary
  48 #define MMU_MODE1_SUFFIX _secondary
  49 #define MMU_MODE2_SUFFIX _home
  50
  51 #define MMU_USER_IDX 1
  52
  53 #define MAX_EXT_QUEUE 16
  54 #define MAX_IO_QUEUE 16
  55 #define MAX_MCHK_QUEUE 16
  56
  57 #define PSW_MCHK_MASK 0x0004000000000000
  58 #define PSW_IO_MASK 0x0200000000000000
  59
  60 typedef struct PSW {
  61     uint64_t mask;
  62     uint64_t addr;
  63 } PSW;
  64
  65 typedef struct ExtQueue {
  66     uint32_t code;
  67     uint32_t param;
  68     uint32_t param64;
  69 } ExtQueue;
  70
  71 typedef struct IOIntQueue {
  72     uint16_t id;
  73     uint16_t nr;
  74     uint32_t parm;
  75     uint32_t word;
  76 } IOIntQueue;
  77
  78 typedef struct MchkQueue {
  79     uint16_t type;
  80 } MchkQueue;
  81
  82 typedef struct CPUS390XState {
  83     uint64_t regs[16];     /* GP registers */
  84     CPU_DoubleU fregs[16]; /* FP registers */
  85     uint32_t aregs[16];    /* access registers */
  86
  87     uint32_t fpc;          /* floating-point control register */
  88     uint32_t cc_op;
  89
  90     float_status fpu_status; /* passed to softfloat lib */
  91
  92     /* The low part of a 128-bit return, or remainder of a divide.  */
  93     uint64_t retxl;
  94
  95     PSW psw;
  96
  97     uint64_t cc_src;
  98     uint64_t cc_dst;
  99     uint64_t cc_vr;
 100
 101     uint64_t __excp_addr;
 102     uint64_t psa;
 103
 104     uint32_t int_pgm_code;
 105     uint32_t int_pgm_ilen;
 106
 107     uint32_t int_svc_code;
 108     uint32_t int_svc_ilen;
 109
 110     uint64_t cregs[16]; /* control registers */
 111
 112     ExtQueue ext_queue[MAX_EXT_QUEUE];
 113     IOIntQueue io_queue[MAX_IO_QUEUE][8];
 114     MchkQueue mchk_queue[MAX_MCHK_QUEUE];
 115
 116     int pending_int;
 117     int ext_index;
 118     int io_index[8];
 119     int mchk_index;
 120
 121     uint64_t ckc;
 122     uint64_t cputm;
 123     uint32_t todpr;
 124
 125     uint64_t pfault_token;
 126     uint64_t pfault_compare;
 127     uint64_t pfault_select;
 128
 129     uint64_t gbea;
 130     uint64_t pp;
 131
 132     CPU_COMMON
 133
 134     /* reset does memset(0) up to here */
 135
 136     int cpu_num;
 137     uint8_t *storage_keys;
 138
 139     uint64_t tod_offset;
 140     uint64_t tod_basetime;
 141     QEMUTimer *tod_timer;
 142
 143     QEMUTimer *cpu_timer;
 144 } CPUS390XState;
 145
 146 #include "cpu-qom.h"
 147 #include <sysemu/kvm.h>
 148
 149 /* distinguish between 24 bit and 31 bit addressing */
 150 #define HIGH_ORDER_BIT 0x80000000
 151
 152 /* Interrupt Codes */
 153 /* Program Interrupts */
 154 #define PGM_OPERATION                   0x0001
 155 #define PGM_PRIVILEGED                  0x0002
 156 #define PGM_EXECUTE                     0x0003
 157 #define PGM_PROTECTION                  0x0004
 158 #define PGM_ADDRESSING                  0x0005
 159 #define PGM_SPECIFICATION               0x0006
 160 #define PGM_DATA                        0x0007
 161 #define PGM_FIXPT_OVERFLOW              0x0008
 162 #define PGM_FIXPT_DIVIDE                0x0009
 163 #define PGM_DEC_OVERFLOW                0x000a
 164 #define PGM_DEC_DIVIDE                  0x000b
 165 #define PGM_HFP_EXP_OVERFLOW            0x000c
 166 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 167 #define PGM_HFP_SIGNIFICANCE            0x000e
 168 #define PGM_HFP_DIVIDE                  0x000f
 169 #define PGM_SEGMENT_TRANS               0x0010
 170 #define PGM_PAGE_TRANS                  0x0011
 171 #define PGM_TRANS_SPEC                  0x0012
 172 #define PGM_SPECIAL_OP                  0x0013
 173 #define PGM_OPERAND                     0x0015
 174 #define PGM_TRACE_TABLE                 0x0016
 175 #define PGM_SPACE_SWITCH                0x001c
 176 #define PGM_HFP_SQRT                    0x001d
 177 #define PGM_PC_TRANS_SPEC               0x001f
 178 #define PGM_AFX_TRANS                   0x0020
 179 #define PGM_ASX_TRANS                   0x0021
 180 #define PGM_LX_TRANS                    0x0022
 181 #define PGM_EX_TRANS                    0x0023
 182 #define PGM_PRIM_AUTH                   0x0024
 183 #define PGM_SEC_AUTH                    0x0025
 184 #define PGM_ALET_SPEC                   0x0028
 185 #define PGM_ALEN_SPEC                   0x0029
 186 #define PGM_ALE_SEQ                     0x002a
 187 #define PGM_ASTE_VALID                  0x002b
 188 #define PGM_ASTE_SEQ                    0x002c
 189 #define PGM_EXT_AUTH                    0x002d
 190 #define PGM_STACK_FULL                  0x0030
 191 #define PGM_STACK_EMPTY                 0x0031
 192 #define PGM_STACK_SPEC                  0x0032
 193 #define PGM_STACK_TYPE                  0x0033
 194 #define PGM_STACK_OP                    0x0034
 195 #define PGM_ASCE_TYPE                   0x0038
 196 #define PGM_REG_FIRST_TRANS             0x0039
 197 #define PGM_REG_SEC_TRANS               0x003a
 198 #define PGM_REG_THIRD_TRANS             0x003b
 199 #define PGM_MONITOR                     0x0040
 200 #define PGM_PER                         0x0080
 201 #define PGM_CRYPTO                      0x0119
 202
 203 /* External Interrupts */
 204 #define EXT_INTERRUPT_KEY               0x0040
 205 #define EXT_CLOCK_COMP                  0x1004
 206 #define EXT_CPU_TIMER                   0x1005
 207 #define EXT_MALFUNCTION                 0x1200
 208 #define EXT_EMERGENCY                   0x1201
 209 #define EXT_EXTERNAL_CALL               0x1202
 210 #define EXT_ETR                         0x1406
 211 #define EXT_SERVICE                     0x2401
 212 #define EXT_VIRTIO                      0x2603
 213
 214 /* PSW defines */
 215 #undef PSW_MASK_PER
 216 #undef PSW_MASK_DAT
 217 #undef PSW_MASK_IO
 218 #undef PSW_MASK_EXT
 219 #undef PSW_MASK_KEY
 220 #undef PSW_SHIFT_KEY
 221 #undef PSW_MASK_MCHECK
 222 #undef PSW_MASK_WAIT
 223 #undef PSW_MASK_PSTATE
 224 #undef PSW_MASK_ASC
 225 #undef PSW_MASK_CC
 226 #undef PSW_MASK_PM
 227 #undef PSW_MASK_64
 228 #undef PSW_MASK_32
 229 #undef PSW_MASK_ESA_ADDR
 230
 231 #define PSW_MASK_PER            0x4000000000000000ULL
 232 #define PSW_MASK_DAT            0x0400000000000000ULL
 233 #define PSW_MASK_IO             0x0200000000000000ULL
 234 #define PSW_MASK_EXT            0x0100000000000000ULL
 235 #define PSW_MASK_KEY            0x00F0000000000000ULL
 236 #define PSW_SHIFT_KEY           56
 237 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 238 #define PSW_MASK_WAIT           0x0002000000000000ULL
 239 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 240 #define PSW_MASK_ASC            0x0000C00000000000ULL
 241 #define PSW_MASK_CC             0x0000300000000000ULL
 242 #define PSW_MASK_PM             0x00000F0000000000ULL
 243 #define PSW_MASK_64             0x0000000100000000ULL
 244 #define PSW_MASK_32             0x0000000080000000ULL
 245 #define PSW_MASK_ESA_ADDR       0x000000007fffffffULL
 246
 247 #undef PSW_ASC_PRIMARY
 248 #undef PSW_ASC_ACCREG
 249 #undef PSW_ASC_SECONDARY
 250 #undef PSW_ASC_HOME
 251
 252 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 253 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 254 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 255 #define PSW_ASC_HOME            0x0000C00000000000ULL
 256
 257 /* tb flags */
 258
 259 #define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
 260 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
 261 #define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
 262 #define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
 263 #define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
 264 #define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
 265 #define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
 266 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
 267 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
 268 #define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
 269 #define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
 270 #define FLAG_MASK_64            (PSW_MASK_64     >> 32)
 271 #define FLAG_MASK_32            0x00001000
 272
 273 /* Control register 0 bits */
 274 #define CR0_EDAT                0x0000000000800000ULL
 275
 276 static inline int cpu_mmu_index (CPUS390XState *env)
 277 {
 278     if (env->psw.mask & PSW_MASK_PSTATE) {
 279         return 1;
 280     }
 281
 282     return 0;
 283 }
 284
 285 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 286                                         target_ulong *cs_base, int *flags)
 287 {
 288     *pc = env->psw.addr;
 289     *cs_base = 0;
 290     *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
 291              ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
 292 }
 293
 294 /* While the PoO talks about ILC (a number between 1-3) what is actually
 295    stored in LowCore is shifted left one bit (an even between 2-6).  As
 296    this is the actual length of the insn and therefore more useful, that
 297    is what we want to pass around and manipulate.  To make sure that we
 298    have applied this distinction universally, rename the "ILC" to "ILEN".  */
 299 static inline int get_ilen(uint8_t opc)
 300 {
 301     switch (opc >> 6) {
 302     case 0:
 303         return 2;
 304     case 1:
 305     case 2:
 306         return 4;
 307     default:
 308         return 6;
 309     }
 310 }
 311
 312 #ifndef CONFIG_USER_ONLY
 313 /* In several cases of runtime exceptions, we havn't recorded the true
 314    instruction length.  Use these codes when raising exceptions in order
 315    to re-compute the length by examining the insn in memory.  */
 316 #define ILEN_LATER       0x20
 317 #define ILEN_LATER_INC   0x21
 318 #endif
 319
 320 S390CPU *cpu_s390x_init(const char *cpu_model);
 321 void s390x_translate_init(void);
 322 int cpu_s390x_exec(CPUS390XState *s);
 323
 324 /* you can call this signal handler from your SIGBUS and SIGSEGV
 325    signal handlers to inform the virtual CPU of exceptions. non zero
 326    is returned if the signal was handled by the virtual CPU.  */
 327 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 328                            void *puc);
 329 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 330                               int mmu_idx);
 331
 332 #include "ioinst.h"
 333
 334 #ifndef CONFIG_USER_ONLY
 335 void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
 336                                    int is_write);
 337 void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
 338                                     int is_write);
 339 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
 340 {
 341     hwaddr addr = 0;
 342     uint8_t reg;
 343
 344     reg = ipb >> 28;
 345     if (reg > 0) {
 346         addr = env->regs[reg];
 347     }
 348     addr += (ipb >> 16) & 0xfff;
 349
 350     return addr;
 351 }
 352
 353 /* Base/displacement are at the same locations. */
 354 #define decode_basedisp_rs decode_basedisp_s
 355
 356 /* helper functions for run_on_cpu() */
 357 static inline void s390_do_cpu_reset(void *arg)
 358 {
 359     CPUState *cs = arg;
 360     S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 361
 362     scc->cpu_reset(cs);
 363 }
 364 static inline void s390_do_cpu_full_reset(void *arg)
 365 {
 366     CPUState *cs = arg;
 367
 368     cpu_reset(cs);
 369 }
 370
 371 void s390x_tod_timer(void *opaque);
 372 void s390x_cpu_timer(void *opaque);
 373
 374 int s390_virtio_hypercall(CPUS390XState *env);
 375 void s390_virtio_irq(int config_change, uint64_t token);
 376
 377 #ifdef CONFIG_KVM
 378 void kvm_s390_reset_vcpu(S390CPU *cpu);
 379 void kvm_s390_virtio_irq(int config_change, uint64_t token);
 380 void kvm_s390_service_interrupt(uint32_t parm);
 381 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
 382 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
 383 int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
 384 #else
 385 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
 386 {
 387 }
 388 static inline void kvm_s390_virtio_irq(int config_change, uint64_t token)
 389 {
 390 }
 391 static inline void kvm_s390_service_interrupt(uint32_t parm)
 392 {
 393 }
 394 #endif
 395 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 396 void s390_add_running_cpu(S390CPU *cpu);
 397 unsigned s390_del_running_cpu(S390CPU *cpu);
 398
 399 /* service interrupts are floating therefore we must not pass an cpustate */
 400 void s390_sclp_extint(uint32_t parm);
 401
 402 /* from s390-virtio-bus */
 403 extern const hwaddr virtio_size;
 404
 405 #else
 406 static inline void s390_add_running_cpu(S390CPU *cpu)
 407 {
 408 }
 409
 410 static inline unsigned s390_del_running_cpu(S390CPU *cpu)
 411 {
 412     return 0;
 413 }
 414 #endif
 415 void cpu_lock(void);
 416 void cpu_unlock(void);
 417
 418 typedef struct SubchDev SubchDev;
 419
 420 #ifndef CONFIG_USER_ONLY
 421 extern void io_subsystem_reset(void);
 422 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 423                          uint16_t schid);
 424 bool css_subch_visible(SubchDev *sch);
 425 void css_conditional_io_interrupt(SubchDev *sch);
 426 int css_do_stsch(SubchDev *sch, SCHIB *schib);
 427 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
 428 int css_do_msch(SubchDev *sch, SCHIB *schib);
 429 int css_do_xsch(SubchDev *sch);
 430 int css_do_csch(SubchDev *sch);
 431 int css_do_hsch(SubchDev *sch);
 432 int css_do_ssch(SubchDev *sch, ORB *orb);
 433 int css_do_tsch(SubchDev *sch, IRB *irb);
 434 int css_do_stcrw(CRW *crw);
 435 int css_do_tpi(IOIntCode *int_code, int lowcore);
 436 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
 437                          int rfmt, void *buf);
 438 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
 439 int css_enable_mcsse(void);
 440 int css_enable_mss(void);
 441 int css_do_rsch(SubchDev *sch);
 442 int css_do_rchp(uint8_t cssid, uint8_t chpid);
 443 bool css_present(uint8_t cssid);
 444 #else
 445 static inline SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 446                                        uint16_t schid)
 447 {
 448     return NULL;
 449 }
 450 static inline bool css_subch_visible(SubchDev *sch)
 451 {
 452     return false;
 453 }
 454 static inline void css_conditional_io_interrupt(SubchDev *sch)
 455 {
 456 }
 457 static inline int css_do_stsch(SubchDev *sch, SCHIB *schib)
 458 {
 459     return -ENODEV;
 460 }
 461 static inline bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid)
 462 {
 463     return true;
 464 }
 465 static inline int css_do_msch(SubchDev *sch, SCHIB *schib)
 466 {
 467     return -ENODEV;
 468 }
 469 static inline int css_do_xsch(SubchDev *sch)
 470 {
 471     return -ENODEV;
 472 }
 473 static inline int css_do_csch(SubchDev *sch)
 474 {
 475     return -ENODEV;
 476 }
 477 static inline int css_do_hsch(SubchDev *sch)
 478 {
 479     return -ENODEV;
 480 }
 481 static inline int css_do_ssch(SubchDev *sch, ORB *orb)
 482 {
 483     return -ENODEV;
 484 }
 485 static inline int css_do_tsch(SubchDev *sch, IRB *irb)
 486 {
 487     return -ENODEV;
 488 }
 489 static inline int css_do_stcrw(CRW *crw)
 490 {
 491     return 1;
 492 }
 493 static inline int css_do_tpi(IOIntCode *int_code, int lowcore)
 494 {
 495     return 0;
 496 }
 497 static inline int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid,
 498                                        int rfmt, uint8_t l_chpid, void *buf)
 499 {
 500     return 0;
 501 }
 502 static inline void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
 503 {
 504 }
 505 static inline int css_enable_mss(void)
 506 {
 507     return -EINVAL;
 508 }
 509 static inline int css_enable_mcsse(void)
 510 {
 511     return -EINVAL;
 512 }
 513 static inline int css_do_rsch(SubchDev *sch)
 514 {
 515     return -ENODEV;
 516 }
 517 static inline int css_do_rchp(uint8_t cssid, uint8_t chpid)
 518 {
 519     return -ENODEV;
 520 }
 521 static inline bool css_present(uint8_t cssid)
 522 {
 523     return false;
 524 }
 525 #endif
 526
 527 #define cpu_init(model) (&cpu_s390x_init(model)->env)
 528 #define cpu_exec cpu_s390x_exec
 529 #define cpu_gen_code cpu_s390x_gen_code
 530 #define cpu_signal_handler cpu_s390x_signal_handler
 531
 532 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 533 #define cpu_list s390_cpu_list
 534
 535 #include "exec/exec-all.h"
 536
 537 #define EXCP_EXT 1 /* external interrupt */
 538 #define EXCP_SVC 2 /* supervisor call (syscall) */
 539 #define EXCP_PGM 3 /* program interruption */
 540 #define EXCP_IO  7 /* I/O interrupt */
 541 #define EXCP_MCHK 8 /* machine check */
 542
 543 #define INTERRUPT_EXT        (1 << 0)
 544 #define INTERRUPT_TOD        (1 << 1)
 545 #define INTERRUPT_CPUTIMER   (1 << 2)
 546 #define INTERRUPT_IO         (1 << 3)
 547 #define INTERRUPT_MCHK       (1 << 4)
 548
 549 /* Program Status Word.  */
 550 #define S390_PSWM_REGNUM 0
 551 #define S390_PSWA_REGNUM 1
 552 /* General Purpose Registers.  */
 553 #define S390_R0_REGNUM 2
 554 #define S390_R1_REGNUM 3
 555 #define S390_R2_REGNUM 4
 556 #define S390_R3_REGNUM 5
 557 #define S390_R4_REGNUM 6
 558 #define S390_R5_REGNUM 7
 559 #define S390_R6_REGNUM 8
 560 #define S390_R7_REGNUM 9
 561 #define S390_R8_REGNUM 10
 562 #define S390_R9_REGNUM 11
 563 #define S390_R10_REGNUM 12
 564 #define S390_R11_REGNUM 13
 565 #define S390_R12_REGNUM 14
 566 #define S390_R13_REGNUM 15
 567 #define S390_R14_REGNUM 16
 568 #define S390_R15_REGNUM 17
 569 /* Total Core Registers. */
 570 #define S390_NUM_CORE_REGS 18
 571
 572 /* CC optimization */
 573
 574 enum cc_op {
 575     CC_OP_CONST0 = 0,           /* CC is 0 */
 576     CC_OP_CONST1,               /* CC is 1 */
 577     CC_OP_CONST2,               /* CC is 2 */
 578     CC_OP_CONST3,               /* CC is 3 */
 579
 580     CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
 581     CC_OP_STATIC,               /* CC value is env->cc_op */
 582
 583     CC_OP_NZ,                   /* env->cc_dst != 0 */
 584     CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
 585     CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
 586     CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
 587     CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
 588     CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
 589     CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
 590
 591     CC_OP_ADD_64,               /* overflow on add (64bit) */
 592     CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
 593     CC_OP_ADDC_64,              /* overflow on unsigned add-carry (64bit) */
 594     CC_OP_SUB_64,               /* overflow on subtraction (64bit) */
 595     CC_OP_SUBU_64,              /* overflow on unsigned subtraction (64bit) */
 596     CC_OP_SUBB_64,              /* overflow on unsigned sub-borrow (64bit) */
 597     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
 598     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
 599
 600     CC_OP_ADD_32,               /* overflow on add (32bit) */
 601     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
 602     CC_OP_ADDC_32,              /* overflow on unsigned add-carry (32bit) */
 603     CC_OP_SUB_32,               /* overflow on subtraction (32bit) */
 604     CC_OP_SUBU_32,              /* overflow on unsigned subtraction (32bit) */
 605     CC_OP_SUBB_32,              /* overflow on unsigned sub-borrow (32bit) */
 606     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
 607     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
 608
 609     CC_OP_COMP_32,              /* complement */
 610     CC_OP_COMP_64,              /* complement */
 611
 612     CC_OP_TM_32,                /* test under mask (32bit) */
 613     CC_OP_TM_64,                /* test under mask (64bit) */
 614
 615     CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
 616     CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
 617     CC_OP_NZ_F128,              /* FP dst != 0 (128bit) */
 618
 619     CC_OP_ICM,                  /* insert characters under mask */
 620     CC_OP_SLA_32,               /* Calculate shift left signed (32bit) */
 621     CC_OP_SLA_64,               /* Calculate shift left signed (64bit) */
 622     CC_OP_FLOGR,                /* find leftmost one */
 623     CC_OP_MAX
 624 };
 625
 626 static const char *cc_names[] = {
 627     [CC_OP_CONST0]    = "CC_OP_CONST0",
 628     [CC_OP_CONST1]    = "CC_OP_CONST1",
 629     [CC_OP_CONST2]    = "CC_OP_CONST2",
 630     [CC_OP_CONST3]    = "CC_OP_CONST3",
 631     [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 632     [CC_OP_STATIC]    = "CC_OP_STATIC",
 633     [CC_OP_NZ]        = "CC_OP_NZ",
 634     [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 635     [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 636     [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 637     [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 638     [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 639     [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 640     [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 641     [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 642     [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 643     [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 644     [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 645     [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 646     [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 647     [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 648     [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 649     [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 650     [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 651     [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 652     [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 653     [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 654     [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 655     [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 656     [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 657     [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 658     [CC_OP_TM_32]     = "CC_OP_TM_32",
 659     [CC_OP_TM_64]     = "CC_OP_TM_64",
 660     [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 661     [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 662     [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 663     [CC_OP_ICM]       = "CC_OP_ICM",
 664     [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 665     [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 666     [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 667 };
 668
 669 static inline const char *cc_name(int cc_op)
 670 {
 671     return cc_names[cc_op];
 672 }
 673
 674 static inline void setcc(S390CPU *cpu, uint64_t cc)
 675 {
 676     CPUS390XState *env = &cpu->env;
 677
 678     env->psw.mask &= ~(3ull << 44);
 679     env->psw.mask |= (cc & 3) << 44;
 680 }
 681
 682 typedef struct LowCore
 683 {
 684     /* prefix area: defined by architecture */
 685     uint32_t        ccw1[2];                  /* 0x000 */
 686     uint32_t        ccw2[4];                  /* 0x008 */
 687     uint8_t         pad1[0x80-0x18];          /* 0x018 */
 688     uint32_t        ext_params;               /* 0x080 */
 689     uint16_t        cpu_addr;                 /* 0x084 */
 690     uint16_t        ext_int_code;             /* 0x086 */
 691     uint16_t        svc_ilen;                 /* 0x088 */
 692     uint16_t        svc_code;                 /* 0x08a */
 693     uint16_t        pgm_ilen;                 /* 0x08c */
 694     uint16_t        pgm_code;                 /* 0x08e */
 695     uint32_t        data_exc_code;            /* 0x090 */
 696     uint16_t        mon_class_num;            /* 0x094 */
 697     uint16_t        per_perc_atmid;           /* 0x096 */
 698     uint64_t        per_address;              /* 0x098 */
 699     uint8_t         exc_access_id;            /* 0x0a0 */
 700     uint8_t         per_access_id;            /* 0x0a1 */
 701     uint8_t         op_access_id;             /* 0x0a2 */
 702     uint8_t         ar_access_id;             /* 0x0a3 */
 703     uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
 704     uint64_t        trans_exc_code;           /* 0x0a8 */
 705     uint64_t        monitor_code;             /* 0x0b0 */
 706     uint16_t        subchannel_id;            /* 0x0b8 */
 707     uint16_t        subchannel_nr;            /* 0x0ba */
 708     uint32_t        io_int_parm;              /* 0x0bc */
 709     uint32_t        io_int_word;              /* 0x0c0 */
 710     uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
 711     uint32_t        stfl_fac_list;            /* 0x0c8 */
 712     uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
 713     uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
 714     uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
 715     uint32_t        external_damage_code;     /* 0x0f4 */
 716     uint64_t        failing_storage_address;  /* 0x0f8 */
 717     uint8_t         pad6[0x120-0x100];        /* 0x100 */
 718     PSW             restart_old_psw;          /* 0x120 */
 719     PSW             external_old_psw;         /* 0x130 */
 720     PSW             svc_old_psw;              /* 0x140 */
 721     PSW             program_old_psw;          /* 0x150 */
 722     PSW             mcck_old_psw;             /* 0x160 */
 723     PSW             io_old_psw;               /* 0x170 */
 724     uint8_t         pad7[0x1a0-0x180];        /* 0x180 */
 725     PSW             restart_psw;              /* 0x1a0 */
 726     PSW             external_new_psw;         /* 0x1b0 */
 727     PSW             svc_new_psw;              /* 0x1c0 */
 728     PSW             program_new_psw;          /* 0x1d0 */
 729     PSW             mcck_new_psw;             /* 0x1e0 */
 730     PSW             io_new_psw;               /* 0x1f0 */
 731     PSW             return_psw;               /* 0x200 */
 732     uint8_t         irb[64];                  /* 0x210 */
 733     uint64_t        sync_enter_timer;         /* 0x250 */
 734     uint64_t        async_enter_timer;        /* 0x258 */
 735     uint64_t        exit_timer;               /* 0x260 */
 736     uint64_t        last_update_timer;        /* 0x268 */
 737     uint64_t        user_timer;               /* 0x270 */
 738     uint64_t        system_timer;             /* 0x278 */
 739     uint64_t        last_update_clock;        /* 0x280 */
 740     uint64_t        steal_clock;              /* 0x288 */
 741     PSW             return_mcck_psw;          /* 0x290 */
 742     uint8_t         pad8[0xc00-0x2a0];        /* 0x2a0 */
 743     /* System info area */
 744     uint64_t        save_area[16];            /* 0xc00 */
 745     uint8_t         pad9[0xd40-0xc80];        /* 0xc80 */
 746     uint64_t        kernel_stack;             /* 0xd40 */
 747     uint64_t        thread_info;              /* 0xd48 */
 748     uint64_t        async_stack;              /* 0xd50 */
 749     uint64_t        kernel_asce;              /* 0xd58 */
 750     uint64_t        user_asce;                /* 0xd60 */
 751     uint64_t        panic_stack;              /* 0xd68 */
 752     uint64_t        user_exec_asce;           /* 0xd70 */
 753     uint8_t         pad10[0xdc0-0xd78];       /* 0xd78 */
 754
 755     /* SMP info area: defined by DJB */
 756     uint64_t        clock_comparator;         /* 0xdc0 */
 757     uint64_t        ext_call_fast;            /* 0xdc8 */
 758     uint64_t        percpu_offset;            /* 0xdd0 */
 759     uint64_t        current_task;             /* 0xdd8 */
 760     uint32_t        softirq_pending;          /* 0xde0 */
 761     uint32_t        pad_0x0de4;               /* 0xde4 */
 762     uint64_t        int_clock;                /* 0xde8 */
 763     uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
 764
 765     /* 0xe00 is used as indicator for dump tools */
 766     /* whether the kernel died with panic() or not */
 767     uint32_t        panic_magic;              /* 0xe00 */
 768
 769     uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
 770
 771     /* 64 bit extparam used for pfault, diag 250 etc  */
 772     uint64_t        ext_params2;               /* 0x11B8 */
 773
 774     uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
 775
 776     /* System info area */
 777
 778     uint64_t        floating_pt_save_area[16]; /* 0x1200 */
 779     uint64_t        gpregs_save_area[16];      /* 0x1280 */
 780     uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
 781     uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
 782     uint32_t        prefixreg_save_area;       /* 0x1318 */
 783     uint32_t        fpt_creg_save_area;        /* 0x131c */
 784     uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
 785     uint32_t        tod_progreg_save_area;     /* 0x1324 */
 786     uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
 787     uint32_t        clock_comp_save_area[2];   /* 0x1330 */
 788     uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
 789     uint32_t        access_regs_save_area[16]; /* 0x1340 */
 790     uint64_t        cregs_save_area[16];       /* 0x1380 */
 791
 792     /* align to the top of the prefix area */
 793
 794     uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
 795 } QEMU_PACKED LowCore;
 796
 797 /* STSI */
 798 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 799 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 800 #define STSI_LEVEL_1            0x0000000010000000ULL
 801 #define STSI_LEVEL_2            0x0000000020000000ULL
 802 #define STSI_LEVEL_3            0x0000000030000000ULL
 803 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 804 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 805 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 806 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 807
 808 /* Basic Machine Configuration */
 809 struct sysib_111 {
 810     uint32_t res1[8];
 811     uint8_t  manuf[16];
 812     uint8_t  type[4];
 813     uint8_t  res2[12];
 814     uint8_t  model[16];
 815     uint8_t  sequence[16];
 816     uint8_t  plant[4];
 817     uint8_t  res3[156];
 818 };
 819
 820 /* Basic Machine CPU */
 821 struct sysib_121 {
 822     uint32_t res1[80];
 823     uint8_t  sequence[16];
 824     uint8_t  plant[4];
 825     uint8_t  res2[2];
 826     uint16_t cpu_addr;
 827     uint8_t  res3[152];
 828 };
 829
 830 /* Basic Machine CPUs */
 831 struct sysib_122 {
 832     uint8_t res1[32];
 833     uint32_t capability;
 834     uint16_t total_cpus;
 835     uint16_t active_cpus;
 836     uint16_t standby_cpus;
 837     uint16_t reserved_cpus;
 838     uint16_t adjustments[2026];
 839 };
 840
 841 /* LPAR CPU */
 842 struct sysib_221 {
 843     uint32_t res1[80];
 844     uint8_t  sequence[16];
 845     uint8_t  plant[4];
 846     uint16_t cpu_id;
 847     uint16_t cpu_addr;
 848     uint8_t  res3[152];
 849 };
 850
 851 /* LPAR CPUs */
 852 struct sysib_222 {
 853     uint32_t res1[32];
 854     uint16_t lpar_num;
 855     uint8_t  res2;
 856     uint8_t  lcpuc;
 857     uint16_t total_cpus;
 858     uint16_t conf_cpus;
 859     uint16_t standby_cpus;
 860     uint16_t reserved_cpus;
 861     uint8_t  name[8];
 862     uint32_t caf;
 863     uint8_t  res3[16];
 864     uint16_t dedicated_cpus;
 865     uint16_t shared_cpus;
 866     uint8_t  res4[180];
 867 };
 868
 869 /* VM CPUs */
 870 struct sysib_322 {
 871     uint8_t  res1[31];
 872     uint8_t  count;
 873     struct {
 874         uint8_t  res2[4];
 875         uint16_t total_cpus;
 876         uint16_t conf_cpus;
 877         uint16_t standby_cpus;
 878         uint16_t reserved_cpus;
 879         uint8_t  name[8];
 880         uint32_t caf;
 881         uint8_t  cpi[16];
 882         uint8_t  res3[24];
 883     } vm[8];
 884     uint8_t res4[3552];
 885 };
 886
 887 /* MMU defines */
 888 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 889 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 890 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 891 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 892 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 893 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 894 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 895 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 896 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 897 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 898 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 899 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 900
 901 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 902 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 903 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 904 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 905 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 906 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 907 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 908
 909 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 910 #define _SEGMENT_ENTRY_FC       0x400     /* format control                   */
 911 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 912 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 913
 914 #define _PAGE_RO        0x200            /* HW read-only bit  */
 915 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 916
 917 #define SK_C                    (0x1 << 1)
 918 #define SK_R                    (0x1 << 2)
 919 #define SK_F                    (0x1 << 3)
 920 #define SK_ACC_MASK             (0xf << 4)
 921
 922 #define SIGP_SENSE             0x01
 923 #define SIGP_EXTERNAL_CALL     0x02
 924 #define SIGP_EMERGENCY         0x03
 925 #define SIGP_START             0x04
 926 #define SIGP_STOP              0x05
 927 #define SIGP_RESTART           0x06
 928 #define SIGP_STOP_STORE_STATUS 0x09
 929 #define SIGP_INITIAL_CPU_RESET 0x0b
 930 #define SIGP_CPU_RESET         0x0c
 931 #define SIGP_SET_PREFIX        0x0d
 932 #define SIGP_STORE_STATUS_ADDR 0x0e
 933 #define SIGP_SET_ARCH          0x12
 934
 935 /* cpu status bits */
 936 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 937 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 938 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 939 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 940 #define SIGP_STAT_STOPPED           0x00000040UL
 941 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 942 #define SIGP_STAT_CHECK_STOP        0x00000010UL
 943 #define SIGP_STAT_INOPERATIVE       0x00000004UL
 944 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
 945 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 946
 947 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
 948 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 949                   target_ulong *raddr, int *flags);
 950 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
 951 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
 952                  uint64_t vr);
 953
 954 #define TARGET_HAS_ICE 1
 955
 956 /* The value of the TOD clock for 1.1.1970. */
 957 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
 958
 959 /* Converts ns to s390's clock format */
 960 static inline uint64_t time2tod(uint64_t ns) {
 961     return (ns << 9) / 125;
 962 }
 963
 964 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
 965                                   uint64_t param64)
 966 {
 967     CPUS390XState *env = &cpu->env;
 968
 969     if (env->ext_index == MAX_EXT_QUEUE - 1) {
 970         /* ugh - can't queue anymore. Let's drop. */
 971         return;
 972     }
 973
 974     env->ext_index++;
 975     assert(env->ext_index < MAX_EXT_QUEUE);
 976
 977     env->ext_queue[env->ext_index].code = code;
 978     env->ext_queue[env->ext_index].param = param;
 979     env->ext_queue[env->ext_index].param64 = param64;
 980
 981     env->pending_int |= INTERRUPT_EXT;
 982     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
 983 }
 984
 985 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
 986                                  uint16_t subchannel_number,
 987                                  uint32_t io_int_parm, uint32_t io_int_word)
 988 {
 989     CPUS390XState *env = &cpu->env;
 990     int isc = IO_INT_WORD_ISC(io_int_word);
 991
 992     if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
 993         /* ugh - can't queue anymore. Let's drop. */
 994         return;
 995     }
 996
 997     env->io_index[isc]++;
 998     assert(env->io_index[isc] < MAX_IO_QUEUE);
 999
1000     env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1001     env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1002     env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1003     env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1004
1005     env->pending_int |= INTERRUPT_IO;
1006     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1007 }
1008
1009 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
1010 {
1011     CPUS390XState *env = &cpu->env;
1012
1013     if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1014         /* ugh - can't queue anymore. Let's drop. */
1015         return;
1016     }
1017
1018     env->mchk_index++;
1019     assert(env->mchk_index < MAX_MCHK_QUEUE);
1020
1021     env->mchk_queue[env->mchk_index].type = 1;
1022
1023     env->pending_int |= INTERRUPT_MCHK;
1024     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1025 }
1026
1027 /* from s390-virtio-ccw */
1028 #define MEM_SECTION_SIZE             0x10000000UL
1029 #define MAX_AVAIL_SLOTS              32
1030
1031 /* fpu_helper.c */
1032 uint32_t set_cc_nz_f32(float32 v);
1033 uint32_t set_cc_nz_f64(float64 v);
1034 uint32_t set_cc_nz_f128(float128 v);
1035
1036 /* misc_helper.c */
1037 #ifndef CONFIG_USER_ONLY
1038 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1039 #endif
1040 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1041 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1042                                      uintptr_t retaddr);
1043
1044 #ifdef CONFIG_KVM
1045 void kvm_s390_io_interrupt(uint16_t subchannel_id,
1046                            uint16_t subchannel_nr, uint32_t io_int_parm,
1047                            uint32_t io_int_word);
1048 void kvm_s390_crw_mchk(void);
1049 void kvm_s390_enable_css_support(S390CPU *cpu);
1050 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1051                                     int vq, bool assign);
1052 int kvm_s390_cpu_restart(S390CPU *cpu);
1053 int kvm_s390_get_memslot_count(KVMState *s);
1054 void kvm_s390_clear_cmma_callback(void *opaque);
1055 #else
1056 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1057                                         uint16_t subchannel_nr,
1058                                         uint32_t io_int_parm,
1059                                         uint32_t io_int_word)
1060 {
1061 }
1062 static inline void kvm_s390_crw_mchk(void)
1063 {
1064 }
1065 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1066 {
1067 }
1068 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1069                                                   uint32_t sch, int vq,
1070                                                   bool assign)
1071 {
1072     return -ENOSYS;
1073 }
1074 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1075 {
1076     return -ENOSYS;
1077 }
1078 static inline void kvm_s390_clear_cmma_callback(void *opaque)
1079 {
1080 }
1081 static inline int kvm_s390_get_memslot_count(KVMState *s)
1082 {
1083   return MAX_AVAIL_SLOTS;
1084 }
1085 #endif
1086
1087 static inline void cmma_reset(S390CPU *cpu)
1088 {
1089     if (kvm_enabled()) {
1090         CPUState *cs = CPU(cpu);
1091         kvm_s390_clear_cmma_callback(cs->kvm_state);
1092     }
1093 }
1094
1095 static inline int s390_cpu_restart(S390CPU *cpu)
1096 {
1097     if (kvm_enabled()) {
1098         return kvm_s390_cpu_restart(cpu);
1099     }
1100     return -ENOSYS;
1101 }
1102
1103 static inline int s390_get_memslot_count(KVMState *s)
1104 {
1105     if (kvm_enabled()) {
1106         return kvm_s390_get_memslot_count(s);
1107     } else {
1108         return MAX_AVAIL_SLOTS;
1109     }
1110 }
1111
1112 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1113                        uint32_t io_int_parm, uint32_t io_int_word);
1114 void s390_crw_mchk(void);
1115
1116 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1117                                               uint32_t sch_id, int vq,
1118                                               bool assign)
1119 {
1120     if (kvm_enabled()) {
1121         return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1122     } else {
1123         return -ENOSYS;
1124     }
1125 }
1126
1127 #endif