2 * CRIS emulation for qemu: main translation routines.
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 * The condition code translation is in need of attention.
27 #include "disas/disas.h"
31 #include "crisv32-decode.h"
38 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 # define LOG_DIS(...) do { } while (0)
44 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
45 #define BUG_ON(x) ({if (x) BUG();})
49 /* Used by the decoder. */
50 #define EXTRACT_FIELD(src, start, end) \
51 (((src) >> start) & ((1 << (end - start + 1)) - 1))
53 #define CC_MASK_NZ 0xc
54 #define CC_MASK_NZV 0xe
55 #define CC_MASK_NZVC 0xf
56 #define CC_MASK_RNZV 0x10e
58 static TCGv_ptr cpu_env
;
59 static TCGv cpu_R
[16];
60 static TCGv cpu_PR
[16];
64 static TCGv cc_result
;
69 static TCGv env_btaken
;
70 static TCGv env_btarget
;
73 #include "exec/gen-icount.h"
75 /* This is the state at translation time. */
76 typedef struct DisasContext
{
81 unsigned int (*decoder
)(CPUCRISState
*env
, struct DisasContext
*dc
);
86 unsigned int zsize
, zzsize
;
100 int cc_size_uptodate
; /* -1 invalid or last written value. */
102 int cc_x_uptodate
; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
103 int flags_uptodate
; /* Wether or not $ccs is uptodate. */
104 int flagx_known
; /* Wether or not flags_x has the x flag known at
108 int clear_x
; /* Clear x after this insn? */
109 int clear_prefix
; /* Clear prefix after this insn? */
110 int clear_locked_irq
; /* Clear the irq lockout. */
111 int cpustate_changed
;
112 unsigned int tb_flags
; /* tb dependent flags. */
117 #define JMP_DIRECT_CC 2
118 #define JMP_INDIRECT 3
119 int jmp
; /* 0=nojmp, 1=direct, 2=indirect. */
124 struct TranslationBlock
*tb
;
125 int singlestep_enabled
;
128 static void gen_BUG(DisasContext
*dc
, const char *file
, int line
)
130 printf("BUG: pc=%x %s %d\n", dc
->pc
, file
, line
);
131 qemu_log("BUG: pc=%x %s %d\n", dc
->pc
, file
, line
);
132 cpu_abort(dc
->env
, "%s:%d\n", file
, line
);
135 static const char *regnames
[] =
137 "$r0", "$r1", "$r2", "$r3",
138 "$r4", "$r5", "$r6", "$r7",
139 "$r8", "$r9", "$r10", "$r11",
140 "$r12", "$r13", "$sp", "$acr",
142 static const char *pregnames
[] =
144 "$bz", "$vr", "$pid", "$srs",
145 "$wz", "$exs", "$eda", "$mof",
146 "$dz", "$ebp", "$erp", "$srp",
147 "$nrp", "$ccs", "$usp", "$spc",
150 /* We need this table to handle preg-moves with implicit width. */
151 static int preg_sizes
[] = {
162 #define t_gen_mov_TN_env(tn, member) \
163 _t_gen_mov_TN_env((tn), offsetof(CPUCRISState, member))
164 #define t_gen_mov_env_TN(member, tn) \
165 _t_gen_mov_env_TN(offsetof(CPUCRISState, member), (tn))
167 static inline void t_gen_mov_TN_reg(TCGv tn
, int r
)
169 if (r
< 0 || r
> 15) {
170 fprintf(stderr
, "wrong register read $r%d\n", r
);
172 tcg_gen_mov_tl(tn
, cpu_R
[r
]);
174 static inline void t_gen_mov_reg_TN(int r
, TCGv tn
)
176 if (r
< 0 || r
> 15) {
177 fprintf(stderr
, "wrong register write $r%d\n", r
);
179 tcg_gen_mov_tl(cpu_R
[r
], tn
);
182 static inline void _t_gen_mov_TN_env(TCGv tn
, int offset
)
184 if (offset
> sizeof(CPUCRISState
)) {
185 fprintf(stderr
, "wrong load from env from off=%d\n", offset
);
187 tcg_gen_ld_tl(tn
, cpu_env
, offset
);
189 static inline void _t_gen_mov_env_TN(int offset
, TCGv tn
)
191 if (offset
> sizeof(CPUCRISState
)) {
192 fprintf(stderr
, "wrong store to env at off=%d\n", offset
);
194 tcg_gen_st_tl(tn
, cpu_env
, offset
);
197 static inline void t_gen_mov_TN_preg(TCGv tn
, int r
)
199 if (r
< 0 || r
> 15) {
200 fprintf(stderr
, "wrong register read $p%d\n", r
);
202 if (r
== PR_BZ
|| r
== PR_WZ
|| r
== PR_DZ
) {
203 tcg_gen_mov_tl(tn
, tcg_const_tl(0));
204 } else if (r
== PR_VR
) {
205 tcg_gen_mov_tl(tn
, tcg_const_tl(32));
207 tcg_gen_mov_tl(tn
, cpu_PR
[r
]);
210 static inline void t_gen_mov_preg_TN(DisasContext
*dc
, int r
, TCGv tn
)
212 if (r
< 0 || r
> 15) {
213 fprintf(stderr
, "wrong register write $p%d\n", r
);
215 if (r
== PR_BZ
|| r
== PR_WZ
|| r
== PR_DZ
) {
217 } else if (r
== PR_SRS
) {
218 tcg_gen_andi_tl(cpu_PR
[r
], tn
, 3);
221 gen_helper_tlb_flush_pid(cpu_env
, tn
);
223 if (dc
->tb_flags
& S_FLAG
&& r
== PR_SPC
) {
224 gen_helper_spc_write(cpu_env
, tn
);
225 } else if (r
== PR_CCS
) {
226 dc
->cpustate_changed
= 1;
228 tcg_gen_mov_tl(cpu_PR
[r
], tn
);
232 /* Sign extend at translation time. */
233 static int sign_extend(unsigned int val
, unsigned int width
)
245 static int cris_fetch(CPUCRISState
*env
, DisasContext
*dc
, uint32_t addr
,
246 unsigned int size
, unsigned int sign
)
253 r
= cpu_ldl_code(env
, addr
);
259 r
= cpu_ldsw_code(env
, addr
);
261 r
= cpu_lduw_code(env
, addr
);
268 r
= cpu_ldsb_code(env
, addr
);
270 r
= cpu_ldub_code(env
, addr
);
275 cpu_abort(dc
->env
, "Invalid fetch size %d\n", size
);
281 static void cris_lock_irq(DisasContext
*dc
)
283 dc
->clear_locked_irq
= 0;
284 t_gen_mov_env_TN(locked_irq
, tcg_const_tl(1));
287 static inline void t_gen_raise_exception(uint32_t index
)
289 TCGv_i32 tmp
= tcg_const_i32(index
);
290 gen_helper_raise_exception(cpu_env
, tmp
);
291 tcg_temp_free_i32(tmp
);
294 static void t_gen_lsl(TCGv d
, TCGv a
, TCGv b
)
299 t_31
= tcg_const_tl(31);
300 tcg_gen_shl_tl(d
, a
, b
);
302 tcg_gen_sub_tl(t0
, t_31
, b
);
303 tcg_gen_sar_tl(t0
, t0
, t_31
);
304 tcg_gen_and_tl(t0
, t0
, d
);
305 tcg_gen_xor_tl(d
, d
, t0
);
310 static void t_gen_lsr(TCGv d
, TCGv a
, TCGv b
)
315 t_31
= tcg_temp_new();
316 tcg_gen_shr_tl(d
, a
, b
);
318 tcg_gen_movi_tl(t_31
, 31);
319 tcg_gen_sub_tl(t0
, t_31
, b
);
320 tcg_gen_sar_tl(t0
, t0
, t_31
);
321 tcg_gen_and_tl(t0
, t0
, d
);
322 tcg_gen_xor_tl(d
, d
, t0
);
327 static void t_gen_asr(TCGv d
, TCGv a
, TCGv b
)
332 t_31
= tcg_temp_new();
333 tcg_gen_sar_tl(d
, a
, b
);
335 tcg_gen_movi_tl(t_31
, 31);
336 tcg_gen_sub_tl(t0
, t_31
, b
);
337 tcg_gen_sar_tl(t0
, t0
, t_31
);
338 tcg_gen_or_tl(d
, d
, t0
);
343 static void t_gen_cris_dstep(TCGv d
, TCGv a
, TCGv b
)
347 l1
= gen_new_label();
354 tcg_gen_shli_tl(d
, a
, 1);
355 tcg_gen_brcond_tl(TCG_COND_LTU
, d
, b
, l1
);
356 tcg_gen_sub_tl(d
, d
, b
);
360 static void t_gen_cris_mstep(TCGv d
, TCGv a
, TCGv b
, TCGv ccs
)
370 tcg_gen_shli_tl(d
, a
, 1);
371 tcg_gen_shli_tl(t
, ccs
, 31 - 3);
372 tcg_gen_sari_tl(t
, t
, 31);
373 tcg_gen_and_tl(t
, t
, b
);
374 tcg_gen_add_tl(d
, d
, t
);
378 /* Extended arithmetics on CRIS. */
379 static inline void t_gen_add_flag(TCGv d
, int flag
)
384 t_gen_mov_TN_preg(c
, PR_CCS
);
385 /* Propagate carry into d. */
386 tcg_gen_andi_tl(c
, c
, 1 << flag
);
388 tcg_gen_shri_tl(c
, c
, flag
);
390 tcg_gen_add_tl(d
, d
, c
);
394 static inline void t_gen_addx_carry(DisasContext
*dc
, TCGv d
)
396 if (dc
->flagx_known
) {
401 t_gen_mov_TN_preg(c
, PR_CCS
);
402 /* C flag is already at bit 0. */
403 tcg_gen_andi_tl(c
, c
, C_FLAG
);
404 tcg_gen_add_tl(d
, d
, c
);
412 t_gen_mov_TN_preg(x
, PR_CCS
);
413 tcg_gen_mov_tl(c
, x
);
415 /* Propagate carry into d if X is set. Branch free. */
416 tcg_gen_andi_tl(c
, c
, C_FLAG
);
417 tcg_gen_andi_tl(x
, x
, X_FLAG
);
418 tcg_gen_shri_tl(x
, x
, 4);
420 tcg_gen_and_tl(x
, x
, c
);
421 tcg_gen_add_tl(d
, d
, x
);
427 static inline void t_gen_subx_carry(DisasContext
*dc
, TCGv d
)
429 if (dc
->flagx_known
) {
434 t_gen_mov_TN_preg(c
, PR_CCS
);
435 /* C flag is already at bit 0. */
436 tcg_gen_andi_tl(c
, c
, C_FLAG
);
437 tcg_gen_sub_tl(d
, d
, c
);
445 t_gen_mov_TN_preg(x
, PR_CCS
);
446 tcg_gen_mov_tl(c
, x
);
448 /* Propagate carry into d if X is set. Branch free. */
449 tcg_gen_andi_tl(c
, c
, C_FLAG
);
450 tcg_gen_andi_tl(x
, x
, X_FLAG
);
451 tcg_gen_shri_tl(x
, x
, 4);
453 tcg_gen_and_tl(x
, x
, c
);
454 tcg_gen_sub_tl(d
, d
, x
);
460 /* Swap the two bytes within each half word of the s operand.
461 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
462 static inline void t_gen_swapb(TCGv d
, TCGv s
)
467 org_s
= tcg_temp_new();
469 /* d and s may refer to the same object. */
470 tcg_gen_mov_tl(org_s
, s
);
471 tcg_gen_shli_tl(t
, org_s
, 8);
472 tcg_gen_andi_tl(d
, t
, 0xff00ff00);
473 tcg_gen_shri_tl(t
, org_s
, 8);
474 tcg_gen_andi_tl(t
, t
, 0x00ff00ff);
475 tcg_gen_or_tl(d
, d
, t
);
477 tcg_temp_free(org_s
);
480 /* Swap the halfwords of the s operand. */
481 static inline void t_gen_swapw(TCGv d
, TCGv s
)
484 /* d and s refer the same object. */
486 tcg_gen_mov_tl(t
, s
);
487 tcg_gen_shli_tl(d
, t
, 16);
488 tcg_gen_shri_tl(t
, t
, 16);
489 tcg_gen_or_tl(d
, d
, t
);
493 /* Reverse the within each byte.
494 T0 = (((T0 << 7) & 0x80808080) |
495 ((T0 << 5) & 0x40404040) |
496 ((T0 << 3) & 0x20202020) |
497 ((T0 << 1) & 0x10101010) |
498 ((T0 >> 1) & 0x08080808) |
499 ((T0 >> 3) & 0x04040404) |
500 ((T0 >> 5) & 0x02020202) |
501 ((T0 >> 7) & 0x01010101));
503 static inline void t_gen_swapr(TCGv d
, TCGv s
)
506 int shift
; /* LSL when positive, LSR when negative. */
521 /* d and s refer the same object. */
523 org_s
= tcg_temp_new();
524 tcg_gen_mov_tl(org_s
, s
);
526 tcg_gen_shli_tl(t
, org_s
, bitrev
[0].shift
);
527 tcg_gen_andi_tl(d
, t
, bitrev
[0].mask
);
528 for (i
= 1; i
< ARRAY_SIZE(bitrev
); i
++) {
529 if (bitrev
[i
].shift
>= 0) {
530 tcg_gen_shli_tl(t
, org_s
, bitrev
[i
].shift
);
532 tcg_gen_shri_tl(t
, org_s
, -bitrev
[i
].shift
);
534 tcg_gen_andi_tl(t
, t
, bitrev
[i
].mask
);
535 tcg_gen_or_tl(d
, d
, t
);
538 tcg_temp_free(org_s
);
541 static void t_gen_cc_jmp(TCGv pc_true
, TCGv pc_false
)
545 l1
= gen_new_label();
547 /* Conditional jmp. */
548 tcg_gen_mov_tl(env_pc
, pc_false
);
549 tcg_gen_brcondi_tl(TCG_COND_EQ
, env_btaken
, 0, l1
);
550 tcg_gen_mov_tl(env_pc
, pc_true
);
554 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
556 TranslationBlock
*tb
;
558 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
560 tcg_gen_movi_tl(env_pc
, dest
);
561 tcg_gen_exit_tb((uintptr_t)tb
+ n
);
563 tcg_gen_movi_tl(env_pc
, dest
);
568 static inline void cris_clear_x_flag(DisasContext
*dc
)
570 if (dc
->flagx_known
&& dc
->flags_x
) {
571 dc
->flags_uptodate
= 0;
578 static void cris_flush_cc_state(DisasContext
*dc
)
580 if (dc
->cc_size_uptodate
!= dc
->cc_size
) {
581 tcg_gen_movi_tl(cc_size
, dc
->cc_size
);
582 dc
->cc_size_uptodate
= dc
->cc_size
;
584 tcg_gen_movi_tl(cc_op
, dc
->cc_op
);
585 tcg_gen_movi_tl(cc_mask
, dc
->cc_mask
);
588 static void cris_evaluate_flags(DisasContext
*dc
)
590 if (dc
->flags_uptodate
) {
594 cris_flush_cc_state(dc
);
598 gen_helper_evaluate_flags_mcp(cpu_PR
[PR_CCS
], cpu_env
,
599 cpu_PR
[PR_CCS
], cc_src
,
603 gen_helper_evaluate_flags_muls(cpu_PR
[PR_CCS
], cpu_env
,
604 cpu_PR
[PR_CCS
], cc_result
,
608 gen_helper_evaluate_flags_mulu(cpu_PR
[PR_CCS
], cpu_env
,
609 cpu_PR
[PR_CCS
], cc_result
,
619 switch (dc
->cc_size
) {
621 gen_helper_evaluate_flags_move_4(cpu_PR
[PR_CCS
],
622 cpu_env
, cpu_PR
[PR_CCS
], cc_result
);
625 gen_helper_evaluate_flags_move_2(cpu_PR
[PR_CCS
],
626 cpu_env
, cpu_PR
[PR_CCS
], cc_result
);
629 gen_helper_evaluate_flags(cpu_env
);
638 if (dc
->cc_size
== 4) {
639 gen_helper_evaluate_flags_sub_4(cpu_PR
[PR_CCS
], cpu_env
,
640 cpu_PR
[PR_CCS
], cc_src
, cc_dest
, cc_result
);
642 gen_helper_evaluate_flags(cpu_env
);
647 switch (dc
->cc_size
) {
649 gen_helper_evaluate_flags_alu_4(cpu_PR
[PR_CCS
], cpu_env
,
650 cpu_PR
[PR_CCS
], cc_src
, cc_dest
, cc_result
);
653 gen_helper_evaluate_flags(cpu_env
);
659 if (dc
->flagx_known
) {
661 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], X_FLAG
);
662 } else if (dc
->cc_op
== CC_OP_FLAGS
) {
663 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~X_FLAG
);
666 dc
->flags_uptodate
= 1;
669 static void cris_cc_mask(DisasContext
*dc
, unsigned int mask
)
678 /* Check if we need to evaluate the condition codes due to
680 ovl
= (dc
->cc_mask
^ mask
) & ~mask
;
682 /* TODO: optimize this case. It trigs all the time. */
683 cris_evaluate_flags(dc
);
689 static void cris_update_cc_op(DisasContext
*dc
, int op
, int size
)
693 dc
->flags_uptodate
= 0;
696 static inline void cris_update_cc_x(DisasContext
*dc
)
698 /* Save the x flag state at the time of the cc snapshot. */
699 if (dc
->flagx_known
) {
700 if (dc
->cc_x_uptodate
== (2 | dc
->flags_x
)) {
703 tcg_gen_movi_tl(cc_x
, dc
->flags_x
);
704 dc
->cc_x_uptodate
= 2 | dc
->flags_x
;
706 tcg_gen_andi_tl(cc_x
, cpu_PR
[PR_CCS
], X_FLAG
);
707 dc
->cc_x_uptodate
= 1;
711 /* Update cc prior to executing ALU op. Needs source operands untouched. */
712 static void cris_pre_alu_update_cc(DisasContext
*dc
, int op
,
713 TCGv dst
, TCGv src
, int size
)
716 cris_update_cc_op(dc
, op
, size
);
717 tcg_gen_mov_tl(cc_src
, src
);
725 && op
!= CC_OP_LSL
) {
726 tcg_gen_mov_tl(cc_dest
, dst
);
729 cris_update_cc_x(dc
);
733 /* Update cc after executing ALU op. needs the result. */
734 static inline void cris_update_result(DisasContext
*dc
, TCGv res
)
737 tcg_gen_mov_tl(cc_result
, res
);
741 /* Returns one if the write back stage should execute. */
742 static void cris_alu_op_exec(DisasContext
*dc
, int op
,
743 TCGv dst
, TCGv a
, TCGv b
, int size
)
745 /* Emit the ALU insns. */
748 tcg_gen_add_tl(dst
, a
, b
);
749 /* Extended arithmetics. */
750 t_gen_addx_carry(dc
, dst
);
753 tcg_gen_add_tl(dst
, a
, b
);
754 t_gen_add_flag(dst
, 0); /* C_FLAG. */
757 tcg_gen_add_tl(dst
, a
, b
);
758 t_gen_add_flag(dst
, 8); /* R_FLAG. */
761 tcg_gen_sub_tl(dst
, a
, b
);
762 /* Extended arithmetics. */
763 t_gen_subx_carry(dc
, dst
);
766 tcg_gen_mov_tl(dst
, b
);
769 tcg_gen_or_tl(dst
, a
, b
);
772 tcg_gen_and_tl(dst
, a
, b
);
775 tcg_gen_xor_tl(dst
, a
, b
);
778 t_gen_lsl(dst
, a
, b
);
781 t_gen_lsr(dst
, a
, b
);
784 t_gen_asr(dst
, a
, b
);
787 tcg_gen_neg_tl(dst
, b
);
788 /* Extended arithmetics. */
789 t_gen_subx_carry(dc
, dst
);
792 gen_helper_lz(dst
, b
);
795 tcg_gen_muls2_tl(dst
, cpu_PR
[PR_MOF
], a
, b
);
798 tcg_gen_mulu2_tl(dst
, cpu_PR
[PR_MOF
], a
, b
);
801 t_gen_cris_dstep(dst
, a
, b
);
804 t_gen_cris_mstep(dst
, a
, b
, cpu_PR
[PR_CCS
]);
809 l1
= gen_new_label();
810 tcg_gen_mov_tl(dst
, a
);
811 tcg_gen_brcond_tl(TCG_COND_LEU
, a
, b
, l1
);
812 tcg_gen_mov_tl(dst
, b
);
817 tcg_gen_sub_tl(dst
, a
, b
);
818 /* Extended arithmetics. */
819 t_gen_subx_carry(dc
, dst
);
822 qemu_log("illegal ALU op.\n");
828 tcg_gen_andi_tl(dst
, dst
, 0xff);
829 } else if (size
== 2) {
830 tcg_gen_andi_tl(dst
, dst
, 0xffff);
834 static void cris_alu(DisasContext
*dc
, int op
,
835 TCGv d
, TCGv op_a
, TCGv op_b
, int size
)
842 if (op
== CC_OP_CMP
) {
843 tmp
= tcg_temp_new();
845 } else if (size
== 4) {
849 tmp
= tcg_temp_new();
853 cris_pre_alu_update_cc(dc
, op
, op_a
, op_b
, size
);
854 cris_alu_op_exec(dc
, op
, tmp
, op_a
, op_b
, size
);
855 cris_update_result(dc
, tmp
);
860 tcg_gen_andi_tl(d
, d
, ~0xff);
862 tcg_gen_andi_tl(d
, d
, ~0xffff);
864 tcg_gen_or_tl(d
, d
, tmp
);
866 if (!TCGV_EQUAL(tmp
, d
)) {
871 static int arith_cc(DisasContext
*dc
)
875 case CC_OP_ADDC
: return 1;
876 case CC_OP_ADD
: return 1;
877 case CC_OP_SUB
: return 1;
878 case CC_OP_DSTEP
: return 1;
879 case CC_OP_LSL
: return 1;
880 case CC_OP_LSR
: return 1;
881 case CC_OP_ASR
: return 1;
882 case CC_OP_CMP
: return 1;
883 case CC_OP_NEG
: return 1;
884 case CC_OP_OR
: return 1;
885 case CC_OP_AND
: return 1;
886 case CC_OP_XOR
: return 1;
887 case CC_OP_MULU
: return 1;
888 case CC_OP_MULS
: return 1;
896 static void gen_tst_cc (DisasContext
*dc
, TCGv cc
, int cond
)
898 int arith_opt
, move_opt
;
900 /* TODO: optimize more condition codes. */
903 * If the flags are live, we've gotta look into the bits of CCS.
904 * Otherwise, if we just did an arithmetic operation we try to
905 * evaluate the condition code faster.
907 * When this function is done, T0 should be non-zero if the condition
910 arith_opt
= arith_cc(dc
) && !dc
->flags_uptodate
;
911 move_opt
= (dc
->cc_op
== CC_OP_MOVE
);
914 if ((arith_opt
|| move_opt
)
915 && dc
->cc_x_uptodate
!= (2 | X_FLAG
)) {
916 tcg_gen_setcond_tl(TCG_COND_EQ
, cc
,
917 cc_result
, tcg_const_tl(0));
919 cris_evaluate_flags(dc
);
921 cpu_PR
[PR_CCS
], Z_FLAG
);
925 if ((arith_opt
|| move_opt
)
926 && dc
->cc_x_uptodate
!= (2 | X_FLAG
)) {
927 tcg_gen_mov_tl(cc
, cc_result
);
929 cris_evaluate_flags(dc
);
930 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
932 tcg_gen_andi_tl(cc
, cc
, Z_FLAG
);
936 cris_evaluate_flags(dc
);
937 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], C_FLAG
);
940 cris_evaluate_flags(dc
);
941 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
], C_FLAG
);
942 tcg_gen_andi_tl(cc
, cc
, C_FLAG
);
945 cris_evaluate_flags(dc
);
946 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], V_FLAG
);
949 cris_evaluate_flags(dc
);
950 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
952 tcg_gen_andi_tl(cc
, cc
, V_FLAG
);
955 if (arith_opt
|| move_opt
) {
958 if (dc
->cc_size
== 1) {
960 } else if (dc
->cc_size
== 2) {
964 tcg_gen_shri_tl(cc
, cc_result
, bits
);
965 tcg_gen_xori_tl(cc
, cc
, 1);
967 cris_evaluate_flags(dc
);
968 tcg_gen_xori_tl(cc
, cpu_PR
[PR_CCS
],
970 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
974 if (arith_opt
|| move_opt
) {
977 if (dc
->cc_size
== 1) {
979 } else if (dc
->cc_size
== 2) {
983 tcg_gen_shri_tl(cc
, cc_result
, bits
);
984 tcg_gen_andi_tl(cc
, cc
, 1);
986 cris_evaluate_flags(dc
);
987 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
],
992 cris_evaluate_flags(dc
);
993 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
],
997 cris_evaluate_flags(dc
);
1001 tmp
= tcg_temp_new();
1002 tcg_gen_xori_tl(tmp
, cpu_PR
[PR_CCS
],
1004 /* Overlay the C flag on top of the Z. */
1005 tcg_gen_shli_tl(cc
, tmp
, 2);
1006 tcg_gen_and_tl(cc
, tmp
, cc
);
1007 tcg_gen_andi_tl(cc
, cc
, Z_FLAG
);
1013 cris_evaluate_flags(dc
);
1014 /* Overlay the V flag on top of the N. */
1015 tcg_gen_shli_tl(cc
, cpu_PR
[PR_CCS
], 2);
1017 cpu_PR
[PR_CCS
], cc
);
1018 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
1019 tcg_gen_xori_tl(cc
, cc
, N_FLAG
);
1022 cris_evaluate_flags(dc
);
1023 /* Overlay the V flag on top of the N. */
1024 tcg_gen_shli_tl(cc
, cpu_PR
[PR_CCS
], 2);
1026 cpu_PR
[PR_CCS
], cc
);
1027 tcg_gen_andi_tl(cc
, cc
, N_FLAG
);
1030 cris_evaluate_flags(dc
);
1037 /* To avoid a shift we overlay everything on
1039 tcg_gen_shri_tl(n
, cpu_PR
[PR_CCS
], 2);
1040 tcg_gen_shri_tl(z
, cpu_PR
[PR_CCS
], 1);
1042 tcg_gen_xori_tl(z
, z
, 2);
1044 tcg_gen_xor_tl(n
, n
, cpu_PR
[PR_CCS
]);
1045 tcg_gen_xori_tl(n
, n
, 2);
1046 tcg_gen_and_tl(cc
, z
, n
);
1047 tcg_gen_andi_tl(cc
, cc
, 2);
1054 cris_evaluate_flags(dc
);
1061 /* To avoid a shift we overlay everything on
1063 tcg_gen_shri_tl(n
, cpu_PR
[PR_CCS
], 2);
1064 tcg_gen_shri_tl(z
, cpu_PR
[PR_CCS
], 1);
1066 tcg_gen_xor_tl(n
, n
, cpu_PR
[PR_CCS
]);
1067 tcg_gen_or_tl(cc
, z
, n
);
1068 tcg_gen_andi_tl(cc
, cc
, 2);
1075 cris_evaluate_flags(dc
);
1076 tcg_gen_andi_tl(cc
, cpu_PR
[PR_CCS
], P_FLAG
);
1079 tcg_gen_movi_tl(cc
, 1);
1087 static void cris_store_direct_jmp(DisasContext
*dc
)
1089 /* Store the direct jmp state into the cpu-state. */
1090 if (dc
->jmp
== JMP_DIRECT
|| dc
->jmp
== JMP_DIRECT_CC
) {
1091 if (dc
->jmp
== JMP_DIRECT
) {
1092 tcg_gen_movi_tl(env_btaken
, 1);
1094 tcg_gen_movi_tl(env_btarget
, dc
->jmp_pc
);
1095 dc
->jmp
= JMP_INDIRECT
;
1099 static void cris_prepare_cc_branch (DisasContext
*dc
,
1100 int offset
, int cond
)
1102 /* This helps us re-schedule the micro-code to insns in delay-slots
1103 before the actual jump. */
1104 dc
->delayed_branch
= 2;
1105 dc
->jmp
= JMP_DIRECT_CC
;
1106 dc
->jmp_pc
= dc
->pc
+ offset
;
1108 gen_tst_cc(dc
, env_btaken
, cond
);
1109 tcg_gen_movi_tl(env_btarget
, dc
->jmp_pc
);
1113 /* jumps, when the dest is in a live reg for example. Direct should be set
1114 when the dest addr is constant to allow tb chaining. */
1115 static inline void cris_prepare_jmp (DisasContext
*dc
, unsigned int type
)
1117 /* This helps us re-schedule the micro-code to insns in delay-slots
1118 before the actual jump. */
1119 dc
->delayed_branch
= 2;
1121 if (type
== JMP_INDIRECT
) {
1122 tcg_gen_movi_tl(env_btaken
, 1);
1126 static void gen_load64(DisasContext
*dc
, TCGv_i64 dst
, TCGv addr
)
1128 int mem_index
= cpu_mmu_index(dc
->env
);
1130 /* If we get a fault on a delayslot we must keep the jmp state in
1131 the cpu-state to be able to re-execute the jmp. */
1132 if (dc
->delayed_branch
== 1) {
1133 cris_store_direct_jmp(dc
);
1136 tcg_gen_qemu_ld64(dst
, addr
, mem_index
);
1139 static void gen_load(DisasContext
*dc
, TCGv dst
, TCGv addr
,
1140 unsigned int size
, int sign
)
1142 int mem_index
= cpu_mmu_index(dc
->env
);
1144 /* If we get a fault on a delayslot we must keep the jmp state in
1145 the cpu-state to be able to re-execute the jmp. */
1146 if (dc
->delayed_branch
== 1) {
1147 cris_store_direct_jmp(dc
);
1152 tcg_gen_qemu_ld8s(dst
, addr
, mem_index
);
1154 tcg_gen_qemu_ld8u(dst
, addr
, mem_index
);
1156 } else if (size
== 2) {
1158 tcg_gen_qemu_ld16s(dst
, addr
, mem_index
);
1160 tcg_gen_qemu_ld16u(dst
, addr
, mem_index
);
1162 } else if (size
== 4) {
1163 tcg_gen_qemu_ld32u(dst
, addr
, mem_index
);
1169 static void gen_store (DisasContext
*dc
, TCGv addr
, TCGv val
,
1172 int mem_index
= cpu_mmu_index(dc
->env
);
1174 /* If we get a fault on a delayslot we must keep the jmp state in
1175 the cpu-state to be able to re-execute the jmp. */
1176 if (dc
->delayed_branch
== 1) {
1177 cris_store_direct_jmp(dc
);
1181 /* Conditional writes. We only support the kind were X and P are known
1182 at translation time. */
1183 if (dc
->flagx_known
&& dc
->flags_x
&& (dc
->tb_flags
& P_FLAG
)) {
1185 cris_evaluate_flags(dc
);
1186 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], C_FLAG
);
1191 tcg_gen_qemu_st8(val
, addr
, mem_index
);
1192 } else if (size
== 2) {
1193 tcg_gen_qemu_st16(val
, addr
, mem_index
);
1195 tcg_gen_qemu_st32(val
, addr
, mem_index
);
1198 if (dc
->flagx_known
&& dc
->flags_x
) {
1199 cris_evaluate_flags(dc
);
1200 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~C_FLAG
);
1204 static inline void t_gen_sext(TCGv d
, TCGv s
, int size
)
1207 tcg_gen_ext8s_i32(d
, s
);
1208 } else if (size
== 2) {
1209 tcg_gen_ext16s_i32(d
, s
);
1210 } else if (!TCGV_EQUAL(d
, s
)) {
1211 tcg_gen_mov_tl(d
, s
);
1215 static inline void t_gen_zext(TCGv d
, TCGv s
, int size
)
1218 tcg_gen_ext8u_i32(d
, s
);
1219 } else if (size
== 2) {
1220 tcg_gen_ext16u_i32(d
, s
);
1221 } else if (!TCGV_EQUAL(d
, s
)) {
1222 tcg_gen_mov_tl(d
, s
);
1227 static char memsize_char(int size
)
1230 case 1: return 'b'; break;
1231 case 2: return 'w'; break;
1232 case 4: return 'd'; break;
1240 static inline unsigned int memsize_z(DisasContext
*dc
)
1242 return dc
->zsize
+ 1;
1245 static inline unsigned int memsize_zz(DisasContext
*dc
)
1247 switch (dc
->zzsize
) {
1255 static inline void do_postinc (DisasContext
*dc
, int size
)
1258 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], size
);
1262 static inline void dec_prep_move_r(DisasContext
*dc
, int rs
, int rd
,
1263 int size
, int s_ext
, TCGv dst
)
1266 t_gen_sext(dst
, cpu_R
[rs
], size
);
1268 t_gen_zext(dst
, cpu_R
[rs
], size
);
1272 /* Prepare T0 and T1 for a register alu operation.
1273 s_ext decides if the operand1 should be sign-extended or zero-extended when
1275 static void dec_prep_alu_r(DisasContext
*dc
, int rs
, int rd
,
1276 int size
, int s_ext
, TCGv dst
, TCGv src
)
1278 dec_prep_move_r(dc
, rs
, rd
, size
, s_ext
, src
);
1281 t_gen_sext(dst
, cpu_R
[rd
], size
);
1283 t_gen_zext(dst
, cpu_R
[rd
], size
);
1287 static int dec_prep_move_m(CPUCRISState
*env
, DisasContext
*dc
,
1288 int s_ext
, int memsize
, TCGv dst
)
1296 is_imm
= rs
== 15 && dc
->postinc
;
1298 /* Load [$rs] onto T1. */
1300 insn_len
= 2 + memsize
;
1305 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, memsize
, s_ext
);
1306 tcg_gen_movi_tl(dst
, imm
);
1309 cris_flush_cc_state(dc
);
1310 gen_load(dc
, dst
, cpu_R
[rs
], memsize
, 0);
1312 t_gen_sext(dst
, dst
, memsize
);
1314 t_gen_zext(dst
, dst
, memsize
);
1320 /* Prepare T0 and T1 for a memory + alu operation.
1321 s_ext decides if the operand1 should be sign-extended or zero-extended when
1323 static int dec_prep_alu_m(CPUCRISState
*env
, DisasContext
*dc
,
1324 int s_ext
, int memsize
, TCGv dst
, TCGv src
)
1328 insn_len
= dec_prep_move_m(env
, dc
, s_ext
, memsize
, src
);
1329 tcg_gen_mov_tl(dst
, cpu_R
[dc
->op2
]);
1334 static const char *cc_name(int cc
)
1336 static const char *cc_names
[16] = {
1337 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1338 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1341 return cc_names
[cc
];
1345 /* Start of insn decoders. */
1347 static int dec_bccq(CPUCRISState
*env
, DisasContext
*dc
)
1351 uint32_t cond
= dc
->op2
;
1353 offset
= EXTRACT_FIELD(dc
->ir
, 1, 7);
1354 sign
= EXTRACT_FIELD(dc
->ir
, 0, 0);
1357 offset
|= sign
<< 8;
1358 offset
= sign_extend(offset
, 8);
1360 LOG_DIS("b%s %x\n", cc_name(cond
), dc
->pc
+ offset
);
1362 /* op2 holds the condition-code. */
1363 cris_cc_mask(dc
, 0);
1364 cris_prepare_cc_branch(dc
, offset
, cond
);
1367 static int dec_addoq(CPUCRISState
*env
, DisasContext
*dc
)
1371 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 7);
1372 imm
= sign_extend(dc
->op1
, 7);
1374 LOG_DIS("addoq %d, $r%u\n", imm
, dc
->op2
);
1375 cris_cc_mask(dc
, 0);
1376 /* Fetch register operand, */
1377 tcg_gen_addi_tl(cpu_R
[R_ACR
], cpu_R
[dc
->op2
], imm
);
1381 static int dec_addq(CPUCRISState
*env
, DisasContext
*dc
)
1383 LOG_DIS("addq %u, $r%u\n", dc
->op1
, dc
->op2
);
1385 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1387 cris_cc_mask(dc
, CC_MASK_NZVC
);
1389 cris_alu(dc
, CC_OP_ADD
,
1390 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(dc
->op1
), 4);
1393 static int dec_moveq(CPUCRISState
*env
, DisasContext
*dc
)
1397 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1398 imm
= sign_extend(dc
->op1
, 5);
1399 LOG_DIS("moveq %d, $r%u\n", imm
, dc
->op2
);
1401 tcg_gen_movi_tl(cpu_R
[dc
->op2
], imm
);
1404 static int dec_subq(CPUCRISState
*env
, DisasContext
*dc
)
1406 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1408 LOG_DIS("subq %u, $r%u\n", dc
->op1
, dc
->op2
);
1410 cris_cc_mask(dc
, CC_MASK_NZVC
);
1411 cris_alu(dc
, CC_OP_SUB
,
1412 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(dc
->op1
), 4);
1415 static int dec_cmpq(CPUCRISState
*env
, DisasContext
*dc
)
1418 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1419 imm
= sign_extend(dc
->op1
, 5);
1421 LOG_DIS("cmpq %d, $r%d\n", imm
, dc
->op2
);
1422 cris_cc_mask(dc
, CC_MASK_NZVC
);
1424 cris_alu(dc
, CC_OP_CMP
,
1425 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(imm
), 4);
1428 static int dec_andq(CPUCRISState
*env
, DisasContext
*dc
)
1431 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1432 imm
= sign_extend(dc
->op1
, 5);
1434 LOG_DIS("andq %d, $r%d\n", imm
, dc
->op2
);
1435 cris_cc_mask(dc
, CC_MASK_NZ
);
1437 cris_alu(dc
, CC_OP_AND
,
1438 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(imm
), 4);
1441 static int dec_orq(CPUCRISState
*env
, DisasContext
*dc
)
1444 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1445 imm
= sign_extend(dc
->op1
, 5);
1446 LOG_DIS("orq %d, $r%d\n", imm
, dc
->op2
);
1447 cris_cc_mask(dc
, CC_MASK_NZ
);
1449 cris_alu(dc
, CC_OP_OR
,
1450 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], tcg_const_tl(imm
), 4);
1453 static int dec_btstq(CPUCRISState
*env
, DisasContext
*dc
)
1455 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1456 LOG_DIS("btstq %u, $r%d\n", dc
->op1
, dc
->op2
);
1458 cris_cc_mask(dc
, CC_MASK_NZ
);
1459 cris_evaluate_flags(dc
);
1460 gen_helper_btst(cpu_PR
[PR_CCS
], cpu_env
, cpu_R
[dc
->op2
],
1461 tcg_const_tl(dc
->op1
), cpu_PR
[PR_CCS
]);
1462 cris_alu(dc
, CC_OP_MOVE
,
1463 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1464 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
1465 dc
->flags_uptodate
= 1;
1468 static int dec_asrq(CPUCRISState
*env
, DisasContext
*dc
)
1470 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1471 LOG_DIS("asrq %u, $r%d\n", dc
->op1
, dc
->op2
);
1472 cris_cc_mask(dc
, CC_MASK_NZ
);
1474 tcg_gen_sari_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1475 cris_alu(dc
, CC_OP_MOVE
,
1477 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1480 static int dec_lslq(CPUCRISState
*env
, DisasContext
*dc
)
1482 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1483 LOG_DIS("lslq %u, $r%d\n", dc
->op1
, dc
->op2
);
1485 cris_cc_mask(dc
, CC_MASK_NZ
);
1487 tcg_gen_shli_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1489 cris_alu(dc
, CC_OP_MOVE
,
1491 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1494 static int dec_lsrq(CPUCRISState
*env
, DisasContext
*dc
)
1496 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1497 LOG_DIS("lsrq %u, $r%d\n", dc
->op1
, dc
->op2
);
1499 cris_cc_mask(dc
, CC_MASK_NZ
);
1501 tcg_gen_shri_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], dc
->op1
);
1502 cris_alu(dc
, CC_OP_MOVE
,
1504 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1508 static int dec_move_r(CPUCRISState
*env
, DisasContext
*dc
)
1510 int size
= memsize_zz(dc
);
1512 LOG_DIS("move.%c $r%u, $r%u\n",
1513 memsize_char(size
), dc
->op1
, dc
->op2
);
1515 cris_cc_mask(dc
, CC_MASK_NZ
);
1517 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, cpu_R
[dc
->op2
]);
1518 cris_cc_mask(dc
, CC_MASK_NZ
);
1519 cris_update_cc_op(dc
, CC_OP_MOVE
, 4);
1520 cris_update_cc_x(dc
);
1521 cris_update_result(dc
, cpu_R
[dc
->op2
]);
1525 t0
= tcg_temp_new();
1526 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t0
);
1527 cris_alu(dc
, CC_OP_MOVE
,
1529 cpu_R
[dc
->op2
], t0
, size
);
1535 static int dec_scc_r(CPUCRISState
*env
, DisasContext
*dc
)
1539 LOG_DIS("s%s $r%u\n",
1540 cc_name(cond
), dc
->op1
);
1545 gen_tst_cc(dc
, cpu_R
[dc
->op1
], cond
);
1546 l1
= gen_new_label();
1547 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_R
[dc
->op1
], 0, l1
);
1548 tcg_gen_movi_tl(cpu_R
[dc
->op1
], 1);
1551 tcg_gen_movi_tl(cpu_R
[dc
->op1
], 1);
1554 cris_cc_mask(dc
, 0);
1558 static inline void cris_alu_alloc_temps(DisasContext
*dc
, int size
, TCGv
*t
)
1561 t
[0] = cpu_R
[dc
->op2
];
1562 t
[1] = cpu_R
[dc
->op1
];
1564 t
[0] = tcg_temp_new();
1565 t
[1] = tcg_temp_new();
1569 static inline void cris_alu_free_temps(DisasContext
*dc
, int size
, TCGv
*t
)
1572 tcg_temp_free(t
[0]);
1573 tcg_temp_free(t
[1]);
1577 static int dec_and_r(CPUCRISState
*env
, DisasContext
*dc
)
1580 int size
= memsize_zz(dc
);
1582 LOG_DIS("and.%c $r%u, $r%u\n",
1583 memsize_char(size
), dc
->op1
, dc
->op2
);
1585 cris_cc_mask(dc
, CC_MASK_NZ
);
1587 cris_alu_alloc_temps(dc
, size
, t
);
1588 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1589 cris_alu(dc
, CC_OP_AND
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1590 cris_alu_free_temps(dc
, size
, t
);
1594 static int dec_lz_r(CPUCRISState
*env
, DisasContext
*dc
)
1597 LOG_DIS("lz $r%u, $r%u\n",
1599 cris_cc_mask(dc
, CC_MASK_NZ
);
1600 t0
= tcg_temp_new();
1601 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0, cpu_R
[dc
->op2
], t0
);
1602 cris_alu(dc
, CC_OP_LZ
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1607 static int dec_lsl_r(CPUCRISState
*env
, DisasContext
*dc
)
1610 int size
= memsize_zz(dc
);
1612 LOG_DIS("lsl.%c $r%u, $r%u\n",
1613 memsize_char(size
), dc
->op1
, dc
->op2
);
1615 cris_cc_mask(dc
, CC_MASK_NZ
);
1616 cris_alu_alloc_temps(dc
, size
, t
);
1617 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1618 tcg_gen_andi_tl(t
[1], t
[1], 63);
1619 cris_alu(dc
, CC_OP_LSL
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1620 cris_alu_alloc_temps(dc
, size
, t
);
1624 static int dec_lsr_r(CPUCRISState
*env
, DisasContext
*dc
)
1627 int size
= memsize_zz(dc
);
1629 LOG_DIS("lsr.%c $r%u, $r%u\n",
1630 memsize_char(size
), dc
->op1
, dc
->op2
);
1632 cris_cc_mask(dc
, CC_MASK_NZ
);
1633 cris_alu_alloc_temps(dc
, size
, t
);
1634 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1635 tcg_gen_andi_tl(t
[1], t
[1], 63);
1636 cris_alu(dc
, CC_OP_LSR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1637 cris_alu_free_temps(dc
, size
, t
);
1641 static int dec_asr_r(CPUCRISState
*env
, DisasContext
*dc
)
1644 int size
= memsize_zz(dc
);
1646 LOG_DIS("asr.%c $r%u, $r%u\n",
1647 memsize_char(size
), dc
->op1
, dc
->op2
);
1649 cris_cc_mask(dc
, CC_MASK_NZ
);
1650 cris_alu_alloc_temps(dc
, size
, t
);
1651 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1, t
[0], t
[1]);
1652 tcg_gen_andi_tl(t
[1], t
[1], 63);
1653 cris_alu(dc
, CC_OP_ASR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1654 cris_alu_free_temps(dc
, size
, t
);
1658 static int dec_muls_r(CPUCRISState
*env
, DisasContext
*dc
)
1661 int size
= memsize_zz(dc
);
1663 LOG_DIS("muls.%c $r%u, $r%u\n",
1664 memsize_char(size
), dc
->op1
, dc
->op2
);
1665 cris_cc_mask(dc
, CC_MASK_NZV
);
1666 cris_alu_alloc_temps(dc
, size
, t
);
1667 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1, t
[0], t
[1]);
1669 cris_alu(dc
, CC_OP_MULS
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1670 cris_alu_free_temps(dc
, size
, t
);
1674 static int dec_mulu_r(CPUCRISState
*env
, DisasContext
*dc
)
1677 int size
= memsize_zz(dc
);
1679 LOG_DIS("mulu.%c $r%u, $r%u\n",
1680 memsize_char(size
), dc
->op1
, dc
->op2
);
1681 cris_cc_mask(dc
, CC_MASK_NZV
);
1682 cris_alu_alloc_temps(dc
, size
, t
);
1683 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1685 cris_alu(dc
, CC_OP_MULU
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1686 cris_alu_alloc_temps(dc
, size
, t
);
1691 static int dec_dstep_r(CPUCRISState
*env
, DisasContext
*dc
)
1693 LOG_DIS("dstep $r%u, $r%u\n", dc
->op1
, dc
->op2
);
1694 cris_cc_mask(dc
, CC_MASK_NZ
);
1695 cris_alu(dc
, CC_OP_DSTEP
,
1696 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], 4);
1700 static int dec_xor_r(CPUCRISState
*env
, DisasContext
*dc
)
1703 int size
= memsize_zz(dc
);
1704 LOG_DIS("xor.%c $r%u, $r%u\n",
1705 memsize_char(size
), dc
->op1
, dc
->op2
);
1706 BUG_ON(size
!= 4); /* xor is dword. */
1707 cris_cc_mask(dc
, CC_MASK_NZ
);
1708 cris_alu_alloc_temps(dc
, size
, t
);
1709 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1711 cris_alu(dc
, CC_OP_XOR
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
1712 cris_alu_free_temps(dc
, size
, t
);
1716 static int dec_bound_r(CPUCRISState
*env
, DisasContext
*dc
)
1719 int size
= memsize_zz(dc
);
1720 LOG_DIS("bound.%c $r%u, $r%u\n",
1721 memsize_char(size
), dc
->op1
, dc
->op2
);
1722 cris_cc_mask(dc
, CC_MASK_NZ
);
1723 l0
= tcg_temp_local_new();
1724 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, l0
);
1725 cris_alu(dc
, CC_OP_BOUND
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], l0
, 4);
1730 static int dec_cmp_r(CPUCRISState
*env
, DisasContext
*dc
)
1733 int size
= memsize_zz(dc
);
1734 LOG_DIS("cmp.%c $r%u, $r%u\n",
1735 memsize_char(size
), dc
->op1
, dc
->op2
);
1736 cris_cc_mask(dc
, CC_MASK_NZVC
);
1737 cris_alu_alloc_temps(dc
, size
, t
);
1738 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1740 cris_alu(dc
, CC_OP_CMP
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1741 cris_alu_free_temps(dc
, size
, t
);
1745 static int dec_abs_r(CPUCRISState
*env
, DisasContext
*dc
)
1749 LOG_DIS("abs $r%u, $r%u\n",
1751 cris_cc_mask(dc
, CC_MASK_NZ
);
1753 t0
= tcg_temp_new();
1754 tcg_gen_sari_tl(t0
, cpu_R
[dc
->op1
], 31);
1755 tcg_gen_xor_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], t0
);
1756 tcg_gen_sub_tl(cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
);
1759 cris_alu(dc
, CC_OP_MOVE
,
1760 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1764 static int dec_add_r(CPUCRISState
*env
, DisasContext
*dc
)
1767 int size
= memsize_zz(dc
);
1768 LOG_DIS("add.%c $r%u, $r%u\n",
1769 memsize_char(size
), dc
->op1
, dc
->op2
);
1770 cris_cc_mask(dc
, CC_MASK_NZVC
);
1771 cris_alu_alloc_temps(dc
, size
, t
);
1772 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1774 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1775 cris_alu_free_temps(dc
, size
, t
);
1779 static int dec_addc_r(CPUCRISState
*env
, DisasContext
*dc
)
1781 LOG_DIS("addc $r%u, $r%u\n",
1783 cris_evaluate_flags(dc
);
1784 /* Set for this insn. */
1785 dc
->flagx_known
= 1;
1786 dc
->flags_x
= X_FLAG
;
1788 cris_cc_mask(dc
, CC_MASK_NZVC
);
1789 cris_alu(dc
, CC_OP_ADDC
,
1790 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], 4);
1794 static int dec_mcp_r(CPUCRISState
*env
, DisasContext
*dc
)
1796 LOG_DIS("mcp $p%u, $r%u\n",
1798 cris_evaluate_flags(dc
);
1799 cris_cc_mask(dc
, CC_MASK_RNZV
);
1800 cris_alu(dc
, CC_OP_MCP
,
1801 cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], cpu_PR
[dc
->op2
], 4);
1806 static char * swapmode_name(int mode
, char *modename
) {
1809 modename
[i
++] = 'n';
1812 modename
[i
++] = 'w';
1815 modename
[i
++] = 'b';
1818 modename
[i
++] = 'r';
1825 static int dec_swap_r(CPUCRISState
*env
, DisasContext
*dc
)
1831 LOG_DIS("swap%s $r%u\n",
1832 swapmode_name(dc
->op2
, modename
), dc
->op1
);
1834 cris_cc_mask(dc
, CC_MASK_NZ
);
1835 t0
= tcg_temp_new();
1836 t_gen_mov_TN_reg(t0
, dc
->op1
);
1838 tcg_gen_not_tl(t0
, t0
);
1841 t_gen_swapw(t0
, t0
);
1844 t_gen_swapb(t0
, t0
);
1847 t_gen_swapr(t0
, t0
);
1849 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
, 4);
1854 static int dec_or_r(CPUCRISState
*env
, DisasContext
*dc
)
1857 int size
= memsize_zz(dc
);
1858 LOG_DIS("or.%c $r%u, $r%u\n",
1859 memsize_char(size
), dc
->op1
, dc
->op2
);
1860 cris_cc_mask(dc
, CC_MASK_NZ
);
1861 cris_alu_alloc_temps(dc
, size
, t
);
1862 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1863 cris_alu(dc
, CC_OP_OR
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1864 cris_alu_free_temps(dc
, size
, t
);
1868 static int dec_addi_r(CPUCRISState
*env
, DisasContext
*dc
)
1871 LOG_DIS("addi.%c $r%u, $r%u\n",
1872 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
);
1873 cris_cc_mask(dc
, 0);
1874 t0
= tcg_temp_new();
1875 tcg_gen_shl_tl(t0
, cpu_R
[dc
->op2
], tcg_const_tl(dc
->zzsize
));
1876 tcg_gen_add_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
);
1881 static int dec_addi_acr(CPUCRISState
*env
, DisasContext
*dc
)
1884 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1885 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
);
1886 cris_cc_mask(dc
, 0);
1887 t0
= tcg_temp_new();
1888 tcg_gen_shl_tl(t0
, cpu_R
[dc
->op2
], tcg_const_tl(dc
->zzsize
));
1889 tcg_gen_add_tl(cpu_R
[R_ACR
], cpu_R
[dc
->op1
], t0
);
1894 static int dec_neg_r(CPUCRISState
*env
, DisasContext
*dc
)
1897 int size
= memsize_zz(dc
);
1898 LOG_DIS("neg.%c $r%u, $r%u\n",
1899 memsize_char(size
), dc
->op1
, dc
->op2
);
1900 cris_cc_mask(dc
, CC_MASK_NZVC
);
1901 cris_alu_alloc_temps(dc
, size
, t
);
1902 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1904 cris_alu(dc
, CC_OP_NEG
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1905 cris_alu_free_temps(dc
, size
, t
);
1909 static int dec_btst_r(CPUCRISState
*env
, DisasContext
*dc
)
1911 LOG_DIS("btst $r%u, $r%u\n",
1913 cris_cc_mask(dc
, CC_MASK_NZ
);
1914 cris_evaluate_flags(dc
);
1915 gen_helper_btst(cpu_PR
[PR_CCS
], cpu_env
, cpu_R
[dc
->op2
],
1916 cpu_R
[dc
->op1
], cpu_PR
[PR_CCS
]);
1917 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op2
],
1918 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], 4);
1919 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
1920 dc
->flags_uptodate
= 1;
1924 static int dec_sub_r(CPUCRISState
*env
, DisasContext
*dc
)
1927 int size
= memsize_zz(dc
);
1928 LOG_DIS("sub.%c $r%u, $r%u\n",
1929 memsize_char(size
), dc
->op1
, dc
->op2
);
1930 cris_cc_mask(dc
, CC_MASK_NZVC
);
1931 cris_alu_alloc_temps(dc
, size
, t
);
1932 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t
[0], t
[1]);
1933 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], t
[0], t
[1], size
);
1934 cris_alu_free_temps(dc
, size
, t
);
1938 /* Zero extension. From size to dword. */
1939 static int dec_movu_r(CPUCRISState
*env
, DisasContext
*dc
)
1942 int size
= memsize_z(dc
);
1943 LOG_DIS("movu.%c $r%u, $r%u\n",
1947 cris_cc_mask(dc
, CC_MASK_NZ
);
1948 t0
= tcg_temp_new();
1949 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0, t0
);
1950 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1955 /* Sign extension. From size to dword. */
1956 static int dec_movs_r(CPUCRISState
*env
, DisasContext
*dc
)
1959 int size
= memsize_z(dc
);
1960 LOG_DIS("movs.%c $r%u, $r%u\n",
1964 cris_cc_mask(dc
, CC_MASK_NZ
);
1965 t0
= tcg_temp_new();
1966 /* Size can only be qi or hi. */
1967 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
1968 cris_alu(dc
, CC_OP_MOVE
,
1969 cpu_R
[dc
->op2
], cpu_R
[dc
->op1
], t0
, 4);
1974 /* zero extension. From size to dword. */
1975 static int dec_addu_r(CPUCRISState
*env
, DisasContext
*dc
)
1978 int size
= memsize_z(dc
);
1979 LOG_DIS("addu.%c $r%u, $r%u\n",
1983 cris_cc_mask(dc
, CC_MASK_NZVC
);
1984 t0
= tcg_temp_new();
1985 /* Size can only be qi or hi. */
1986 t_gen_zext(t0
, cpu_R
[dc
->op1
], size
);
1987 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
1992 /* Sign extension. From size to dword. */
1993 static int dec_adds_r(CPUCRISState
*env
, DisasContext
*dc
)
1996 int size
= memsize_z(dc
);
1997 LOG_DIS("adds.%c $r%u, $r%u\n",
2001 cris_cc_mask(dc
, CC_MASK_NZVC
);
2002 t0
= tcg_temp_new();
2003 /* Size can only be qi or hi. */
2004 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
2005 cris_alu(dc
, CC_OP_ADD
,
2006 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
2011 /* Zero extension. From size to dword. */
2012 static int dec_subu_r(CPUCRISState
*env
, DisasContext
*dc
)
2015 int size
= memsize_z(dc
);
2016 LOG_DIS("subu.%c $r%u, $r%u\n",
2020 cris_cc_mask(dc
, CC_MASK_NZVC
);
2021 t0
= tcg_temp_new();
2022 /* Size can only be qi or hi. */
2023 t_gen_zext(t0
, cpu_R
[dc
->op1
], size
);
2024 cris_alu(dc
, CC_OP_SUB
,
2025 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
2030 /* Sign extension. From size to dword. */
2031 static int dec_subs_r(CPUCRISState
*env
, DisasContext
*dc
)
2034 int size
= memsize_z(dc
);
2035 LOG_DIS("subs.%c $r%u, $r%u\n",
2039 cris_cc_mask(dc
, CC_MASK_NZVC
);
2040 t0
= tcg_temp_new();
2041 /* Size can only be qi or hi. */
2042 t_gen_sext(t0
, cpu_R
[dc
->op1
], size
);
2043 cris_alu(dc
, CC_OP_SUB
,
2044 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, 4);
2049 static int dec_setclrf(CPUCRISState
*env
, DisasContext
*dc
)
2052 int set
= (~dc
->opcode
>> 2) & 1;
2055 flags
= (EXTRACT_FIELD(dc
->ir
, 12, 15) << 4)
2056 | EXTRACT_FIELD(dc
->ir
, 0, 3);
2057 if (set
&& flags
== 0) {
2060 } else if (!set
&& (flags
& 0x20)) {
2063 LOG_DIS("%sf %x\n", set
? "set" : "clr", flags
);
2066 /* User space is not allowed to touch these. Silently ignore. */
2067 if (dc
->tb_flags
& U_FLAG
) {
2068 flags
&= ~(S_FLAG
| I_FLAG
| U_FLAG
);
2071 if (flags
& X_FLAG
) {
2072 dc
->flagx_known
= 1;
2074 dc
->flags_x
= X_FLAG
;
2080 /* Break the TB if any of the SPI flag changes. */
2081 if (flags
& (P_FLAG
| S_FLAG
)) {
2082 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2083 dc
->is_jmp
= DISAS_UPDATE
;
2084 dc
->cpustate_changed
= 1;
2087 /* For the I flag, only act on posedge. */
2088 if ((flags
& I_FLAG
)) {
2089 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2090 dc
->is_jmp
= DISAS_UPDATE
;
2091 dc
->cpustate_changed
= 1;
2095 /* Simply decode the flags. */
2096 cris_evaluate_flags(dc
);
2097 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
2098 cris_update_cc_x(dc
);
2099 tcg_gen_movi_tl(cc_op
, dc
->cc_op
);
2102 if (!(dc
->tb_flags
& U_FLAG
) && (flags
& U_FLAG
)) {
2103 /* Enter user mode. */
2104 t_gen_mov_env_TN(ksp
, cpu_R
[R_SP
]);
2105 tcg_gen_mov_tl(cpu_R
[R_SP
], cpu_PR
[PR_USP
]);
2106 dc
->cpustate_changed
= 1;
2108 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], flags
);
2110 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~flags
);
2113 dc
->flags_uptodate
= 1;
2118 static int dec_move_rs(CPUCRISState
*env
, DisasContext
*dc
)
2120 LOG_DIS("move $r%u, $s%u\n", dc
->op1
, dc
->op2
);
2121 cris_cc_mask(dc
, 0);
2122 gen_helper_movl_sreg_reg(cpu_env
, tcg_const_tl(dc
->op2
),
2123 tcg_const_tl(dc
->op1
));
2126 static int dec_move_sr(CPUCRISState
*env
, DisasContext
*dc
)
2128 LOG_DIS("move $s%u, $r%u\n", dc
->op2
, dc
->op1
);
2129 cris_cc_mask(dc
, 0);
2130 gen_helper_movl_reg_sreg(cpu_env
, tcg_const_tl(dc
->op1
),
2131 tcg_const_tl(dc
->op2
));
2135 static int dec_move_rp(CPUCRISState
*env
, DisasContext
*dc
)
2138 LOG_DIS("move $r%u, $p%u\n", dc
->op1
, dc
->op2
);
2139 cris_cc_mask(dc
, 0);
2141 t
[0] = tcg_temp_new();
2142 if (dc
->op2
== PR_CCS
) {
2143 cris_evaluate_flags(dc
);
2144 t_gen_mov_TN_reg(t
[0], dc
->op1
);
2145 if (dc
->tb_flags
& U_FLAG
) {
2146 t
[1] = tcg_temp_new();
2147 /* User space is not allowed to touch all flags. */
2148 tcg_gen_andi_tl(t
[0], t
[0], 0x39f);
2149 tcg_gen_andi_tl(t
[1], cpu_PR
[PR_CCS
], ~0x39f);
2150 tcg_gen_or_tl(t
[0], t
[1], t
[0]);
2151 tcg_temp_free(t
[1]);
2154 t_gen_mov_TN_reg(t
[0], dc
->op1
);
2157 t_gen_mov_preg_TN(dc
, dc
->op2
, t
[0]);
2158 if (dc
->op2
== PR_CCS
) {
2159 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
2160 dc
->flags_uptodate
= 1;
2162 tcg_temp_free(t
[0]);
2165 static int dec_move_pr(CPUCRISState
*env
, DisasContext
*dc
)
2168 LOG_DIS("move $p%u, $r%u\n", dc
->op2
, dc
->op1
);
2169 cris_cc_mask(dc
, 0);
2171 if (dc
->op2
== PR_CCS
) {
2172 cris_evaluate_flags(dc
);
2175 if (dc
->op2
== PR_DZ
) {
2176 tcg_gen_movi_tl(cpu_R
[dc
->op1
], 0);
2178 t0
= tcg_temp_new();
2179 t_gen_mov_TN_preg(t0
, dc
->op2
);
2180 cris_alu(dc
, CC_OP_MOVE
,
2181 cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], t0
,
2182 preg_sizes
[dc
->op2
]);
2188 static int dec_move_mr(CPUCRISState
*env
, DisasContext
*dc
)
2190 int memsize
= memsize_zz(dc
);
2192 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2193 memsize_char(memsize
),
2194 dc
->op1
, dc
->postinc
? "+]" : "]",
2198 insn_len
= dec_prep_move_m(env
, dc
, 0, 4, cpu_R
[dc
->op2
]);
2199 cris_cc_mask(dc
, CC_MASK_NZ
);
2200 cris_update_cc_op(dc
, CC_OP_MOVE
, 4);
2201 cris_update_cc_x(dc
);
2202 cris_update_result(dc
, cpu_R
[dc
->op2
]);
2206 t0
= tcg_temp_new();
2207 insn_len
= dec_prep_move_m(env
, dc
, 0, memsize
, t0
);
2208 cris_cc_mask(dc
, CC_MASK_NZ
);
2209 cris_alu(dc
, CC_OP_MOVE
,
2210 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t0
, memsize
);
2213 do_postinc(dc
, memsize
);
2217 static inline void cris_alu_m_alloc_temps(TCGv
*t
)
2219 t
[0] = tcg_temp_new();
2220 t
[1] = tcg_temp_new();
2223 static inline void cris_alu_m_free_temps(TCGv
*t
)
2225 tcg_temp_free(t
[0]);
2226 tcg_temp_free(t
[1]);
2229 static int dec_movs_m(CPUCRISState
*env
, DisasContext
*dc
)
2232 int memsize
= memsize_z(dc
);
2234 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2235 memsize_char(memsize
),
2236 dc
->op1
, dc
->postinc
? "+]" : "]",
2239 cris_alu_m_alloc_temps(t
);
2241 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2242 cris_cc_mask(dc
, CC_MASK_NZ
);
2243 cris_alu(dc
, CC_OP_MOVE
,
2244 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2245 do_postinc(dc
, memsize
);
2246 cris_alu_m_free_temps(t
);
2250 static int dec_addu_m(CPUCRISState
*env
, DisasContext
*dc
)
2253 int memsize
= memsize_z(dc
);
2255 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2256 memsize_char(memsize
),
2257 dc
->op1
, dc
->postinc
? "+]" : "]",
2260 cris_alu_m_alloc_temps(t
);
2262 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2263 cris_cc_mask(dc
, CC_MASK_NZVC
);
2264 cris_alu(dc
, CC_OP_ADD
,
2265 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2266 do_postinc(dc
, memsize
);
2267 cris_alu_m_free_temps(t
);
2271 static int dec_adds_m(CPUCRISState
*env
, DisasContext
*dc
)
2274 int memsize
= memsize_z(dc
);
2276 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2277 memsize_char(memsize
),
2278 dc
->op1
, dc
->postinc
? "+]" : "]",
2281 cris_alu_m_alloc_temps(t
);
2283 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2284 cris_cc_mask(dc
, CC_MASK_NZVC
);
2285 cris_alu(dc
, CC_OP_ADD
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2286 do_postinc(dc
, memsize
);
2287 cris_alu_m_free_temps(t
);
2291 static int dec_subu_m(CPUCRISState
*env
, DisasContext
*dc
)
2294 int memsize
= memsize_z(dc
);
2296 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2297 memsize_char(memsize
),
2298 dc
->op1
, dc
->postinc
? "+]" : "]",
2301 cris_alu_m_alloc_temps(t
);
2303 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2304 cris_cc_mask(dc
, CC_MASK_NZVC
);
2305 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2306 do_postinc(dc
, memsize
);
2307 cris_alu_m_free_temps(t
);
2311 static int dec_subs_m(CPUCRISState
*env
, DisasContext
*dc
)
2314 int memsize
= memsize_z(dc
);
2316 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2317 memsize_char(memsize
),
2318 dc
->op1
, dc
->postinc
? "+]" : "]",
2321 cris_alu_m_alloc_temps(t
);
2323 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2324 cris_cc_mask(dc
, CC_MASK_NZVC
);
2325 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2326 do_postinc(dc
, memsize
);
2327 cris_alu_m_free_temps(t
);
2331 static int dec_movu_m(CPUCRISState
*env
, DisasContext
*dc
)
2334 int memsize
= memsize_z(dc
);
2337 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2338 memsize_char(memsize
),
2339 dc
->op1
, dc
->postinc
? "+]" : "]",
2342 cris_alu_m_alloc_temps(t
);
2343 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2344 cris_cc_mask(dc
, CC_MASK_NZ
);
2345 cris_alu(dc
, CC_OP_MOVE
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2346 do_postinc(dc
, memsize
);
2347 cris_alu_m_free_temps(t
);
2351 static int dec_cmpu_m(CPUCRISState
*env
, DisasContext
*dc
)
2354 int memsize
= memsize_z(dc
);
2356 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2357 memsize_char(memsize
),
2358 dc
->op1
, dc
->postinc
? "+]" : "]",
2361 cris_alu_m_alloc_temps(t
);
2362 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2363 cris_cc_mask(dc
, CC_MASK_NZVC
);
2364 cris_alu(dc
, CC_OP_CMP
, cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1], 4);
2365 do_postinc(dc
, memsize
);
2366 cris_alu_m_free_temps(t
);
2370 static int dec_cmps_m(CPUCRISState
*env
, DisasContext
*dc
)
2373 int memsize
= memsize_z(dc
);
2375 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2376 memsize_char(memsize
),
2377 dc
->op1
, dc
->postinc
? "+]" : "]",
2380 cris_alu_m_alloc_temps(t
);
2381 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2382 cris_cc_mask(dc
, CC_MASK_NZVC
);
2383 cris_alu(dc
, CC_OP_CMP
,
2384 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1],
2386 do_postinc(dc
, memsize
);
2387 cris_alu_m_free_temps(t
);
2391 static int dec_cmp_m(CPUCRISState
*env
, DisasContext
*dc
)
2394 int memsize
= memsize_zz(dc
);
2396 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2397 memsize_char(memsize
),
2398 dc
->op1
, dc
->postinc
? "+]" : "]",
2401 cris_alu_m_alloc_temps(t
);
2402 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2403 cris_cc_mask(dc
, CC_MASK_NZVC
);
2404 cris_alu(dc
, CC_OP_CMP
,
2405 cpu_R
[dc
->op2
], cpu_R
[dc
->op2
], t
[1],
2407 do_postinc(dc
, memsize
);
2408 cris_alu_m_free_temps(t
);
2412 static int dec_test_m(CPUCRISState
*env
, DisasContext
*dc
)
2415 int memsize
= memsize_zz(dc
);
2417 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2418 memsize_char(memsize
),
2419 dc
->op1
, dc
->postinc
? "+]" : "]",
2422 cris_evaluate_flags(dc
);
2424 cris_alu_m_alloc_temps(t
);
2425 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2426 cris_cc_mask(dc
, CC_MASK_NZ
);
2427 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~3);
2429 cris_alu(dc
, CC_OP_CMP
,
2430 cpu_R
[dc
->op2
], t
[1], tcg_const_tl(0), memsize_zz(dc
));
2431 do_postinc(dc
, memsize
);
2432 cris_alu_m_free_temps(t
);
2436 static int dec_and_m(CPUCRISState
*env
, DisasContext
*dc
)
2439 int memsize
= memsize_zz(dc
);
2441 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2442 memsize_char(memsize
),
2443 dc
->op1
, dc
->postinc
? "+]" : "]",
2446 cris_alu_m_alloc_temps(t
);
2447 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2448 cris_cc_mask(dc
, CC_MASK_NZ
);
2449 cris_alu(dc
, CC_OP_AND
, cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2450 do_postinc(dc
, memsize
);
2451 cris_alu_m_free_temps(t
);
2455 static int dec_add_m(CPUCRISState
*env
, DisasContext
*dc
)
2458 int memsize
= memsize_zz(dc
);
2460 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2461 memsize_char(memsize
),
2462 dc
->op1
, dc
->postinc
? "+]" : "]",
2465 cris_alu_m_alloc_temps(t
);
2466 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2467 cris_cc_mask(dc
, CC_MASK_NZVC
);
2468 cris_alu(dc
, CC_OP_ADD
,
2469 cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2470 do_postinc(dc
, memsize
);
2471 cris_alu_m_free_temps(t
);
2475 static int dec_addo_m(CPUCRISState
*env
, DisasContext
*dc
)
2478 int memsize
= memsize_zz(dc
);
2480 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2481 memsize_char(memsize
),
2482 dc
->op1
, dc
->postinc
? "+]" : "]",
2485 cris_alu_m_alloc_temps(t
);
2486 insn_len
= dec_prep_alu_m(env
, dc
, 1, memsize
, t
[0], t
[1]);
2487 cris_cc_mask(dc
, 0);
2488 cris_alu(dc
, CC_OP_ADD
, cpu_R
[R_ACR
], t
[0], t
[1], 4);
2489 do_postinc(dc
, memsize
);
2490 cris_alu_m_free_temps(t
);
2494 static int dec_bound_m(CPUCRISState
*env
, DisasContext
*dc
)
2497 int memsize
= memsize_zz(dc
);
2499 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2500 memsize_char(memsize
),
2501 dc
->op1
, dc
->postinc
? "+]" : "]",
2504 l
[0] = tcg_temp_local_new();
2505 l
[1] = tcg_temp_local_new();
2506 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, l
[0], l
[1]);
2507 cris_cc_mask(dc
, CC_MASK_NZ
);
2508 cris_alu(dc
, CC_OP_BOUND
, cpu_R
[dc
->op2
], l
[0], l
[1], 4);
2509 do_postinc(dc
, memsize
);
2510 tcg_temp_free(l
[0]);
2511 tcg_temp_free(l
[1]);
2515 static int dec_addc_mr(CPUCRISState
*env
, DisasContext
*dc
)
2519 LOG_DIS("addc [$r%u%s, $r%u\n",
2520 dc
->op1
, dc
->postinc
? "+]" : "]",
2523 cris_evaluate_flags(dc
);
2525 /* Set for this insn. */
2526 dc
->flagx_known
= 1;
2527 dc
->flags_x
= X_FLAG
;
2529 cris_alu_m_alloc_temps(t
);
2530 insn_len
= dec_prep_alu_m(env
, dc
, 0, 4, t
[0], t
[1]);
2531 cris_cc_mask(dc
, CC_MASK_NZVC
);
2532 cris_alu(dc
, CC_OP_ADDC
, cpu_R
[dc
->op2
], t
[0], t
[1], 4);
2534 cris_alu_m_free_temps(t
);
2538 static int dec_sub_m(CPUCRISState
*env
, DisasContext
*dc
)
2541 int memsize
= memsize_zz(dc
);
2543 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2544 memsize_char(memsize
),
2545 dc
->op1
, dc
->postinc
? "+]" : "]",
2546 dc
->op2
, dc
->ir
, dc
->zzsize
);
2548 cris_alu_m_alloc_temps(t
);
2549 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2550 cris_cc_mask(dc
, CC_MASK_NZVC
);
2551 cris_alu(dc
, CC_OP_SUB
, cpu_R
[dc
->op2
], t
[0], t
[1], memsize
);
2552 do_postinc(dc
, memsize
);
2553 cris_alu_m_free_temps(t
);
2557 static int dec_or_m(CPUCRISState
*env
, DisasContext
*dc
)
2560 int memsize
= memsize_zz(dc
);
2562 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2563 memsize_char(memsize
),
2564 dc
->op1
, dc
->postinc
? "+]" : "]",
2567 cris_alu_m_alloc_temps(t
);
2568 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2569 cris_cc_mask(dc
, CC_MASK_NZ
);
2570 cris_alu(dc
, CC_OP_OR
,
2571 cpu_R
[dc
->op2
], t
[0], t
[1], memsize_zz(dc
));
2572 do_postinc(dc
, memsize
);
2573 cris_alu_m_free_temps(t
);
2577 static int dec_move_mp(CPUCRISState
*env
, DisasContext
*dc
)
2580 int memsize
= memsize_zz(dc
);
2583 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2584 memsize_char(memsize
),
2586 dc
->postinc
? "+]" : "]",
2589 cris_alu_m_alloc_temps(t
);
2590 insn_len
= dec_prep_alu_m(env
, dc
, 0, memsize
, t
[0], t
[1]);
2591 cris_cc_mask(dc
, 0);
2592 if (dc
->op2
== PR_CCS
) {
2593 cris_evaluate_flags(dc
);
2594 if (dc
->tb_flags
& U_FLAG
) {
2595 /* User space is not allowed to touch all flags. */
2596 tcg_gen_andi_tl(t
[1], t
[1], 0x39f);
2597 tcg_gen_andi_tl(t
[0], cpu_PR
[PR_CCS
], ~0x39f);
2598 tcg_gen_or_tl(t
[1], t
[0], t
[1]);
2602 t_gen_mov_preg_TN(dc
, dc
->op2
, t
[1]);
2604 do_postinc(dc
, memsize
);
2605 cris_alu_m_free_temps(t
);
2609 static int dec_move_pm(CPUCRISState
*env
, DisasContext
*dc
)
2614 memsize
= preg_sizes
[dc
->op2
];
2616 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2617 memsize_char(memsize
),
2618 dc
->op2
, dc
->op1
, dc
->postinc
? "+]" : "]");
2620 /* prepare store. Address in T0, value in T1. */
2621 if (dc
->op2
== PR_CCS
) {
2622 cris_evaluate_flags(dc
);
2624 t0
= tcg_temp_new();
2625 t_gen_mov_TN_preg(t0
, dc
->op2
);
2626 cris_flush_cc_state(dc
);
2627 gen_store(dc
, cpu_R
[dc
->op1
], t0
, memsize
);
2630 cris_cc_mask(dc
, 0);
2632 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], memsize
);
2637 static int dec_movem_mr(CPUCRISState
*env
, DisasContext
*dc
)
2643 int nr
= dc
->op2
+ 1;
2645 LOG_DIS("movem [$r%u%s, $r%u\n", dc
->op1
,
2646 dc
->postinc
? "+]" : "]", dc
->op2
);
2648 addr
= tcg_temp_new();
2649 /* There are probably better ways of doing this. */
2650 cris_flush_cc_state(dc
);
2651 for (i
= 0; i
< (nr
>> 1); i
++) {
2652 tmp
[i
] = tcg_temp_new_i64();
2653 tcg_gen_addi_tl(addr
, cpu_R
[dc
->op1
], i
* 8);
2654 gen_load64(dc
, tmp
[i
], addr
);
2657 tmp32
= tcg_temp_new_i32();
2658 tcg_gen_addi_tl(addr
, cpu_R
[dc
->op1
], i
* 8);
2659 gen_load(dc
, tmp32
, addr
, 4, 0);
2663 tcg_temp_free(addr
);
2665 for (i
= 0; i
< (nr
>> 1); i
++) {
2666 tcg_gen_trunc_i64_i32(cpu_R
[i
* 2], tmp
[i
]);
2667 tcg_gen_shri_i64(tmp
[i
], tmp
[i
], 32);
2668 tcg_gen_trunc_i64_i32(cpu_R
[i
* 2 + 1], tmp
[i
]);
2669 tcg_temp_free_i64(tmp
[i
]);
2672 tcg_gen_mov_tl(cpu_R
[dc
->op2
], tmp32
);
2673 tcg_temp_free(tmp32
);
2676 /* writeback the updated pointer value. */
2678 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], nr
* 4);
2681 /* gen_load might want to evaluate the previous insns flags. */
2682 cris_cc_mask(dc
, 0);
2686 static int dec_movem_rm(CPUCRISState
*env
, DisasContext
*dc
)
2692 LOG_DIS("movem $r%u, [$r%u%s\n", dc
->op2
, dc
->op1
,
2693 dc
->postinc
? "+]" : "]");
2695 cris_flush_cc_state(dc
);
2697 tmp
= tcg_temp_new();
2698 addr
= tcg_temp_new();
2699 tcg_gen_movi_tl(tmp
, 4);
2700 tcg_gen_mov_tl(addr
, cpu_R
[dc
->op1
]);
2701 for (i
= 0; i
<= dc
->op2
; i
++) {
2702 /* Displace addr. */
2703 /* Perform the store. */
2704 gen_store(dc
, addr
, cpu_R
[i
], 4);
2705 tcg_gen_add_tl(addr
, addr
, tmp
);
2708 tcg_gen_mov_tl(cpu_R
[dc
->op1
], addr
);
2710 cris_cc_mask(dc
, 0);
2712 tcg_temp_free(addr
);
2716 static int dec_move_rm(CPUCRISState
*env
, DisasContext
*dc
)
2720 memsize
= memsize_zz(dc
);
2722 LOG_DIS("move.%c $r%u, [$r%u]\n",
2723 memsize_char(memsize
), dc
->op2
, dc
->op1
);
2725 /* prepare store. */
2726 cris_flush_cc_state(dc
);
2727 gen_store(dc
, cpu_R
[dc
->op1
], cpu_R
[dc
->op2
], memsize
);
2730 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], memsize
);
2732 cris_cc_mask(dc
, 0);
2736 static int dec_lapcq(CPUCRISState
*env
, DisasContext
*dc
)
2738 LOG_DIS("lapcq %x, $r%u\n",
2739 dc
->pc
+ dc
->op1
*2, dc
->op2
);
2740 cris_cc_mask(dc
, 0);
2741 tcg_gen_movi_tl(cpu_R
[dc
->op2
], dc
->pc
+ dc
->op1
* 2);
2745 static int dec_lapc_im(CPUCRISState
*env
, DisasContext
*dc
)
2753 cris_cc_mask(dc
, 0);
2754 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2755 LOG_DIS("lapc 0x%x, $r%u\n", imm
+ dc
->pc
, dc
->op2
);
2759 tcg_gen_movi_tl(cpu_R
[rd
], pc
);
2763 /* Jump to special reg. */
2764 static int dec_jump_p(CPUCRISState
*env
, DisasContext
*dc
)
2766 LOG_DIS("jump $p%u\n", dc
->op2
);
2768 if (dc
->op2
== PR_CCS
) {
2769 cris_evaluate_flags(dc
);
2771 t_gen_mov_TN_preg(env_btarget
, dc
->op2
);
2772 /* rete will often have low bit set to indicate delayslot. */
2773 tcg_gen_andi_tl(env_btarget
, env_btarget
, ~1);
2774 cris_cc_mask(dc
, 0);
2775 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2779 /* Jump and save. */
2780 static int dec_jas_r(CPUCRISState
*env
, DisasContext
*dc
)
2782 LOG_DIS("jas $r%u, $p%u\n", dc
->op1
, dc
->op2
);
2783 cris_cc_mask(dc
, 0);
2784 /* Store the return address in Pd. */
2785 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->op1
]);
2789 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 4));
2791 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2795 static int dec_jas_im(CPUCRISState
*env
, DisasContext
*dc
)
2799 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2801 LOG_DIS("jas 0x%x\n", imm
);
2802 cris_cc_mask(dc
, 0);
2803 /* Store the return address in Pd. */
2804 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 8));
2807 cris_prepare_jmp(dc
, JMP_DIRECT
);
2811 static int dec_jasc_im(CPUCRISState
*env
, DisasContext
*dc
)
2815 imm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2817 LOG_DIS("jasc 0x%x\n", imm
);
2818 cris_cc_mask(dc
, 0);
2819 /* Store the return address in Pd. */
2820 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 8 + 4));
2823 cris_prepare_jmp(dc
, JMP_DIRECT
);
2827 static int dec_jasc_r(CPUCRISState
*env
, DisasContext
*dc
)
2829 LOG_DIS("jasc_r $r%u, $p%u\n", dc
->op1
, dc
->op2
);
2830 cris_cc_mask(dc
, 0);
2831 /* Store the return address in Pd. */
2832 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->op1
]);
2833 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 4 + 4));
2834 cris_prepare_jmp(dc
, JMP_INDIRECT
);
2838 static int dec_bcc_im(CPUCRISState
*env
, DisasContext
*dc
)
2841 uint32_t cond
= dc
->op2
;
2843 offset
= cris_fetch(env
, dc
, dc
->pc
+ 2, 2, 1);
2845 LOG_DIS("b%s %d pc=%x dst=%x\n",
2846 cc_name(cond
), offset
,
2847 dc
->pc
, dc
->pc
+ offset
);
2849 cris_cc_mask(dc
, 0);
2850 /* op2 holds the condition-code. */
2851 cris_prepare_cc_branch(dc
, offset
, cond
);
2855 static int dec_bas_im(CPUCRISState
*env
, DisasContext
*dc
)
2859 simm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2861 LOG_DIS("bas 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
);
2862 cris_cc_mask(dc
, 0);
2863 /* Store the return address in Pd. */
2864 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 8));
2866 dc
->jmp_pc
= dc
->pc
+ simm
;
2867 cris_prepare_jmp(dc
, JMP_DIRECT
);
2871 static int dec_basc_im(CPUCRISState
*env
, DisasContext
*dc
)
2874 simm
= cris_fetch(env
, dc
, dc
->pc
+ 2, 4, 0);
2876 LOG_DIS("basc 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
);
2877 cris_cc_mask(dc
, 0);
2878 /* Store the return address in Pd. */
2879 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 12));
2881 dc
->jmp_pc
= dc
->pc
+ simm
;
2882 cris_prepare_jmp(dc
, JMP_DIRECT
);
2886 static int dec_rfe_etc(CPUCRISState
*env
, DisasContext
*dc
)
2888 cris_cc_mask(dc
, 0);
2890 if (dc
->op2
== 15) {
2891 tcg_gen_st_i32(tcg_const_i32(1), cpu_env
,
2892 -offsetof(CRISCPU
, env
) + offsetof(CPUState
, halted
));
2893 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2894 t_gen_raise_exception(EXCP_HLT
);
2898 switch (dc
->op2
& 7) {
2902 cris_evaluate_flags(dc
);
2903 gen_helper_rfe(cpu_env
);
2904 dc
->is_jmp
= DISAS_UPDATE
;
2909 cris_evaluate_flags(dc
);
2910 gen_helper_rfn(cpu_env
);
2911 dc
->is_jmp
= DISAS_UPDATE
;
2914 LOG_DIS("break %d\n", dc
->op1
);
2915 cris_evaluate_flags(dc
);
2917 tcg_gen_movi_tl(env_pc
, dc
->pc
+ 2);
2919 /* Breaks start at 16 in the exception vector. */
2920 t_gen_mov_env_TN(trap_vector
,
2921 tcg_const_tl(dc
->op1
+ 16));
2922 t_gen_raise_exception(EXCP_BREAK
);
2923 dc
->is_jmp
= DISAS_UPDATE
;
2926 printf("op2=%x\n", dc
->op2
);
2934 static int dec_ftag_fidx_d_m(CPUCRISState
*env
, DisasContext
*dc
)
2939 static int dec_ftag_fidx_i_m(CPUCRISState
*env
, DisasContext
*dc
)
2944 static int dec_null(CPUCRISState
*env
, DisasContext
*dc
)
2946 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2947 dc
->pc
, dc
->opcode
, dc
->op1
, dc
->op2
);
2953 static struct decoder_info
{
2958 int (*dec
)(CPUCRISState
*env
, DisasContext
*dc
);
2960 /* Order matters here. */
2961 {DEC_MOVEQ
, dec_moveq
},
2962 {DEC_BTSTQ
, dec_btstq
},
2963 {DEC_CMPQ
, dec_cmpq
},
2964 {DEC_ADDOQ
, dec_addoq
},
2965 {DEC_ADDQ
, dec_addq
},
2966 {DEC_SUBQ
, dec_subq
},
2967 {DEC_ANDQ
, dec_andq
},
2969 {DEC_ASRQ
, dec_asrq
},
2970 {DEC_LSLQ
, dec_lslq
},
2971 {DEC_LSRQ
, dec_lsrq
},
2972 {DEC_BCCQ
, dec_bccq
},
2974 {DEC_BCC_IM
, dec_bcc_im
},
2975 {DEC_JAS_IM
, dec_jas_im
},
2976 {DEC_JAS_R
, dec_jas_r
},
2977 {DEC_JASC_IM
, dec_jasc_im
},
2978 {DEC_JASC_R
, dec_jasc_r
},
2979 {DEC_BAS_IM
, dec_bas_im
},
2980 {DEC_BASC_IM
, dec_basc_im
},
2981 {DEC_JUMP_P
, dec_jump_p
},
2982 {DEC_LAPC_IM
, dec_lapc_im
},
2983 {DEC_LAPCQ
, dec_lapcq
},
2985 {DEC_RFE_ETC
, dec_rfe_etc
},
2986 {DEC_ADDC_MR
, dec_addc_mr
},
2988 {DEC_MOVE_MP
, dec_move_mp
},
2989 {DEC_MOVE_PM
, dec_move_pm
},
2990 {DEC_MOVEM_MR
, dec_movem_mr
},
2991 {DEC_MOVEM_RM
, dec_movem_rm
},
2992 {DEC_MOVE_PR
, dec_move_pr
},
2993 {DEC_SCC_R
, dec_scc_r
},
2994 {DEC_SETF
, dec_setclrf
},
2995 {DEC_CLEARF
, dec_setclrf
},
2997 {DEC_MOVE_SR
, dec_move_sr
},
2998 {DEC_MOVE_RP
, dec_move_rp
},
2999 {DEC_SWAP_R
, dec_swap_r
},
3000 {DEC_ABS_R
, dec_abs_r
},
3001 {DEC_LZ_R
, dec_lz_r
},
3002 {DEC_MOVE_RS
, dec_move_rs
},
3003 {DEC_BTST_R
, dec_btst_r
},
3004 {DEC_ADDC_R
, dec_addc_r
},
3006 {DEC_DSTEP_R
, dec_dstep_r
},
3007 {DEC_XOR_R
, dec_xor_r
},
3008 {DEC_MCP_R
, dec_mcp_r
},
3009 {DEC_CMP_R
, dec_cmp_r
},
3011 {DEC_ADDI_R
, dec_addi_r
},
3012 {DEC_ADDI_ACR
, dec_addi_acr
},
3014 {DEC_ADD_R
, dec_add_r
},
3015 {DEC_SUB_R
, dec_sub_r
},
3017 {DEC_ADDU_R
, dec_addu_r
},
3018 {DEC_ADDS_R
, dec_adds_r
},
3019 {DEC_SUBU_R
, dec_subu_r
},
3020 {DEC_SUBS_R
, dec_subs_r
},
3021 {DEC_LSL_R
, dec_lsl_r
},
3023 {DEC_AND_R
, dec_and_r
},
3024 {DEC_OR_R
, dec_or_r
},
3025 {DEC_BOUND_R
, dec_bound_r
},
3026 {DEC_ASR_R
, dec_asr_r
},
3027 {DEC_LSR_R
, dec_lsr_r
},
3029 {DEC_MOVU_R
, dec_movu_r
},
3030 {DEC_MOVS_R
, dec_movs_r
},
3031 {DEC_NEG_R
, dec_neg_r
},
3032 {DEC_MOVE_R
, dec_move_r
},
3034 {DEC_FTAG_FIDX_I_M
, dec_ftag_fidx_i_m
},
3035 {DEC_FTAG_FIDX_D_M
, dec_ftag_fidx_d_m
},
3037 {DEC_MULS_R
, dec_muls_r
},
3038 {DEC_MULU_R
, dec_mulu_r
},
3040 {DEC_ADDU_M
, dec_addu_m
},
3041 {DEC_ADDS_M
, dec_adds_m
},
3042 {DEC_SUBU_M
, dec_subu_m
},
3043 {DEC_SUBS_M
, dec_subs_m
},
3045 {DEC_CMPU_M
, dec_cmpu_m
},
3046 {DEC_CMPS_M
, dec_cmps_m
},
3047 {DEC_MOVU_M
, dec_movu_m
},
3048 {DEC_MOVS_M
, dec_movs_m
},
3050 {DEC_CMP_M
, dec_cmp_m
},
3051 {DEC_ADDO_M
, dec_addo_m
},
3052 {DEC_BOUND_M
, dec_bound_m
},
3053 {DEC_ADD_M
, dec_add_m
},
3054 {DEC_SUB_M
, dec_sub_m
},
3055 {DEC_AND_M
, dec_and_m
},
3056 {DEC_OR_M
, dec_or_m
},
3057 {DEC_MOVE_RM
, dec_move_rm
},
3058 {DEC_TEST_M
, dec_test_m
},
3059 {DEC_MOVE_MR
, dec_move_mr
},
3064 static unsigned int crisv32_decoder(CPUCRISState
*env
, DisasContext
*dc
)
3069 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
3070 tcg_gen_debug_insn_start(dc
->pc
);
3073 /* Load a halfword onto the instruction register. */
3074 dc
->ir
= cris_fetch(env
, dc
, dc
->pc
, 2, 0);
3076 /* Now decode it. */
3077 dc
->opcode
= EXTRACT_FIELD(dc
->ir
, 4, 11);
3078 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 3);
3079 dc
->op2
= EXTRACT_FIELD(dc
->ir
, 12, 15);
3080 dc
->zsize
= EXTRACT_FIELD(dc
->ir
, 4, 4);
3081 dc
->zzsize
= EXTRACT_FIELD(dc
->ir
, 4, 5);
3082 dc
->postinc
= EXTRACT_FIELD(dc
->ir
, 10, 10);
3084 /* Large switch for all insns. */
3085 for (i
= 0; i
< ARRAY_SIZE(decinfo
); i
++) {
3086 if ((dc
->opcode
& decinfo
[i
].mask
) == decinfo
[i
].bits
) {
3087 insn_len
= decinfo
[i
].dec(env
, dc
);
3092 #if !defined(CONFIG_USER_ONLY)
3093 /* Single-stepping ? */
3094 if (dc
->tb_flags
& S_FLAG
) {
3097 l1
= gen_new_label();
3098 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_PR
[PR_SPC
], dc
->pc
, l1
);
3099 /* We treat SPC as a break with an odd trap vector. */
3100 cris_evaluate_flags(dc
);
3101 t_gen_mov_env_TN(trap_vector
, tcg_const_tl(3));
3102 tcg_gen_movi_tl(env_pc
, dc
->pc
+ insn_len
);
3103 tcg_gen_movi_tl(cpu_PR
[PR_SPC
], dc
->pc
+ insn_len
);
3104 t_gen_raise_exception(EXCP_BREAK
);
3111 static void check_breakpoint(CPUCRISState
*env
, DisasContext
*dc
)
3115 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
3116 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
3117 if (bp
->pc
== dc
->pc
) {
3118 cris_evaluate_flags(dc
);
3119 tcg_gen_movi_tl(env_pc
, dc
->pc
);
3120 t_gen_raise_exception(EXCP_DEBUG
);
3121 dc
->is_jmp
= DISAS_UPDATE
;
3127 #include "translate_v10.c"
3130 * Delay slots on QEMU/CRIS.
3132 * If an exception hits on a delayslot, the core will let ERP (the Exception
3133 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3134 * to give SW a hint that the exception actually hit on the dslot.
3136 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3137 * the core and any jmp to an odd addresses will mask off that lsb. It is
3138 * simply there to let sw know there was an exception on a dslot.
3140 * When the software returns from an exception, the branch will re-execute.
3141 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3142 * and the branch and delayslot dont share pages.
3144 * The TB contaning the branch insn will set up env->btarget and evaluate
3145 * env->btaken. When the translation loop exits we will note that the branch
3146 * sequence is broken and let env->dslot be the size of the branch insn (those
3149 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3150 * set). It will also expect to have env->dslot setup with the size of the
3151 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3152 * will execute the dslot and take the branch, either to btarget or just one
3155 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3156 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3157 * branch and set lsb). Then env->dslot gets cleared so that the exception
3158 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3159 * masked off and we will reexecute the branch insn.
3163 /* generate intermediate code for basic block 'tb'. */
3165 gen_intermediate_code_internal(CRISCPU
*cpu
, TranslationBlock
*tb
,
3168 CPUState
*cs
= CPU(cpu
);
3169 CPUCRISState
*env
= &cpu
->env
;
3170 uint16_t *gen_opc_end
;
3172 unsigned int insn_len
;
3174 struct DisasContext ctx
;
3175 struct DisasContext
*dc
= &ctx
;
3176 uint32_t next_page_start
;
3181 if (env
->pregs
[PR_VR
] == 32) {
3182 dc
->decoder
= crisv32_decoder
;
3183 dc
->clear_locked_irq
= 0;
3185 dc
->decoder
= crisv10_decoder
;
3186 dc
->clear_locked_irq
= 1;
3189 /* Odd PC indicates that branch is rexecuting due to exception in the
3190 * delayslot, like in real hw.
3192 pc_start
= tb
->pc
& ~1;
3196 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
3198 dc
->is_jmp
= DISAS_NEXT
;
3201 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
3202 dc
->flags_uptodate
= 1;
3203 dc
->flagx_known
= 1;
3204 dc
->flags_x
= tb
->flags
& X_FLAG
;
3205 dc
->cc_x_uptodate
= 0;
3208 dc
->clear_prefix
= 0;
3210 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
3211 dc
->cc_size_uptodate
= -1;
3213 /* Decode TB flags. */
3214 dc
->tb_flags
= tb
->flags
& (S_FLAG
| P_FLAG
| U_FLAG \
3215 | X_FLAG
| PFIX_FLAG
);
3216 dc
->delayed_branch
= !!(tb
->flags
& 7);
3217 if (dc
->delayed_branch
) {
3218 dc
->jmp
= JMP_INDIRECT
;
3220 dc
->jmp
= JMP_NOJMP
;
3223 dc
->cpustate_changed
= 0;
3225 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
3227 "srch=%d pc=%x %x flg=%" PRIx64
" bt=%x ds=%u ccs=%x\n"
3233 search_pc
, dc
->pc
, dc
->ppc
,
3234 (uint64_t)tb
->flags
,
3235 env
->btarget
, (unsigned)tb
->flags
& 7,
3237 env
->pregs
[PR_PID
], env
->pregs
[PR_USP
],
3238 env
->regs
[0], env
->regs
[1], env
->regs
[2], env
->regs
[3],
3239 env
->regs
[4], env
->regs
[5], env
->regs
[6], env
->regs
[7],
3240 env
->regs
[8], env
->regs
[9],
3241 env
->regs
[10], env
->regs
[11],
3242 env
->regs
[12], env
->regs
[13],
3243 env
->regs
[14], env
->regs
[15]);
3244 qemu_log("--------------\n");
3245 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
3248 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
3251 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
3252 if (max_insns
== 0) {
3253 max_insns
= CF_COUNT_MASK
;
3258 check_breakpoint(env
, dc
);
3261 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
3265 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
3268 if (dc
->delayed_branch
== 1) {
3269 tcg_ctx
.gen_opc_pc
[lj
] = dc
->ppc
| 1;
3271 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
3273 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
3274 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
3278 LOG_DIS("%8.8x:\t", dc
->pc
);
3280 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
3285 insn_len
= dc
->decoder(env
, dc
);
3289 cris_clear_x_flag(dc
);
3293 /* Check for delayed branches here. If we do it before
3294 actually generating any host code, the simulator will just
3295 loop doing nothing for on this program location. */
3296 if (dc
->delayed_branch
) {
3297 dc
->delayed_branch
--;
3298 if (dc
->delayed_branch
== 0) {
3299 if (tb
->flags
& 7) {
3300 t_gen_mov_env_TN(dslot
, tcg_const_tl(0));
3302 if (dc
->cpustate_changed
|| !dc
->flagx_known
3303 || (dc
->flags_x
!= (tb
->flags
& X_FLAG
))) {
3304 cris_store_direct_jmp(dc
);
3307 if (dc
->clear_locked_irq
) {
3308 dc
->clear_locked_irq
= 0;
3309 t_gen_mov_env_TN(locked_irq
, tcg_const_tl(0));
3312 if (dc
->jmp
== JMP_DIRECT_CC
) {
3315 l1
= gen_new_label();
3316 cris_evaluate_flags(dc
);
3318 /* Conditional jmp. */
3319 tcg_gen_brcondi_tl(TCG_COND_EQ
,
3321 gen_goto_tb(dc
, 1, dc
->jmp_pc
);
3323 gen_goto_tb(dc
, 0, dc
->pc
);
3324 dc
->is_jmp
= DISAS_TB_JUMP
;
3325 dc
->jmp
= JMP_NOJMP
;
3326 } else if (dc
->jmp
== JMP_DIRECT
) {
3327 cris_evaluate_flags(dc
);
3328 gen_goto_tb(dc
, 0, dc
->jmp_pc
);
3329 dc
->is_jmp
= DISAS_TB_JUMP
;
3330 dc
->jmp
= JMP_NOJMP
;
3332 t_gen_cc_jmp(env_btarget
, tcg_const_tl(dc
->pc
));
3333 dc
->is_jmp
= DISAS_JUMP
;
3339 /* If we are rexecuting a branch due to exceptions on
3340 delay slots dont break. */
3341 if (!(tb
->pc
& 1) && cs
->singlestep_enabled
) {
3344 } while (!dc
->is_jmp
&& !dc
->cpustate_changed
3345 && tcg_ctx
.gen_opc_ptr
< gen_opc_end
3347 && (dc
->pc
< next_page_start
)
3348 && num_insns
< max_insns
);
3350 if (dc
->clear_locked_irq
) {
3351 t_gen_mov_env_TN(locked_irq
, tcg_const_tl(0));
3356 if (tb
->cflags
& CF_LAST_IO
)
3358 /* Force an update if the per-tb cpu state has changed. */
3359 if (dc
->is_jmp
== DISAS_NEXT
3360 && (dc
->cpustate_changed
|| !dc
->flagx_known
3361 || (dc
->flags_x
!= (tb
->flags
& X_FLAG
)))) {
3362 dc
->is_jmp
= DISAS_UPDATE
;
3363 tcg_gen_movi_tl(env_pc
, npc
);
3365 /* Broken branch+delayslot sequence. */
3366 if (dc
->delayed_branch
== 1) {
3367 /* Set env->dslot to the size of the branch insn. */
3368 t_gen_mov_env_TN(dslot
, tcg_const_tl(dc
->pc
- dc
->ppc
));
3369 cris_store_direct_jmp(dc
);
3372 cris_evaluate_flags(dc
);
3374 if (unlikely(cs
->singlestep_enabled
)) {
3375 if (dc
->is_jmp
== DISAS_NEXT
) {
3376 tcg_gen_movi_tl(env_pc
, npc
);
3378 t_gen_raise_exception(EXCP_DEBUG
);
3380 switch (dc
->is_jmp
) {
3382 gen_goto_tb(dc
, 1, npc
);
3387 /* indicate that the hash table must be used
3388 to find the next TB */
3393 /* nothing more to generate */
3397 gen_tb_end(tb
, num_insns
);
3398 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
3400 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
3403 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
3406 tb
->size
= dc
->pc
- pc_start
;
3407 tb
->icount
= num_insns
;
3412 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
3413 log_target_disas(env
, pc_start
, dc
->pc
- pc_start
,
3414 dc
->env
->pregs
[PR_VR
]);
3415 qemu_log("\nisize=%d osize=%td\n",
3416 dc
->pc
- pc_start
, tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
);
3422 void gen_intermediate_code (CPUCRISState
*env
, struct TranslationBlock
*tb
)
3424 gen_intermediate_code_internal(cris_env_get_cpu(env
), tb
, false);
3427 void gen_intermediate_code_pc (CPUCRISState
*env
, struct TranslationBlock
*tb
)
3429 gen_intermediate_code_internal(cris_env_get_cpu(env
), tb
, true);
3432 void cris_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
3435 CRISCPU
*cpu
= CRIS_CPU(cs
);
3436 CPUCRISState
*env
= &cpu
->env
;
3444 cpu_fprintf(f
, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3445 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3446 env
->pc
, env
->pregs
[PR_CCS
], env
->btaken
, env
->btarget
,
3448 env
->cc_src
, env
->cc_dest
, env
->cc_result
, env
->cc_mask
);
3451 for (i
= 0; i
< 16; i
++) {
3452 cpu_fprintf(f
, "%s=%8.8x ", regnames
[i
], env
->regs
[i
]);
3453 if ((i
+ 1) % 4 == 0) {
3454 cpu_fprintf(f
, "\n");
3457 cpu_fprintf(f
, "\nspecial regs:\n");
3458 for (i
= 0; i
< 16; i
++) {
3459 cpu_fprintf(f
, "%s=%8.8x ", pregnames
[i
], env
->pregs
[i
]);
3460 if ((i
+ 1) % 4 == 0) {
3461 cpu_fprintf(f
, "\n");
3464 srs
= env
->pregs
[PR_SRS
];
3465 cpu_fprintf(f
, "\nsupport function regs bank %x:\n", srs
);
3466 if (srs
< ARRAY_SIZE(env
->sregs
)) {
3467 for (i
= 0; i
< 16; i
++) {
3468 cpu_fprintf(f
, "s%2.2d=%8.8x ",
3469 i
, env
->sregs
[srs
][i
]);
3470 if ((i
+ 1) % 4 == 0) {
3471 cpu_fprintf(f
, "\n");
3475 cpu_fprintf(f
, "\n\n");
3479 void cris_initialize_tcg(void)
3483 #define GEN_HELPER 2
3486 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
3487 cc_x
= tcg_global_mem_new(TCG_AREG0
,
3488 offsetof(CPUCRISState
, cc_x
), "cc_x");
3489 cc_src
= tcg_global_mem_new(TCG_AREG0
,
3490 offsetof(CPUCRISState
, cc_src
), "cc_src");
3491 cc_dest
= tcg_global_mem_new(TCG_AREG0
,
3492 offsetof(CPUCRISState
, cc_dest
),
3494 cc_result
= tcg_global_mem_new(TCG_AREG0
,
3495 offsetof(CPUCRISState
, cc_result
),
3497 cc_op
= tcg_global_mem_new(TCG_AREG0
,
3498 offsetof(CPUCRISState
, cc_op
), "cc_op");
3499 cc_size
= tcg_global_mem_new(TCG_AREG0
,
3500 offsetof(CPUCRISState
, cc_size
),
3502 cc_mask
= tcg_global_mem_new(TCG_AREG0
,
3503 offsetof(CPUCRISState
, cc_mask
),
3506 env_pc
= tcg_global_mem_new(TCG_AREG0
,
3507 offsetof(CPUCRISState
, pc
),
3509 env_btarget
= tcg_global_mem_new(TCG_AREG0
,
3510 offsetof(CPUCRISState
, btarget
),
3512 env_btaken
= tcg_global_mem_new(TCG_AREG0
,
3513 offsetof(CPUCRISState
, btaken
),
3515 for (i
= 0; i
< 16; i
++) {
3516 cpu_R
[i
] = tcg_global_mem_new(TCG_AREG0
,
3517 offsetof(CPUCRISState
, regs
[i
]),
3520 for (i
= 0; i
< 16; i
++) {
3521 cpu_PR
[i
] = tcg_global_mem_new(TCG_AREG0
,
3522 offsetof(CPUCRISState
, pregs
[i
]),
3527 void restore_state_to_opc(CPUCRISState
*env
, TranslationBlock
*tb
, int pc_pos
)
3529 env
->pc
= tcg_ctx
.gen_opc_pc
[pc_pos
];