?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
tcg-ppc64: Support the ppc64 elfv2 ABI
[qemu.git] / tcg / ppc64 / tcg-target.c
blobd3cc237b366fabec954c607a3c5cb1622cc70fba
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "tcg-be-ldst.h"
26
27 /* Shorthand for size of a pointer. Avoid promotion to unsigned. */
28 #define SZP ((int)sizeof(void *))
29
30 /* Shorthand for size of a register. */
31 #define SZR (TCG_TARGET_REG_BITS / 8)
32
33 #define TCG_CT_CONST_S16 0x100
34 #define TCG_CT_CONST_U16 0x200
35 #define TCG_CT_CONST_S32 0x400
36 #define TCG_CT_CONST_U32 0x800
37 #define TCG_CT_CONST_ZERO 0x1000
38 #define TCG_CT_CONST_MONE 0x2000
39
40 static tcg_insn_unit *tb_ret_addr;
41
42 #ifndef GUEST_BASE
43 #define GUEST_BASE 0
44 #endif
45
46 #include "elf.h"
47 static bool have_isa_2_06;
48 #define HAVE_ISA_2_06 have_isa_2_06
49 #define HAVE_ISEL have_isa_2_06
50
51 #ifdef CONFIG_USE_GUEST_BASE
52 #define TCG_GUEST_BASE_REG 30
53 #else
54 #define TCG_GUEST_BASE_REG 0
55 #endif
56
57 #ifndef NDEBUG
58 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
59 "r0",
60 "r1",
61 "r2",
62 "r3",
63 "r4",
64 "r5",
65 "r6",
66 "r7",
67 "r8",
68 "r9",
69 "r10",
70 "r11",
71 "r12",
72 "r13",
73 "r14",
74 "r15",
75 "r16",
76 "r17",
77 "r18",
78 "r19",
79 "r20",
80 "r21",
81 "r22",
82 "r23",
83 "r24",
84 "r25",
85 "r26",
86 "r27",
87 "r28",
88 "r29",
89 "r30",
90 "r31"
91 };
92 #endif
93
94 static const int tcg_target_reg_alloc_order[] = {
95 TCG_REG_R14, /* call saved registers */
96 TCG_REG_R15,
97 TCG_REG_R16,
98 TCG_REG_R17,
99 TCG_REG_R18,
100 TCG_REG_R19,
101 TCG_REG_R20,
102 TCG_REG_R21,
103 TCG_REG_R22,
104 TCG_REG_R23,
105 TCG_REG_R24,
106 TCG_REG_R25,
107 TCG_REG_R26,
108 TCG_REG_R27,
109 TCG_REG_R28,
110 TCG_REG_R29,
111 TCG_REG_R30,
112 TCG_REG_R31,
113 TCG_REG_R12, /* call clobbered, non-arguments */
114 TCG_REG_R11,
115 TCG_REG_R10, /* call clobbered, arguments */
116 TCG_REG_R9,
117 TCG_REG_R8,
118 TCG_REG_R7,
119 TCG_REG_R6,
120 TCG_REG_R5,
121 TCG_REG_R4,
122 TCG_REG_R3,
123 };
124
125 static const int tcg_target_call_iarg_regs[] = {
126 TCG_REG_R3,
127 TCG_REG_R4,
128 TCG_REG_R5,
129 TCG_REG_R6,
130 TCG_REG_R7,
131 TCG_REG_R8,
132 TCG_REG_R9,
133 TCG_REG_R10
134 };
135
136 static const int tcg_target_call_oarg_regs[] = {
137 TCG_REG_R3
138 };
139
140 static const int tcg_target_callee_save_regs[] = {
141 #ifdef __APPLE__
142 TCG_REG_R11,
143 #endif
144 TCG_REG_R14,
145 TCG_REG_R15,
146 TCG_REG_R16,
147 TCG_REG_R17,
148 TCG_REG_R18,
149 TCG_REG_R19,
150 TCG_REG_R20,
151 TCG_REG_R21,
152 TCG_REG_R22,
153 TCG_REG_R23,
154 TCG_REG_R24,
155 TCG_REG_R25,
156 TCG_REG_R26,
157 TCG_REG_R27, /* currently used for the global env */
158 TCG_REG_R28,
159 TCG_REG_R29,
160 TCG_REG_R30,
161 TCG_REG_R31
162 };
163
164 static inline bool in_range_b(tcg_target_long target)
165 {
166 return target == sextract64(target, 0, 26);
167 }
168
169 static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target)
170 {
171 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
172 assert(in_range_b(disp));
173 return disp & 0x3fffffc;
174 }
175
176 static void reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target)
177 {
178 *pc = (*pc & ~0x3fffffc) | reloc_pc24_val(pc, target);
179 }
180
181 static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target)
182 {
183 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
184 assert(disp == (int16_t) disp);
185 return disp & 0xfffc;
186 }
187
188 static void reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
189 {
190 *pc = (*pc & ~0xfffc) | reloc_pc14_val(pc, target);
191 }
192
193 static inline void tcg_out_b_noaddr(TCGContext *s, int insn)
194 {
195 unsigned retrans = *s->code_ptr & 0x3fffffc;
196 tcg_out32(s, insn | retrans);
197 }
198
199 static inline void tcg_out_bc_noaddr(TCGContext *s, int insn)
200 {
201 unsigned retrans = *s->code_ptr & 0xfffc;
202 tcg_out32(s, insn | retrans);
203 }
204
205 static void patch_reloc(tcg_insn_unit *code_ptr, int type,
206 intptr_t value, intptr_t addend)
207 {
208 tcg_insn_unit *target = (tcg_insn_unit *)value;
209
210 assert(addend == 0);
211 switch (type) {
212 case R_PPC_REL14:
213 reloc_pc14(code_ptr, target);
214 break;
215 case R_PPC_REL24:
216 reloc_pc24(code_ptr, target);
217 break;
218 default:
219 tcg_abort();
220 }
221 }
222
223 /* parse target specific constraints */
224 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
225 {
226 const char *ct_str;
227
228 ct_str = *pct_str;
229 switch (ct_str[0]) {
230 case 'A': case 'B': case 'C': case 'D':
231 ct->ct |= TCG_CT_REG;
232 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
233 break;
234 case 'r':
235 ct->ct |= TCG_CT_REG;
236 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
237 break;
238 case 'L': /* qemu_ld constraint */
239 ct->ct |= TCG_CT_REG;
240 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
241 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
242 #ifdef CONFIG_SOFTMMU
243 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
244 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
245 #endif
246 break;
247 case 'S': /* qemu_st constraint */
248 ct->ct |= TCG_CT_REG;
249 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
250 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
251 #ifdef CONFIG_SOFTMMU
252 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
253 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
254 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
255 #endif
256 break;
257 case 'I':
258 ct->ct |= TCG_CT_CONST_S16;
259 break;
260 case 'J':
261 ct->ct |= TCG_CT_CONST_U16;
262 break;
263 case 'M':
264 ct->ct |= TCG_CT_CONST_MONE;
265 break;
266 case 'T':
267 ct->ct |= TCG_CT_CONST_S32;
268 break;
269 case 'U':
270 ct->ct |= TCG_CT_CONST_U32;
271 break;
272 case 'Z':
273 ct->ct |= TCG_CT_CONST_ZERO;
274 break;
275 default:
276 return -1;
277 }
278 ct_str++;
279 *pct_str = ct_str;
280 return 0;
281 }
282
283 /* test if a constant matches the constraint */
284 static int tcg_target_const_match(tcg_target_long val, TCGType type,
285 const TCGArgConstraint *arg_ct)
286 {
287 int ct = arg_ct->ct;
288 if (ct & TCG_CT_CONST) {
289 return 1;
290 }
291
292 /* The only 32-bit constraint we use aside from
293 TCG_CT_CONST is TCG_CT_CONST_S16. */
294 if (type == TCG_TYPE_I32) {
295 val = (int32_t)val;
296 }
297
298 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
299 return 1;
300 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
301 return 1;
302 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
303 return 1;
304 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
305 return 1;
306 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
307 return 1;
308 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
309 return 1;
310 }
311 return 0;
312 }
313
314 #define OPCD(opc) ((opc)<<26)
315 #define XO19(opc) (OPCD(19)|((opc)<<1))
316 #define MD30(opc) (OPCD(30)|((opc)<<2))
317 #define MDS30(opc) (OPCD(30)|((opc)<<1))
318 #define XO31(opc) (OPCD(31)|((opc)<<1))
319 #define XO58(opc) (OPCD(58)|(opc))
320 #define XO62(opc) (OPCD(62)|(opc))
321
322 #define B OPCD( 18)
323 #define BC OPCD( 16)
324 #define LBZ OPCD( 34)
325 #define LHZ OPCD( 40)
326 #define LHA OPCD( 42)
327 #define LWZ OPCD( 32)
328 #define STB OPCD( 38)
329 #define STH OPCD( 44)
330 #define STW OPCD( 36)
331
332 #define STD XO62( 0)
333 #define STDU XO62( 1)
334 #define STDX XO31(149)
335
336 #define LD XO58( 0)
337 #define LDX XO31( 21)
338 #define LDU XO58( 1)
339 #define LWA XO58( 2)
340 #define LWAX XO31(341)
341
342 #define ADDIC OPCD( 12)
343 #define ADDI OPCD( 14)
344 #define ADDIS OPCD( 15)
345 #define ORI OPCD( 24)
346 #define ORIS OPCD( 25)
347 #define XORI OPCD( 26)
348 #define XORIS OPCD( 27)
349 #define ANDI OPCD( 28)
350 #define ANDIS OPCD( 29)
351 #define MULLI OPCD( 7)
352 #define CMPLI OPCD( 10)
353 #define CMPI OPCD( 11)
354 #define SUBFIC OPCD( 8)
355
356 #define LWZU OPCD( 33)
357 #define STWU OPCD( 37)
358
359 #define RLWIMI OPCD( 20)
360 #define RLWINM OPCD( 21)
361 #define RLWNM OPCD( 23)
362
363 #define RLDICL MD30( 0)
364 #define RLDICR MD30( 1)
365 #define RLDIMI MD30( 3)
366 #define RLDCL MDS30( 8)
367
368 #define BCLR XO19( 16)
369 #define BCCTR XO19(528)
370 #define CRAND XO19(257)
371 #define CRANDC XO19(129)
372 #define CRNAND XO19(225)
373 #define CROR XO19(449)
374 #define CRNOR XO19( 33)
375
376 #define EXTSB XO31(954)
377 #define EXTSH XO31(922)
378 #define EXTSW XO31(986)
379 #define ADD XO31(266)
380 #define ADDE XO31(138)
381 #define ADDME XO31(234)
382 #define ADDZE XO31(202)
383 #define ADDC XO31( 10)
384 #define AND XO31( 28)
385 #define SUBF XO31( 40)
386 #define SUBFC XO31( 8)
387 #define SUBFE XO31(136)
388 #define SUBFME XO31(232)
389 #define SUBFZE XO31(200)
390 #define OR XO31(444)
391 #define XOR XO31(316)
392 #define MULLW XO31(235)
393 #define MULHWU XO31( 11)
394 #define DIVW XO31(491)
395 #define DIVWU XO31(459)
396 #define CMP XO31( 0)
397 #define CMPL XO31( 32)
398 #define LHBRX XO31(790)
399 #define LWBRX XO31(534)
400 #define LDBRX XO31(532)
401 #define STHBRX XO31(918)
402 #define STWBRX XO31(662)
403 #define STDBRX XO31(660)
404 #define MFSPR XO31(339)
405 #define MTSPR XO31(467)
406 #define SRAWI XO31(824)
407 #define NEG XO31(104)
408 #define MFCR XO31( 19)
409 #define MFOCRF (MFCR | (1u << 20))
410 #define NOR XO31(124)
411 #define CNTLZW XO31( 26)
412 #define CNTLZD XO31( 58)
413 #define ANDC XO31( 60)
414 #define ORC XO31(412)
415 #define EQV XO31(284)
416 #define NAND XO31(476)
417 #define ISEL XO31( 15)
418
419 #define MULLD XO31(233)
420 #define MULHD XO31( 73)
421 #define MULHDU XO31( 9)
422 #define DIVD XO31(489)
423 #define DIVDU XO31(457)
424
425 #define LBZX XO31( 87)
426 #define LHZX XO31(279)
427 #define LHAX XO31(343)
428 #define LWZX XO31( 23)
429 #define STBX XO31(215)
430 #define STHX XO31(407)
431 #define STWX XO31(151)
432
433 #define SPR(a, b) ((((a)<<5)|(b))<<11)
434 #define LR SPR(8, 0)
435 #define CTR SPR(9, 0)
436
437 #define SLW XO31( 24)
438 #define SRW XO31(536)
439 #define SRAW XO31(792)
440
441 #define SLD XO31( 27)
442 #define SRD XO31(539)
443 #define SRAD XO31(794)
444 #define SRADI XO31(413<<1)
445
446 #define TW XO31( 4)
447 #define TRAP (TW | TO(31))
448
449 #define RT(r) ((r)<<21)
450 #define RS(r) ((r)<<21)
451 #define RA(r) ((r)<<16)
452 #define RB(r) ((r)<<11)
453 #define TO(t) ((t)<<21)
454 #define SH(s) ((s)<<11)
455 #define MB(b) ((b)<<6)
456 #define ME(e) ((e)<<1)
457 #define BO(o) ((o)<<21)
458 #define MB64(b) ((b)<<5)
459 #define FXM(b) (1 << (19 - (b)))
460
461 #define LK 1
462
463 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
464 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
465 #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
466 #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
467
468 #define BF(n) ((n)<<23)
469 #define BI(n, c) (((c)+((n)*4))<<16)
470 #define BT(n, c) (((c)+((n)*4))<<21)
471 #define BA(n, c) (((c)+((n)*4))<<16)
472 #define BB(n, c) (((c)+((n)*4))<<11)
473 #define BC_(n, c) (((c)+((n)*4))<<6)
474
475 #define BO_COND_TRUE BO(12)
476 #define BO_COND_FALSE BO( 4)
477 #define BO_ALWAYS BO(20)
478
479 enum {
480 CR_LT,
481 CR_GT,
482 CR_EQ,
483 CR_SO
484 };
485
486 static const uint32_t tcg_to_bc[] = {
487 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
488 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
489 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
490 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
491 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
492 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
493 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
494 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
495 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
496 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
497 };
498
499 /* The low bit here is set if the RA and RB fields must be inverted. */
500 static const uint32_t tcg_to_isel[] = {
501 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
502 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
503 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
504 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
505 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
506 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
507 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
508 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
509 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
510 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
511 };
512
513 static inline void tcg_out_mov(TCGContext *s, TCGType type,
514 TCGReg ret, TCGReg arg)
515 {
516 if (ret != arg) {
517 tcg_out32(s, OR | SAB(arg, ret, arg));
518 }
519 }
520
521 static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
522 int sh, int mb)
523 {
524 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
525 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
526 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
527 }
528
529 static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
530 int sh, int mb, int me)
531 {
532 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
533 }
534
535 static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
536 {
537 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
538 }
539
540 static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
541 {
542 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
543 }
544
545 static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
546 {
547 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
548 }
549
550 static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg)
551 {
552 if (arg == (int16_t) arg) {
553 tcg_out32(s, ADDI | TAI(ret, 0, arg));
554 } else {
555 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
556 if (arg & 0xffff) {
557 tcg_out32(s, ORI | SAI(ret, ret, arg));
558 }
559 }
560 }
561
562 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
563 tcg_target_long arg)
564 {
565 if (type == TCG_TYPE_I32 || arg == (int32_t)arg) {
566 tcg_out_movi32(s, ret, arg);
567 } else if (arg == (uint32_t)arg && !(arg & 0x8000)) {
568 tcg_out32(s, ADDI | TAI(ret, 0, arg));
569 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
570 } else {
571 int32_t high = arg >> 32;
572 tcg_out_movi32(s, ret, high);
573 if (high) {
574 tcg_out_shli64(s, ret, ret, 32);
575 }
576 if (arg & 0xffff0000) {
577 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
578 }
579 if (arg & 0xffff) {
580 tcg_out32(s, ORI | SAI(ret, ret, arg));
581 }
582 }
583 }
584
585 static bool mask_operand(uint32_t c, int *mb, int *me)
586 {
587 uint32_t lsb, test;
588
589 /* Accept a bit pattern like:
590 0....01....1
591 1....10....0
592 0..01..10..0
593 Keep track of the transitions. */
594 if (c == 0 || c == -1) {
595 return false;
596 }
597 test = c;
598 lsb = test & -test;
599 test += lsb;
600 if (test & (test - 1)) {
601 return false;
602 }
603
604 *me = clz32(lsb);
605 *mb = test ? clz32(test & -test) + 1 : 0;
606 return true;
607 }
608
609 static bool mask64_operand(uint64_t c, int *mb, int *me)
610 {
611 uint64_t lsb;
612
613 if (c == 0) {
614 return false;
615 }
616
617 lsb = c & -c;
618 /* Accept 1..10..0. */
619 if (c == -lsb) {
620 *mb = 0;
621 *me = clz64(lsb);
622 return true;
623 }
624 /* Accept 0..01..1. */
625 if (lsb == 1 && (c & (c + 1)) == 0) {
626 *mb = clz64(c + 1) + 1;
627 *me = 63;
628 return true;
629 }
630 return false;
631 }
632
633 static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
634 {
635 int mb, me;
636
637 if ((c & 0xffff) == c) {
638 tcg_out32(s, ANDI | SAI(src, dst, c));
639 return;
640 } else if ((c & 0xffff0000) == c) {
641 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
642 return;
643 } else if (mask_operand(c, &mb, &me)) {
644 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
645 } else {
646 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
647 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
648 }
649 }
650
651 static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
652 {
653 int mb, me;
654
655 if ((c & 0xffff) == c) {
656 tcg_out32(s, ANDI | SAI(src, dst, c));
657 return;
658 } else if ((c & 0xffff0000) == c) {
659 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
660 return;
661 } else if (mask64_operand(c, &mb, &me)) {
662 if (mb == 0) {
663 tcg_out_rld(s, RLDICR, dst, src, 0, me);
664 } else {
665 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
666 }
667 } else {
668 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
669 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
670 }
671 }
672
673 static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
674 int op_lo, int op_hi)
675 {
676 if (c >> 16) {
677 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
678 src = dst;
679 }
680 if (c & 0xffff) {
681 tcg_out32(s, op_lo | SAI(src, dst, c));
682 src = dst;
683 }
684 }
685
686 static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
687 {
688 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
689 }
690
691 static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
692 {
693 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
694 }
695
696 static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target)
697 {
698 ptrdiff_t disp = tcg_pcrel_diff(s, target);
699 if (in_range_b(disp)) {
700 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
701 } else {
702 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
703 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
704 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
705 }
706 }
707
708 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
709 TCGReg base, tcg_target_long offset)
710 {
711 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
712 bool is_store = false;
713 TCGReg rs = TCG_REG_R2;
714
715 switch (opi) {
716 case LD: case LWA:
717 align = 3;
718 /* FALLTHRU */
719 default:
720 if (rt != TCG_REG_R0) {
721 rs = rt;
722 break;
723 }
724 break;
725 case STD:
726 align = 3;
727 /* FALLTHRU */
728 case STB: case STH: case STW:
729 is_store = true;
730 break;
731 }
732
733 /* For unaligned, or very large offsets, use the indexed form. */
734 if (offset & align || offset != (int32_t)offset) {
735 tcg_debug_assert(rs != base && (!is_store || rs != rt));
736 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
737 tcg_out32(s, opx | TAB(rt, base, rs));
738 return;
739 }
740
741 l0 = (int16_t)offset;
742 offset = (offset - l0) >> 16;
743 l1 = (int16_t)offset;
744
745 if (l1 < 0 && orig >= 0) {
746 extra = 0x4000;
747 l1 = (int16_t)(offset - 0x4000);
748 }
749 if (l1) {
750 tcg_out32(s, ADDIS | TAI(rs, base, l1));
751 base = rs;
752 }
753 if (extra) {
754 tcg_out32(s, ADDIS | TAI(rs, base, extra));
755 base = rs;
756 }
757 if (opi != ADDI || base != rt || l0 != 0) {
758 tcg_out32(s, opi | TAI(rt, base, l0));
759 }
760 }
761
762 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
763 TCGReg arg1, intptr_t arg2)
764 {
765 int opi, opx;
766
767 if (type == TCG_TYPE_I32) {
768 opi = LWZ, opx = LWZX;
769 } else {
770 opi = LD, opx = LDX;
771 }
772 tcg_out_mem_long(s, opi, opx, ret, arg1, arg2);
773 }
774
775 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
776 TCGReg arg1, intptr_t arg2)
777 {
778 int opi, opx;
779
780 if (type == TCG_TYPE_I32) {
781 opi = STW, opx = STWX;
782 } else {
783 opi = STD, opx = STDX;
784 }
785 tcg_out_mem_long(s, opi, opx, arg, arg1, arg2);
786 }
787
788 static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
789 int const_arg2, int cr, TCGType type)
790 {
791 int imm;
792 uint32_t op;
793
794 /* Simplify the comparisons below wrt CMPI. */
795 if (type == TCG_TYPE_I32) {
796 arg2 = (int32_t)arg2;
797 }
798
799 switch (cond) {
800 case TCG_COND_EQ:
801 case TCG_COND_NE:
802 if (const_arg2) {
803 if ((int16_t) arg2 == arg2) {
804 op = CMPI;
805 imm = 1;
806 break;
807 } else if ((uint16_t) arg2 == arg2) {
808 op = CMPLI;
809 imm = 1;
810 break;
811 }
812 }
813 op = CMPL;
814 imm = 0;
815 break;
816
817 case TCG_COND_LT:
818 case TCG_COND_GE:
819 case TCG_COND_LE:
820 case TCG_COND_GT:
821 if (const_arg2) {
822 if ((int16_t) arg2 == arg2) {
823 op = CMPI;
824 imm = 1;
825 break;
826 }
827 }
828 op = CMP;
829 imm = 0;
830 break;
831
832 case TCG_COND_LTU:
833 case TCG_COND_GEU:
834 case TCG_COND_LEU:
835 case TCG_COND_GTU:
836 if (const_arg2) {
837 if ((uint16_t) arg2 == arg2) {
838 op = CMPLI;
839 imm = 1;
840 break;
841 }
842 }
843 op = CMPL;
844 imm = 0;
845 break;
846
847 default:
848 tcg_abort();
849 }
850 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
851
852 if (imm) {
853 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
854 } else {
855 if (const_arg2) {
856 tcg_out_movi(s, type, TCG_REG_R0, arg2);
857 arg2 = TCG_REG_R0;
858 }
859 tcg_out32(s, op | RA(arg1) | RB(arg2));
860 }
861 }
862
863 static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
864 TCGReg dst, TCGReg src)
865 {
866 tcg_out32(s, (type == TCG_TYPE_I64 ? CNTLZD : CNTLZW) | RS(src) | RA(dst));
867 tcg_out_shri64(s, dst, dst, type == TCG_TYPE_I64 ? 6 : 5);
868 }
869
870 static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
871 {
872 /* X != 0 implies X + -1 generates a carry. Extra addition
873 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
874 if (dst != src) {
875 tcg_out32(s, ADDIC | TAI(dst, src, -1));
876 tcg_out32(s, SUBFE | TAB(dst, dst, src));
877 } else {
878 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
879 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
880 }
881 }
882
883 static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
884 bool const_arg2)
885 {
886 if (const_arg2) {
887 if ((uint32_t)arg2 == arg2) {
888 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
889 } else {
890 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
891 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
892 }
893 } else {
894 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
895 }
896 return TCG_REG_R0;
897 }
898
899 static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
900 TCGArg arg0, TCGArg arg1, TCGArg arg2,
901 int const_arg2)
902 {
903 int crop, sh;
904
905 /* Ignore high bits of a potential constant arg2. */
906 if (type == TCG_TYPE_I32) {
907 arg2 = (uint32_t)arg2;
908 }
909
910 /* Handle common and trivial cases before handling anything else. */
911 if (arg2 == 0) {
912 switch (cond) {
913 case TCG_COND_EQ:
914 tcg_out_setcond_eq0(s, type, arg0, arg1);
915 return;
916 case TCG_COND_NE:
917 if (type == TCG_TYPE_I32) {
918 tcg_out_ext32u(s, TCG_REG_R0, arg1);
919 arg1 = TCG_REG_R0;
920 }
921 tcg_out_setcond_ne0(s, arg0, arg1);
922 return;
923 case TCG_COND_GE:
924 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
925 arg1 = arg0;
926 /* FALLTHRU */
927 case TCG_COND_LT:
928 /* Extract the sign bit. */
929 tcg_out_rld(s, RLDICL, arg0, arg1,
930 type == TCG_TYPE_I64 ? 1 : 33, 63);
931 return;
932 default:
933 break;
934 }
935 }
936
937 /* If we have ISEL, we can implement everything with 3 or 4 insns.
938 All other cases below are also at least 3 insns, so speed up the
939 code generator by not considering them and always using ISEL. */
940 if (HAVE_ISEL) {
941 int isel, tab;
942
943 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
944
945 isel = tcg_to_isel[cond];
946
947 tcg_out_movi(s, type, arg0, 1);
948 if (isel & 1) {
949 /* arg0 = (bc ? 0 : 1) */
950 tab = TAB(arg0, 0, arg0);
951 isel &= ~1;
952 } else {
953 /* arg0 = (bc ? 1 : 0) */
954 tcg_out_movi(s, type, TCG_REG_R0, 0);
955 tab = TAB(arg0, arg0, TCG_REG_R0);
956 }
957 tcg_out32(s, isel | tab);
958 return;
959 }
960
961 switch (cond) {
962 case TCG_COND_EQ:
963 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
964 tcg_out_setcond_eq0(s, type, arg0, arg1);
965 return;
966
967 case TCG_COND_NE:
968 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
969 /* Discard the high bits only once, rather than both inputs. */
970 if (type == TCG_TYPE_I32) {
971 tcg_out_ext32u(s, TCG_REG_R0, arg1);
972 arg1 = TCG_REG_R0;
973 }
974 tcg_out_setcond_ne0(s, arg0, arg1);
975 return;
976
977 case TCG_COND_GT:
978 case TCG_COND_GTU:
979 sh = 30;
980 crop = 0;
981 goto crtest;
982
983 case TCG_COND_LT:
984 case TCG_COND_LTU:
985 sh = 29;
986 crop = 0;
987 goto crtest;
988
989 case TCG_COND_GE:
990 case TCG_COND_GEU:
991 sh = 31;
992 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
993 goto crtest;
994
995 case TCG_COND_LE:
996 case TCG_COND_LEU:
997 sh = 31;
998 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
999 crtest:
1000 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1001 if (crop) {
1002 tcg_out32(s, crop);
1003 }
1004 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1005 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1006 break;
1007
1008 default:
1009 tcg_abort();
1010 }
1011 }
1012
1013 static void tcg_out_bc(TCGContext *s, int bc, int label_index)
1014 {
1015 TCGLabel *l = &s->labels[label_index];
1016
1017 if (l->has_value) {
1018 tcg_out32(s, bc | reloc_pc14_val(s->code_ptr, l->u.value_ptr));
1019 } else {
1020 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, label_index, 0);
1021 tcg_out_bc_noaddr(s, bc);
1022 }
1023 }
1024
1025 static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1026 TCGArg arg1, TCGArg arg2, int const_arg2,
1027 int label_index, TCGType type)
1028 {
1029 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1030 tcg_out_bc(s, tcg_to_bc[cond], label_index);
1031 }
1032
1033 static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1034 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1035 TCGArg v2, bool const_c2)
1036 {
1037 /* If for some reason both inputs are zero, don't produce bad code. */
1038 if (v1 == 0 && v2 == 0) {
1039 tcg_out_movi(s, type, dest, 0);
1040 return;
1041 }
1042
1043 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
1044
1045 if (HAVE_ISEL) {
1046 int isel = tcg_to_isel[cond];
1047
1048 /* Swap the V operands if the operation indicates inversion. */
1049 if (isel & 1) {
1050 int t = v1;
1051 v1 = v2;
1052 v2 = t;
1053 isel &= ~1;
1054 }
1055 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1056 if (v2 == 0) {
1057 tcg_out_movi(s, type, TCG_REG_R0, 0);
1058 }
1059 tcg_out32(s, isel | TAB(dest, v1, v2));
1060 } else {
1061 if (dest == v2) {
1062 cond = tcg_invert_cond(cond);
1063 v2 = v1;
1064 } else if (dest != v1) {
1065 if (v1 == 0) {
1066 tcg_out_movi(s, type, dest, 0);
1067 } else {
1068 tcg_out_mov(s, type, dest, v1);
1069 }
1070 }
1071 /* Branch forward over one insn */
1072 tcg_out32(s, tcg_to_bc[cond] | 8);
1073 if (v2 == 0) {
1074 tcg_out_movi(s, type, dest, 0);
1075 } else {
1076 tcg_out_mov(s, type, dest, v2);
1077 }
1078 }
1079 }
1080
1081 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
1082 {
1083 TCGContext s;
1084
1085 s.code_buf = s.code_ptr = (tcg_insn_unit *)jmp_addr;
1086 tcg_out_b(&s, 0, (tcg_insn_unit *)addr);
1087 flush_icache_range(jmp_addr, jmp_addr + tcg_current_code_size(&s));
1088 }
1089
1090 static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
1091 {
1092 #ifdef _CALL_AIX
1093 /* Look through the descriptor. If the branch is in range, and we
1094 don't have to spend too much effort on building the toc. */
1095 void *tgt = ((void **)target)[0];
1096 uintptr_t toc = ((uintptr_t *)target)[1];
1097 intptr_t diff = tcg_pcrel_diff(s, tgt);
1098
1099 if (in_range_b(diff) && toc == (uint32_t)toc) {
1100 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, toc);
1101 tcg_out_b(s, LK, tgt);
1102 } else {
1103 /* Fold the low bits of the constant into the addresses below. */
1104 intptr_t arg = (intptr_t)target;
1105 int ofs = (int16_t)arg;
1106
1107 if (ofs + 8 < 0x8000) {
1108 arg -= ofs;
1109 } else {
1110 ofs = 0;
1111 }
1112 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg);
1113 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R2, ofs);
1114 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
1115 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_R2, ofs + SZP);
1116 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1117 }
1118 #else
1119 tcg_out_b(s, LK, target);
1120 #endif
1121 }
1122
1123 static const uint32_t qemu_ldx_opc[16] = {
1124 [MO_UB] = LBZX,
1125 [MO_UW] = LHZX,
1126 [MO_UL] = LWZX,
1127 [MO_Q] = LDX,
1128 [MO_SW] = LHAX,
1129 [MO_SL] = LWAX,
1130 [MO_BSWAP | MO_UB] = LBZX,
1131 [MO_BSWAP | MO_UW] = LHBRX,
1132 [MO_BSWAP | MO_UL] = LWBRX,
1133 [MO_BSWAP | MO_Q] = LDBRX,
1134 };
1135
1136 static const uint32_t qemu_stx_opc[16] = {
1137 [MO_UB] = STBX,
1138 [MO_UW] = STHX,
1139 [MO_UL] = STWX,
1140 [MO_Q] = STDX,
1141 [MO_BSWAP | MO_UB] = STBX,
1142 [MO_BSWAP | MO_UW] = STHBRX,
1143 [MO_BSWAP | MO_UL] = STWBRX,
1144 [MO_BSWAP | MO_Q] = STDBRX,
1145 };
1146
1147 static const uint32_t qemu_exts_opc[4] = {
1148 EXTSB, EXTSH, EXTSW, 0
1149 };
1150
1151 #if defined (CONFIG_SOFTMMU)
1152 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1153 * int mmu_idx, uintptr_t ra)
1154 */
1155 static void * const qemu_ld_helpers[16] = {
1156 [MO_UB] = helper_ret_ldub_mmu,
1157 [MO_LEUW] = helper_le_lduw_mmu,
1158 [MO_LEUL] = helper_le_ldul_mmu,
1159 [MO_LEQ] = helper_le_ldq_mmu,
1160 [MO_BEUW] = helper_be_lduw_mmu,
1161 [MO_BEUL] = helper_be_ldul_mmu,
1162 [MO_BEQ] = helper_be_ldq_mmu,
1163 };
1164
1165 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1166 * uintxx_t val, int mmu_idx, uintptr_t ra)
1167 */
1168 static void * const qemu_st_helpers[16] = {
1169 [MO_UB] = helper_ret_stb_mmu,
1170 [MO_LEUW] = helper_le_stw_mmu,
1171 [MO_LEUL] = helper_le_stl_mmu,
1172 [MO_LEQ] = helper_le_stq_mmu,
1173 [MO_BEUW] = helper_be_stw_mmu,
1174 [MO_BEUL] = helper_be_stl_mmu,
1175 [MO_BEQ] = helper_be_stq_mmu,
1176 };
1177
1178 /* Perform the TLB load and compare. Places the result of the comparison
1179 in CR7, loads the addend of the TLB into R3, and returns the register
1180 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
1181
1182 static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp s_bits, TCGReg addr_reg,
1183 int mem_index, bool is_read)
1184 {
1185 int cmp_off
1186 = (is_read
1187 ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
1188 : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
1189 int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
1190 TCGReg base = TCG_AREG0;
1191
1192 /* Extract the page index, shifted into place for tlb index. */
1193 if (TARGET_LONG_BITS == 32) {
1194 /* Zero-extend the address into a place helpful for further use. */
1195 tcg_out_ext32u(s, TCG_REG_R4, addr_reg);
1196 addr_reg = TCG_REG_R4;
1197 } else {
1198 tcg_out_rld(s, RLDICL, TCG_REG_R3, addr_reg,
1199 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS);
1200 }
1201
1202 /* Compensate for very large offsets. */
1203 if (add_off >= 0x8000) {
1204 /* Most target env are smaller than 32k; none are larger than 64k.
1205 Simplify the logic here merely to offset by 0x7ff0, giving us a
1206 range just shy of 64k. Check this assumption. */
1207 QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
1208 tlb_table[NB_MMU_MODES - 1][1])
1209 > 0x7ff0 + 0x7fff);
1210 tcg_out32(s, ADDI | TAI(TCG_REG_R2, base, 0x7ff0));
1211 base = TCG_REG_R2;
1212 cmp_off -= 0x7ff0;
1213 add_off -= 0x7ff0;
1214 }
1215
1216 /* Extraction and shifting, part 2. */
1217 if (TARGET_LONG_BITS == 32) {
1218 tcg_out_rlw(s, RLWINM, TCG_REG_R3, addr_reg,
1219 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
1220 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
1221 31 - CPU_TLB_ENTRY_BITS);
1222 } else {
1223 tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS);
1224 }
1225
1226 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base));
1227
1228 /* Load the tlb comparator. */
1229 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_R2, TCG_REG_R3, cmp_off);
1230
1231 /* Load the TLB addend for use on the fast path. Do this asap
1232 to minimize any load use delay. */
1233 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, add_off);
1234
1235 /* Clear the non-page, non-alignment bits from the address. */
1236 if (TARGET_LONG_BITS == 32) {
1237 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addr_reg, 0,
1238 (32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
1239 } else if (!s_bits) {
1240 tcg_out_rld(s, RLDICR, TCG_REG_R0, addr_reg, 0, 63 - TARGET_PAGE_BITS);
1241 } else {
1242 tcg_out_rld(s, RLDICL, TCG_REG_R0, addr_reg,
1243 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - s_bits);
1244 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
1245 }
1246
1247 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_R2, 0, 7, TCG_TYPE_TL);
1248
1249 return addr_reg;
1250 }
1251
1252 /* Record the context of a call to the out of line helper code for the slow
1253 path for a load or store, so that we can later generate the correct
1254 helper code. */
1255 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOp opc,
1256 int data_reg, int addr_reg, int mem_index,
1257 tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
1258 {
1259 TCGLabelQemuLdst *label = new_ldst_label(s);
1260
1261 label->is_ld = is_ld;
1262 label->opc = opc;
1263 label->datalo_reg = data_reg;
1264 label->addrlo_reg = addr_reg;
1265 label->mem_index = mem_index;
1266 label->raddr = raddr;
1267 label->label_ptr[0] = label_ptr;
1268 }
1269
1270 static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1271 {
1272 TCGMemOp opc = lb->opc;
1273
1274 reloc_pc14(lb->label_ptr[0], s->code_ptr);
1275
1276 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0);
1277
1278 /* If the address needed to be zero-extended, we'll have already
1279 placed it in R4. The only remaining case is 64-bit guest. */
1280 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, lb->addrlo_reg);
1281
1282 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, lb->mem_index);
1283 tcg_out32(s, MFSPR | RT(TCG_REG_R6) | LR);
1284
1285 tcg_out_call(s, qemu_ld_helpers[opc & ~MO_SIGN]);
1286
1287 if (opc & MO_SIGN) {
1288 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
1289 tcg_out32(s, insn | RA(lb->datalo_reg) | RS(TCG_REG_R3));
1290 } else {
1291 tcg_out_mov(s, TCG_TYPE_I64, lb->datalo_reg, TCG_REG_R3);
1292 }
1293
1294 tcg_out_b(s, 0, lb->raddr);
1295 }
1296
1297 static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1298 {
1299 TCGMemOp opc = lb->opc;
1300 TCGMemOp s_bits = opc & MO_SIZE;
1301
1302 reloc_pc14(lb->label_ptr[0], s->code_ptr);
1303
1304 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, TCG_AREG0);
1305
1306 /* If the address needed to be zero-extended, we'll have already
1307 placed it in R4. The only remaining case is 64-bit guest. */
1308 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, lb->addrlo_reg);
1309
1310 tcg_out_rld(s, RLDICL, TCG_REG_R5, lb->datalo_reg,
1311 0, 64 - (1 << (3 + s_bits)));
1312 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R6, lb->mem_index);
1313 tcg_out32(s, MFSPR | RT(TCG_REG_R7) | LR);
1314
1315 tcg_out_call(s, qemu_st_helpers[opc]);
1316
1317 tcg_out_b(s, 0, lb->raddr);
1318 }
1319 #endif /* SOFTMMU */
1320
1321 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1322 TCGMemOp opc, int mem_index)
1323 {
1324 TCGReg rbase;
1325 uint32_t insn;
1326 TCGMemOp s_bits = opc & MO_SIZE;
1327 #ifdef CONFIG_SOFTMMU
1328 tcg_insn_unit *label_ptr;
1329 #endif
1330
1331 #ifdef CONFIG_SOFTMMU
1332 addr_reg = tcg_out_tlb_read(s, s_bits, addr_reg, mem_index, true);
1333
1334 /* Load a pointer into the current opcode w/conditional branch-link. */
1335 label_ptr = s->code_ptr;
1336 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1337
1338 rbase = TCG_REG_R3;
1339 #else /* !CONFIG_SOFTMMU */
1340 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
1341 if (TARGET_LONG_BITS == 32) {
1342 tcg_out_ext32u(s, TCG_REG_R2, addr_reg);
1343 addr_reg = TCG_REG_R2;
1344 }
1345 #endif
1346
1347 insn = qemu_ldx_opc[opc];
1348 if (!HAVE_ISA_2_06 && insn == LDBRX) {
1349 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addr_reg, 4));
1350 tcg_out32(s, LWBRX | TAB(data_reg, rbase, addr_reg));
1351 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
1352 tcg_out_rld(s, RLDIMI, data_reg, TCG_REG_R0, 32, 0);
1353 } else if (insn) {
1354 tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
1355 } else {
1356 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
1357 tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
1358 insn = qemu_exts_opc[s_bits];
1359 tcg_out32(s, insn | RA(data_reg) | RS(data_reg));
1360 }
1361
1362 #ifdef CONFIG_SOFTMMU
1363 add_qemu_ldst_label(s, true, opc, data_reg, addr_reg, mem_index,
1364 s->code_ptr, label_ptr);
1365 #endif
1366 }
1367
1368 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1369 TCGMemOp opc, int mem_index)
1370 {
1371 TCGReg rbase;
1372 uint32_t insn;
1373 #ifdef CONFIG_SOFTMMU
1374 tcg_insn_unit *label_ptr;
1375 #endif
1376
1377 #ifdef CONFIG_SOFTMMU
1378 addr_reg = tcg_out_tlb_read(s, opc & MO_SIZE, addr_reg, mem_index, false);
1379
1380 /* Load a pointer into the current opcode w/conditional branch-link. */
1381 label_ptr = s->code_ptr;
1382 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1383
1384 rbase = TCG_REG_R3;
1385 #else /* !CONFIG_SOFTMMU */
1386 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
1387 if (TARGET_LONG_BITS == 32) {
1388 tcg_out_ext32u(s, TCG_REG_R2, addr_reg);
1389 addr_reg = TCG_REG_R2;
1390 }
1391 #endif
1392
1393 insn = qemu_stx_opc[opc];
1394 if (!HAVE_ISA_2_06 && insn == STDBRX) {
1395 tcg_out32(s, STWBRX | SAB(data_reg, rbase, addr_reg));
1396 tcg_out32(s, ADDI | TAI(TCG_REG_R2, addr_reg, 4));
1397 tcg_out_shri64(s, TCG_REG_R0, data_reg, 32);
1398 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_R2));
1399 } else {
1400 tcg_out32(s, insn | SAB(data_reg, rbase, addr_reg));
1401 }
1402
1403 #ifdef CONFIG_SOFTMMU
1404 add_qemu_ldst_label(s, false, opc, data_reg, addr_reg, mem_index,
1405 s->code_ptr, label_ptr);
1406 #endif
1407 }
1408
1409 /* Parameters for function call generation, used in tcg.c. */
1410 #define TCG_TARGET_STACK_ALIGN 16
1411 #define TCG_TARGET_EXTEND_ARGS 1
1412
1413 #ifdef _CALL_AIX
1414 # define LINK_AREA_SIZE (6 * SZR)
1415 # define LR_OFFSET (1 * SZR)
1416 # define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
1417 #elif defined(_CALL_ELF) && _CALL_ELF == 2
1418 # define LINK_AREA_SIZE (4 * SZR)
1419 # define LR_OFFSET (1 * SZR)
1420 # define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
1421 #else
1422 # error
1423 #endif
1424
1425 #define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1426 #define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
1427
1428 #define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
1429 + TCG_STATIC_CALL_ARGS_SIZE \
1430 + CPU_TEMP_BUF_SIZE \
1431 + REG_SAVE_SIZE \
1432 + TCG_TARGET_STACK_ALIGN - 1) \
1433 & -TCG_TARGET_STACK_ALIGN)
1434
1435 #define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
1436
1437 static void tcg_target_qemu_prologue(TCGContext *s)
1438 {
1439 int i;
1440
1441 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE,
1442 CPU_TEMP_BUF_SIZE);
1443
1444 #ifdef _CALL_AIX
1445 {
1446 void **desc = (void **)s->code_ptr;
1447 desc[0] = desc + 2; /* entry point */
1448 desc[1] = 0; /* environment pointer */
1449 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */
1450 }
1451 #endif
1452
1453 /* Prologue */
1454 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
1455 tcg_out32(s, STDU | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
1456
1457 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1458 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1459 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
1460 }
1461 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
1462
1463 #ifdef CONFIG_USE_GUEST_BASE
1464 if (GUEST_BASE) {
1465 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE);
1466 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1467 }
1468 #endif
1469
1470 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1471 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
1472 tcg_out32(s, BCCTR | BO_ALWAYS);
1473
1474 /* Epilogue */
1475 tb_ret_addr = s->code_ptr;
1476
1477 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
1478 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1479 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1480 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
1481 }
1482 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
1483 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
1484 tcg_out32(s, BCLR | BO_ALWAYS);
1485 }
1486
1487 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1488 const int *const_args)
1489 {
1490 TCGArg a0, a1, a2;
1491 int c;
1492
1493 switch (opc) {
1494 case INDEX_op_exit_tb:
1495 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
1496 tcg_out_b(s, 0, tb_ret_addr);
1497 break;
1498 case INDEX_op_goto_tb:
1499 if (s->tb_jmp_offset) {
1500 /* Direct jump method. */
1501 s->tb_jmp_offset[args[0]] = tcg_current_code_size(s);
1502 s->code_ptr += 7;
1503 } else {
1504 /* Indirect jump method. */
1505 tcg_abort();
1506 }
1507 s->tb_next_offset[args[0]] = tcg_current_code_size(s);
1508 break;
1509 case INDEX_op_br:
1510 {
1511 TCGLabel *l = &s->labels[args[0]];
1512
1513 if (l->has_value) {
1514 tcg_out_b(s, 0, l->u.value_ptr);
1515 } else {
1516 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, args[0], 0);
1517 tcg_out_b_noaddr(s, B);
1518 }
1519 }
1520 break;
1521 case INDEX_op_ld8u_i32:
1522 case INDEX_op_ld8u_i64:
1523 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
1524 break;
1525 case INDEX_op_ld8s_i32:
1526 case INDEX_op_ld8s_i64:
1527 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
1528 tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
1529 break;
1530 case INDEX_op_ld16u_i32:
1531 case INDEX_op_ld16u_i64:
1532 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
1533 break;
1534 case INDEX_op_ld16s_i32:
1535 case INDEX_op_ld16s_i64:
1536 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
1537 break;
1538 case INDEX_op_ld_i32:
1539 case INDEX_op_ld32u_i64:
1540 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
1541 break;
1542 case INDEX_op_ld32s_i64:
1543 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
1544 break;
1545 case INDEX_op_ld_i64:
1546 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
1547 break;
1548 case INDEX_op_st8_i32:
1549 case INDEX_op_st8_i64:
1550 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
1551 break;
1552 case INDEX_op_st16_i32:
1553 case INDEX_op_st16_i64:
1554 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
1555 break;
1556 case INDEX_op_st_i32:
1557 case INDEX_op_st32_i64:
1558 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
1559 break;
1560 case INDEX_op_st_i64:
1561 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
1562 break;
1563
1564 case INDEX_op_add_i32:
1565 a0 = args[0], a1 = args[1], a2 = args[2];
1566 if (const_args[2]) {
1567 do_addi_32:
1568 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
1569 } else {
1570 tcg_out32(s, ADD | TAB(a0, a1, a2));
1571 }
1572 break;
1573 case INDEX_op_sub_i32:
1574 a0 = args[0], a1 = args[1], a2 = args[2];
1575 if (const_args[1]) {
1576 if (const_args[2]) {
1577 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
1578 } else {
1579 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1580 }
1581 } else if (const_args[2]) {
1582 a2 = -a2;
1583 goto do_addi_32;
1584 } else {
1585 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1586 }
1587 break;
1588
1589 case INDEX_op_and_i32:
1590 a0 = args[0], a1 = args[1], a2 = args[2];
1591 if (const_args[2]) {
1592 tcg_out_andi32(s, a0, a1, a2);
1593 } else {
1594 tcg_out32(s, AND | SAB(a1, a0, a2));
1595 }
1596 break;
1597 case INDEX_op_and_i64:
1598 a0 = args[0], a1 = args[1], a2 = args[2];
1599 if (const_args[2]) {
1600 tcg_out_andi64(s, a0, a1, a2);
1601 } else {
1602 tcg_out32(s, AND | SAB(a1, a0, a2));
1603 }
1604 break;
1605 case INDEX_op_or_i64:
1606 case INDEX_op_or_i32:
1607 a0 = args[0], a1 = args[1], a2 = args[2];
1608 if (const_args[2]) {
1609 tcg_out_ori32(s, a0, a1, a2);
1610 } else {
1611 tcg_out32(s, OR | SAB(a1, a0, a2));
1612 }
1613 break;
1614 case INDEX_op_xor_i64:
1615 case INDEX_op_xor_i32:
1616 a0 = args[0], a1 = args[1], a2 = args[2];
1617 if (const_args[2]) {
1618 tcg_out_xori32(s, a0, a1, a2);
1619 } else {
1620 tcg_out32(s, XOR | SAB(a1, a0, a2));
1621 }
1622 break;
1623 case INDEX_op_andc_i32:
1624 a0 = args[0], a1 = args[1], a2 = args[2];
1625 if (const_args[2]) {
1626 tcg_out_andi32(s, a0, a1, ~a2);
1627 } else {
1628 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1629 }
1630 break;
1631 case INDEX_op_andc_i64:
1632 a0 = args[0], a1 = args[1], a2 = args[2];
1633 if (const_args[2]) {
1634 tcg_out_andi64(s, a0, a1, ~a2);
1635 } else {
1636 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1637 }
1638 break;
1639 case INDEX_op_orc_i32:
1640 if (const_args[2]) {
1641 tcg_out_ori32(s, args[0], args[1], ~args[2]);
1642 break;
1643 }
1644 /* FALLTHRU */
1645 case INDEX_op_orc_i64:
1646 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
1647 break;
1648 case INDEX_op_eqv_i32:
1649 if (const_args[2]) {
1650 tcg_out_xori32(s, args[0], args[1], ~args[2]);
1651 break;
1652 }
1653 /* FALLTHRU */
1654 case INDEX_op_eqv_i64:
1655 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
1656 break;
1657 case INDEX_op_nand_i32:
1658 case INDEX_op_nand_i64:
1659 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
1660 break;
1661 case INDEX_op_nor_i32:
1662 case INDEX_op_nor_i64:
1663 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
1664 break;
1665
1666 case INDEX_op_mul_i32:
1667 a0 = args[0], a1 = args[1], a2 = args[2];
1668 if (const_args[2]) {
1669 tcg_out32(s, MULLI | TAI(a0, a1, a2));
1670 } else {
1671 tcg_out32(s, MULLW | TAB(a0, a1, a2));
1672 }
1673 break;
1674
1675 case INDEX_op_div_i32:
1676 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
1677 break;
1678
1679 case INDEX_op_divu_i32:
1680 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
1681 break;
1682
1683 case INDEX_op_shl_i32:
1684 if (const_args[2]) {
1685 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31 - args[2]);
1686 } else {
1687 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
1688 }
1689 break;
1690 case INDEX_op_shr_i32:
1691 if (const_args[2]) {
1692 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], args[2], 31);
1693 } else {
1694 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
1695 }
1696 break;
1697 case INDEX_op_sar_i32:
1698 if (const_args[2]) {
1699 tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2]));
1700 } else {
1701 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
1702 }
1703 break;
1704 case INDEX_op_rotl_i32:
1705 if (const_args[2]) {
1706 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
1707 } else {
1708 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
1709 | MB(0) | ME(31));
1710 }
1711 break;
1712 case INDEX_op_rotr_i32:
1713 if (const_args[2]) {
1714 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
1715 } else {
1716 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
1717 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
1718 | MB(0) | ME(31));
1719 }
1720 break;
1721
1722 case INDEX_op_brcond_i32:
1723 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1724 args[3], TCG_TYPE_I32);
1725 break;
1726
1727 case INDEX_op_brcond_i64:
1728 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1729 args[3], TCG_TYPE_I64);
1730 break;
1731
1732 case INDEX_op_neg_i32:
1733 case INDEX_op_neg_i64:
1734 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
1735 break;
1736
1737 case INDEX_op_not_i32:
1738 case INDEX_op_not_i64:
1739 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
1740 break;
1741
1742 case INDEX_op_add_i64:
1743 a0 = args[0], a1 = args[1], a2 = args[2];
1744 if (const_args[2]) {
1745 do_addi_64:
1746 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
1747 } else {
1748 tcg_out32(s, ADD | TAB(a0, a1, a2));
1749 }
1750 break;
1751 case INDEX_op_sub_i64:
1752 a0 = args[0], a1 = args[1], a2 = args[2];
1753 if (const_args[1]) {
1754 if (const_args[2]) {
1755 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
1756 } else {
1757 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1758 }
1759 } else if (const_args[2]) {
1760 a2 = -a2;
1761 goto do_addi_64;
1762 } else {
1763 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1764 }
1765 break;
1766
1767 case INDEX_op_shl_i64:
1768 if (const_args[2]) {
1769 tcg_out_shli64(s, args[0], args[1], args[2]);
1770 } else {
1771 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
1772 }
1773 break;
1774 case INDEX_op_shr_i64:
1775 if (const_args[2]) {
1776 tcg_out_shri64(s, args[0], args[1], args[2]);
1777 } else {
1778 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
1779 }
1780 break;
1781 case INDEX_op_sar_i64:
1782 if (const_args[2]) {
1783 int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
1784 tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
1785 } else {
1786 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
1787 }
1788 break;
1789 case INDEX_op_rotl_i64:
1790 if (const_args[2]) {
1791 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
1792 } else {
1793 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
1794 }
1795 break;
1796 case INDEX_op_rotr_i64:
1797 if (const_args[2]) {
1798 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
1799 } else {
1800 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
1801 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
1802 }
1803 break;
1804
1805 case INDEX_op_mul_i64:
1806 a0 = args[0], a1 = args[1], a2 = args[2];
1807 if (const_args[2]) {
1808 tcg_out32(s, MULLI | TAI(a0, a1, a2));
1809 } else {
1810 tcg_out32(s, MULLD | TAB(a0, a1, a2));
1811 }
1812 break;
1813 case INDEX_op_div_i64:
1814 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
1815 break;
1816 case INDEX_op_divu_i64:
1817 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
1818 break;
1819
1820 case INDEX_op_qemu_ld_i32:
1821 case INDEX_op_qemu_ld_i64:
1822 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3]);
1823 break;
1824 case INDEX_op_qemu_st_i32:
1825 case INDEX_op_qemu_st_i64:
1826 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3]);
1827 break;
1828
1829 case INDEX_op_ext8s_i32:
1830 case INDEX_op_ext8s_i64:
1831 c = EXTSB;
1832 goto gen_ext;
1833 case INDEX_op_ext16s_i32:
1834 case INDEX_op_ext16s_i64:
1835 c = EXTSH;
1836 goto gen_ext;
1837 case INDEX_op_ext32s_i64:
1838 c = EXTSW;
1839 goto gen_ext;
1840 gen_ext:
1841 tcg_out32(s, c | RS(args[1]) | RA(args[0]));
1842 break;
1843
1844 case INDEX_op_setcond_i32:
1845 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
1846 const_args[2]);
1847 break;
1848 case INDEX_op_setcond_i64:
1849 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
1850 const_args[2]);
1851 break;
1852
1853 case INDEX_op_bswap16_i32:
1854 case INDEX_op_bswap16_i64:
1855 a0 = args[0], a1 = args[1];
1856 /* a1 = abcd */
1857 if (a0 != a1) {
1858 /* a0 = (a1 r<< 24) & 0xff # 000c */
1859 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
1860 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
1861 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
1862 } else {
1863 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
1864 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
1865 /* a0 = (a1 r<< 24) & 0xff # 000c */
1866 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
1867 /* a0 = a0 | r0 # 00dc */
1868 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
1869 }
1870 break;
1871
1872 case INDEX_op_bswap32_i32:
1873 case INDEX_op_bswap32_i64:
1874 /* Stolen from gcc's builtin_bswap32 */
1875 a1 = args[1];
1876 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
1877
1878 /* a1 = args[1] # abcd */
1879 /* a0 = rotate_left (a1, 8) # bcda */
1880 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
1881 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
1882 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
1883 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
1884 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
1885
1886 if (a0 == TCG_REG_R0) {
1887 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
1888 }
1889 break;
1890
1891 case INDEX_op_bswap64_i64:
1892 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
1893 if (a0 == a1) {
1894 a0 = TCG_REG_R0;
1895 a2 = a1;
1896 }
1897
1898 /* a1 = # abcd efgh */
1899 /* a0 = rl32(a1, 8) # 0000 fghe */
1900 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
1901 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
1902 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
1903 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
1904 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
1905
1906 /* a0 = rl64(a0, 32) # hgfe 0000 */
1907 /* a2 = rl64(a1, 32) # efgh abcd */
1908 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
1909 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
1910
1911 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
1912 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
1913 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
1914 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
1915 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
1916 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
1917
1918 if (a0 == 0) {
1919 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
1920 }
1921 break;
1922
1923 case INDEX_op_deposit_i32:
1924 if (const_args[2]) {
1925 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
1926 tcg_out_andi32(s, args[0], args[0], ~mask);
1927 } else {
1928 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
1929 32 - args[3] - args[4], 31 - args[3]);
1930 }
1931 break;
1932 case INDEX_op_deposit_i64:
1933 if (const_args[2]) {
1934 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
1935 tcg_out_andi64(s, args[0], args[0], ~mask);
1936 } else {
1937 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
1938 64 - args[3] - args[4]);
1939 }
1940 break;
1941
1942 case INDEX_op_movcond_i32:
1943 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
1944 args[3], args[4], const_args[2]);
1945 break;
1946 case INDEX_op_movcond_i64:
1947 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
1948 args[3], args[4], const_args[2]);
1949 break;
1950
1951 case INDEX_op_add2_i64:
1952 /* Note that the CA bit is defined based on the word size of the
1953 environment. So in 64-bit mode it's always carry-out of bit 63.
1954 The fallback code using deposit works just as well for 32-bit. */
1955 a0 = args[0], a1 = args[1];
1956 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
1957 a0 = TCG_REG_R0;
1958 }
1959 if (const_args[4]) {
1960 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
1961 } else {
1962 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
1963 }
1964 if (const_args[5]) {
1965 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
1966 } else {
1967 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
1968 }
1969 if (a0 != args[0]) {
1970 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
1971 }
1972 break;
1973
1974 case INDEX_op_sub2_i64:
1975 a0 = args[0], a1 = args[1];
1976 if (a0 == args[5] || (!const_args[4] && a0 == args[4])) {
1977 a0 = TCG_REG_R0;
1978 }
1979 if (const_args[2]) {
1980 tcg_out32(s, SUBFIC | TAI(a0, args[3], args[2]));
1981 } else {
1982 tcg_out32(s, SUBFC | TAB(a0, args[3], args[2]));
1983 }
1984 if (const_args[4]) {
1985 tcg_out32(s, (args[4] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
1986 } else {
1987 tcg_out32(s, SUBFE | TAB(a1, args[5], args[4]));
1988 }
1989 if (a0 != args[0]) {
1990 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
1991 }
1992 break;
1993
1994 case INDEX_op_muluh_i64:
1995 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
1996 break;
1997 case INDEX_op_mulsh_i64:
1998 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
1999 break;
2000
2001 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2002 case INDEX_op_mov_i64:
2003 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2004 case INDEX_op_movi_i64:
2005 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2006 default:
2007 tcg_abort();
2008 }
2009 }
2010
2011 static const TCGTargetOpDef ppc_op_defs[] = {
2012 { INDEX_op_exit_tb, { } },
2013 { INDEX_op_goto_tb, { } },
2014 { INDEX_op_br, { } },
2015
2016 { INDEX_op_ld8u_i32, { "r", "r" } },
2017 { INDEX_op_ld8s_i32, { "r", "r" } },
2018 { INDEX_op_ld16u_i32, { "r", "r" } },
2019 { INDEX_op_ld16s_i32, { "r", "r" } },
2020 { INDEX_op_ld_i32, { "r", "r" } },
2021 { INDEX_op_ld_i64, { "r", "r" } },
2022 { INDEX_op_st8_i32, { "r", "r" } },
2023 { INDEX_op_st8_i64, { "r", "r" } },
2024 { INDEX_op_st16_i32, { "r", "r" } },
2025 { INDEX_op_st16_i64, { "r", "r" } },
2026 { INDEX_op_st_i32, { "r", "r" } },
2027 { INDEX_op_st_i64, { "r", "r" } },
2028 { INDEX_op_st32_i64, { "r", "r" } },
2029
2030 { INDEX_op_ld8u_i64, { "r", "r" } },
2031 { INDEX_op_ld8s_i64, { "r", "r" } },
2032 { INDEX_op_ld16u_i64, { "r", "r" } },
2033 { INDEX_op_ld16s_i64, { "r", "r" } },
2034 { INDEX_op_ld32u_i64, { "r", "r" } },
2035 { INDEX_op_ld32s_i64, { "r", "r" } },
2036
2037 { INDEX_op_add_i32, { "r", "r", "ri" } },
2038 { INDEX_op_mul_i32, { "r", "r", "rI" } },
2039 { INDEX_op_div_i32, { "r", "r", "r" } },
2040 { INDEX_op_divu_i32, { "r", "r", "r" } },
2041 { INDEX_op_sub_i32, { "r", "rI", "ri" } },
2042 { INDEX_op_and_i32, { "r", "r", "ri" } },
2043 { INDEX_op_or_i32, { "r", "r", "ri" } },
2044 { INDEX_op_xor_i32, { "r", "r", "ri" } },
2045 { INDEX_op_andc_i32, { "r", "r", "ri" } },
2046 { INDEX_op_orc_i32, { "r", "r", "ri" } },
2047 { INDEX_op_eqv_i32, { "r", "r", "ri" } },
2048 { INDEX_op_nand_i32, { "r", "r", "r" } },
2049 { INDEX_op_nor_i32, { "r", "r", "r" } },
2050
2051 { INDEX_op_shl_i32, { "r", "r", "ri" } },
2052 { INDEX_op_shr_i32, { "r", "r", "ri" } },
2053 { INDEX_op_sar_i32, { "r", "r", "ri" } },
2054 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
2055 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
2056
2057 { INDEX_op_brcond_i32, { "r", "ri" } },
2058 { INDEX_op_brcond_i64, { "r", "ri" } },
2059
2060 { INDEX_op_neg_i32, { "r", "r" } },
2061 { INDEX_op_not_i32, { "r", "r" } },
2062
2063 { INDEX_op_add_i64, { "r", "r", "rT" } },
2064 { INDEX_op_sub_i64, { "r", "rI", "rT" } },
2065 { INDEX_op_and_i64, { "r", "r", "ri" } },
2066 { INDEX_op_or_i64, { "r", "r", "rU" } },
2067 { INDEX_op_xor_i64, { "r", "r", "rU" } },
2068 { INDEX_op_andc_i64, { "r", "r", "ri" } },
2069 { INDEX_op_orc_i64, { "r", "r", "r" } },
2070 { INDEX_op_eqv_i64, { "r", "r", "r" } },
2071 { INDEX_op_nand_i64, { "r", "r", "r" } },
2072 { INDEX_op_nor_i64, { "r", "r", "r" } },
2073
2074 { INDEX_op_shl_i64, { "r", "r", "ri" } },
2075 { INDEX_op_shr_i64, { "r", "r", "ri" } },
2076 { INDEX_op_sar_i64, { "r", "r", "ri" } },
2077 { INDEX_op_rotl_i64, { "r", "r", "ri" } },
2078 { INDEX_op_rotr_i64, { "r", "r", "ri" } },
2079
2080 { INDEX_op_mul_i64, { "r", "r", "rI" } },
2081 { INDEX_op_div_i64, { "r", "r", "r" } },
2082 { INDEX_op_divu_i64, { "r", "r", "r" } },
2083
2084 { INDEX_op_neg_i64, { "r", "r" } },
2085 { INDEX_op_not_i64, { "r", "r" } },
2086
2087 { INDEX_op_qemu_ld_i32, { "r", "L" } },
2088 { INDEX_op_qemu_ld_i64, { "r", "L" } },
2089 { INDEX_op_qemu_st_i32, { "S", "S" } },
2090 { INDEX_op_qemu_st_i64, { "S", "S" } },
2091
2092 { INDEX_op_ext8s_i32, { "r", "r" } },
2093 { INDEX_op_ext16s_i32, { "r", "r" } },
2094 { INDEX_op_ext8s_i64, { "r", "r" } },
2095 { INDEX_op_ext16s_i64, { "r", "r" } },
2096 { INDEX_op_ext32s_i64, { "r", "r" } },
2097
2098 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
2099 { INDEX_op_setcond_i64, { "r", "r", "ri" } },
2100 { INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
2101 { INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
2102
2103 { INDEX_op_bswap16_i32, { "r", "r" } },
2104 { INDEX_op_bswap16_i64, { "r", "r" } },
2105 { INDEX_op_bswap32_i32, { "r", "r" } },
2106 { INDEX_op_bswap32_i64, { "r", "r" } },
2107 { INDEX_op_bswap64_i64, { "r", "r" } },
2108
2109 { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
2110 { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
2111
2112 { INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
2113 { INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } },
2114 { INDEX_op_mulsh_i64, { "r", "r", "r" } },
2115 { INDEX_op_muluh_i64, { "r", "r", "r" } },
2116
2117 { -1 },
2118 };
2119
2120 static void tcg_target_init(TCGContext *s)
2121 {
2122 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
2123 if (hwcap & PPC_FEATURE_ARCH_2_06) {
2124 have_isa_2_06 = true;
2125 }
2126
2127 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
2128 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
2129 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
2130 (1 << TCG_REG_R0) |
2131 (1 << TCG_REG_R2) |
2132 (1 << TCG_REG_R3) |
2133 (1 << TCG_REG_R4) |
2134 (1 << TCG_REG_R5) |
2135 (1 << TCG_REG_R6) |
2136 (1 << TCG_REG_R7) |
2137 (1 << TCG_REG_R8) |
2138 (1 << TCG_REG_R9) |
2139 (1 << TCG_REG_R10) |
2140 (1 << TCG_REG_R11) |
2141 (1 << TCG_REG_R12));
2142
2143 tcg_regset_clear(s->reserved_regs);
2144 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
2145 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
2146 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* mem temp */
2147 #ifdef __APPLE__
2148 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R11); /* ??? */
2149 #endif
2150 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2151
2152 tcg_add_target_add_op_defs(ppc_op_defs);
2153 }
2154
2155 typedef struct {
2156 DebugFrameCIE cie;
2157 DebugFrameFDEHeader fde;
2158 uint8_t fde_def_cfa[4];
2159 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
2160 } DebugFrame;
2161
2162 /* We're expecting a 2 byte uleb128 encoded value. */
2163 QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2164
2165 #define ELF_HOST_MACHINE EM_PPC64
2166
2167 static DebugFrame debug_frame = {
2168 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2169 .cie.id = -1,
2170 .cie.version = 1,
2171 .cie.code_align = 1,
2172 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */
2173 .cie.return_column = 65,
2174
2175 /* Total FDE size does not include the "len" member. */
2176 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
2177
2178 .fde_def_cfa = {
2179 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
2180 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2181 (FRAME_SIZE >> 7)
2182 },
2183 .fde_reg_ofs = {
2184 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
2185 0x11, 65, (LR_OFFSET / -SZR) & 0x7f,
2186 }
2187 };
2188
2189 void tcg_register_jit(void *buf, size_t buf_size)
2190 {
2191 uint8_t *p = &debug_frame.fde_reg_ofs[3];
2192 int i;
2193
2194 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
2195 p[0] = 0x80 + tcg_target_callee_save_regs[i];
2196 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR;
2197 }
2198
2199 debug_frame.fde.func_start = (uintptr_t)buf;
2200 debug_frame.fde.func_len = buf_size;
2201
2202 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2203 }
QEmu