tcg-ppc64: Support the ppc64 elfv2 ABI
[qemu.git] / target-arm / kvm64.c
blob5d217ca2ad1f024c9c6e6b303a40a5c0c2002eeb
1 /*
2 * ARM implementation of KVM hooks, 64 bit specific code
4 * Copyright Mian-M. Hamayun 2013, Virtual Open Systems
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
9 */
11 #include <stdio.h>
12 #include <sys/types.h>
13 #include <sys/ioctl.h>
14 #include <sys/mman.h>
16 #include <linux/kvm.h>
18 #include "qemu-common.h"
19 #include "qemu/timer.h"
20 #include "sysemu/sysemu.h"
21 #include "sysemu/kvm.h"
22 #include "kvm_arm.h"
23 #include "cpu.h"
24 #include "hw/arm/arm.h"
26 static inline void set_feature(uint64_t *features, int feature)
28 *features |= 1ULL << feature;
31 bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
33 /* Identify the feature bits corresponding to the host CPU, and
34 * fill out the ARMHostCPUClass fields accordingly. To do this
35 * we have to create a scratch VM, create a single CPU inside it,
36 * and then query that CPU for the relevant ID registers.
37 * For AArch64 we currently don't care about ID registers at
38 * all; we just want to know the CPU type.
40 int fdarray[3];
41 uint64_t features = 0;
42 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
43 * we know these will only support creating one kind of guest CPU,
44 * which is its preferred CPU type. Fortunately these old kernels
45 * support only a very limited number of CPUs.
47 static const uint32_t cpus_to_try[] = {
48 KVM_ARM_TARGET_AEM_V8,
49 KVM_ARM_TARGET_FOUNDATION_V8,
50 KVM_ARM_TARGET_CORTEX_A57,
51 QEMU_KVM_ARM_TARGET_NONE
53 struct kvm_vcpu_init init;
55 if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
56 return false;
59 ahcc->target = init.target;
60 ahcc->dtb_compatible = "arm,arm-v8";
62 kvm_arm_destroy_scratch_host_vcpu(fdarray);
64 /* We can assume any KVM supporting CPU is at least a v8
65 * with VFPv4+Neon; this in turn implies most of the other
66 * feature bits.
68 set_feature(&features, ARM_FEATURE_V8);
69 set_feature(&features, ARM_FEATURE_VFP4);
70 set_feature(&features, ARM_FEATURE_NEON);
71 set_feature(&features, ARM_FEATURE_AARCH64);
73 ahcc->features = features;
75 return true;
78 int kvm_arch_init_vcpu(CPUState *cs)
80 int ret;
81 ARMCPU *cpu = ARM_CPU(cs);
83 if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
84 !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
85 fprintf(stderr, "KVM is not supported for this guest CPU type\n");
86 return -EINVAL;
89 /* Determine init features for this CPU */
90 memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
91 if (cpu->start_powered_off) {
92 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
94 if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
95 cpu->psci_version = 2;
96 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
99 /* Do KVM_ARM_VCPU_INIT ioctl */
100 ret = kvm_arm_vcpu_init(cs);
101 if (ret) {
102 return ret;
105 /* TODO : support for save/restore/reset of system regs via tuple list */
107 return 0;
110 #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
111 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
113 int kvm_arch_put_registers(CPUState *cs, int level)
115 struct kvm_one_reg reg;
116 uint64_t val;
117 int i;
118 int ret;
120 ARMCPU *cpu = ARM_CPU(cs);
121 CPUARMState *env = &cpu->env;
123 for (i = 0; i < 31; i++) {
124 reg.id = AARCH64_CORE_REG(regs.regs[i]);
125 reg.addr = (uintptr_t) &env->xregs[i];
126 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
127 if (ret) {
128 return ret;
132 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
133 * QEMU side we keep the current SP in xregs[31] as well.
135 if (env->pstate & PSTATE_SP) {
136 env->sp_el[1] = env->xregs[31];
137 } else {
138 env->sp_el[0] = env->xregs[31];
141 reg.id = AARCH64_CORE_REG(regs.sp);
142 reg.addr = (uintptr_t) &env->sp_el[0];
143 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
144 if (ret) {
145 return ret;
148 reg.id = AARCH64_CORE_REG(sp_el1);
149 reg.addr = (uintptr_t) &env->sp_el[1];
150 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
151 if (ret) {
152 return ret;
155 /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */
156 val = pstate_read(env);
157 reg.id = AARCH64_CORE_REG(regs.pstate);
158 reg.addr = (uintptr_t) &val;
159 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
160 if (ret) {
161 return ret;
164 reg.id = AARCH64_CORE_REG(regs.pc);
165 reg.addr = (uintptr_t) &env->pc;
166 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
167 if (ret) {
168 return ret;
171 reg.id = AARCH64_CORE_REG(elr_el1);
172 reg.addr = (uintptr_t) &env->elr_el[1];
173 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
174 if (ret) {
175 return ret;
178 for (i = 0; i < KVM_NR_SPSR; i++) {
179 reg.id = AARCH64_CORE_REG(spsr[i]);
180 reg.addr = (uintptr_t) &env->banked_spsr[i - 1];
181 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
182 if (ret) {
183 return ret;
187 /* TODO:
188 * FP state
189 * system registers
191 return ret;
194 int kvm_arch_get_registers(CPUState *cs)
196 struct kvm_one_reg reg;
197 uint64_t val;
198 int i;
199 int ret;
201 ARMCPU *cpu = ARM_CPU(cs);
202 CPUARMState *env = &cpu->env;
204 for (i = 0; i < 31; i++) {
205 reg.id = AARCH64_CORE_REG(regs.regs[i]);
206 reg.addr = (uintptr_t) &env->xregs[i];
207 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
208 if (ret) {
209 return ret;
213 reg.id = AARCH64_CORE_REG(regs.sp);
214 reg.addr = (uintptr_t) &env->sp_el[0];
215 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
216 if (ret) {
217 return ret;
220 reg.id = AARCH64_CORE_REG(sp_el1);
221 reg.addr = (uintptr_t) &env->sp_el[1];
222 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
223 if (ret) {
224 return ret;
227 reg.id = AARCH64_CORE_REG(regs.pstate);
228 reg.addr = (uintptr_t) &val;
229 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
230 if (ret) {
231 return ret;
233 pstate_write(env, val);
235 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
236 * QEMU side we keep the current SP in xregs[31] as well.
238 if (env->pstate & PSTATE_SP) {
239 env->xregs[31] = env->sp_el[1];
240 } else {
241 env->xregs[31] = env->sp_el[0];
244 reg.id = AARCH64_CORE_REG(regs.pc);
245 reg.addr = (uintptr_t) &env->pc;
246 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
247 if (ret) {
248 return ret;
251 reg.id = AARCH64_CORE_REG(elr_el1);
252 reg.addr = (uintptr_t) &env->elr_el[1];
253 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
254 if (ret) {
255 return ret;
258 for (i = 0; i < KVM_NR_SPSR; i++) {
259 reg.id = AARCH64_CORE_REG(spsr[i]);
260 reg.addr = (uintptr_t) &env->banked_spsr[i - 1];
261 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
262 if (ret) {
263 return ret;
267 /* TODO: other registers */
268 return ret;
271 void kvm_arm_reset_vcpu(ARMCPU *cpu)
273 /* Re-init VCPU so that all registers are set to
274 * their respective reset values.
276 kvm_arm_vcpu_init(CPU(cpu));