target/rx/cpu.c

   1 /*
   2  * QEMU RX CPU
   3  *
   4  * Copyright (c) 2019 Yoshinori Sato
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "qemu/qemu-print.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "migration/vmstate.h"
  24 #include "exec/exec-all.h"
  25 #include "hw/loader.h"
  26 #include "fpu/softfloat.h"
  27
  28 static void rx_cpu_set_pc(CPUState *cs, vaddr value)
  29 {
  30     RXCPU *cpu = RX_CPU(cs);
  31
  32     cpu->env.pc = value;
  33 }
  34
  35 static vaddr rx_cpu_get_pc(CPUState *cs)
  36 {
  37     RXCPU *cpu = RX_CPU(cs);
  38
  39     return cpu->env.pc;
  40 }
  41
  42 static void rx_cpu_synchronize_from_tb(CPUState *cs,
  43                                        const TranslationBlock *tb)
  44 {
  45     RXCPU *cpu = RX_CPU(cs);
  46
  47     cpu->env.pc = tb_pc(tb);
  48 }
  49
  50 static void rx_restore_state_to_opc(CPUState *cs,
  51                                     const TranslationBlock *tb,
  52                                     const uint64_t *data)
  53 {
  54     RXCPU *cpu = RX_CPU(cs);
  55
  56     cpu->env.pc = data[0];
  57 }
  58
  59 static bool rx_cpu_has_work(CPUState *cs)
  60 {
  61     return cs->interrupt_request &
  62         (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
  63 }
  64
  65 static void rx_cpu_reset(DeviceState *dev)
  66 {
  67     RXCPU *cpu = RX_CPU(dev);
  68     RXCPUClass *rcc = RX_CPU_GET_CLASS(cpu);
  69     CPURXState *env = &cpu->env;
  70     uint32_t *resetvec;
  71
  72     rcc->parent_reset(dev);
  73
  74     memset(env, 0, offsetof(CPURXState, end_reset_fields));
  75
  76     resetvec = rom_ptr(0xfffffffc, 4);
  77     if (resetvec) {
  78         /* In the case of kernel, it is ignored because it is not set. */
  79         env->pc = ldl_p(resetvec);
  80     }
  81     rx_cpu_unpack_psw(env, 0, 1);
  82     env->regs[0] = env->isp = env->usp = 0;
  83     env->fpsw = 0;
  84     set_flush_to_zero(1, &env->fp_status);
  85     set_flush_inputs_to_zero(1, &env->fp_status);
  86 }
  87
  88 static void rx_cpu_list_entry(gpointer data, gpointer user_data)
  89 {
  90     ObjectClass *oc = data;
  91
  92     qemu_printf("  %s\n", object_class_get_name(oc));
  93 }
  94
  95 void rx_cpu_list(void)
  96 {
  97     GSList *list;
  98     list = object_class_get_list_sorted(TYPE_RX_CPU, false);
  99     qemu_printf("Available CPUs:\n");
 100     g_slist_foreach(list, rx_cpu_list_entry, NULL);
 101     g_slist_free(list);
 102 }
 103
 104 static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
 105 {
 106     ObjectClass *oc;
 107     char *typename;
 108
 109     oc = object_class_by_name(cpu_model);
 110     if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL &&
 111         !object_class_is_abstract(oc)) {
 112         return oc;
 113     }
 114     typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model);
 115     oc = object_class_by_name(typename);
 116     g_free(typename);
 117     if (oc != NULL && object_class_is_abstract(oc)) {
 118         oc = NULL;
 119     }
 120
 121     return oc;
 122 }
 123
 124 static void rx_cpu_realize(DeviceState *dev, Error **errp)
 125 {
 126     CPUState *cs = CPU(dev);
 127     RXCPUClass *rcc = RX_CPU_GET_CLASS(dev);
 128     Error *local_err = NULL;
 129
 130     cpu_exec_realizefn(cs, &local_err);
 131     if (local_err != NULL) {
 132         error_propagate(errp, local_err);
 133         return;
 134     }
 135
 136     qemu_init_vcpu(cs);
 137     cpu_reset(cs);
 138
 139     rcc->parent_realize(dev, errp);
 140 }
 141
 142 static void rx_cpu_set_irq(void *opaque, int no, int request)
 143 {
 144     RXCPU *cpu = opaque;
 145     CPUState *cs = CPU(cpu);
 146     int irq = request & 0xff;
 147
 148     static const int mask[] = {
 149         [RX_CPU_IRQ] = CPU_INTERRUPT_HARD,
 150         [RX_CPU_FIR] = CPU_INTERRUPT_FIR,
 151     };
 152     if (irq) {
 153         cpu->env.req_irq = irq;
 154         cpu->env.req_ipl = (request >> 8) & 0x0f;
 155         cpu_interrupt(cs, mask[no]);
 156     } else {
 157         cpu_reset_interrupt(cs, mask[no]);
 158     }
 159 }
 160
 161 static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
 162 {
 163     info->mach = bfd_mach_rx;
 164     info->print_insn = print_insn_rx;
 165 }
 166
 167 static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
 168                             MMUAccessType access_type, int mmu_idx,
 169                             bool probe, uintptr_t retaddr)
 170 {
 171     uint32_t address, physical, prot;
 172
 173     /* Linear mapping */
 174     address = physical = addr & TARGET_PAGE_MASK;
 175     prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 176     tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
 177     return true;
 178 }
 179
 180 static void rx_cpu_init(Object *obj)
 181 {
 182     CPUState *cs = CPU(obj);
 183     RXCPU *cpu = RX_CPU(obj);
 184     CPURXState *env = &cpu->env;
 185
 186     cpu_set_cpustate_pointers(cpu);
 187     cs->env_ptr = env;
 188     qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
 189 }
 190
 191 #ifndef CONFIG_USER_ONLY
 192 #include "hw/core/sysemu-cpu-ops.h"
 193
 194 static const struct SysemuCPUOps rx_sysemu_ops = {
 195     .get_phys_page_debug = rx_cpu_get_phys_page_debug,
 196 };
 197 #endif
 198
 199 #include "hw/core/tcg-cpu-ops.h"
 200
 201 static const struct TCGCPUOps rx_tcg_ops = {
 202     .initialize = rx_translate_init,
 203     .synchronize_from_tb = rx_cpu_synchronize_from_tb,
 204     .restore_state_to_opc = rx_restore_state_to_opc,
 205     .tlb_fill = rx_cpu_tlb_fill,
 206
 207 #ifndef CONFIG_USER_ONLY
 208     .cpu_exec_interrupt = rx_cpu_exec_interrupt,
 209     .do_interrupt = rx_cpu_do_interrupt,
 210 #endif /* !CONFIG_USER_ONLY */
 211 };
 212
 213 static void rx_cpu_class_init(ObjectClass *klass, void *data)
 214 {
 215     DeviceClass *dc = DEVICE_CLASS(klass);
 216     CPUClass *cc = CPU_CLASS(klass);
 217     RXCPUClass *rcc = RX_CPU_CLASS(klass);
 218
 219     device_class_set_parent_realize(dc, rx_cpu_realize,
 220                                     &rcc->parent_realize);
 221     device_class_set_parent_reset(dc, rx_cpu_reset,
 222                                   &rcc->parent_reset);
 223
 224     cc->class_by_name = rx_cpu_class_by_name;
 225     cc->has_work = rx_cpu_has_work;
 226     cc->dump_state = rx_cpu_dump_state;
 227     cc->set_pc = rx_cpu_set_pc;
 228     cc->get_pc = rx_cpu_get_pc;
 229
 230 #ifndef CONFIG_USER_ONLY
 231     cc->sysemu_ops = &rx_sysemu_ops;
 232 #endif
 233     cc->gdb_read_register = rx_cpu_gdb_read_register;
 234     cc->gdb_write_register = rx_cpu_gdb_write_register;
 235     cc->disas_set_info = rx_cpu_disas_set_info;
 236
 237     cc->gdb_num_core_regs = 26;
 238     cc->gdb_core_xml_file = "rx-core.xml";
 239     cc->tcg_ops = &rx_tcg_ops;
 240 }
 241
 242 static const TypeInfo rx_cpu_info = {
 243     .name = TYPE_RX_CPU,
 244     .parent = TYPE_CPU,
 245     .instance_size = sizeof(RXCPU),
 246     .instance_init = rx_cpu_init,
 247     .abstract = true,
 248     .class_size = sizeof(RXCPUClass),
 249     .class_init = rx_cpu_class_init,
 250 };
 251
 252 static const TypeInfo rx62n_rx_cpu_info = {
 253     .name = TYPE_RX62N_CPU,
 254     .parent = TYPE_RX_CPU,
 255 };
 256
 257 static void rx_cpu_register_types(void)
 258 {
 259     type_register_static(&rx_cpu_info);
 260     type_register_static(&rx62n_rx_cpu_info);
 261 }
 262
 263 type_init(rx_cpu_register_types)