2 * QEMU PowerPC e500-based platforms
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
6 * Author: Yu Liu, <yu.liu@freescale.com>
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include "qemu/osdep.h"
18 #include "qemu/datadir.h"
19 #include "qemu/units.h"
20 #include "qemu/guest-random.h"
21 #include "qapi/error.h"
23 #include "e500-ccsr.h"
25 #include "qemu/config-file.h"
26 #include "hw/char/serial.h"
27 #include "hw/pci/pci.h"
28 #include "sysemu/sysemu.h"
29 #include "sysemu/kvm.h"
30 #include "sysemu/reset.h"
31 #include "sysemu/runstate.h"
33 #include "sysemu/device_tree.h"
34 #include "hw/ppc/openpic.h"
35 #include "hw/ppc/openpic_kvm.h"
36 #include "hw/ppc/ppc.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/loader.h"
40 #include "hw/sysbus.h"
41 #include "qemu/host-utils.h"
42 #include "qemu/option.h"
43 #include "hw/pci-host/ppce500.h"
44 #include "qemu/error-report.h"
45 #include "hw/platform-bus.h"
46 #include "hw/net/fsl_etsec/etsec.h"
47 #include "hw/i2c/i2c.h"
50 #define EPAPR_MAGIC (0x45504150)
51 #define DTC_LOAD_PAD 0x1800000
52 #define DTC_PAD_MASK 0xFFFFF
53 #define DTB_MAX_SIZE (8 * MiB)
54 #define INITRD_LOAD_PAD 0x2000000
55 #define INITRD_PAD_MASK 0xFFFFFF
57 #define RAM_SIZES_ALIGN (64 * MiB)
59 /* TODO: parameterize */
60 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL
61 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
62 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL
63 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
64 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
65 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL
66 #define MPC8544_PCI_REGS_SIZE 0x1000ULL
67 #define MPC8544_UTIL_OFFSET 0xe0000ULL
68 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
69 #define MPC8544_I2C_REGS_OFFSET 0x3000ULL
70 #define MPC8XXX_GPIO_IRQ 47
71 #define MPC8544_I2C_IRQ 43
72 #define RTC_REGS_OFFSET 0x68
74 #define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
83 static uint32_t *pci_map_create(void *fdt
, uint32_t mpic
, int first_slot
,
84 int nr_slots
, int *len
)
90 int last_slot
= first_slot
+ nr_slots
;
93 *len
= nr_slots
* 4 * 7 * sizeof(uint32_t);
94 pci_map
= g_malloc(*len
);
96 for (slot
= first_slot
; slot
< last_slot
; slot
++) {
97 for (pci_irq
= 0; pci_irq
< 4; pci_irq
++) {
98 pci_map
[i
++] = cpu_to_be32(slot
<< 11);
99 pci_map
[i
++] = cpu_to_be32(0x0);
100 pci_map
[i
++] = cpu_to_be32(0x0);
101 pci_map
[i
++] = cpu_to_be32(pci_irq
+ 1);
102 pci_map
[i
++] = cpu_to_be32(mpic
);
103 host_irq
= ppce500_pci_map_irq_slot(slot
, pci_irq
);
104 pci_map
[i
++] = cpu_to_be32(host_irq
+ 1);
105 pci_map
[i
++] = cpu_to_be32(0x1);
109 assert((i
* sizeof(uint32_t)) == *len
);
114 static void dt_serial_create(void *fdt
, unsigned long long offset
,
115 const char *soc
, const char *mpic
,
116 const char *alias
, int idx
, bool defcon
)
120 ser
= g_strdup_printf("%s/serial@%llx", soc
, offset
);
121 qemu_fdt_add_subnode(fdt
, ser
);
122 qemu_fdt_setprop_string(fdt
, ser
, "device_type", "serial");
123 qemu_fdt_setprop_string(fdt
, ser
, "compatible", "ns16550");
124 qemu_fdt_setprop_cells(fdt
, ser
, "reg", offset
, 0x100);
125 qemu_fdt_setprop_cell(fdt
, ser
, "cell-index", idx
);
126 qemu_fdt_setprop_cell(fdt
, ser
, "clock-frequency", PLATFORM_CLK_FREQ_HZ
);
127 qemu_fdt_setprop_cells(fdt
, ser
, "interrupts", 42, 2);
128 qemu_fdt_setprop_phandle(fdt
, ser
, "interrupt-parent", mpic
);
129 qemu_fdt_setprop_string(fdt
, "/aliases", alias
, ser
);
133 * "linux,stdout-path" and "stdout" properties are deprecated by linux
134 * kernel. New platforms should only use the "stdout-path" property. Set
135 * the new property and continue using older property to remain
136 * compatible with the existing firmware.
138 qemu_fdt_setprop_string(fdt
, "/chosen", "linux,stdout-path", ser
);
139 qemu_fdt_setprop_string(fdt
, "/chosen", "stdout-path", ser
);
144 static void create_dt_mpc8xxx_gpio(void *fdt
, const char *soc
, const char *mpic
)
146 hwaddr mmio0
= MPC8XXX_GPIO_OFFSET
;
147 int irq0
= MPC8XXX_GPIO_IRQ
;
148 gchar
*node
= g_strdup_printf("%s/gpio@%"PRIx64
, soc
, mmio0
);
149 gchar
*poweroff
= g_strdup_printf("%s/power-off", soc
);
152 qemu_fdt_add_subnode(fdt
, node
);
153 qemu_fdt_setprop_string(fdt
, node
, "compatible", "fsl,qoriq-gpio");
154 qemu_fdt_setprop_cells(fdt
, node
, "reg", mmio0
, 0x1000);
155 qemu_fdt_setprop_cells(fdt
, node
, "interrupts", irq0
, 0x2);
156 qemu_fdt_setprop_phandle(fdt
, node
, "interrupt-parent", mpic
);
157 qemu_fdt_setprop_cells(fdt
, node
, "#gpio-cells", 2);
158 qemu_fdt_setprop(fdt
, node
, "gpio-controller", NULL
, 0);
159 gpio_ph
= qemu_fdt_alloc_phandle(fdt
);
160 qemu_fdt_setprop_cell(fdt
, node
, "phandle", gpio_ph
);
161 qemu_fdt_setprop_cell(fdt
, node
, "linux,phandle", gpio_ph
);
164 qemu_fdt_add_subnode(fdt
, poweroff
);
165 qemu_fdt_setprop_string(fdt
, poweroff
, "compatible", "gpio-poweroff");
166 qemu_fdt_setprop_cells(fdt
, poweroff
, "gpios", gpio_ph
, 0, 0);
172 static void dt_rtc_create(void *fdt
, const char *i2c
, const char *alias
)
174 int offset
= RTC_REGS_OFFSET
;
176 gchar
*rtc
= g_strdup_printf("%s/rtc@%"PRIx32
, i2c
, offset
);
177 qemu_fdt_add_subnode(fdt
, rtc
);
178 qemu_fdt_setprop_string(fdt
, rtc
, "compatible", "pericom,pt7c4338");
179 qemu_fdt_setprop_cells(fdt
, rtc
, "reg", offset
);
180 qemu_fdt_setprop_string(fdt
, "/aliases", alias
, rtc
);
185 static void dt_i2c_create(void *fdt
, const char *soc
, const char *mpic
,
188 hwaddr mmio0
= MPC8544_I2C_REGS_OFFSET
;
189 int irq0
= MPC8544_I2C_IRQ
;
191 gchar
*i2c
= g_strdup_printf("%s/i2c@%"PRIx64
, soc
, mmio0
);
192 qemu_fdt_add_subnode(fdt
, i2c
);
193 qemu_fdt_setprop_string(fdt
, i2c
, "device_type", "i2c");
194 qemu_fdt_setprop_string(fdt
, i2c
, "compatible", "fsl-i2c");
195 qemu_fdt_setprop_cells(fdt
, i2c
, "reg", mmio0
, 0x14);
196 qemu_fdt_setprop_cells(fdt
, i2c
, "cell-index", 0);
197 qemu_fdt_setprop_cells(fdt
, i2c
, "interrupts", irq0
, 0x2);
198 qemu_fdt_setprop_phandle(fdt
, i2c
, "interrupt-parent", mpic
);
199 qemu_fdt_setprop_string(fdt
, "/aliases", alias
, i2c
);
205 typedef struct PlatformDevtreeData
{
210 PlatformBusDevice
*pbus
;
211 } PlatformDevtreeData
;
213 static int create_devtree_etsec(SysBusDevice
*sbdev
, PlatformDevtreeData
*data
)
215 eTSEC
*etsec
= ETSEC_COMMON(sbdev
);
216 PlatformBusDevice
*pbus
= data
->pbus
;
217 hwaddr mmio0
= platform_bus_get_mmio_addr(pbus
, sbdev
, 0);
218 int irq0
= platform_bus_get_irqn(pbus
, sbdev
, 0);
219 int irq1
= platform_bus_get_irqn(pbus
, sbdev
, 1);
220 int irq2
= platform_bus_get_irqn(pbus
, sbdev
, 2);
221 gchar
*node
= g_strdup_printf("/platform/ethernet@%"PRIx64
, mmio0
);
222 gchar
*group
= g_strdup_printf("%s/queue-group", node
);
223 void *fdt
= data
->fdt
;
225 assert((int64_t)mmio0
>= 0);
230 qemu_fdt_add_subnode(fdt
, node
);
231 qemu_fdt_setprop(fdt
, node
, "ranges", NULL
, 0);
232 qemu_fdt_setprop_string(fdt
, node
, "device_type", "network");
233 qemu_fdt_setprop_string(fdt
, node
, "compatible", "fsl,etsec2");
234 qemu_fdt_setprop_string(fdt
, node
, "model", "eTSEC");
235 qemu_fdt_setprop(fdt
, node
, "local-mac-address", etsec
->conf
.macaddr
.a
, 6);
236 qemu_fdt_setprop_cells(fdt
, node
, "fixed-link", 0, 1, 1000, 0, 0);
237 qemu_fdt_setprop_cells(fdt
, node
, "#size-cells", 1);
238 qemu_fdt_setprop_cells(fdt
, node
, "#address-cells", 1);
240 qemu_fdt_add_subnode(fdt
, group
);
241 qemu_fdt_setprop_cells(fdt
, group
, "reg", mmio0
, 0x1000);
242 qemu_fdt_setprop_cells(fdt
, group
, "interrupts",
243 data
->irq_start
+ irq0
, 0x2,
244 data
->irq_start
+ irq1
, 0x2,
245 data
->irq_start
+ irq2
, 0x2);
253 static void sysbus_device_create_devtree(SysBusDevice
*sbdev
, void *opaque
)
255 PlatformDevtreeData
*data
= opaque
;
256 bool matched
= false;
258 if (object_dynamic_cast(OBJECT(sbdev
), TYPE_ETSEC_COMMON
)) {
259 create_devtree_etsec(sbdev
, data
);
264 error_report("Device %s is not supported by this machine yet.",
265 qdev_fw_name(DEVICE(sbdev
)));
270 static void platform_bus_create_devtree(PPCE500MachineState
*pms
,
271 void *fdt
, const char *mpic
)
273 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
274 gchar
*node
= g_strdup_printf("/platform@%"PRIx64
, pmc
->platform_bus_base
);
275 const char platcomp
[] = "qemu,platform\0simple-bus";
276 uint64_t addr
= pmc
->platform_bus_base
;
277 uint64_t size
= pmc
->platform_bus_size
;
278 int irq_start
= pmc
->platform_bus_first_irq
;
280 /* Create a /platform node that we can put all devices into */
282 qemu_fdt_add_subnode(fdt
, node
);
283 qemu_fdt_setprop(fdt
, node
, "compatible", platcomp
, sizeof(platcomp
));
285 /* Our platform bus region is less than 32bit big, so 1 cell is enough for
287 qemu_fdt_setprop_cells(fdt
, node
, "#size-cells", 1);
288 qemu_fdt_setprop_cells(fdt
, node
, "#address-cells", 1);
289 qemu_fdt_setprop_cells(fdt
, node
, "ranges", 0, addr
>> 32, addr
, size
);
291 qemu_fdt_setprop_phandle(fdt
, node
, "interrupt-parent", mpic
);
293 /* Create dt nodes for dynamic devices */
294 PlatformDevtreeData data
= {
297 .irq_start
= irq_start
,
299 .pbus
= pms
->pbus_dev
,
302 /* Loop through all dynamic sysbus devices and create nodes for them */
303 foreach_dynamic_sysbus_device(sysbus_device_create_devtree
, &data
);
308 static int ppce500_load_device_tree(PPCE500MachineState
*pms
,
316 MachineState
*machine
= MACHINE(pms
);
317 unsigned int smp_cpus
= machine
->smp
.cpus
;
318 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
319 CPUPPCState
*env
= first_cpu
->env_ptr
;
321 uint64_t mem_reg_property
[] = { 0, cpu_to_be64(machine
->ram_size
) };
324 uint8_t hypercall
[16];
325 uint32_t clock_freq
= PLATFORM_CLK_FREQ_HZ
;
326 uint32_t tb_freq
= PLATFORM_CLK_FREQ_HZ
;
328 char compatible_sb
[] = "fsl,mpc8544-immr\0simple-bus";
336 uint32_t *pci_map
= NULL
;
338 uint32_t pci_ranges
[14] =
340 0x2000000, 0x0, pmc
->pci_mmio_bus_base
,
341 pmc
->pci_mmio_base
>> 32, pmc
->pci_mmio_base
,
345 pmc
->pci_pio_base
>> 32, pmc
->pci_pio_base
,
348 const char *dtb_file
= machine
->dtb
;
349 const char *toplevel_compat
= machine
->dt_compatible
;
350 uint8_t rng_seed
[32];
354 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, dtb_file
);
359 fdt
= load_device_tree(filename
, &fdt_size
);
367 fdt
= create_device_tree(&fdt_size
);
372 /* Manipulate device tree in memory. */
373 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 2);
374 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 2);
376 qemu_fdt_add_subnode(fdt
, "/memory");
377 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
378 qemu_fdt_setprop(fdt
, "/memory", "reg", mem_reg_property
,
379 sizeof(mem_reg_property
));
381 qemu_fdt_add_subnode(fdt
, "/chosen");
383 ret
= qemu_fdt_setprop_cell(fdt
, "/chosen", "linux,initrd-start",
386 fprintf(stderr
, "couldn't set /chosen/linux,initrd-start\n");
389 ret
= qemu_fdt_setprop_cell(fdt
, "/chosen", "linux,initrd-end",
390 (initrd_base
+ initrd_size
));
392 fprintf(stderr
, "couldn't set /chosen/linux,initrd-end\n");
397 if (kernel_base
!= -1ULL) {
398 qemu_fdt_setprop_cells(fdt
, "/chosen", "qemu,boot-kernel",
399 kernel_base
>> 32, kernel_base
,
400 kernel_size
>> 32, kernel_size
);
403 ret
= qemu_fdt_setprop_string(fdt
, "/chosen", "bootargs",
404 machine
->kernel_cmdline
);
406 fprintf(stderr
, "couldn't set /chosen/bootargs\n");
408 qemu_guest_getrandom_nofail(rng_seed
, sizeof(rng_seed
));
409 qemu_fdt_setprop(fdt
, "/chosen", "rng-seed", rng_seed
, sizeof(rng_seed
));
412 /* Read out host's frequencies */
413 clock_freq
= kvmppc_get_clockfreq();
414 tb_freq
= kvmppc_get_tbfreq();
416 /* indicate KVM hypercall interface */
417 qemu_fdt_add_subnode(fdt
, "/hypervisor");
418 qemu_fdt_setprop_string(fdt
, "/hypervisor", "compatible",
420 kvmppc_get_hypercall(env
, hypercall
, sizeof(hypercall
));
421 qemu_fdt_setprop(fdt
, "/hypervisor", "hcall-instructions",
422 hypercall
, sizeof(hypercall
));
423 /* if KVM supports the idle hcall, set property indicating this */
424 if (kvmppc_get_hasidle(env
)) {
425 qemu_fdt_setprop(fdt
, "/hypervisor", "has-idle", NULL
, 0);
429 /* Create CPU nodes */
430 qemu_fdt_add_subnode(fdt
, "/cpus");
431 qemu_fdt_setprop_cell(fdt
, "/cpus", "#address-cells", 1);
432 qemu_fdt_setprop_cell(fdt
, "/cpus", "#size-cells", 0);
434 /* We need to generate the cpu nodes in reverse order, so Linux can pick
435 the first node as boot node and be happy */
436 for (i
= smp_cpus
- 1; i
>= 0; i
--) {
439 uint64_t cpu_release_addr
= pmc
->spin_base
+ (i
* 0x20);
441 cpu
= qemu_get_cpu(i
);
447 cpu_name
= g_strdup_printf("/cpus/PowerPC,8544@%x", i
);
448 qemu_fdt_add_subnode(fdt
, cpu_name
);
449 qemu_fdt_setprop_cell(fdt
, cpu_name
, "clock-frequency", clock_freq
);
450 qemu_fdt_setprop_cell(fdt
, cpu_name
, "timebase-frequency", tb_freq
);
451 qemu_fdt_setprop_string(fdt
, cpu_name
, "device_type", "cpu");
452 qemu_fdt_setprop_cell(fdt
, cpu_name
, "reg", i
);
453 qemu_fdt_setprop_cell(fdt
, cpu_name
, "d-cache-line-size",
454 env
->dcache_line_size
);
455 qemu_fdt_setprop_cell(fdt
, cpu_name
, "i-cache-line-size",
456 env
->icache_line_size
);
457 qemu_fdt_setprop_cell(fdt
, cpu_name
, "d-cache-size", 0x8000);
458 qemu_fdt_setprop_cell(fdt
, cpu_name
, "i-cache-size", 0x8000);
459 qemu_fdt_setprop_cell(fdt
, cpu_name
, "bus-frequency", 0);
460 if (cpu
->cpu_index
) {
461 qemu_fdt_setprop_string(fdt
, cpu_name
, "status", "disabled");
462 qemu_fdt_setprop_string(fdt
, cpu_name
, "enable-method",
464 qemu_fdt_setprop_u64(fdt
, cpu_name
, "cpu-release-addr",
467 qemu_fdt_setprop_string(fdt
, cpu_name
, "status", "okay");
472 qemu_fdt_add_subnode(fdt
, "/aliases");
473 /* XXX These should go into their respective devices' code */
474 soc
= g_strdup_printf("/soc@%"PRIx64
, pmc
->ccsrbar_base
);
475 qemu_fdt_add_subnode(fdt
, soc
);
476 qemu_fdt_setprop_string(fdt
, soc
, "device_type", "soc");
477 qemu_fdt_setprop(fdt
, soc
, "compatible", compatible_sb
,
478 sizeof(compatible_sb
));
479 qemu_fdt_setprop_cell(fdt
, soc
, "#address-cells", 1);
480 qemu_fdt_setprop_cell(fdt
, soc
, "#size-cells", 1);
481 qemu_fdt_setprop_cells(fdt
, soc
, "ranges", 0x0,
482 pmc
->ccsrbar_base
>> 32, pmc
->ccsrbar_base
,
483 MPC8544_CCSRBAR_SIZE
);
484 /* XXX should contain a reasonable value */
485 qemu_fdt_setprop_cell(fdt
, soc
, "bus-frequency", 0);
487 mpic
= g_strdup_printf("%s/pic@%llx", soc
, MPC8544_MPIC_REGS_OFFSET
);
488 qemu_fdt_add_subnode(fdt
, mpic
);
489 qemu_fdt_setprop_string(fdt
, mpic
, "device_type", "open-pic");
490 qemu_fdt_setprop_string(fdt
, mpic
, "compatible", "fsl,mpic");
491 qemu_fdt_setprop_cells(fdt
, mpic
, "reg", MPC8544_MPIC_REGS_OFFSET
,
493 qemu_fdt_setprop_cell(fdt
, mpic
, "#address-cells", 0);
494 qemu_fdt_setprop_cell(fdt
, mpic
, "#interrupt-cells", 2);
495 mpic_ph
= qemu_fdt_alloc_phandle(fdt
);
496 qemu_fdt_setprop_cell(fdt
, mpic
, "phandle", mpic_ph
);
497 qemu_fdt_setprop_cell(fdt
, mpic
, "linux,phandle", mpic_ph
);
498 qemu_fdt_setprop(fdt
, mpic
, "interrupt-controller", NULL
, 0);
501 * We have to generate ser1 first, because Linux takes the first
502 * device it finds in the dt as serial output device. And we generate
503 * devices in reverse order to the dt.
506 dt_serial_create(fdt
, MPC8544_SERIAL1_REGS_OFFSET
,
507 soc
, mpic
, "serial1", 1, false);
511 dt_serial_create(fdt
, MPC8544_SERIAL0_REGS_OFFSET
,
512 soc
, mpic
, "serial0", 0, true);
516 dt_i2c_create(fdt
, soc
, mpic
, "i2c");
518 dt_rtc_create(fdt
, "i2c", "rtc");
521 gutil
= g_strdup_printf("%s/global-utilities@%llx", soc
,
522 MPC8544_UTIL_OFFSET
);
523 qemu_fdt_add_subnode(fdt
, gutil
);
524 qemu_fdt_setprop_string(fdt
, gutil
, "compatible", "fsl,mpc8544-guts");
525 qemu_fdt_setprop_cells(fdt
, gutil
, "reg", MPC8544_UTIL_OFFSET
, 0x1000);
526 qemu_fdt_setprop(fdt
, gutil
, "fsl,has-rstcr", NULL
, 0);
529 msi
= g_strdup_printf("/%s/msi@%llx", soc
, MPC8544_MSI_REGS_OFFSET
);
530 qemu_fdt_add_subnode(fdt
, msi
);
531 qemu_fdt_setprop_string(fdt
, msi
, "compatible", "fsl,mpic-msi");
532 qemu_fdt_setprop_cells(fdt
, msi
, "reg", MPC8544_MSI_REGS_OFFSET
, 0x200);
533 msi_ph
= qemu_fdt_alloc_phandle(fdt
);
534 qemu_fdt_setprop_cells(fdt
, msi
, "msi-available-ranges", 0x0, 0x100);
535 qemu_fdt_setprop_phandle(fdt
, msi
, "interrupt-parent", mpic
);
536 qemu_fdt_setprop_cells(fdt
, msi
, "interrupts",
545 qemu_fdt_setprop_cell(fdt
, msi
, "phandle", msi_ph
);
546 qemu_fdt_setprop_cell(fdt
, msi
, "linux,phandle", msi_ph
);
549 pci
= g_strdup_printf("/pci@%llx",
550 pmc
->ccsrbar_base
+ MPC8544_PCI_REGS_OFFSET
);
551 qemu_fdt_add_subnode(fdt
, pci
);
552 qemu_fdt_setprop_cell(fdt
, pci
, "cell-index", 0);
553 qemu_fdt_setprop_string(fdt
, pci
, "compatible", "fsl,mpc8540-pci");
554 qemu_fdt_setprop_string(fdt
, pci
, "device_type", "pci");
555 qemu_fdt_setprop_cells(fdt
, pci
, "interrupt-map-mask", 0xf800, 0x0,
557 pci_map
= pci_map_create(fdt
, qemu_fdt_get_phandle(fdt
, mpic
),
558 pmc
->pci_first_slot
, pmc
->pci_nr_slots
,
560 qemu_fdt_setprop(fdt
, pci
, "interrupt-map", pci_map
, len
);
561 qemu_fdt_setprop_phandle(fdt
, pci
, "interrupt-parent", mpic
);
562 qemu_fdt_setprop_cells(fdt
, pci
, "interrupts", 24, 2);
563 qemu_fdt_setprop_cells(fdt
, pci
, "bus-range", 0, 255);
564 for (i
= 0; i
< 14; i
++) {
565 pci_ranges
[i
] = cpu_to_be32(pci_ranges
[i
]);
567 qemu_fdt_setprop_cell(fdt
, pci
, "fsl,msi", msi_ph
);
568 qemu_fdt_setprop(fdt
, pci
, "ranges", pci_ranges
, sizeof(pci_ranges
));
569 qemu_fdt_setprop_cells(fdt
, pci
, "reg",
570 (pmc
->ccsrbar_base
+ MPC8544_PCI_REGS_OFFSET
) >> 32,
571 (pmc
->ccsrbar_base
+ MPC8544_PCI_REGS_OFFSET
),
573 qemu_fdt_setprop_cell(fdt
, pci
, "clock-frequency", 66666666);
574 qemu_fdt_setprop_cell(fdt
, pci
, "#interrupt-cells", 1);
575 qemu_fdt_setprop_cell(fdt
, pci
, "#size-cells", 2);
576 qemu_fdt_setprop_cell(fdt
, pci
, "#address-cells", 3);
577 qemu_fdt_setprop_string(fdt
, "/aliases", "pci0", pci
);
580 if (pmc
->has_mpc8xxx_gpio
) {
581 create_dt_mpc8xxx_gpio(fdt
, soc
, mpic
);
586 platform_bus_create_devtree(pms
, fdt
, mpic
);
590 pmc
->fixup_devtree(fdt
);
592 if (toplevel_compat
) {
593 qemu_fdt_setprop(fdt
, "/", "compatible", toplevel_compat
,
594 strlen(toplevel_compat
) + 1);
599 qemu_fdt_dumpdtb(fdt
, fdt_size
);
600 cpu_physical_memory_write(addr
, fdt
, fdt_size
);
611 typedef struct DeviceTreeParams
{
612 PPCE500MachineState
*machine
;
621 static void ppce500_reset_device_tree(void *opaque
)
623 DeviceTreeParams
*p
= opaque
;
624 ppce500_load_device_tree(p
->machine
, p
->addr
, p
->initrd_base
,
625 p
->initrd_size
, p
->kernel_base
, p
->kernel_size
,
629 static void ppce500_init_notify(Notifier
*notifier
, void *data
)
631 DeviceTreeParams
*p
= container_of(notifier
, DeviceTreeParams
, notifier
);
632 ppce500_reset_device_tree(p
);
635 static int ppce500_prep_device_tree(PPCE500MachineState
*machine
,
642 DeviceTreeParams
*p
= g_new(DeviceTreeParams
, 1);
643 p
->machine
= machine
;
645 p
->initrd_base
= initrd_base
;
646 p
->initrd_size
= initrd_size
;
647 p
->kernel_base
= kernel_base
;
648 p
->kernel_size
= kernel_size
;
650 qemu_register_reset(ppce500_reset_device_tree
, p
);
651 p
->notifier
.notify
= ppce500_init_notify
;
652 qemu_add_machine_init_done_notifier(&p
->notifier
);
654 /* Issue the device tree loader once, so that we get the size of the blob */
655 return ppce500_load_device_tree(machine
, addr
, initrd_base
, initrd_size
,
656 kernel_base
, kernel_size
, true);
659 /* Create -kernel TLB entries for BookE. */
660 hwaddr
booke206_page_size_to_tlb(uint64_t size
)
662 return 63 - clz64(size
/ KiB
);
665 static int booke206_initial_map_tsize(CPUPPCState
*env
)
667 struct boot_info
*bi
= env
->load_info
;
671 /* Our initial TLB entry needs to cover everything from 0 to
672 the device tree top */
673 dt_end
= bi
->dt_base
+ bi
->dt_size
;
674 ps
= booke206_page_size_to_tlb(dt_end
) + 1;
676 /* e500v2 can only do even TLB size bits */
682 static uint64_t mmubooke_initial_mapsize(CPUPPCState
*env
)
686 tsize
= booke206_initial_map_tsize(env
);
687 return (1ULL << 10 << tsize
);
690 static void mmubooke_create_initial_mapping(CPUPPCState
*env
)
692 ppcmas_tlb_t
*tlb
= booke206_get_tlbm(env
, 1, 0, 0);
696 ps
= booke206_initial_map_tsize(env
);
697 size
= (ps
<< MAS1_TSIZE_SHIFT
);
698 tlb
->mas1
= MAS1_VALID
| size
;
701 tlb
->mas7_3
|= MAS3_UR
| MAS3_UW
| MAS3_UX
| MAS3_SR
| MAS3_SW
| MAS3_SX
;
703 env
->tlb_dirty
= true;
706 static void ppce500_cpu_reset_sec(void *opaque
)
708 PowerPCCPU
*cpu
= opaque
;
709 CPUState
*cs
= CPU(cpu
);
713 cs
->exception_index
= EXCP_HLT
;
716 static void ppce500_cpu_reset(void *opaque
)
718 PowerPCCPU
*cpu
= opaque
;
719 CPUState
*cs
= CPU(cpu
);
720 CPUPPCState
*env
= &cpu
->env
;
721 struct boot_info
*bi
= env
->load_info
;
725 /* Set initial guest state. */
727 env
->gpr
[1] = (16 * MiB
) - 8;
728 env
->gpr
[3] = bi
->dt_base
;
731 env
->gpr
[6] = EPAPR_MAGIC
;
732 env
->gpr
[7] = mmubooke_initial_mapsize(env
);
735 env
->nip
= bi
->entry
;
736 mmubooke_create_initial_mapping(env
);
739 static DeviceState
*ppce500_init_mpic_qemu(PPCE500MachineState
*pms
,
745 MachineState
*machine
= MACHINE(pms
);
746 unsigned int smp_cpus
= machine
->smp
.cpus
;
747 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
749 dev
= qdev_new(TYPE_OPENPIC
);
750 object_property_add_child(OBJECT(machine
), "pic", OBJECT(dev
));
751 qdev_prop_set_uint32(dev
, "model", pmc
->mpic_version
);
752 qdev_prop_set_uint32(dev
, "nb_cpus", smp_cpus
);
754 s
= SYS_BUS_DEVICE(dev
);
755 sysbus_realize_and_unref(s
, &error_fatal
);
758 for (i
= 0; i
< smp_cpus
; i
++) {
759 for (j
= 0; j
< OPENPIC_OUTPUT_NB
; j
++) {
760 sysbus_connect_irq(s
, k
++, irqs
[i
].irq
[j
]);
767 static DeviceState
*ppce500_init_mpic_kvm(const PPCE500MachineClass
*pmc
,
768 IrqLines
*irqs
, Error
**errp
)
773 dev
= qdev_new(TYPE_KVM_OPENPIC
);
774 qdev_prop_set_uint32(dev
, "model", pmc
->mpic_version
);
776 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), errp
)) {
777 object_unparent(OBJECT(dev
));
782 if (kvm_openpic_connect_vcpu(dev
, cs
)) {
783 fprintf(stderr
, "%s: failed to connect vcpu to irqchip\n",
792 static DeviceState
*ppce500_init_mpic(PPCE500MachineState
*pms
,
796 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(pms
);
797 DeviceState
*dev
= NULL
;
803 if (kvm_kernel_irqchip_allowed()) {
804 dev
= ppce500_init_mpic_kvm(pmc
, irqs
, &err
);
806 if (kvm_kernel_irqchip_required() && !dev
) {
807 error_reportf_err(err
,
808 "kernel_irqchip requested but unavailable: ");
814 dev
= ppce500_init_mpic_qemu(pms
, irqs
);
817 s
= SYS_BUS_DEVICE(dev
);
818 memory_region_add_subregion(ccsr
, MPC8544_MPIC_REGS_OFFSET
,
824 static void ppce500_power_off(void *opaque
, int line
, int on
)
827 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN
);
831 void ppce500_init(MachineState
*machine
)
833 MemoryRegion
*address_space_mem
= get_system_memory();
834 PPCE500MachineState
*pms
= PPCE500_MACHINE(machine
);
835 const PPCE500MachineClass
*pmc
= PPCE500_MACHINE_GET_CLASS(machine
);
837 CPUPPCState
*env
= NULL
;
839 hwaddr kernel_base
= -1LL;
842 hwaddr initrd_base
= 0;
846 const char *payload_name
;
847 bool kernel_as_payload
;
848 hwaddr bios_entry
= 0;
849 target_long payload_size
;
850 struct boot_info
*boot_info
;
853 unsigned int smp_cpus
= machine
->smp
.cpus
;
854 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
856 unsigned int pci_irq_nrs
[PCI_NUM_PINS
] = {1, 2, 3, 4};
858 DeviceState
*dev
, *mpicdev
;
859 CPUPPCState
*firstenv
= NULL
;
860 MemoryRegion
*ccsr_addr_space
;
862 PPCE500CCSRState
*ccsr
;
865 irqs
= g_new0(IrqLines
, smp_cpus
);
866 for (i
= 0; i
< smp_cpus
; i
++) {
870 cpu
= POWERPC_CPU(object_new(machine
->cpu_type
));
874 if (env
->mmu_model
!= POWERPC_MMU_BOOKE206
) {
875 error_report("MMU model %i not supported by this machine",
881 * Secondary CPU starts in halted state for now. Needs to change
882 * when implementing non-kernel boot.
884 object_property_set_bool(OBJECT(cs
), "start-powered-off", i
!= 0,
886 qdev_realize_and_unref(DEVICE(cs
), NULL
, &error_fatal
);
892 irqs
[i
].irq
[OPENPIC_OUTPUT_INT
] =
893 qdev_get_gpio_in(DEVICE(cpu
), PPCE500_INPUT_INT
);
894 irqs
[i
].irq
[OPENPIC_OUTPUT_CINT
] =
895 qdev_get_gpio_in(DEVICE(cpu
), PPCE500_INPUT_CINT
);
896 env
->spr_cb
[SPR_BOOKE_PIR
].default_value
= cs
->cpu_index
= i
;
897 env
->mpic_iack
= pmc
->ccsrbar_base
+ MPC8544_MPIC_REGS_OFFSET
+ 0xa0;
899 ppc_booke_timers_init(cpu
, PLATFORM_CLK_FREQ_HZ
, PPC_TIMER_E500
);
901 /* Register reset handler */
904 struct boot_info
*boot_info
;
905 boot_info
= g_new0(struct boot_info
, 1);
906 qemu_register_reset(ppce500_cpu_reset
, cpu
);
907 env
->load_info
= boot_info
;
910 qemu_register_reset(ppce500_cpu_reset_sec
, cpu
);
916 if (!QEMU_IS_ALIGNED(machine
->ram_size
, RAM_SIZES_ALIGN
)) {
917 error_report("RAM size must be multiple of %" PRIu64
, RAM_SIZES_ALIGN
);
921 /* Register Memory */
922 memory_region_add_subregion(address_space_mem
, 0, machine
->ram
);
924 dev
= qdev_new("e500-ccsr");
925 object_property_add_child(qdev_get_machine(), "e500-ccsr",
927 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
929 ccsr_addr_space
= &ccsr
->ccsr_space
;
930 memory_region_add_subregion(address_space_mem
, pmc
->ccsrbar_base
,
933 mpicdev
= ppce500_init_mpic(pms
, ccsr_addr_space
, irqs
);
938 serial_mm_init(ccsr_addr_space
, MPC8544_SERIAL0_REGS_OFFSET
,
939 0, qdev_get_gpio_in(mpicdev
, 42), 399193,
940 serial_hd(0), DEVICE_BIG_ENDIAN
);
944 serial_mm_init(ccsr_addr_space
, MPC8544_SERIAL1_REGS_OFFSET
,
945 0, qdev_get_gpio_in(mpicdev
, 42), 399193,
946 serial_hd(1), DEVICE_BIG_ENDIAN
);
949 dev
= qdev_new("mpc-i2c");
950 s
= SYS_BUS_DEVICE(dev
);
951 sysbus_realize_and_unref(s
, &error_fatal
);
952 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(mpicdev
, MPC8544_I2C_IRQ
));
953 memory_region_add_subregion(ccsr_addr_space
, MPC8544_I2C_REGS_OFFSET
,
954 sysbus_mmio_get_region(s
, 0));
955 i2c
= (I2CBus
*)qdev_get_child_bus(dev
, "i2c");
956 i2c_slave_create_simple(i2c
, "ds1338", RTC_REGS_OFFSET
);
959 /* General Utility device */
960 dev
= qdev_new("mpc8544-guts");
961 s
= SYS_BUS_DEVICE(dev
);
962 sysbus_realize_and_unref(s
, &error_fatal
);
963 memory_region_add_subregion(ccsr_addr_space
, MPC8544_UTIL_OFFSET
,
964 sysbus_mmio_get_region(s
, 0));
967 dev
= qdev_new("e500-pcihost");
968 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev
));
969 qdev_prop_set_uint32(dev
, "first_slot", pmc
->pci_first_slot
);
970 qdev_prop_set_uint32(dev
, "first_pin_irq", pci_irq_nrs
[0]);
971 s
= SYS_BUS_DEVICE(dev
);
972 sysbus_realize_and_unref(s
, &error_fatal
);
973 for (i
= 0; i
< PCI_NUM_PINS
; i
++) {
974 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(mpicdev
, pci_irq_nrs
[i
]));
977 memory_region_add_subregion(ccsr_addr_space
, MPC8544_PCI_REGS_OFFSET
,
978 sysbus_mmio_get_region(s
, 0));
980 pci_bus
= (PCIBus
*)qdev_get_child_bus(dev
, "pci.0");
982 printf("couldn't create PCI controller!\n");
985 /* Register network interfaces. */
986 for (i
= 0; i
< nb_nics
; i
++) {
987 pci_nic_init_nofail(&nd_table
[i
], pci_bus
, "virtio-net-pci", NULL
);
991 /* Register spinning region */
992 sysbus_create_simple("e500-spin", pmc
->spin_base
, NULL
);
994 if (pmc
->has_mpc8xxx_gpio
) {
995 qemu_irq poweroff_irq
;
997 dev
= qdev_new("mpc8xxx_gpio");
998 s
= SYS_BUS_DEVICE(dev
);
999 sysbus_realize_and_unref(s
, &error_fatal
);
1000 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(mpicdev
, MPC8XXX_GPIO_IRQ
));
1001 memory_region_add_subregion(ccsr_addr_space
, MPC8XXX_GPIO_OFFSET
,
1002 sysbus_mmio_get_region(s
, 0));
1004 /* Power Off GPIO at Pin 0 */
1005 poweroff_irq
= qemu_allocate_irq(ppce500_power_off
, NULL
, 0);
1006 qdev_connect_gpio_out(dev
, 0, poweroff_irq
);
1009 /* Platform Bus Device */
1010 dev
= qdev_new(TYPE_PLATFORM_BUS_DEVICE
);
1011 dev
->id
= g_strdup(TYPE_PLATFORM_BUS_DEVICE
);
1012 qdev_prop_set_uint32(dev
, "num_irqs", pmc
->platform_bus_num_irqs
);
1013 qdev_prop_set_uint32(dev
, "mmio_size", pmc
->platform_bus_size
);
1014 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1015 pms
->pbus_dev
= PLATFORM_BUS_DEVICE(dev
);
1017 s
= SYS_BUS_DEVICE(pms
->pbus_dev
);
1018 for (i
= 0; i
< pmc
->platform_bus_num_irqs
; i
++) {
1019 int irqn
= pmc
->platform_bus_first_irq
+ i
;
1020 sysbus_connect_irq(s
, i
, qdev_get_gpio_in(mpicdev
, irqn
));
1023 memory_region_add_subregion(address_space_mem
,
1024 pmc
->platform_bus_base
,
1025 &pms
->pbus_dev
->mmio
);
1028 * Smart firmware defaults ahead!
1030 * We follow the following table to select which payload we execute.
1032 * -kernel | -bios | payload
1033 * ---------+-------+---------
1039 * This ensures backwards compatibility with how we used to expose
1040 * -kernel to users but allows them to run through u-boot as well.
1042 kernel_as_payload
= false;
1043 if (machine
->firmware
== NULL
) {
1044 if (machine
->kernel_filename
) {
1045 payload_name
= machine
->kernel_filename
;
1046 kernel_as_payload
= true;
1048 payload_name
= "u-boot.e500";
1051 payload_name
= machine
->firmware
;
1054 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, payload_name
);
1056 error_report("could not find firmware/kernel file '%s'", payload_name
);
1060 payload_size
= load_elf(filename
, NULL
, NULL
, NULL
,
1061 &bios_entry
, &loadaddr
, NULL
, NULL
,
1062 1, PPC_ELF_MACHINE
, 0, 0);
1063 if (payload_size
< 0) {
1065 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an
1066 * ePAPR compliant kernel
1068 loadaddr
= LOAD_UIMAGE_LOADADDR_INVALID
;
1069 payload_size
= load_uimage(filename
, &bios_entry
, &loadaddr
, NULL
,
1071 if (payload_size
< 0) {
1072 error_report("could not load firmware '%s'", filename
);
1079 if (kernel_as_payload
) {
1080 kernel_base
= loadaddr
;
1081 kernel_size
= payload_size
;
1084 cur_base
= loadaddr
+ payload_size
;
1085 if (cur_base
< 32 * MiB
) {
1086 /* u-boot occupies memory up to 32MB, so load blobs above */
1087 cur_base
= 32 * MiB
;
1090 /* Load bare kernel only if no bios/u-boot has been provided */
1091 if (machine
->kernel_filename
&& !kernel_as_payload
) {
1092 kernel_base
= cur_base
;
1093 kernel_size
= load_image_targphys(machine
->kernel_filename
,
1095 machine
->ram_size
- cur_base
);
1096 if (kernel_size
< 0) {
1097 error_report("could not load kernel '%s'",
1098 machine
->kernel_filename
);
1102 cur_base
+= kernel_size
;
1106 if (machine
->initrd_filename
) {
1107 initrd_base
= (cur_base
+ INITRD_LOAD_PAD
) & ~INITRD_PAD_MASK
;
1108 initrd_size
= load_image_targphys(machine
->initrd_filename
, initrd_base
,
1109 machine
->ram_size
- initrd_base
);
1111 if (initrd_size
< 0) {
1112 error_report("could not load initial ram disk '%s'",
1113 machine
->initrd_filename
);
1117 cur_base
= initrd_base
+ initrd_size
;
1121 * Reserve space for dtb behind the kernel image because Linux has a bug
1122 * where it can only handle the dtb if it's within the first 64MB of where
1123 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD
1124 * ensures enough space between kernel and initrd.
1126 dt_base
= (loadaddr
+ payload_size
+ DTC_LOAD_PAD
) & ~DTC_PAD_MASK
;
1127 if (dt_base
+ DTB_MAX_SIZE
> machine
->ram_size
) {
1128 error_report("not enough memory for device tree");
1132 dt_size
= ppce500_prep_device_tree(pms
, dt_base
,
1133 initrd_base
, initrd_size
,
1134 kernel_base
, kernel_size
);
1136 error_report("couldn't load device tree");
1139 assert(dt_size
< DTB_MAX_SIZE
);
1141 boot_info
= env
->load_info
;
1142 boot_info
->entry
= bios_entry
;
1143 boot_info
->dt_base
= dt_base
;
1144 boot_info
->dt_size
= dt_size
;
1147 static void e500_ccsr_initfn(Object
*obj
)
1149 PPCE500CCSRState
*ccsr
= CCSR(obj
);
1150 memory_region_init(&ccsr
->ccsr_space
, obj
, "e500-ccsr",
1151 MPC8544_CCSRBAR_SIZE
);
1154 static const TypeInfo e500_ccsr_info
= {
1156 .parent
= TYPE_SYS_BUS_DEVICE
,
1157 .instance_size
= sizeof(PPCE500CCSRState
),
1158 .instance_init
= e500_ccsr_initfn
,
1161 static const TypeInfo ppce500_info
= {
1162 .name
= TYPE_PPCE500_MACHINE
,
1163 .parent
= TYPE_MACHINE
,
1165 .instance_size
= sizeof(PPCE500MachineState
),
1166 .class_size
= sizeof(PPCE500MachineClass
),
1169 static void e500_register_types(void)
1171 type_register_static(&e500_ccsr_info
);
1172 type_register_static(&ppce500_info
);
1175 type_init(e500_register_types
)