2 * ARM Generic/Distributed Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 /* This file contains implementation code for the RealView EB interrupt
11 * controller, MPCore distributed interrupt controller and ARMv7-M
12 * Nested Vectored Interrupt Controller.
13 * It is compiled in two ways:
14 * (1) as a standalone file to produce a sysbus device which is a GIC
15 * that can be used on the realview board and as one of the builtin
16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
17 * (2) by being directly #included into armv7m_nvic.c to produce the
21 #include "qemu/osdep.h"
23 #include "hw/sysbus.h"
24 #include "gic_internal.h"
25 #include "qapi/error.h"
26 #include "hw/core/cpu.h"
28 #include "qemu/module.h"
30 #include "sysemu/kvm.h"
32 /* #define DEBUG_GIC */
35 #define DEBUG_GIC_GATE 1
37 #define DEBUG_GIC_GATE 0
40 #define DPRINTF(fmt, ...) do { \
41 if (DEBUG_GIC_GATE) { \
42 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
46 static const uint8_t gic_id_11mpcore
[] = {
47 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
50 static const uint8_t gic_id_gicv1
[] = {
51 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
54 static const uint8_t gic_id_gicv2
[] = {
55 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
58 static inline int gic_get_current_cpu(GICState
*s
)
61 return current_cpu
->cpu_index
;
66 static inline int gic_get_current_vcpu(GICState
*s
)
68 return gic_get_current_cpu(s
) + GIC_NCPU
;
71 /* Return true if this GIC config has interrupt groups, which is
72 * true if we're a GICv2, or a GICv1 with the security extensions.
74 static inline bool gic_has_groups(GICState
*s
)
76 return s
->revision
== 2 || s
->security_extn
;
79 static inline bool gic_cpu_ns_access(GICState
*s
, int cpu
, MemTxAttrs attrs
)
81 return !gic_is_vcpu(cpu
) && s
->security_extn
&& !attrs
.secure
;
84 static inline void gic_get_best_irq(GICState
*s
, int cpu
,
85 int *best_irq
, int *best_prio
, int *group
)
93 for (irq
= 0; irq
< s
->num_irq
; irq
++) {
94 if (GIC_DIST_TEST_ENABLED(irq
, cm
) && gic_test_pending(s
, irq
, cm
) &&
95 (!GIC_DIST_TEST_ACTIVE(irq
, cm
)) &&
96 (irq
< GIC_INTERNAL
|| GIC_DIST_TARGET(irq
) & cm
)) {
97 if (GIC_DIST_GET_PRIORITY(irq
, cpu
) < *best_prio
) {
98 *best_prio
= GIC_DIST_GET_PRIORITY(irq
, cpu
);
104 if (*best_irq
< 1023) {
105 *group
= GIC_DIST_TEST_GROUP(*best_irq
, cm
);
109 static inline void gic_get_best_virq(GICState
*s
, int cpu
,
110 int *best_irq
, int *best_prio
, int *group
)
117 for (lr_idx
= 0; lr_idx
< s
->num_lrs
; lr_idx
++) {
118 uint32_t lr_entry
= s
->h_lr
[lr_idx
][cpu
];
119 int state
= GICH_LR_STATE(lr_entry
);
121 if (state
== GICH_LR_STATE_PENDING
) {
122 int prio
= GICH_LR_PRIORITY(lr_entry
);
124 if (prio
< *best_prio
) {
126 *best_irq
= GICH_LR_VIRT_ID(lr_entry
);
127 *group
= GICH_LR_GROUP(lr_entry
);
133 /* Return true if IRQ signaling is enabled for the given cpu and at least one
134 * of the given groups:
135 * - in the non-virt case, the distributor must be enabled for one of the
137 * - in the virt case, the virtual interface must be enabled.
138 * - in all cases, the (v)CPU interface must be enabled for one of the given
141 static inline bool gic_irq_signaling_enabled(GICState
*s
, int cpu
, bool virt
,
144 int cpu_iface
= virt
? (cpu
+ GIC_NCPU
) : cpu
;
146 if (!virt
&& !(s
->ctlr
& group_mask
)) {
150 if (virt
&& !(s
->h_hcr
[cpu
] & R_GICH_HCR_EN_MASK
)) {
154 if (!(s
->cpu_ctlr
[cpu_iface
] & group_mask
)) {
161 /* TODO: Many places that call this routine could be optimized. */
162 /* Update interrupt status after enabled or pending bits have been changed. */
163 static inline void gic_update_internal(GICState
*s
, bool virt
)
167 int irq_level
, fiq_level
;
170 qemu_irq
*irq_lines
= virt
? s
->parent_virq
: s
->parent_irq
;
171 qemu_irq
*fiq_lines
= virt
? s
->parent_vfiq
: s
->parent_fiq
;
173 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
174 cpu_iface
= virt
? (cpu
+ GIC_NCPU
) : cpu
;
176 s
->current_pending
[cpu_iface
] = 1023;
177 if (!gic_irq_signaling_enabled(s
, cpu
, virt
,
178 GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
)) {
179 qemu_irq_lower(irq_lines
[cpu
]);
180 qemu_irq_lower(fiq_lines
[cpu
]);
185 gic_get_best_virq(s
, cpu
, &best_irq
, &best_prio
, &group
);
187 gic_get_best_irq(s
, cpu
, &best_irq
, &best_prio
, &group
);
190 if (best_irq
!= 1023) {
191 trace_gic_update_bestirq(virt
? "vcpu" : "cpu", cpu
,
193 s
->priority_mask
[cpu_iface
],
194 s
->running_priority
[cpu_iface
]);
197 irq_level
= fiq_level
= 0;
199 if (best_prio
< s
->priority_mask
[cpu_iface
]) {
200 s
->current_pending
[cpu_iface
] = best_irq
;
201 if (best_prio
< s
->running_priority
[cpu_iface
]) {
202 if (gic_irq_signaling_enabled(s
, cpu
, virt
, 1 << group
)) {
204 s
->cpu_ctlr
[cpu_iface
] & GICC_CTLR_FIQ_EN
) {
205 DPRINTF("Raised pending FIQ %d (cpu %d)\n",
206 best_irq
, cpu_iface
);
208 trace_gic_update_set_irq(cpu
, virt
? "vfiq" : "fiq",
211 DPRINTF("Raised pending IRQ %d (cpu %d)\n",
212 best_irq
, cpu_iface
);
214 trace_gic_update_set_irq(cpu
, virt
? "virq" : "irq",
221 qemu_set_irq(irq_lines
[cpu
], irq_level
);
222 qemu_set_irq(fiq_lines
[cpu
], fiq_level
);
226 static void gic_update(GICState
*s
)
228 gic_update_internal(s
, false);
231 /* Return true if this LR is empty, i.e. the corresponding bit
234 static inline bool gic_lr_entry_is_free(uint32_t entry
)
236 return (GICH_LR_STATE(entry
) == GICH_LR_STATE_INVALID
)
237 && (GICH_LR_HW(entry
) || !GICH_LR_EOI(entry
));
240 /* Return true if this LR should trigger an EOI maintenance interrupt, i.e. the
241 * corrsponding bit in EISR is set.
243 static inline bool gic_lr_entry_is_eoi(uint32_t entry
)
245 return (GICH_LR_STATE(entry
) == GICH_LR_STATE_INVALID
)
246 && !GICH_LR_HW(entry
) && GICH_LR_EOI(entry
);
249 static inline void gic_extract_lr_info(GICState
*s
, int cpu
,
250 int *num_eoi
, int *num_valid
, int *num_pending
)
258 for (lr_idx
= 0; lr_idx
< s
->num_lrs
; lr_idx
++) {
259 uint32_t *entry
= &s
->h_lr
[lr_idx
][cpu
];
261 if (gic_lr_entry_is_eoi(*entry
)) {
265 if (GICH_LR_STATE(*entry
) != GICH_LR_STATE_INVALID
) {
269 if (GICH_LR_STATE(*entry
) == GICH_LR_STATE_PENDING
) {
275 static void gic_compute_misr(GICState
*s
, int cpu
)
278 int vcpu
= cpu
+ GIC_NCPU
;
280 int num_eoi
, num_valid
, num_pending
;
282 gic_extract_lr_info(s
, cpu
, &num_eoi
, &num_valid
, &num_pending
);
286 value
|= R_GICH_MISR_EOI_MASK
;
289 /* U: true if only 0 or 1 LR entry is valid */
290 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_UIE_MASK
) && (num_valid
< 2)) {
291 value
|= R_GICH_MISR_U_MASK
;
294 /* LRENP: EOICount is not 0 */
295 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_LRENPIE_MASK
) &&
296 ((s
->h_hcr
[cpu
] & R_GICH_HCR_EOICount_MASK
) != 0)) {
297 value
|= R_GICH_MISR_LRENP_MASK
;
300 /* NP: no pending interrupts */
301 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_NPIE_MASK
) && (num_pending
== 0)) {
302 value
|= R_GICH_MISR_NP_MASK
;
305 /* VGrp0E: group0 virq signaling enabled */
306 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_VGRP0EIE_MASK
) &&
307 (s
->cpu_ctlr
[vcpu
] & GICC_CTLR_EN_GRP0
)) {
308 value
|= R_GICH_MISR_VGrp0E_MASK
;
311 /* VGrp0D: group0 virq signaling disabled */
312 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_VGRP0DIE_MASK
) &&
313 !(s
->cpu_ctlr
[vcpu
] & GICC_CTLR_EN_GRP0
)) {
314 value
|= R_GICH_MISR_VGrp0D_MASK
;
317 /* VGrp1E: group1 virq signaling enabled */
318 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_VGRP1EIE_MASK
) &&
319 (s
->cpu_ctlr
[vcpu
] & GICC_CTLR_EN_GRP1
)) {
320 value
|= R_GICH_MISR_VGrp1E_MASK
;
323 /* VGrp1D: group1 virq signaling disabled */
324 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_VGRP1DIE_MASK
) &&
325 !(s
->cpu_ctlr
[vcpu
] & GICC_CTLR_EN_GRP1
)) {
326 value
|= R_GICH_MISR_VGrp1D_MASK
;
329 s
->h_misr
[cpu
] = value
;
332 static void gic_update_maintenance(GICState
*s
)
337 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
338 gic_compute_misr(s
, cpu
);
339 maint_level
= (s
->h_hcr
[cpu
] & R_GICH_HCR_EN_MASK
) && s
->h_misr
[cpu
];
341 trace_gic_update_maintenance_irq(cpu
, maint_level
);
342 qemu_set_irq(s
->maintenance_irq
[cpu
], maint_level
);
346 static void gic_update_virt(GICState
*s
)
348 gic_update_internal(s
, true);
349 gic_update_maintenance(s
);
352 static void gic_set_irq_11mpcore(GICState
*s
, int irq
, int level
,
356 GIC_DIST_SET_LEVEL(irq
, cm
);
357 if (GIC_DIST_TEST_EDGE_TRIGGER(irq
) || GIC_DIST_TEST_ENABLED(irq
, cm
)) {
358 DPRINTF("Set %d pending mask %x\n", irq
, target
);
359 GIC_DIST_SET_PENDING(irq
, target
);
362 GIC_DIST_CLEAR_LEVEL(irq
, cm
);
366 static void gic_set_irq_generic(GICState
*s
, int irq
, int level
,
370 GIC_DIST_SET_LEVEL(irq
, cm
);
371 DPRINTF("Set %d pending mask %x\n", irq
, target
);
372 if (GIC_DIST_TEST_EDGE_TRIGGER(irq
)) {
373 GIC_DIST_SET_PENDING(irq
, target
);
376 GIC_DIST_CLEAR_LEVEL(irq
, cm
);
380 /* Process a change in an external IRQ input. */
381 static void gic_set_irq(void *opaque
, int irq
, int level
)
383 /* Meaning of the 'irq' parameter:
384 * [0..N-1] : external interrupts
385 * [N..N+31] : PPI (internal) interrupts for CPU 0
386 * [N+32..N+63] : PPI (internal interrupts for CPU 1
389 GICState
*s
= (GICState
*)opaque
;
391 if (irq
< (s
->num_irq
- GIC_INTERNAL
)) {
392 /* The first external input line is internal interrupt 32. */
395 target
= GIC_DIST_TARGET(irq
);
398 irq
-= (s
->num_irq
- GIC_INTERNAL
);
399 cpu
= irq
/ GIC_INTERNAL
;
405 assert(irq
>= GIC_NR_SGIS
);
407 if (level
== GIC_DIST_TEST_LEVEL(irq
, cm
)) {
411 if (s
->revision
== REV_11MPCORE
) {
412 gic_set_irq_11mpcore(s
, irq
, level
, cm
, target
);
414 gic_set_irq_generic(s
, irq
, level
, cm
, target
);
416 trace_gic_set_irq(irq
, level
, cm
, target
);
421 static uint16_t gic_get_current_pending_irq(GICState
*s
, int cpu
,
424 uint16_t pending_irq
= s
->current_pending
[cpu
];
426 if (pending_irq
< GIC_MAXIRQ
&& gic_has_groups(s
)) {
427 int group
= gic_test_group(s
, pending_irq
, cpu
);
429 /* On a GIC without the security extensions, reading this register
430 * behaves in the same way as a secure access to a GIC with them.
432 bool secure
= !gic_cpu_ns_access(s
, cpu
, attrs
);
434 if (group
== 0 && !secure
) {
435 /* Group0 interrupts hidden from Non-secure access */
438 if (group
== 1 && secure
&& !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_ACK_CTL
)) {
439 /* Group1 interrupts only seen by Secure access if
448 static int gic_get_group_priority(GICState
*s
, int cpu
, int irq
)
450 /* Return the group priority of the specified interrupt
451 * (which is the top bits of its priority, with the number
452 * of bits masked determined by the applicable binary point register).
457 if (gic_has_groups(s
) &&
458 !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) &&
459 gic_test_group(s
, irq
, cpu
)) {
460 bpr
= s
->abpr
[cpu
] - 1;
466 /* a BPR of 0 means the group priority bits are [7:1];
467 * a BPR of 1 means they are [7:2], and so on down to
468 * a BPR of 7 meaning no group priority bits at all.
470 mask
= ~0U << ((bpr
& 7) + 1);
472 return gic_get_priority(s
, irq
, cpu
) & mask
;
475 static void gic_activate_irq(GICState
*s
, int cpu
, int irq
)
477 /* Set the appropriate Active Priority Register bit for this IRQ,
478 * and update the running priority.
480 int prio
= gic_get_group_priority(s
, cpu
, irq
);
481 int min_bpr
= gic_is_vcpu(cpu
) ? GIC_VIRT_MIN_BPR
: GIC_MIN_BPR
;
482 int preemption_level
= prio
>> (min_bpr
+ 1);
483 int regno
= preemption_level
/ 32;
484 int bitno
= preemption_level
% 32;
485 uint32_t *papr
= NULL
;
487 if (gic_is_vcpu(cpu
)) {
489 papr
= &s
->h_apr
[gic_get_vcpu_real_id(cpu
)];
490 } else if (gic_has_groups(s
) && gic_test_group(s
, irq
, cpu
)) {
491 papr
= &s
->nsapr
[regno
][cpu
];
493 papr
= &s
->apr
[regno
][cpu
];
496 *papr
|= (1 << bitno
);
498 s
->running_priority
[cpu
] = prio
;
499 gic_set_active(s
, irq
, cpu
);
502 static int gic_get_prio_from_apr_bits(GICState
*s
, int cpu
)
504 /* Recalculate the current running priority for this CPU based
505 * on the set bits in the Active Priority Registers.
509 if (gic_is_vcpu(cpu
)) {
510 uint32_t apr
= s
->h_apr
[gic_get_vcpu_real_id(cpu
)];
512 return ctz32(apr
) << (GIC_VIRT_MIN_BPR
+ 1);
518 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
519 uint32_t apr
= s
->apr
[i
][cpu
] | s
->nsapr
[i
][cpu
];
523 return (i
* 32 + ctz32(apr
)) << (GIC_MIN_BPR
+ 1);
528 static void gic_drop_prio(GICState
*s
, int cpu
, int group
)
530 /* Drop the priority of the currently active interrupt in the
533 * Note that we can guarantee (because of the requirement to nest
534 * GICC_IAR reads [which activate an interrupt and raise priority]
535 * with GICC_EOIR writes [which drop the priority for the interrupt])
536 * that the interrupt we're being called for is the highest priority
537 * active interrupt, meaning that it has the lowest set bit in the
540 * If the guest does not honour the ordering constraints then the
541 * behaviour of the GIC is UNPREDICTABLE, which for us means that
542 * the values of the APR registers might become incorrect and the
543 * running priority will be wrong, so interrupts that should preempt
544 * might not do so, and interrupts that should not preempt might do so.
546 if (gic_is_vcpu(cpu
)) {
547 int rcpu
= gic_get_vcpu_real_id(cpu
);
549 if (s
->h_apr
[rcpu
]) {
550 /* Clear lowest set bit */
551 s
->h_apr
[rcpu
] &= s
->h_apr
[rcpu
] - 1;
556 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
557 uint32_t *papr
= group
? &s
->nsapr
[i
][cpu
] : &s
->apr
[i
][cpu
];
561 /* Clear lowest set bit */
567 s
->running_priority
[cpu
] = gic_get_prio_from_apr_bits(s
, cpu
);
570 static inline uint32_t gic_clear_pending_sgi(GICState
*s
, int irq
, int cpu
)
575 if (!gic_is_vcpu(cpu
)) {
576 /* Lookup the source CPU for the SGI and clear this in the
577 * sgi_pending map. Return the src and clear the overall pending
578 * state on this CPU if the SGI is not pending from any CPUs.
580 assert(s
->sgi_pending
[irq
][cpu
] != 0);
581 src
= ctz32(s
->sgi_pending
[irq
][cpu
]);
582 s
->sgi_pending
[irq
][cpu
] &= ~(1 << src
);
583 if (s
->sgi_pending
[irq
][cpu
] == 0) {
584 gic_clear_pending(s
, irq
, cpu
);
586 ret
= irq
| ((src
& 0x7) << 10);
588 uint32_t *lr_entry
= gic_get_lr_entry(s
, irq
, cpu
);
589 src
= GICH_LR_CPUID(*lr_entry
);
591 gic_clear_pending(s
, irq
, cpu
);
592 ret
= irq
| (src
<< 10);
598 uint32_t gic_acknowledge_irq(GICState
*s
, int cpu
, MemTxAttrs attrs
)
602 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately
603 * for the case where this GIC supports grouping and the pending interrupt
604 * is in the wrong group.
606 irq
= gic_get_current_pending_irq(s
, cpu
, attrs
);
607 trace_gic_acknowledge_irq(gic_is_vcpu(cpu
) ? "vcpu" : "cpu",
608 gic_get_vcpu_real_id(cpu
), irq
);
610 if (irq
>= GIC_MAXIRQ
) {
611 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq
);
615 if (gic_get_priority(s
, irq
, cpu
) >= s
->running_priority
[cpu
]) {
616 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq
);
620 gic_activate_irq(s
, cpu
, irq
);
622 if (s
->revision
== REV_11MPCORE
) {
623 /* Clear pending flags for both level and edge triggered interrupts.
624 * Level triggered IRQs will be reasserted once they become inactive.
626 gic_clear_pending(s
, irq
, cpu
);
629 if (irq
< GIC_NR_SGIS
) {
630 ret
= gic_clear_pending_sgi(s
, irq
, cpu
);
632 gic_clear_pending(s
, irq
, cpu
);
637 if (gic_is_vcpu(cpu
)) {
642 DPRINTF("ACK %d\n", irq
);
646 static uint32_t gic_fullprio_mask(GICState
*s
, int cpu
)
649 * Return a mask word which clears the unimplemented priority
650 * bits from a priority value for an interrupt. (Not to be
651 * confused with the group priority, whose mask depends on BPR.)
655 if (gic_is_vcpu(cpu
)) {
656 priBits
= GIC_VIRT_MAX_GROUP_PRIO_BITS
;
658 priBits
= s
->n_prio_bits
;
660 return ~0U << (8 - priBits
);
663 void gic_dist_set_priority(GICState
*s
, int cpu
, int irq
, uint8_t val
,
666 if (s
->security_extn
&& !attrs
.secure
) {
667 if (!GIC_DIST_TEST_GROUP(irq
, (1 << cpu
))) {
668 return; /* Ignore Non-secure access of Group0 IRQ */
670 val
= 0x80 | (val
>> 1); /* Non-secure view */
673 val
&= gic_fullprio_mask(s
, cpu
);
675 if (irq
< GIC_INTERNAL
) {
676 s
->priority1
[irq
][cpu
] = val
;
678 s
->priority2
[(irq
) - GIC_INTERNAL
] = val
;
682 static uint32_t gic_dist_get_priority(GICState
*s
, int cpu
, int irq
,
685 uint32_t prio
= GIC_DIST_GET_PRIORITY(irq
, cpu
);
687 if (s
->security_extn
&& !attrs
.secure
) {
688 if (!GIC_DIST_TEST_GROUP(irq
, (1 << cpu
))) {
689 return 0; /* Non-secure access cannot read priority of Group0 IRQ */
691 prio
= (prio
<< 1) & 0xff; /* Non-secure view */
693 return prio
& gic_fullprio_mask(s
, cpu
);
696 static void gic_set_priority_mask(GICState
*s
, int cpu
, uint8_t pmask
,
699 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
700 if (s
->priority_mask
[cpu
] & 0x80) {
701 /* Priority Mask in upper half */
702 pmask
= 0x80 | (pmask
>> 1);
704 /* Non-secure write ignored if priority mask is in lower half */
708 s
->priority_mask
[cpu
] = pmask
& gic_fullprio_mask(s
, cpu
);
711 static uint32_t gic_get_priority_mask(GICState
*s
, int cpu
, MemTxAttrs attrs
)
713 uint32_t pmask
= s
->priority_mask
[cpu
];
715 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
717 /* Priority Mask in upper half, return Non-secure view */
718 pmask
= (pmask
<< 1) & 0xff;
720 /* Priority Mask in lower half, RAZ */
727 static uint32_t gic_get_cpu_control(GICState
*s
, int cpu
, MemTxAttrs attrs
)
729 uint32_t ret
= s
->cpu_ctlr
[cpu
];
731 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
732 /* Construct the NS banked view of GICC_CTLR from the correct
733 * bits of the S banked view. We don't need to move the bypass
734 * control bits because we don't implement that (IMPDEF) part
735 * of the GIC architecture.
737 ret
= (ret
& (GICC_CTLR_EN_GRP1
| GICC_CTLR_EOIMODE_NS
)) >> 1;
742 static void gic_set_cpu_control(GICState
*s
, int cpu
, uint32_t value
,
747 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
748 /* The NS view can only write certain bits in the register;
749 * the rest are unchanged
751 mask
= GICC_CTLR_EN_GRP1
;
752 if (s
->revision
== 2) {
753 mask
|= GICC_CTLR_EOIMODE_NS
;
755 s
->cpu_ctlr
[cpu
] &= ~mask
;
756 s
->cpu_ctlr
[cpu
] |= (value
<< 1) & mask
;
758 if (s
->revision
== 2) {
759 mask
= s
->security_extn
? GICC_CTLR_V2_S_MASK
: GICC_CTLR_V2_MASK
;
761 mask
= s
->security_extn
? GICC_CTLR_V1_S_MASK
: GICC_CTLR_V1_MASK
;
763 s
->cpu_ctlr
[cpu
] = value
& mask
;
765 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, "
766 "Group1 Interrupts %sabled\n", cpu
,
767 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP0
) ? "En" : "Dis",
768 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP1
) ? "En" : "Dis");
771 static uint8_t gic_get_running_priority(GICState
*s
, int cpu
, MemTxAttrs attrs
)
773 if ((s
->revision
!= REV_11MPCORE
) && (s
->running_priority
[cpu
] > 0xff)) {
778 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
779 if (s
->running_priority
[cpu
] & 0x80) {
780 /* Running priority in upper half of range: return the Non-secure
781 * view of the priority.
783 return s
->running_priority
[cpu
] << 1;
785 /* Running priority in lower half of range: RAZ */
789 return s
->running_priority
[cpu
];
793 /* Return true if we should split priority drop and interrupt deactivation,
794 * ie whether the relevant EOIMode bit is set.
796 static bool gic_eoi_split(GICState
*s
, int cpu
, MemTxAttrs attrs
)
798 if (s
->revision
!= 2) {
799 /* Before GICv2 prio-drop and deactivate are not separable */
802 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
803 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE_NS
;
805 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE
;
808 static void gic_deactivate_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
812 if (irq
>= GIC_MAXIRQ
|| (!gic_is_vcpu(cpu
) && irq
>= s
->num_irq
)) {
814 * This handles two cases:
815 * 1. If software writes the ID of a spurious interrupt [ie 1023]
816 * to the GICC_DIR, the GIC ignores that write.
817 * 2. If software writes the number of a non-existent interrupt
818 * this must be a subcase of "value written is not an active interrupt"
819 * and so this is UNPREDICTABLE. We choose to ignore it. For vCPUs,
820 * all IRQs potentially exist, so this limit does not apply.
825 if (!gic_eoi_split(s
, cpu
, attrs
)) {
826 /* This is UNPREDICTABLE; we choose to ignore it */
827 qemu_log_mask(LOG_GUEST_ERROR
,
828 "gic_deactivate_irq: GICC_DIR write when EOIMode clear");
832 if (gic_is_vcpu(cpu
) && !gic_virq_is_valid(s
, irq
, cpu
)) {
833 /* This vIRQ does not have an LR entry which is either active or
834 * pending and active. Increment EOICount and ignore the write.
836 int rcpu
= gic_get_vcpu_real_id(cpu
);
837 s
->h_hcr
[rcpu
] += 1 << R_GICH_HCR_EOICount_SHIFT
;
839 /* Update the virtual interface in case a maintenance interrupt should
846 group
= gic_has_groups(s
) && gic_test_group(s
, irq
, cpu
);
848 if (gic_cpu_ns_access(s
, cpu
, attrs
) && !group
) {
849 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq
);
853 gic_clear_active(s
, irq
, cpu
);
856 static void gic_complete_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
861 DPRINTF("EOI %d\n", irq
);
862 if (gic_is_vcpu(cpu
)) {
863 /* The call to gic_prio_drop() will clear a bit in GICH_APR iff the
864 * running prio is < 0x100.
866 bool prio_drop
= s
->running_priority
[cpu
] < 0x100;
868 if (irq
>= GIC_MAXIRQ
) {
869 /* Ignore spurious interrupt */
873 gic_drop_prio(s
, cpu
, 0);
875 if (!gic_eoi_split(s
, cpu
, attrs
)) {
876 bool valid
= gic_virq_is_valid(s
, irq
, cpu
);
877 if (prio_drop
&& !valid
) {
878 /* We are in a situation where:
879 * - V_CTRL.EOIMode is false (no EOI split),
880 * - The call to gic_drop_prio() cleared a bit in GICH_APR,
881 * - This vIRQ does not have an LR entry which is either
882 * active or pending and active.
883 * In that case, we must increment EOICount.
885 int rcpu
= gic_get_vcpu_real_id(cpu
);
886 s
->h_hcr
[rcpu
] += 1 << R_GICH_HCR_EOICount_SHIFT
;
888 gic_clear_active(s
, irq
, cpu
);
896 if (irq
>= s
->num_irq
) {
897 /* This handles two cases:
898 * 1. If software writes the ID of a spurious interrupt [ie 1023]
899 * to the GICC_EOIR, the GIC ignores that write.
900 * 2. If software writes the number of a non-existent interrupt
901 * this must be a subcase of "value written does not match the last
902 * valid interrupt value read from the Interrupt Acknowledge
903 * register" and so this is UNPREDICTABLE. We choose to ignore it.
907 if (s
->running_priority
[cpu
] == 0x100) {
908 return; /* No active IRQ. */
911 if (s
->revision
== REV_11MPCORE
) {
912 /* Mark level triggered interrupts as pending if they are still
914 if (!GIC_DIST_TEST_EDGE_TRIGGER(irq
) && GIC_DIST_TEST_ENABLED(irq
, cm
)
915 && GIC_DIST_TEST_LEVEL(irq
, cm
)
916 && (GIC_DIST_TARGET(irq
) & cm
) != 0) {
917 DPRINTF("Set %d pending mask %x\n", irq
, cm
);
918 GIC_DIST_SET_PENDING(irq
, cm
);
922 group
= gic_has_groups(s
) && gic_test_group(s
, irq
, cpu
);
924 if (gic_cpu_ns_access(s
, cpu
, attrs
) && !group
) {
925 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq
);
929 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1
930 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1,
931 * i.e. go ahead and complete the irq anyway.
934 gic_drop_prio(s
, cpu
, group
);
936 /* In GICv2 the guest can choose to split priority-drop and deactivate */
937 if (!gic_eoi_split(s
, cpu
, attrs
)) {
938 gic_clear_active(s
, irq
, cpu
);
943 static uint32_t gic_dist_readb(void *opaque
, hwaddr offset
, MemTxAttrs attrs
)
945 GICState
*s
= (GICState
*)opaque
;
953 cpu
= gic_get_current_cpu(s
);
955 if (offset
< 0x100) {
956 if (offset
== 0) { /* GICD_CTLR */
957 if (s
->security_extn
&& !attrs
.secure
) {
958 /* The NS bank of this register is just an alias of the
959 * EnableGrp1 bit in the S bank version.
961 return extract32(s
->ctlr
, 1, 1);
967 /* Interrupt Controller Type Register */
968 return ((s
->num_irq
/ 32) - 1)
969 | ((s
->num_cpu
- 1) << 5)
970 | (s
->security_extn
<< 10);
973 if (offset
>= 0x80) {
974 /* Interrupt Group Registers: these RAZ/WI if this is an NS
975 * access to a GIC with the security extensions, or if the GIC
976 * doesn't have groups at all.
979 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
980 /* Every byte offset holds 8 group status bits */
981 irq
= (offset
- 0x080) * 8;
982 if (irq
>= s
->num_irq
) {
985 for (i
= 0; i
< 8; i
++) {
986 if (GIC_DIST_TEST_GROUP(irq
+ i
, cm
)) {
994 } else if (offset
< 0x200) {
995 /* Interrupt Set/Clear Enable. */
997 irq
= (offset
- 0x100) * 8;
999 irq
= (offset
- 0x180) * 8;
1000 if (irq
>= s
->num_irq
)
1003 for (i
= 0; i
< 8; i
++) {
1004 if (s
->security_extn
&& !attrs
.secure
&&
1005 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1006 continue; /* Ignore Non-secure access of Group0 IRQ */
1009 if (GIC_DIST_TEST_ENABLED(irq
+ i
, cm
)) {
1013 } else if (offset
< 0x300) {
1014 /* Interrupt Set/Clear Pending. */
1016 irq
= (offset
- 0x200) * 8;
1018 irq
= (offset
- 0x280) * 8;
1019 if (irq
>= s
->num_irq
)
1022 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
1023 for (i
= 0; i
< 8; i
++) {
1024 if (s
->security_extn
&& !attrs
.secure
&&
1025 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1026 continue; /* Ignore Non-secure access of Group0 IRQ */
1029 if (gic_test_pending(s
, irq
+ i
, mask
)) {
1033 } else if (offset
< 0x400) {
1034 /* Interrupt Set/Clear Active. */
1035 if (offset
< 0x380) {
1036 irq
= (offset
- 0x300) * 8;
1037 } else if (s
->revision
== 2) {
1038 irq
= (offset
- 0x380) * 8;
1043 if (irq
>= s
->num_irq
)
1046 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
1047 for (i
= 0; i
< 8; i
++) {
1048 if (s
->security_extn
&& !attrs
.secure
&&
1049 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1050 continue; /* Ignore Non-secure access of Group0 IRQ */
1053 if (GIC_DIST_TEST_ACTIVE(irq
+ i
, mask
)) {
1057 } else if (offset
< 0x800) {
1058 /* Interrupt Priority. */
1059 irq
= (offset
- 0x400);
1060 if (irq
>= s
->num_irq
)
1062 res
= gic_dist_get_priority(s
, cpu
, irq
, attrs
);
1063 } else if (offset
< 0xc00) {
1064 /* Interrupt CPU Target. */
1065 if (s
->num_cpu
== 1 && s
->revision
!= REV_11MPCORE
) {
1066 /* For uniprocessor GICs these RAZ/WI */
1069 irq
= (offset
- 0x800);
1070 if (irq
>= s
->num_irq
) {
1073 if (irq
< 29 && s
->revision
== REV_11MPCORE
) {
1075 } else if (irq
< GIC_INTERNAL
) {
1078 res
= GIC_DIST_TARGET(irq
);
1081 } else if (offset
< 0xf00) {
1082 /* Interrupt Configuration. */
1083 irq
= (offset
- 0xc00) * 4;
1084 if (irq
>= s
->num_irq
)
1087 for (i
= 0; i
< 4; i
++) {
1088 if (s
->security_extn
&& !attrs
.secure
&&
1089 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1090 continue; /* Ignore Non-secure access of Group0 IRQ */
1093 if (GIC_DIST_TEST_MODEL(irq
+ i
)) {
1094 res
|= (1 << (i
* 2));
1096 if (GIC_DIST_TEST_EDGE_TRIGGER(irq
+ i
)) {
1097 res
|= (2 << (i
* 2));
1100 } else if (offset
< 0xf10) {
1102 } else if (offset
< 0xf30) {
1103 if (s
->revision
== REV_11MPCORE
) {
1107 if (offset
< 0xf20) {
1108 /* GICD_CPENDSGIRn */
1109 irq
= (offset
- 0xf10);
1111 irq
= (offset
- 0xf20);
1112 /* GICD_SPENDSGIRn */
1115 if (s
->security_extn
&& !attrs
.secure
&&
1116 !GIC_DIST_TEST_GROUP(irq
, 1 << cpu
)) {
1117 res
= 0; /* Ignore Non-secure access of Group0 IRQ */
1119 res
= s
->sgi_pending
[irq
][cpu
];
1121 } else if (offset
< 0xfd0) {
1123 } else if (offset
< 0x1000) {
1127 switch (s
->revision
) {
1129 res
= gic_id_11mpcore
[(offset
- 0xfd0) >> 2];
1132 res
= gic_id_gicv1
[(offset
- 0xfd0) >> 2];
1135 res
= gic_id_gicv2
[(offset
- 0xfd0) >> 2];
1142 g_assert_not_reached();
1146 qemu_log_mask(LOG_GUEST_ERROR
,
1147 "gic_dist_readb: Bad offset %x\n", (int)offset
);
1151 static MemTxResult
gic_dist_read(void *opaque
, hwaddr offset
, uint64_t *data
,
1152 unsigned size
, MemTxAttrs attrs
)
1156 *data
= gic_dist_readb(opaque
, offset
, attrs
);
1159 *data
= gic_dist_readb(opaque
, offset
, attrs
);
1160 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
1163 *data
= gic_dist_readb(opaque
, offset
, attrs
);
1164 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
1165 *data
|= gic_dist_readb(opaque
, offset
+ 2, attrs
) << 16;
1166 *data
|= gic_dist_readb(opaque
, offset
+ 3, attrs
) << 24;
1172 trace_gic_dist_read(offset
, size
, *data
);
1176 static void gic_dist_writeb(void *opaque
, hwaddr offset
,
1177 uint32_t value
, MemTxAttrs attrs
)
1179 GICState
*s
= (GICState
*)opaque
;
1184 cpu
= gic_get_current_cpu(s
);
1185 if (offset
< 0x100) {
1187 if (s
->security_extn
&& !attrs
.secure
) {
1188 /* NS version is just an alias of the S version's bit 1 */
1189 s
->ctlr
= deposit32(s
->ctlr
, 1, 1, value
);
1190 } else if (gic_has_groups(s
)) {
1191 s
->ctlr
= value
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
);
1193 s
->ctlr
= value
& GICD_CTLR_EN_GRP0
;
1195 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n",
1196 s
->ctlr
& GICD_CTLR_EN_GRP0
? "En" : "Dis",
1197 s
->ctlr
& GICD_CTLR_EN_GRP1
? "En" : "Dis");
1198 } else if (offset
< 4) {
1200 } else if (offset
>= 0x80) {
1201 /* Interrupt Group Registers: RAZ/WI for NS access to secure
1202 * GIC, or for GICs without groups.
1204 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
1205 /* Every byte offset holds 8 group status bits */
1206 irq
= (offset
- 0x80) * 8;
1207 if (irq
>= s
->num_irq
) {
1210 for (i
= 0; i
< 8; i
++) {
1211 /* Group bits are banked for private interrupts */
1212 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
1213 if (value
& (1 << i
)) {
1214 /* Group1 (Non-secure) */
1215 GIC_DIST_SET_GROUP(irq
+ i
, cm
);
1217 /* Group0 (Secure) */
1218 GIC_DIST_CLEAR_GROUP(irq
+ i
, cm
);
1225 } else if (offset
< 0x180) {
1226 /* Interrupt Set Enable. */
1227 irq
= (offset
- 0x100) * 8;
1228 if (irq
>= s
->num_irq
)
1230 if (irq
< GIC_NR_SGIS
) {
1234 for (i
= 0; i
< 8; i
++) {
1235 if (value
& (1 << i
)) {
1237 (irq
< GIC_INTERNAL
) ? (1 << cpu
)
1238 : GIC_DIST_TARGET(irq
+ i
);
1239 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
1241 if (s
->security_extn
&& !attrs
.secure
&&
1242 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1243 continue; /* Ignore Non-secure access of Group0 IRQ */
1246 if (!GIC_DIST_TEST_ENABLED(irq
+ i
, cm
)) {
1247 DPRINTF("Enabled IRQ %d\n", irq
+ i
);
1248 trace_gic_enable_irq(irq
+ i
);
1250 GIC_DIST_SET_ENABLED(irq
+ i
, cm
);
1251 /* If a raised level triggered IRQ enabled then mark
1253 if (GIC_DIST_TEST_LEVEL(irq
+ i
, mask
)
1254 && !GIC_DIST_TEST_EDGE_TRIGGER(irq
+ i
)) {
1255 DPRINTF("Set %d pending mask %x\n", irq
+ i
, mask
);
1256 GIC_DIST_SET_PENDING(irq
+ i
, mask
);
1260 } else if (offset
< 0x200) {
1261 /* Interrupt Clear Enable. */
1262 irq
= (offset
- 0x180) * 8;
1263 if (irq
>= s
->num_irq
)
1265 if (irq
< GIC_NR_SGIS
) {
1269 for (i
= 0; i
< 8; i
++) {
1270 if (value
& (1 << i
)) {
1271 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
1273 if (s
->security_extn
&& !attrs
.secure
&&
1274 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1275 continue; /* Ignore Non-secure access of Group0 IRQ */
1278 if (GIC_DIST_TEST_ENABLED(irq
+ i
, cm
)) {
1279 DPRINTF("Disabled IRQ %d\n", irq
+ i
);
1280 trace_gic_disable_irq(irq
+ i
);
1282 GIC_DIST_CLEAR_ENABLED(irq
+ i
, cm
);
1285 } else if (offset
< 0x280) {
1286 /* Interrupt Set Pending. */
1287 irq
= (offset
- 0x200) * 8;
1288 if (irq
>= s
->num_irq
)
1290 if (irq
< GIC_NR_SGIS
) {
1294 for (i
= 0; i
< 8; i
++) {
1295 if (value
& (1 << i
)) {
1296 if (s
->security_extn
&& !attrs
.secure
&&
1297 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1298 continue; /* Ignore Non-secure access of Group0 IRQ */
1301 GIC_DIST_SET_PENDING(irq
+ i
, GIC_DIST_TARGET(irq
+ i
));
1304 } else if (offset
< 0x300) {
1305 /* Interrupt Clear Pending. */
1306 irq
= (offset
- 0x280) * 8;
1307 if (irq
>= s
->num_irq
)
1309 if (irq
< GIC_NR_SGIS
) {
1313 for (i
= 0; i
< 8; i
++) {
1314 if (s
->security_extn
&& !attrs
.secure
&&
1315 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1316 continue; /* Ignore Non-secure access of Group0 IRQ */
1319 /* ??? This currently clears the pending bit for all CPUs, even
1320 for per-CPU interrupts. It's unclear whether this is the
1322 if (value
& (1 << i
)) {
1323 GIC_DIST_CLEAR_PENDING(irq
+ i
, ALL_CPU_MASK
);
1326 } else if (offset
< 0x380) {
1327 /* Interrupt Set Active. */
1328 if (s
->revision
!= 2) {
1332 irq
= (offset
- 0x300) * 8;
1333 if (irq
>= s
->num_irq
) {
1337 /* This register is banked per-cpu for PPIs */
1338 int cm
= irq
< GIC_INTERNAL
? (1 << cpu
) : ALL_CPU_MASK
;
1340 for (i
= 0; i
< 8; i
++) {
1341 if (s
->security_extn
&& !attrs
.secure
&&
1342 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1343 continue; /* Ignore Non-secure access of Group0 IRQ */
1346 if (value
& (1 << i
)) {
1347 GIC_DIST_SET_ACTIVE(irq
+ i
, cm
);
1350 } else if (offset
< 0x400) {
1351 /* Interrupt Clear Active. */
1352 if (s
->revision
!= 2) {
1356 irq
= (offset
- 0x380) * 8;
1357 if (irq
>= s
->num_irq
) {
1361 /* This register is banked per-cpu for PPIs */
1362 int cm
= irq
< GIC_INTERNAL
? (1 << cpu
) : ALL_CPU_MASK
;
1364 for (i
= 0; i
< 8; i
++) {
1365 if (s
->security_extn
&& !attrs
.secure
&&
1366 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1367 continue; /* Ignore Non-secure access of Group0 IRQ */
1370 if (value
& (1 << i
)) {
1371 GIC_DIST_CLEAR_ACTIVE(irq
+ i
, cm
);
1374 } else if (offset
< 0x800) {
1375 /* Interrupt Priority. */
1376 irq
= (offset
- 0x400);
1377 if (irq
>= s
->num_irq
)
1379 gic_dist_set_priority(s
, cpu
, irq
, value
, attrs
);
1380 } else if (offset
< 0xc00) {
1381 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
1382 * annoying exception of the 11MPCore's GIC.
1384 if (s
->num_cpu
!= 1 || s
->revision
== REV_11MPCORE
) {
1385 irq
= (offset
- 0x800);
1386 if (irq
>= s
->num_irq
) {
1389 if (irq
< 29 && s
->revision
== REV_11MPCORE
) {
1391 } else if (irq
< GIC_INTERNAL
) {
1392 value
= ALL_CPU_MASK
;
1394 s
->irq_target
[irq
] = value
& ALL_CPU_MASK
;
1396 } else if (offset
< 0xf00) {
1397 /* Interrupt Configuration. */
1398 irq
= (offset
- 0xc00) * 4;
1399 if (irq
>= s
->num_irq
)
1401 if (irq
< GIC_NR_SGIS
)
1403 for (i
= 0; i
< 4; i
++) {
1404 if (s
->security_extn
&& !attrs
.secure
&&
1405 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1406 continue; /* Ignore Non-secure access of Group0 IRQ */
1409 if (s
->revision
== REV_11MPCORE
) {
1410 if (value
& (1 << (i
* 2))) {
1411 GIC_DIST_SET_MODEL(irq
+ i
);
1413 GIC_DIST_CLEAR_MODEL(irq
+ i
);
1416 if (value
& (2 << (i
* 2))) {
1417 GIC_DIST_SET_EDGE_TRIGGER(irq
+ i
);
1419 GIC_DIST_CLEAR_EDGE_TRIGGER(irq
+ i
);
1422 } else if (offset
< 0xf10) {
1423 /* 0xf00 is only handled for 32-bit writes. */
1425 } else if (offset
< 0xf20) {
1426 /* GICD_CPENDSGIRn */
1427 if (s
->revision
== REV_11MPCORE
) {
1430 irq
= (offset
- 0xf10);
1432 if (!s
->security_extn
|| attrs
.secure
||
1433 GIC_DIST_TEST_GROUP(irq
, 1 << cpu
)) {
1434 s
->sgi_pending
[irq
][cpu
] &= ~value
;
1435 if (s
->sgi_pending
[irq
][cpu
] == 0) {
1436 GIC_DIST_CLEAR_PENDING(irq
, 1 << cpu
);
1439 } else if (offset
< 0xf30) {
1440 /* GICD_SPENDSGIRn */
1441 if (s
->revision
== REV_11MPCORE
) {
1444 irq
= (offset
- 0xf20);
1446 if (!s
->security_extn
|| attrs
.secure
||
1447 GIC_DIST_TEST_GROUP(irq
, 1 << cpu
)) {
1448 GIC_DIST_SET_PENDING(irq
, 1 << cpu
);
1449 s
->sgi_pending
[irq
][cpu
] |= value
;
1457 qemu_log_mask(LOG_GUEST_ERROR
,
1458 "gic_dist_writeb: Bad offset %x\n", (int)offset
);
1461 static void gic_dist_writew(void *opaque
, hwaddr offset
,
1462 uint32_t value
, MemTxAttrs attrs
)
1464 gic_dist_writeb(opaque
, offset
, value
& 0xff, attrs
);
1465 gic_dist_writeb(opaque
, offset
+ 1, value
>> 8, attrs
);
1468 static void gic_dist_writel(void *opaque
, hwaddr offset
,
1469 uint32_t value
, MemTxAttrs attrs
)
1471 GICState
*s
= (GICState
*)opaque
;
1472 if (offset
== 0xf00) {
1478 cpu
= gic_get_current_cpu(s
);
1479 irq
= value
& 0x3ff;
1480 switch ((value
>> 24) & 3) {
1482 mask
= (value
>> 16) & ALL_CPU_MASK
;
1485 mask
= ALL_CPU_MASK
^ (1 << cpu
);
1491 DPRINTF("Bad Soft Int target filter\n");
1492 mask
= ALL_CPU_MASK
;
1495 GIC_DIST_SET_PENDING(irq
, mask
);
1496 target_cpu
= ctz32(mask
);
1497 while (target_cpu
< GIC_NCPU
) {
1498 s
->sgi_pending
[irq
][target_cpu
] |= (1 << cpu
);
1499 mask
&= ~(1 << target_cpu
);
1500 target_cpu
= ctz32(mask
);
1505 gic_dist_writew(opaque
, offset
, value
& 0xffff, attrs
);
1506 gic_dist_writew(opaque
, offset
+ 2, value
>> 16, attrs
);
1509 static MemTxResult
gic_dist_write(void *opaque
, hwaddr offset
, uint64_t data
,
1510 unsigned size
, MemTxAttrs attrs
)
1512 trace_gic_dist_write(offset
, size
, data
);
1516 gic_dist_writeb(opaque
, offset
, data
, attrs
);
1519 gic_dist_writew(opaque
, offset
, data
, attrs
);
1522 gic_dist_writel(opaque
, offset
, data
, attrs
);
1529 static inline uint32_t gic_apr_ns_view(GICState
*s
, int cpu
, int regno
)
1531 /* Return the Nonsecure view of GICC_APR<regno>. This is the
1532 * second half of GICC_NSAPR.
1534 switch (GIC_MIN_BPR
) {
1537 return s
->nsapr
[regno
+ 2][cpu
];
1542 return s
->nsapr
[regno
+ 1][cpu
];
1547 return extract32(s
->nsapr
[0][cpu
], 16, 16);
1552 return extract32(s
->nsapr
[0][cpu
], 8, 8);
1556 g_assert_not_reached();
1561 static inline void gic_apr_write_ns_view(GICState
*s
, int cpu
, int regno
,
1564 /* Write the Nonsecure view of GICC_APR<regno>. */
1565 switch (GIC_MIN_BPR
) {
1568 s
->nsapr
[regno
+ 2][cpu
] = value
;
1573 s
->nsapr
[regno
+ 1][cpu
] = value
;
1578 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 16, 16, value
);
1583 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 8, 8, value
);
1587 g_assert_not_reached();
1591 static MemTxResult
gic_cpu_read(GICState
*s
, int cpu
, int offset
,
1592 uint64_t *data
, MemTxAttrs attrs
)
1595 case 0x00: /* Control */
1596 *data
= gic_get_cpu_control(s
, cpu
, attrs
);
1598 case 0x04: /* Priority mask */
1599 *data
= gic_get_priority_mask(s
, cpu
, attrs
);
1601 case 0x08: /* Binary Point */
1602 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1603 if (s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) {
1604 /* NS view of BPR when CBPR is 1 */
1605 *data
= MIN(s
->bpr
[cpu
] + 1, 7);
1607 /* BPR is banked. Non-secure copy stored in ABPR. */
1608 *data
= s
->abpr
[cpu
];
1611 *data
= s
->bpr
[cpu
];
1614 case 0x0c: /* Acknowledge */
1615 *data
= gic_acknowledge_irq(s
, cpu
, attrs
);
1617 case 0x14: /* Running Priority */
1618 *data
= gic_get_running_priority(s
, cpu
, attrs
);
1620 case 0x18: /* Highest Pending Interrupt */
1621 *data
= gic_get_current_pending_irq(s
, cpu
, attrs
);
1623 case 0x1c: /* Aliased Binary Point */
1624 /* GIC v2, no security: ABPR
1625 * GIC v1, no security: not implemented (RAZ/WI)
1626 * With security extensions, secure access: ABPR (alias of NS BPR)
1627 * With security extensions, nonsecure access: RAZ/WI
1629 if (!gic_has_groups(s
) || (gic_cpu_ns_access(s
, cpu
, attrs
))) {
1632 *data
= s
->abpr
[cpu
];
1635 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1637 int regno
= (offset
- 0xd0) / 4;
1638 int nr_aprs
= gic_is_vcpu(cpu
) ? GIC_VIRT_NR_APRS
: GIC_NR_APRS
;
1640 if (regno
>= nr_aprs
|| s
->revision
!= 2) {
1642 } else if (gic_is_vcpu(cpu
)) {
1643 *data
= s
->h_apr
[gic_get_vcpu_real_id(cpu
)];
1644 } else if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1645 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1646 *data
= gic_apr_ns_view(s
, regno
, cpu
);
1648 *data
= s
->apr
[regno
][cpu
];
1652 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1654 int regno
= (offset
- 0xe0) / 4;
1656 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2 || !gic_has_groups(s
) ||
1657 gic_cpu_ns_access(s
, cpu
, attrs
) || gic_is_vcpu(cpu
)) {
1660 *data
= s
->nsapr
[regno
][cpu
];
1665 qemu_log_mask(LOG_GUEST_ERROR
,
1666 "gic_cpu_read: Bad offset %x\n", (int)offset
);
1671 trace_gic_cpu_read(gic_is_vcpu(cpu
) ? "vcpu" : "cpu",
1672 gic_get_vcpu_real_id(cpu
), offset
, *data
);
1676 static MemTxResult
gic_cpu_write(GICState
*s
, int cpu
, int offset
,
1677 uint32_t value
, MemTxAttrs attrs
)
1679 trace_gic_cpu_write(gic_is_vcpu(cpu
) ? "vcpu" : "cpu",
1680 gic_get_vcpu_real_id(cpu
), offset
, value
);
1683 case 0x00: /* Control */
1684 gic_set_cpu_control(s
, cpu
, value
, attrs
);
1686 case 0x04: /* Priority mask */
1687 gic_set_priority_mask(s
, cpu
, value
, attrs
);
1689 case 0x08: /* Binary Point */
1690 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1691 if (s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) {
1692 /* WI when CBPR is 1 */
1695 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1698 int min_bpr
= gic_is_vcpu(cpu
) ? GIC_VIRT_MIN_BPR
: GIC_MIN_BPR
;
1699 s
->bpr
[cpu
] = MAX(value
& 0x7, min_bpr
);
1702 case 0x10: /* End Of Interrupt */
1703 gic_complete_irq(s
, cpu
, value
& 0x3ff, attrs
);
1705 case 0x1c: /* Aliased Binary Point */
1706 if (!gic_has_groups(s
) || (gic_cpu_ns_access(s
, cpu
, attrs
))) {
1707 /* unimplemented, or NS access: RAZ/WI */
1710 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1713 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1715 int regno
= (offset
- 0xd0) / 4;
1716 int nr_aprs
= gic_is_vcpu(cpu
) ? GIC_VIRT_NR_APRS
: GIC_NR_APRS
;
1718 if (regno
>= nr_aprs
|| s
->revision
!= 2) {
1721 if (gic_is_vcpu(cpu
)) {
1722 s
->h_apr
[gic_get_vcpu_real_id(cpu
)] = value
;
1723 } else if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1724 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1725 gic_apr_write_ns_view(s
, regno
, cpu
, value
);
1727 s
->apr
[regno
][cpu
] = value
;
1731 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1733 int regno
= (offset
- 0xe0) / 4;
1735 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1738 if (gic_is_vcpu(cpu
)) {
1741 if (!gic_has_groups(s
) || (gic_cpu_ns_access(s
, cpu
, attrs
))) {
1744 s
->nsapr
[regno
][cpu
] = value
;
1749 gic_deactivate_irq(s
, cpu
, value
& 0x3ff, attrs
);
1752 qemu_log_mask(LOG_GUEST_ERROR
,
1753 "gic_cpu_write: Bad offset %x\n", (int)offset
);
1757 if (gic_is_vcpu(cpu
)) {
1766 /* Wrappers to read/write the GIC CPU interface for the current CPU */
1767 static MemTxResult
gic_thiscpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1768 unsigned size
, MemTxAttrs attrs
)
1770 GICState
*s
= (GICState
*)opaque
;
1771 return gic_cpu_read(s
, gic_get_current_cpu(s
), addr
, data
, attrs
);
1774 static MemTxResult
gic_thiscpu_write(void *opaque
, hwaddr addr
,
1775 uint64_t value
, unsigned size
,
1778 GICState
*s
= (GICState
*)opaque
;
1779 return gic_cpu_write(s
, gic_get_current_cpu(s
), addr
, value
, attrs
);
1782 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
1783 * These just decode the opaque pointer into GICState* + cpu id.
1785 static MemTxResult
gic_do_cpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1786 unsigned size
, MemTxAttrs attrs
)
1788 GICState
**backref
= (GICState
**)opaque
;
1789 GICState
*s
= *backref
;
1790 int id
= (backref
- s
->backref
);
1791 return gic_cpu_read(s
, id
, addr
, data
, attrs
);
1794 static MemTxResult
gic_do_cpu_write(void *opaque
, hwaddr addr
,
1795 uint64_t value
, unsigned size
,
1798 GICState
**backref
= (GICState
**)opaque
;
1799 GICState
*s
= *backref
;
1800 int id
= (backref
- s
->backref
);
1801 return gic_cpu_write(s
, id
, addr
, value
, attrs
);
1804 static MemTxResult
gic_thisvcpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1805 unsigned size
, MemTxAttrs attrs
)
1807 GICState
*s
= (GICState
*)opaque
;
1809 return gic_cpu_read(s
, gic_get_current_vcpu(s
), addr
, data
, attrs
);
1812 static MemTxResult
gic_thisvcpu_write(void *opaque
, hwaddr addr
,
1813 uint64_t value
, unsigned size
,
1816 GICState
*s
= (GICState
*)opaque
;
1818 return gic_cpu_write(s
, gic_get_current_vcpu(s
), addr
, value
, attrs
);
1821 static uint32_t gic_compute_eisr(GICState
*s
, int cpu
, int lr_start
)
1826 for (lr_idx
= lr_start
; lr_idx
< s
->num_lrs
; lr_idx
++) {
1827 uint32_t *entry
= &s
->h_lr
[lr_idx
][cpu
];
1828 ret
= deposit32(ret
, lr_idx
- lr_start
, 1,
1829 gic_lr_entry_is_eoi(*entry
));
1835 static uint32_t gic_compute_elrsr(GICState
*s
, int cpu
, int lr_start
)
1840 for (lr_idx
= lr_start
; lr_idx
< s
->num_lrs
; lr_idx
++) {
1841 uint32_t *entry
= &s
->h_lr
[lr_idx
][cpu
];
1842 ret
= deposit32(ret
, lr_idx
- lr_start
, 1,
1843 gic_lr_entry_is_free(*entry
));
1849 static void gic_vmcr_write(GICState
*s
, uint32_t value
, MemTxAttrs attrs
)
1851 int vcpu
= gic_get_current_vcpu(s
);
1857 ctlr
= FIELD_EX32(value
, GICH_VMCR
, VMCCtlr
);
1858 abpr
= FIELD_EX32(value
, GICH_VMCR
, VMABP
);
1859 bpr
= FIELD_EX32(value
, GICH_VMCR
, VMBP
);
1860 prio_mask
= FIELD_EX32(value
, GICH_VMCR
, VMPriMask
) << 3;
1862 gic_set_cpu_control(s
, vcpu
, ctlr
, attrs
);
1863 s
->abpr
[vcpu
] = MAX(abpr
, GIC_VIRT_MIN_ABPR
);
1864 s
->bpr
[vcpu
] = MAX(bpr
, GIC_VIRT_MIN_BPR
);
1865 gic_set_priority_mask(s
, vcpu
, prio_mask
, attrs
);
1868 static MemTxResult
gic_hyp_read(void *opaque
, int cpu
, hwaddr addr
,
1869 uint64_t *data
, MemTxAttrs attrs
)
1871 GICState
*s
= ARM_GIC(opaque
);
1872 int vcpu
= cpu
+ GIC_NCPU
;
1875 case A_GICH_HCR
: /* Hypervisor Control */
1876 *data
= s
->h_hcr
[cpu
];
1879 case A_GICH_VTR
: /* VGIC Type */
1880 *data
= FIELD_DP32(0, GICH_VTR
, ListRegs
, s
->num_lrs
- 1);
1881 *data
= FIELD_DP32(*data
, GICH_VTR
, PREbits
,
1882 GIC_VIRT_MAX_GROUP_PRIO_BITS
- 1);
1883 *data
= FIELD_DP32(*data
, GICH_VTR
, PRIbits
,
1884 (7 - GIC_VIRT_MIN_BPR
) - 1);
1887 case A_GICH_VMCR
: /* Virtual Machine Control */
1888 *data
= FIELD_DP32(0, GICH_VMCR
, VMCCtlr
,
1889 extract32(s
->cpu_ctlr
[vcpu
], 0, 10));
1890 *data
= FIELD_DP32(*data
, GICH_VMCR
, VMABP
, s
->abpr
[vcpu
]);
1891 *data
= FIELD_DP32(*data
, GICH_VMCR
, VMBP
, s
->bpr
[vcpu
]);
1892 *data
= FIELD_DP32(*data
, GICH_VMCR
, VMPriMask
,
1893 extract32(s
->priority_mask
[vcpu
], 3, 5));
1896 case A_GICH_MISR
: /* Maintenance Interrupt Status */
1897 *data
= s
->h_misr
[cpu
];
1900 case A_GICH_EISR0
: /* End of Interrupt Status 0 and 1 */
1902 *data
= gic_compute_eisr(s
, cpu
, (addr
- A_GICH_EISR0
) * 8);
1905 case A_GICH_ELRSR0
: /* Empty List Status 0 and 1 */
1907 *data
= gic_compute_elrsr(s
, cpu
, (addr
- A_GICH_ELRSR0
) * 8);
1910 case A_GICH_APR
: /* Active Priorities */
1911 *data
= s
->h_apr
[cpu
];
1914 case A_GICH_LR0
... A_GICH_LR63
: /* List Registers */
1916 int lr_idx
= (addr
- A_GICH_LR0
) / 4;
1918 if (lr_idx
> s
->num_lrs
) {
1921 *data
= s
->h_lr
[lr_idx
][cpu
];
1927 qemu_log_mask(LOG_GUEST_ERROR
,
1928 "gic_hyp_read: Bad offset %" HWADDR_PRIx
"\n", addr
);
1932 trace_gic_hyp_read(addr
, *data
);
1936 static MemTxResult
gic_hyp_write(void *opaque
, int cpu
, hwaddr addr
,
1937 uint64_t value
, MemTxAttrs attrs
)
1939 GICState
*s
= ARM_GIC(opaque
);
1940 int vcpu
= cpu
+ GIC_NCPU
;
1942 trace_gic_hyp_write(addr
, value
);
1945 case A_GICH_HCR
: /* Hypervisor Control */
1946 s
->h_hcr
[cpu
] = value
& GICH_HCR_MASK
;
1949 case A_GICH_VMCR
: /* Virtual Machine Control */
1950 gic_vmcr_write(s
, value
, attrs
);
1953 case A_GICH_APR
: /* Active Priorities */
1954 s
->h_apr
[cpu
] = value
;
1955 s
->running_priority
[vcpu
] = gic_get_prio_from_apr_bits(s
, vcpu
);
1958 case A_GICH_LR0
... A_GICH_LR63
: /* List Registers */
1960 int lr_idx
= (addr
- A_GICH_LR0
) / 4;
1962 if (lr_idx
> s
->num_lrs
) {
1966 s
->h_lr
[lr_idx
][cpu
] = value
& GICH_LR_MASK
;
1967 trace_gic_lr_entry(cpu
, lr_idx
, s
->h_lr
[lr_idx
][cpu
]);
1972 qemu_log_mask(LOG_GUEST_ERROR
,
1973 "gic_hyp_write: Bad offset %" HWADDR_PRIx
"\n", addr
);
1981 static MemTxResult
gic_thiscpu_hyp_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1982 unsigned size
, MemTxAttrs attrs
)
1984 GICState
*s
= (GICState
*)opaque
;
1986 return gic_hyp_read(s
, gic_get_current_cpu(s
), addr
, data
, attrs
);
1989 static MemTxResult
gic_thiscpu_hyp_write(void *opaque
, hwaddr addr
,
1990 uint64_t value
, unsigned size
,
1993 GICState
*s
= (GICState
*)opaque
;
1995 return gic_hyp_write(s
, gic_get_current_cpu(s
), addr
, value
, attrs
);
1998 static MemTxResult
gic_do_hyp_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1999 unsigned size
, MemTxAttrs attrs
)
2001 GICState
**backref
= (GICState
**)opaque
;
2002 GICState
*s
= *backref
;
2003 int id
= (backref
- s
->backref
);
2005 return gic_hyp_read(s
, id
, addr
, data
, attrs
);
2008 static MemTxResult
gic_do_hyp_write(void *opaque
, hwaddr addr
,
2009 uint64_t value
, unsigned size
,
2012 GICState
**backref
= (GICState
**)opaque
;
2013 GICState
*s
= *backref
;
2014 int id
= (backref
- s
->backref
);
2016 return gic_hyp_write(s
, id
+ GIC_NCPU
, addr
, value
, attrs
);
2020 static const MemoryRegionOps gic_ops
[2] = {
2022 .read_with_attrs
= gic_dist_read
,
2023 .write_with_attrs
= gic_dist_write
,
2024 .endianness
= DEVICE_NATIVE_ENDIAN
,
2027 .read_with_attrs
= gic_thiscpu_read
,
2028 .write_with_attrs
= gic_thiscpu_write
,
2029 .endianness
= DEVICE_NATIVE_ENDIAN
,
2033 static const MemoryRegionOps gic_cpu_ops
= {
2034 .read_with_attrs
= gic_do_cpu_read
,
2035 .write_with_attrs
= gic_do_cpu_write
,
2036 .endianness
= DEVICE_NATIVE_ENDIAN
,
2039 static const MemoryRegionOps gic_virt_ops
[2] = {
2041 .read_with_attrs
= gic_thiscpu_hyp_read
,
2042 .write_with_attrs
= gic_thiscpu_hyp_write
,
2043 .endianness
= DEVICE_NATIVE_ENDIAN
,
2046 .read_with_attrs
= gic_thisvcpu_read
,
2047 .write_with_attrs
= gic_thisvcpu_write
,
2048 .endianness
= DEVICE_NATIVE_ENDIAN
,
2052 static const MemoryRegionOps gic_viface_ops
= {
2053 .read_with_attrs
= gic_do_hyp_read
,
2054 .write_with_attrs
= gic_do_hyp_write
,
2055 .endianness
= DEVICE_NATIVE_ENDIAN
,
2058 static void arm_gic_realize(DeviceState
*dev
, Error
**errp
)
2060 /* Device instance realize function for the GIC sysbus device */
2062 GICState
*s
= ARM_GIC(dev
);
2063 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
2064 ARMGICClass
*agc
= ARM_GIC_GET_CLASS(s
);
2065 Error
*local_err
= NULL
;
2067 agc
->parent_realize(dev
, &local_err
);
2069 error_propagate(errp
, local_err
);
2073 if (kvm_enabled() && !kvm_arm_supports_user_irq()) {
2074 error_setg(errp
, "KVM with user space irqchip only works when the "
2075 "host kernel supports KVM_CAP_ARM_USER_IRQ");
2079 if (s
->n_prio_bits
> GIC_MAX_PRIORITY_BITS
||
2080 (s
->virt_extn
? s
->n_prio_bits
< GIC_VIRT_MAX_GROUP_PRIO_BITS
:
2081 s
->n_prio_bits
< GIC_MIN_PRIORITY_BITS
)) {
2082 error_setg(errp
, "num-priority-bits cannot be greater than %d"
2083 " or less than %d", GIC_MAX_PRIORITY_BITS
,
2084 s
->virt_extn
? GIC_VIRT_MAX_GROUP_PRIO_BITS
:
2085 GIC_MIN_PRIORITY_BITS
);
2089 /* This creates distributor, main CPU interface (s->cpuiomem[0]) and if
2090 * enabled, virtualization extensions related interfaces (main virtual
2091 * interface (s->vifaceiomem[0]) and virtual CPU interface).
2093 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
, gic_virt_ops
);
2095 /* Extra core-specific regions for the CPU interfaces. This is
2096 * necessary for "franken-GIC" implementations, for example on
2098 * NB that the memory region size of 0x100 applies for the 11MPCore
2099 * and also cores following the GIC v1 spec (ie A9).
2100 * GIC v2 defines a larger memory region (0x1000) so this will need
2101 * to be extended when we implement A15.
2103 for (i
= 0; i
< s
->num_cpu
; i
++) {
2105 memory_region_init_io(&s
->cpuiomem
[i
+1], OBJECT(s
), &gic_cpu_ops
,
2106 &s
->backref
[i
], "gic_cpu", 0x100);
2107 sysbus_init_mmio(sbd
, &s
->cpuiomem
[i
+1]);
2110 /* Extra core-specific regions for virtual interfaces. This is required by
2111 * the GICv2 specification.
2114 for (i
= 0; i
< s
->num_cpu
; i
++) {
2115 memory_region_init_io(&s
->vifaceiomem
[i
+ 1], OBJECT(s
),
2116 &gic_viface_ops
, &s
->backref
[i
],
2117 "gic_viface", 0x200);
2118 sysbus_init_mmio(sbd
, &s
->vifaceiomem
[i
+ 1]);
2124 static void arm_gic_class_init(ObjectClass
*klass
, void *data
)
2126 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2127 ARMGICClass
*agc
= ARM_GIC_CLASS(klass
);
2129 device_class_set_parent_realize(dc
, arm_gic_realize
, &agc
->parent_realize
);
2132 static const TypeInfo arm_gic_info
= {
2133 .name
= TYPE_ARM_GIC
,
2134 .parent
= TYPE_ARM_GIC_COMMON
,
2135 .instance_size
= sizeof(GICState
),
2136 .class_init
= arm_gic_class_init
,
2137 .class_size
= sizeof(ARMGICClass
),
2140 static void arm_gic_register_types(void)
2142 type_register_static(&arm_gic_info
);
2145 type_init(arm_gic_register_types
)