4 * Altivec/VMX translation
7 /*** Altivec vector extension ***/
8 /* Altivec registers moves */
10 static inline TCGv_ptr gen_avr_ptr(int reg)
12 TCGv_ptr r = tcg_temp_new_ptr();
13 tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg));
17 #define GEN_VR_LDX(name, opc2, opc3) \
18 static void glue(gen_, name)(DisasContext *ctx) \
22 if (unlikely(!ctx->altivec_enabled)) { \
23 gen_exception(ctx, POWERPC_EXCP_VPU); \
26 gen_set_access_type(ctx, ACCESS_INT); \
27 avr = tcg_temp_new_i64(); \
28 EA = tcg_temp_new(); \
29 gen_addr_reg_index(ctx, EA); \
30 tcg_gen_andi_tl(EA, EA, ~0xf); \
32 * We only need to swap high and low halves. gen_qemu_ld64_i64 \
33 * does necessary 64-bit byteswap already. \
36 gen_qemu_ld64_i64(ctx, avr, EA); \
37 set_avr64(rD(ctx->opcode), avr, false); \
38 tcg_gen_addi_tl(EA, EA, 8); \
39 gen_qemu_ld64_i64(ctx, avr, EA); \
40 set_avr64(rD(ctx->opcode), avr, true); \
42 gen_qemu_ld64_i64(ctx, avr, EA); \
43 set_avr64(rD(ctx->opcode), avr, true); \
44 tcg_gen_addi_tl(EA, EA, 8); \
45 gen_qemu_ld64_i64(ctx, avr, EA); \
46 set_avr64(rD(ctx->opcode), avr, false); \
49 tcg_temp_free_i64(avr); \
52 #define GEN_VR_STX(name, opc2, opc3) \
53 static void gen_st##name(DisasContext *ctx) \
57 if (unlikely(!ctx->altivec_enabled)) { \
58 gen_exception(ctx, POWERPC_EXCP_VPU); \
61 gen_set_access_type(ctx, ACCESS_INT); \
62 avr = tcg_temp_new_i64(); \
63 EA = tcg_temp_new(); \
64 gen_addr_reg_index(ctx, EA); \
65 tcg_gen_andi_tl(EA, EA, ~0xf); \
67 * We only need to swap high and low halves. gen_qemu_st64_i64 \
68 * does necessary 64-bit byteswap already. \
71 get_avr64(avr, rD(ctx->opcode), false); \
72 gen_qemu_st64_i64(ctx, avr, EA); \
73 tcg_gen_addi_tl(EA, EA, 8); \
74 get_avr64(avr, rD(ctx->opcode), true); \
75 gen_qemu_st64_i64(ctx, avr, EA); \
77 get_avr64(avr, rD(ctx->opcode), true); \
78 gen_qemu_st64_i64(ctx, avr, EA); \
79 tcg_gen_addi_tl(EA, EA, 8); \
80 get_avr64(avr, rD(ctx->opcode), false); \
81 gen_qemu_st64_i64(ctx, avr, EA); \
84 tcg_temp_free_i64(avr); \
87 #define GEN_VR_LVE(name, opc2, opc3, size) \
88 static void gen_lve##name(DisasContext *ctx) \
92 if (unlikely(!ctx->altivec_enabled)) { \
93 gen_exception(ctx, POWERPC_EXCP_VPU); \
96 gen_set_access_type(ctx, ACCESS_INT); \
97 EA = tcg_temp_new(); \
98 gen_addr_reg_index(ctx, EA); \
100 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
102 rs = gen_avr_ptr(rS(ctx->opcode)); \
103 gen_helper_lve##name(cpu_env, rs, EA); \
105 tcg_temp_free_ptr(rs); \
108 #define GEN_VR_STVE(name, opc2, opc3, size) \
109 static void gen_stve##name(DisasContext *ctx) \
113 if (unlikely(!ctx->altivec_enabled)) { \
114 gen_exception(ctx, POWERPC_EXCP_VPU); \
117 gen_set_access_type(ctx, ACCESS_INT); \
118 EA = tcg_temp_new(); \
119 gen_addr_reg_index(ctx, EA); \
121 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
123 rs = gen_avr_ptr(rS(ctx->opcode)); \
124 gen_helper_stve##name(cpu_env, rs, EA); \
126 tcg_temp_free_ptr(rs); \
129 GEN_VR_LDX(lvx, 0x07, 0x03);
130 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
131 GEN_VR_LDX(lvxl, 0x07, 0x0B);
133 GEN_VR_LVE(bx, 0x07, 0x00, 1);
134 GEN_VR_LVE(hx, 0x07, 0x01, 2);
135 GEN_VR_LVE(wx, 0x07, 0x02, 4);
137 GEN_VR_STX(svx, 0x07, 0x07);
138 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
139 GEN_VR_STX(svxl, 0x07, 0x0F);
141 GEN_VR_STVE(bx, 0x07, 0x04, 1);
142 GEN_VR_STVE(hx, 0x07, 0x05, 2);
143 GEN_VR_STVE(wx, 0x07, 0x06, 4);
145 static void gen_mfvscr(DisasContext *ctx)
149 if (unlikely(!ctx->altivec_enabled)) {
150 gen_exception(ctx, POWERPC_EXCP_VPU);
153 avr = tcg_temp_new_i64();
154 tcg_gen_movi_i64(avr, 0);
155 set_avr64(rD(ctx->opcode), avr, true);
156 t = tcg_temp_new_i32();
157 gen_helper_mfvscr(t, cpu_env);
158 tcg_gen_extu_i32_i64(avr, t);
159 set_avr64(rD(ctx->opcode), avr, false);
160 tcg_temp_free_i32(t);
161 tcg_temp_free_i64(avr);
164 static void gen_mtvscr(DisasContext *ctx)
169 if (unlikely(!ctx->altivec_enabled)) {
170 gen_exception(ctx, POWERPC_EXCP_VPU);
174 val = tcg_temp_new_i32();
175 bofs = avr_full_offset(rB(ctx->opcode));
180 tcg_gen_ld_i32(val, cpu_env, bofs);
181 gen_helper_mtvscr(cpu_env, val);
182 tcg_temp_free_i32(val);
185 #define GEN_VX_VMUL10(name, add_cin, ret_carry) \
186 static void glue(gen_, name)(DisasContext *ctx) \
194 if (unlikely(!ctx->altivec_enabled)) { \
195 gen_exception(ctx, POWERPC_EXCP_VPU); \
199 t0 = tcg_temp_new_i64(); \
200 t1 = tcg_temp_new_i64(); \
201 t2 = tcg_temp_new_i64(); \
202 avr = tcg_temp_new_i64(); \
203 ten = tcg_const_i64(10); \
204 z = tcg_const_i64(0); \
207 get_avr64(avr, rA(ctx->opcode), false); \
208 tcg_gen_mulu2_i64(t0, t1, avr, ten); \
209 get_avr64(avr, rB(ctx->opcode), false); \
210 tcg_gen_andi_i64(t2, avr, 0xF); \
211 tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \
212 set_avr64(rD(ctx->opcode), avr, false); \
214 get_avr64(avr, rA(ctx->opcode), false); \
215 tcg_gen_mulu2_i64(avr, t2, avr, ten); \
216 set_avr64(rD(ctx->opcode), avr, false); \
220 get_avr64(avr, rA(ctx->opcode), true); \
221 tcg_gen_mulu2_i64(t0, t1, avr, ten); \
222 tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \
223 set_avr64(rD(ctx->opcode), avr, false); \
224 set_avr64(rD(ctx->opcode), z, true); \
226 get_avr64(avr, rA(ctx->opcode), true); \
227 tcg_gen_mul_i64(t0, avr, ten); \
228 tcg_gen_add_i64(avr, t0, t2); \
229 set_avr64(rD(ctx->opcode), avr, true); \
232 tcg_temp_free_i64(t0); \
233 tcg_temp_free_i64(t1); \
234 tcg_temp_free_i64(t2); \
235 tcg_temp_free_i64(avr); \
236 tcg_temp_free_i64(ten); \
237 tcg_temp_free_i64(z); \
240 GEN_VX_VMUL10(vmul10uq, 0, 0);
241 GEN_VX_VMUL10(vmul10euq, 1, 0);
242 GEN_VX_VMUL10(vmul10cuq, 0, 1);
243 GEN_VX_VMUL10(vmul10ecuq, 1, 1);
245 #define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \
246 static void glue(gen_, name)(DisasContext *ctx) \
248 if (unlikely(!ctx->altivec_enabled)) { \
249 gen_exception(ctx, POWERPC_EXCP_VPU); \
254 avr_full_offset(rD(ctx->opcode)), \
255 avr_full_offset(rA(ctx->opcode)), \
256 avr_full_offset(rB(ctx->opcode)), \
260 /* Logical operations */
261 GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);
262 GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);
263 GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);
264 GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);
265 GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20);
266 GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26);
267 GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22);
268 GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);
270 #define GEN_VXFORM(name, opc2, opc3) \
271 static void glue(gen_, name)(DisasContext *ctx) \
273 TCGv_ptr ra, rb, rd; \
274 if (unlikely(!ctx->altivec_enabled)) { \
275 gen_exception(ctx, POWERPC_EXCP_VPU); \
278 ra = gen_avr_ptr(rA(ctx->opcode)); \
279 rb = gen_avr_ptr(rB(ctx->opcode)); \
280 rd = gen_avr_ptr(rD(ctx->opcode)); \
281 gen_helper_##name(rd, ra, rb); \
282 tcg_temp_free_ptr(ra); \
283 tcg_temp_free_ptr(rb); \
284 tcg_temp_free_ptr(rd); \
287 #define GEN_VXFORM_TRANS(name, opc2, opc3) \
288 static void glue(gen_, name)(DisasContext *ctx) \
290 if (unlikely(!ctx->altivec_enabled)) { \
291 gen_exception(ctx, POWERPC_EXCP_VPU); \
297 #define GEN_VXFORM_ENV(name, opc2, opc3) \
298 static void glue(gen_, name)(DisasContext *ctx) \
300 TCGv_ptr ra, rb, rd; \
301 if (unlikely(!ctx->altivec_enabled)) { \
302 gen_exception(ctx, POWERPC_EXCP_VPU); \
305 ra = gen_avr_ptr(rA(ctx->opcode)); \
306 rb = gen_avr_ptr(rB(ctx->opcode)); \
307 rd = gen_avr_ptr(rD(ctx->opcode)); \
308 gen_helper_##name(cpu_env, rd, ra, rb); \
309 tcg_temp_free_ptr(ra); \
310 tcg_temp_free_ptr(rb); \
311 tcg_temp_free_ptr(rd); \
314 #define GEN_VXFORM3(name, opc2, opc3) \
315 static void glue(gen_, name)(DisasContext *ctx) \
317 TCGv_ptr ra, rb, rc, rd; \
318 if (unlikely(!ctx->altivec_enabled)) { \
319 gen_exception(ctx, POWERPC_EXCP_VPU); \
322 ra = gen_avr_ptr(rA(ctx->opcode)); \
323 rb = gen_avr_ptr(rB(ctx->opcode)); \
324 rc = gen_avr_ptr(rC(ctx->opcode)); \
325 rd = gen_avr_ptr(rD(ctx->opcode)); \
326 gen_helper_##name(rd, ra, rb, rc); \
327 tcg_temp_free_ptr(ra); \
328 tcg_temp_free_ptr(rb); \
329 tcg_temp_free_ptr(rc); \
330 tcg_temp_free_ptr(rd); \
334 * Support for Altivec instruction pairs that use bit 31 (Rc) as
335 * an opcode bit. In general, these pairs come from different
336 * versions of the ISA, so we must also support a pair of flags for
339 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
340 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
342 if ((Rc(ctx->opcode) == 0) && \
343 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
345 } else if ((Rc(ctx->opcode) == 1) && \
346 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
349 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
354 * We use this macro if one instruction is realized with direct
355 * translation, and second one with helper.
357 #define GEN_VXFORM_TRANS_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)\
358 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
360 if ((Rc(ctx->opcode) == 0) && \
361 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
362 if (unlikely(!ctx->altivec_enabled)) { \
363 gen_exception(ctx, POWERPC_EXCP_VPU); \
366 trans_##name0(ctx); \
367 } else if ((Rc(ctx->opcode) == 1) && \
368 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
371 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
375 /* Adds support to provide invalid mask */
376 #define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \
377 name1, flg1, flg2_1, inval1) \
378 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
380 if ((Rc(ctx->opcode) == 0) && \
381 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) && \
382 !(ctx->opcode & inval0)) { \
384 } else if ((Rc(ctx->opcode) == 1) && \
385 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \
386 !(ctx->opcode & inval1)) { \
389 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
393 #define GEN_VXFORM_HETRO(name, opc2, opc3) \
394 static void glue(gen_, name)(DisasContext *ctx) \
397 if (unlikely(!ctx->altivec_enabled)) { \
398 gen_exception(ctx, POWERPC_EXCP_VPU); \
401 rb = gen_avr_ptr(rB(ctx->opcode)); \
402 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \
403 tcg_temp_free_ptr(rb); \
406 GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0);
407 GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \
408 vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
409 GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);
410 GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \
411 vmul10ecuq, PPC_NONE, PPC2_ISA300)
412 GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);
413 GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);
414 GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
415 GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
416 GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
417 GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
418 GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0);
419 GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1);
420 GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);
421 GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);
422 GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4);
423 GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5);
424 GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);
425 GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);
426 GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8);
427 GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);
428 GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);
429 GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);
430 GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12);
431 GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13);
432 GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);
433 GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);
434 GEN_VXFORM(vavgub, 1, 16);
435 GEN_VXFORM(vabsdub, 1, 16);
436 GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \
437 vabsdub, PPC_NONE, PPC2_ISA300)
438 GEN_VXFORM(vavguh, 1, 17);
439 GEN_VXFORM(vabsduh, 1, 17);
440 GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \
441 vabsduh, PPC_NONE, PPC2_ISA300)
442 GEN_VXFORM(vavguw, 1, 18);
443 GEN_VXFORM(vabsduw, 1, 18);
444 GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \
445 vabsduw, PPC_NONE, PPC2_ISA300)
446 GEN_VXFORM(vavgsb, 1, 20);
447 GEN_VXFORM(vavgsh, 1, 21);
448 GEN_VXFORM(vavgsw, 1, 22);
449 GEN_VXFORM(vmrghb, 6, 0);
450 GEN_VXFORM(vmrghh, 6, 1);
451 GEN_VXFORM(vmrghw, 6, 2);
452 GEN_VXFORM(vmrglb, 6, 4);
453 GEN_VXFORM(vmrglh, 6, 5);
454 GEN_VXFORM(vmrglw, 6, 6);
456 static void trans_vmrgew(DisasContext *ctx)
458 int VT = rD(ctx->opcode);
459 int VA = rA(ctx->opcode);
460 int VB = rB(ctx->opcode);
461 TCGv_i64 tmp = tcg_temp_new_i64();
462 TCGv_i64 avr = tcg_temp_new_i64();
464 get_avr64(avr, VB, true);
465 tcg_gen_shri_i64(tmp, avr, 32);
466 get_avr64(avr, VA, true);
467 tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
468 set_avr64(VT, avr, true);
470 get_avr64(avr, VB, false);
471 tcg_gen_shri_i64(tmp, avr, 32);
472 get_avr64(avr, VA, false);
473 tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
474 set_avr64(VT, avr, false);
476 tcg_temp_free_i64(tmp);
477 tcg_temp_free_i64(avr);
480 static void trans_vmrgow(DisasContext *ctx)
482 int VT = rD(ctx->opcode);
483 int VA = rA(ctx->opcode);
484 int VB = rB(ctx->opcode);
485 TCGv_i64 t0 = tcg_temp_new_i64();
486 TCGv_i64 t1 = tcg_temp_new_i64();
487 TCGv_i64 avr = tcg_temp_new_i64();
489 get_avr64(t0, VB, true);
490 get_avr64(t1, VA, true);
491 tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
492 set_avr64(VT, avr, true);
494 get_avr64(t0, VB, false);
495 get_avr64(t1, VA, false);
496 tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
497 set_avr64(VT, avr, false);
499 tcg_temp_free_i64(t0);
500 tcg_temp_free_i64(t1);
501 tcg_temp_free_i64(avr);
505 * lvsl VRT,RA,RB - Load Vector for Shift Left
507 * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
508 * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
509 * Bytes sh:sh+15 of X are placed into vD.
511 static void trans_lvsl(DisasContext *ctx)
513 int VT = rD(ctx->opcode);
514 TCGv_i64 result = tcg_temp_new_i64();
515 TCGv_i64 sh = tcg_temp_new_i64();
516 TCGv EA = tcg_temp_new();
518 /* Get sh(from description) by anding EA with 0xf. */
519 gen_addr_reg_index(ctx, EA);
520 tcg_gen_extu_tl_i64(sh, EA);
521 tcg_gen_andi_i64(sh, sh, 0xfULL);
524 * Create bytes sh:sh+7 of X(from description) and place them in
525 * higher doubleword of vD.
527 tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
528 tcg_gen_addi_i64(result, sh, 0x0001020304050607ull);
529 set_avr64(VT, result, true);
531 * Create bytes sh+8:sh+15 of X(from description) and place them in
532 * lower doubleword of vD.
534 tcg_gen_addi_i64(result, sh, 0x08090a0b0c0d0e0fULL);
535 set_avr64(VT, result, false);
537 tcg_temp_free_i64(result);
538 tcg_temp_free_i64(sh);
543 * lvsr VRT,RA,RB - Load Vector for Shift Right
545 * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
546 * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
547 * Bytes (16-sh):(31-sh) of X are placed into vD.
549 static void trans_lvsr(DisasContext *ctx)
551 int VT = rD(ctx->opcode);
552 TCGv_i64 result = tcg_temp_new_i64();
553 TCGv_i64 sh = tcg_temp_new_i64();
554 TCGv EA = tcg_temp_new();
557 /* Get sh(from description) by anding EA with 0xf. */
558 gen_addr_reg_index(ctx, EA);
559 tcg_gen_extu_tl_i64(sh, EA);
560 tcg_gen_andi_i64(sh, sh, 0xfULL);
563 * Create bytes (16-sh):(23-sh) of X(from description) and place them in
564 * higher doubleword of vD.
566 tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
567 tcg_gen_subfi_i64(result, 0x1011121314151617ULL, sh);
568 set_avr64(VT, result, true);
570 * Create bytes (24-sh):(32-sh) of X(from description) and place them in
571 * lower doubleword of vD.
573 tcg_gen_subfi_i64(result, 0x18191a1b1c1d1e1fULL, sh);
574 set_avr64(VT, result, false);
576 tcg_temp_free_i64(result);
577 tcg_temp_free_i64(sh);
582 * vsl VRT,VRA,VRB - Vector Shift Left
584 * Shifting left 128 bit value of vA by value specified in bits 125-127 of vB.
585 * Lowest 3 bits in each byte element of register vB must be identical or
586 * result is undefined.
588 static void trans_vsl(DisasContext *ctx)
590 int VT = rD(ctx->opcode);
591 int VA = rA(ctx->opcode);
592 int VB = rB(ctx->opcode);
593 TCGv_i64 avr = tcg_temp_new_i64();
594 TCGv_i64 sh = tcg_temp_new_i64();
595 TCGv_i64 carry = tcg_temp_new_i64();
596 TCGv_i64 tmp = tcg_temp_new_i64();
598 /* Place bits 125-127 of vB in 'sh'. */
599 get_avr64(avr, VB, false);
600 tcg_gen_andi_i64(sh, avr, 0x07ULL);
603 * Save highest 'sh' bits of lower doubleword element of vA in variable
604 * 'carry' and perform shift on lower doubleword.
606 get_avr64(avr, VA, false);
607 tcg_gen_subfi_i64(tmp, 32, sh);
608 tcg_gen_shri_i64(carry, avr, 32);
609 tcg_gen_shr_i64(carry, carry, tmp);
610 tcg_gen_shl_i64(avr, avr, sh);
611 set_avr64(VT, avr, false);
614 * Perform shift on higher doubleword element of vA and replace lowest
615 * 'sh' bits with 'carry'.
617 get_avr64(avr, VA, true);
618 tcg_gen_shl_i64(avr, avr, sh);
619 tcg_gen_or_i64(avr, avr, carry);
620 set_avr64(VT, avr, true);
622 tcg_temp_free_i64(avr);
623 tcg_temp_free_i64(sh);
624 tcg_temp_free_i64(carry);
625 tcg_temp_free_i64(tmp);
629 * vsr VRT,VRA,VRB - Vector Shift Right
631 * Shifting right 128 bit value of vA by value specified in bits 125-127 of vB.
632 * Lowest 3 bits in each byte element of register vB must be identical or
633 * result is undefined.
635 static void trans_vsr(DisasContext *ctx)
637 int VT = rD(ctx->opcode);
638 int VA = rA(ctx->opcode);
639 int VB = rB(ctx->opcode);
640 TCGv_i64 avr = tcg_temp_new_i64();
641 TCGv_i64 sh = tcg_temp_new_i64();
642 TCGv_i64 carry = tcg_temp_new_i64();
643 TCGv_i64 tmp = tcg_temp_new_i64();
645 /* Place bits 125-127 of vB in 'sh'. */
646 get_avr64(avr, VB, false);
647 tcg_gen_andi_i64(sh, avr, 0x07ULL);
650 * Save lowest 'sh' bits of higher doubleword element of vA in variable
651 * 'carry' and perform shift on higher doubleword.
653 get_avr64(avr, VA, true);
654 tcg_gen_subfi_i64(tmp, 32, sh);
655 tcg_gen_shli_i64(carry, avr, 32);
656 tcg_gen_shl_i64(carry, carry, tmp);
657 tcg_gen_shr_i64(avr, avr, sh);
658 set_avr64(VT, avr, true);
660 * Perform shift on lower doubleword element of vA and replace highest
661 * 'sh' bits with 'carry'.
663 get_avr64(avr, VA, false);
664 tcg_gen_shr_i64(avr, avr, sh);
665 tcg_gen_or_i64(avr, avr, carry);
666 set_avr64(VT, avr, false);
668 tcg_temp_free_i64(avr);
669 tcg_temp_free_i64(sh);
670 tcg_temp_free_i64(carry);
671 tcg_temp_free_i64(tmp);
675 * vgbbd VRT,VRB - Vector Gather Bits by Bytes by Doubleword
677 * All ith bits (i in range 1 to 8) of each byte of doubleword element in source
678 * register are concatenated and placed into ith byte of appropriate doubleword
679 * element in destination register.
681 * Following solution is done for both doubleword elements of source register
682 * in parallel, in order to reduce the number of instructions needed(that's why
684 * First, both doubleword elements of source register vB are placed in
685 * appropriate element of array avr. Bits are gathered in 2x8 iterations(2 for
686 * loops). In first iteration bit 1 of byte 1, bit 2 of byte 2,... bit 8 of
687 * byte 8 are in their final spots so avr[i], i={0,1} can be and-ed with
688 * tcg_mask. For every following iteration, both avr[i] and tcg_mask variables
689 * have to be shifted right for 7 and 8 places, respectively, in order to get
690 * bit 1 of byte 2, bit 2 of byte 3.. bit 7 of byte 8 in their final spots so
691 * shifted avr values(saved in tmp) can be and-ed with new value of tcg_mask...
692 * After first 8 iteration(first loop), all the first bits are in their final
693 * places, all second bits but second bit from eight byte are in their places...
694 * only 1 eight bit from eight byte is in it's place). In second loop we do all
695 * operations symmetrically, in order to get other half of bits in their final
696 * spots. Results for first and second doubleword elements are saved in
697 * result[0] and result[1] respectively. In the end those results are saved in
698 * appropriate doubleword element of destination register vD.
700 static void trans_vgbbd(DisasContext *ctx)
702 int VT = rD(ctx->opcode);
703 int VB = rB(ctx->opcode);
704 TCGv_i64 tmp = tcg_temp_new_i64();
705 uint64_t mask = 0x8040201008040201ULL;
709 result[0] = tcg_temp_new_i64();
710 result[1] = tcg_temp_new_i64();
712 avr[0] = tcg_temp_new_i64();
713 avr[1] = tcg_temp_new_i64();
714 TCGv_i64 tcg_mask = tcg_temp_new_i64();
716 tcg_gen_movi_i64(tcg_mask, mask);
717 for (j = 0; j < 2; j++) {
718 get_avr64(avr[j], VB, j);
719 tcg_gen_and_i64(result[j], avr[j], tcg_mask);
721 for (i = 1; i < 8; i++) {
722 tcg_gen_movi_i64(tcg_mask, mask >> (i * 8));
723 for (j = 0; j < 2; j++) {
724 tcg_gen_shri_i64(tmp, avr[j], i * 7);
725 tcg_gen_and_i64(tmp, tmp, tcg_mask);
726 tcg_gen_or_i64(result[j], result[j], tmp);
729 for (i = 1; i < 8; i++) {
730 tcg_gen_movi_i64(tcg_mask, mask << (i * 8));
731 for (j = 0; j < 2; j++) {
732 tcg_gen_shli_i64(tmp, avr[j], i * 7);
733 tcg_gen_and_i64(tmp, tmp, tcg_mask);
734 tcg_gen_or_i64(result[j], result[j], tmp);
737 for (j = 0; j < 2; j++) {
738 set_avr64(VT, result[j], j);
741 tcg_temp_free_i64(tmp);
742 tcg_temp_free_i64(tcg_mask);
743 tcg_temp_free_i64(result[0]);
744 tcg_temp_free_i64(result[1]);
745 tcg_temp_free_i64(avr[0]);
746 tcg_temp_free_i64(avr[1]);
750 * vclzw VRT,VRB - Vector Count Leading Zeros Word
752 * Counting the number of leading zero bits of each word element in source
753 * register and placing result in appropriate word element of destination
756 static void trans_vclzw(DisasContext *ctx)
758 int VT = rD(ctx->opcode);
759 int VB = rB(ctx->opcode);
760 TCGv_i32 tmp = tcg_temp_new_i32();
763 /* Perform count for every word element using tcg_gen_clzi_i32. */
764 for (i = 0; i < 4; i++) {
765 tcg_gen_ld_i32(tmp, cpu_env,
766 offsetof(CPUPPCState, vsr[32 + VB].u64[0]) + i * 4);
767 tcg_gen_clzi_i32(tmp, tmp, 32);
768 tcg_gen_st_i32(tmp, cpu_env,
769 offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4);
772 tcg_temp_free_i32(tmp);
776 * vclzd VRT,VRB - Vector Count Leading Zeros Doubleword
778 * Counting the number of leading zero bits of each doubleword element in source
779 * register and placing result in appropriate doubleword element of destination
782 static void trans_vclzd(DisasContext *ctx)
784 int VT = rD(ctx->opcode);
785 int VB = rB(ctx->opcode);
786 TCGv_i64 avr = tcg_temp_new_i64();
788 /* high doubleword */
789 get_avr64(avr, VB, true);
790 tcg_gen_clzi_i64(avr, avr, 64);
791 set_avr64(VT, avr, true);
794 get_avr64(avr, VB, false);
795 tcg_gen_clzi_i64(avr, avr, 64);
796 set_avr64(VT, avr, false);
798 tcg_temp_free_i64(avr);
801 GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2);
802 GEN_VXFORM(vsrv, 2, 28);
803 GEN_VXFORM(vslv, 2, 29);
804 GEN_VXFORM(vslo, 6, 16);
805 GEN_VXFORM(vsro, 6, 17);
806 GEN_VXFORM(vaddcuw, 0, 6);
807 GEN_VXFORM(vsubcuw, 0, 22);
809 static bool do_vector_gvec3_VX(DisasContext *ctx, arg_VX *a, int vece,
810 void (*gen_gvec)(unsigned, uint32_t, uint32_t,
811 uint32_t, uint32_t, uint32_t))
815 gen_gvec(vece, avr_full_offset(a->vrt), avr_full_offset(a->vra),
816 avr_full_offset(a->vrb), 16, 16);
821 TRANS_FLAGS(ALTIVEC, VSLB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shlv);
822 TRANS_FLAGS(ALTIVEC, VSLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shlv);
823 TRANS_FLAGS(ALTIVEC, VSLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shlv);
824 TRANS_FLAGS2(ALTIVEC_207, VSLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shlv);
826 TRANS_FLAGS(ALTIVEC, VSRB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shrv);
827 TRANS_FLAGS(ALTIVEC, VSRH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shrv);
828 TRANS_FLAGS(ALTIVEC, VSRW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shrv);
829 TRANS_FLAGS2(ALTIVEC_207, VSRD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shrv);
831 TRANS_FLAGS(ALTIVEC, VSRAB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_sarv);
832 TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv);
833 TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
834 TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
836 TRANS_FLAGS(ALTIVEC, VRLB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_rotlv)
837 TRANS_FLAGS(ALTIVEC, VRLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_rotlv)
838 TRANS_FLAGS(ALTIVEC, VRLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_rotlv)
839 TRANS_FLAGS2(ALTIVEC_207, VRLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_rotlv)
841 static TCGv_vec do_vrl_mask_vec(unsigned vece, TCGv_vec vrb)
843 TCGv_vec t0 = tcg_temp_new_vec_matching(vrb),
844 t1 = tcg_temp_new_vec_matching(vrb),
845 t2 = tcg_temp_new_vec_matching(vrb),
846 ones = tcg_constant_vec_matching(vrb, vece, -1);
848 /* Extract b and e */
849 tcg_gen_dupi_vec(vece, t2, (8 << vece) - 1);
851 tcg_gen_shri_vec(vece, t0, vrb, 16);
852 tcg_gen_and_vec(vece, t0, t0, t2);
854 tcg_gen_shri_vec(vece, t1, vrb, 8);
855 tcg_gen_and_vec(vece, t1, t1, t2);
857 /* Compare b and e to negate the mask where begin > end */
858 tcg_gen_cmp_vec(TCG_COND_GT, vece, t2, t0, t1);
860 /* Create the mask with (~0 >> b) ^ ((~0 >> e) >> 1) */
861 tcg_gen_shrv_vec(vece, t0, ones, t0);
862 tcg_gen_shrv_vec(vece, t1, ones, t1);
863 tcg_gen_shri_vec(vece, t1, t1, 1);
864 tcg_gen_xor_vec(vece, t0, t0, t1);
866 /* negate the mask */
867 tcg_gen_xor_vec(vece, t0, t0, t2);
869 tcg_temp_free_vec(t1);
870 tcg_temp_free_vec(t2);
875 static void gen_vrlnm_vec(unsigned vece, TCGv_vec vrt, TCGv_vec vra,
878 TCGv_vec mask, n = tcg_temp_new_vec_matching(vrt);
880 /* Create the mask */
881 mask = do_vrl_mask_vec(vece, vrb);
884 tcg_gen_dupi_vec(vece, n, (8 << vece) - 1);
885 tcg_gen_and_vec(vece, n, vrb, n);
887 /* Rotate and mask */
888 tcg_gen_rotlv_vec(vece, vrt, vra, n);
889 tcg_gen_and_vec(vece, vrt, vrt, mask);
891 tcg_temp_free_vec(n);
892 tcg_temp_free_vec(mask);
895 static bool do_vrlnm(DisasContext *ctx, arg_VX *a, int vece)
897 static const TCGOpcode vecop_list[] = {
898 INDEX_op_cmp_vec, INDEX_op_rotlv_vec, INDEX_op_sari_vec,
899 INDEX_op_shli_vec, INDEX_op_shri_vec, INDEX_op_shrv_vec, 0
901 static const GVecGen3 ops[2] = {
903 .fniv = gen_vrlnm_vec,
904 .fno = gen_helper_VRLWNM,
905 .opt_opc = vecop_list,
910 .fniv = gen_vrlnm_vec,
911 .fno = gen_helper_VRLDNM,
912 .opt_opc = vecop_list,
918 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
921 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
922 avr_full_offset(a->vrb), 16, 16, &ops[vece - 2]);
927 TRANS(VRLWNM, do_vrlnm, MO_32)
928 TRANS(VRLDNM, do_vrlnm, MO_64)
930 static void gen_vrlmi_vec(unsigned vece, TCGv_vec vrt, TCGv_vec vra,
933 TCGv_vec mask, n = tcg_temp_new_vec_matching(vrt),
934 tmp = tcg_temp_new_vec_matching(vrt);
936 /* Create the mask */
937 mask = do_vrl_mask_vec(vece, vrb);
940 tcg_gen_dupi_vec(vece, n, (8 << vece) - 1);
941 tcg_gen_and_vec(vece, n, vrb, n);
943 /* Rotate and insert */
944 tcg_gen_rotlv_vec(vece, tmp, vra, n);
945 tcg_gen_bitsel_vec(vece, vrt, mask, tmp, vrt);
947 tcg_temp_free_vec(n);
948 tcg_temp_free_vec(tmp);
949 tcg_temp_free_vec(mask);
952 static bool do_vrlmi(DisasContext *ctx, arg_VX *a, int vece)
954 static const TCGOpcode vecop_list[] = {
955 INDEX_op_cmp_vec, INDEX_op_rotlv_vec, INDEX_op_sari_vec,
956 INDEX_op_shli_vec, INDEX_op_shri_vec, INDEX_op_shrv_vec, 0
958 static const GVecGen3 ops[2] = {
960 .fniv = gen_vrlmi_vec,
961 .fno = gen_helper_VRLWMI,
962 .opt_opc = vecop_list,
967 .fniv = gen_vrlnm_vec,
968 .fno = gen_helper_VRLDMI,
969 .opt_opc = vecop_list,
975 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
978 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
979 avr_full_offset(a->vrb), 16, 16, &ops[vece - 2]);
984 TRANS(VRLWMI, do_vrlmi, MO_32)
985 TRANS(VRLDMI, do_vrlmi, MO_64)
987 static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right,
990 TCGv_i64 hi, lo, t0, t1, n, zero = tcg_constant_i64(0);
994 n = tcg_temp_new_i64();
995 hi = tcg_temp_new_i64();
996 lo = tcg_temp_new_i64();
997 t0 = tcg_temp_new_i64();
998 t1 = tcg_const_i64(0);
1000 get_avr64(lo, a->vra, false);
1001 get_avr64(hi, a->vra, true);
1003 get_avr64(n, a->vrb, true);
1005 tcg_gen_andi_i64(t0, n, 64);
1007 tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, hi, lo);
1009 tcg_gen_sari_i64(t1, lo, 63);
1011 tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, t1, hi);
1013 tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, lo, hi);
1014 tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, zero, lo);
1016 tcg_gen_andi_i64(n, n, 0x3F);
1020 tcg_gen_sar_i64(t0, hi, n);
1022 tcg_gen_shr_i64(t0, hi, n);
1025 tcg_gen_shl_i64(t0, lo, n);
1027 set_avr64(a->vrt, t0, right);
1030 tcg_gen_shr_i64(lo, lo, n);
1032 tcg_gen_shl_i64(hi, hi, n);
1034 tcg_gen_xori_i64(n, n, 63);
1036 tcg_gen_shl_i64(hi, hi, n);
1037 tcg_gen_shli_i64(hi, hi, 1);
1039 tcg_gen_shr_i64(lo, lo, n);
1040 tcg_gen_shri_i64(lo, lo, 1);
1042 tcg_gen_or_i64(hi, hi, lo);
1043 set_avr64(a->vrt, hi, !right);
1045 tcg_temp_free_i64(hi);
1046 tcg_temp_free_i64(lo);
1047 tcg_temp_free_i64(t0);
1048 tcg_temp_free_i64(t1);
1049 tcg_temp_free_i64(n);
1054 TRANS_FLAGS2(ISA310, VSLQ, do_vector_shift_quad, false, false);
1055 TRANS_FLAGS2(ISA310, VSRQ, do_vector_shift_quad, true, false);
1056 TRANS_FLAGS2(ISA310, VSRAQ, do_vector_shift_quad, true, true);
1058 static void do_vrlq_mask(TCGv_i64 mh, TCGv_i64 ml, TCGv_i64 b, TCGv_i64 e)
1060 TCGv_i64 th, tl, t0, t1, zero = tcg_constant_i64(0),
1061 ones = tcg_constant_i64(-1);
1063 th = tcg_temp_new_i64();
1064 tl = tcg_temp_new_i64();
1065 t0 = tcg_temp_new_i64();
1066 t1 = tcg_temp_new_i64();
1069 tcg_gen_andi_i64(t0, b, 64);
1070 tcg_gen_movcond_i64(TCG_COND_NE, t1, t0, zero, zero, ones);
1071 tcg_gen_andi_i64(t0, b, 0x3F);
1072 tcg_gen_shr_i64(mh, t1, t0);
1073 tcg_gen_shr_i64(ml, ones, t0);
1074 tcg_gen_xori_i64(t0, t0, 63);
1075 tcg_gen_shl_i64(t1, t1, t0);
1076 tcg_gen_shli_i64(t1, t1, 1);
1077 tcg_gen_or_i64(ml, t1, ml);
1080 tcg_gen_andi_i64(t0, e, 64);
1081 tcg_gen_movcond_i64(TCG_COND_NE, t1, t0, zero, zero, ones);
1082 tcg_gen_andi_i64(t0, e, 0x3F);
1083 tcg_gen_shr_i64(th, t1, t0);
1084 tcg_gen_shr_i64(tl, ones, t0);
1085 tcg_gen_xori_i64(t0, t0, 63);
1086 tcg_gen_shl_i64(t1, t1, t0);
1087 tcg_gen_shli_i64(t1, t1, 1);
1088 tcg_gen_or_i64(tl, t1, tl);
1091 tcg_gen_extract2_i64(tl, tl, th, 1);
1092 tcg_gen_shri_i64(th, th, 1);
1095 tcg_gen_xor_i64(mh, mh, th);
1096 tcg_gen_xor_i64(ml, ml, tl);
1098 /* Negate the mask if begin > end */
1099 tcg_gen_movcond_i64(TCG_COND_GT, t0, b, e, ones, zero);
1101 tcg_gen_xor_i64(mh, mh, t0);
1102 tcg_gen_xor_i64(ml, ml, t0);
1104 tcg_temp_free_i64(th);
1105 tcg_temp_free_i64(tl);
1106 tcg_temp_free_i64(t0);
1107 tcg_temp_free_i64(t1);
1110 static bool do_vector_rotl_quad(DisasContext *ctx, arg_VX *a, bool mask,
1113 TCGv_i64 ah, al, vrb, n, t0, t1, zero = tcg_constant_i64(0);
1115 REQUIRE_VECTOR(ctx);
1116 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1118 ah = tcg_temp_new_i64();
1119 al = tcg_temp_new_i64();
1120 vrb = tcg_temp_new_i64();
1121 n = tcg_temp_new_i64();
1122 t0 = tcg_temp_new_i64();
1123 t1 = tcg_temp_new_i64();
1125 get_avr64(ah, a->vra, true);
1126 get_avr64(al, a->vra, false);
1127 get_avr64(vrb, a->vrb, true);
1129 tcg_gen_mov_i64(t0, ah);
1130 tcg_gen_andi_i64(t1, vrb, 64);
1131 tcg_gen_movcond_i64(TCG_COND_NE, ah, t1, zero, al, ah);
1132 tcg_gen_movcond_i64(TCG_COND_NE, al, t1, zero, t0, al);
1133 tcg_gen_andi_i64(n, vrb, 0x3F);
1135 tcg_gen_shl_i64(t0, ah, n);
1136 tcg_gen_shl_i64(t1, al, n);
1138 tcg_gen_xori_i64(n, n, 63);
1140 tcg_gen_shr_i64(al, al, n);
1141 tcg_gen_shri_i64(al, al, 1);
1142 tcg_gen_or_i64(t0, al, t0);
1144 tcg_gen_shr_i64(ah, ah, n);
1145 tcg_gen_shri_i64(ah, ah, 1);
1146 tcg_gen_or_i64(t1, ah, t1);
1148 if (mask || insert) {
1149 tcg_gen_extract_i64(n, vrb, 8, 7);
1150 tcg_gen_extract_i64(vrb, vrb, 16, 7);
1152 do_vrlq_mask(ah, al, vrb, n);
1154 tcg_gen_and_i64(t0, t0, ah);
1155 tcg_gen_and_i64(t1, t1, al);
1158 get_avr64(n, a->vrt, true);
1159 get_avr64(vrb, a->vrt, false);
1160 tcg_gen_andc_i64(n, n, ah);
1161 tcg_gen_andc_i64(vrb, vrb, al);
1162 tcg_gen_or_i64(t0, t0, n);
1163 tcg_gen_or_i64(t1, t1, vrb);
1167 set_avr64(a->vrt, t0, true);
1168 set_avr64(a->vrt, t1, false);
1170 tcg_temp_free_i64(ah);
1171 tcg_temp_free_i64(al);
1172 tcg_temp_free_i64(vrb);
1173 tcg_temp_free_i64(n);
1174 tcg_temp_free_i64(t0);
1175 tcg_temp_free_i64(t1);
1180 TRANS(VRLQ, do_vector_rotl_quad, false, false)
1181 TRANS(VRLQNM, do_vector_rotl_quad, true, false)
1182 TRANS(VRLQMI, do_vector_rotl_quad, false, true)
1184 #define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
1185 static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
1186 TCGv_vec sat, TCGv_vec a, \
1189 TCGv_vec x = tcg_temp_new_vec_matching(t); \
1190 glue(glue(tcg_gen_, NORM), _vec)(VECE, x, a, b); \
1191 glue(glue(tcg_gen_, SAT), _vec)(VECE, t, a, b); \
1192 tcg_gen_cmp_vec(TCG_COND_NE, VECE, x, x, t); \
1193 tcg_gen_or_vec(VECE, sat, sat, x); \
1194 tcg_temp_free_vec(x); \
1196 static void glue(gen_, NAME)(DisasContext *ctx) \
1198 static const TCGOpcode vecop_list[] = { \
1199 glue(glue(INDEX_op_, NORM), _vec), \
1200 glue(glue(INDEX_op_, SAT), _vec), \
1201 INDEX_op_cmp_vec, 0 \
1203 static const GVecGen4 g = { \
1204 .fniv = glue(glue(gen_, NAME), _vec), \
1205 .fno = glue(gen_helper_, NAME), \
1206 .opt_opc = vecop_list, \
1207 .write_aofs = true, \
1210 if (unlikely(!ctx->altivec_enabled)) { \
1211 gen_exception(ctx, POWERPC_EXCP_VPU); \
1214 tcg_gen_gvec_4(avr_full_offset(rD(ctx->opcode)), \
1215 offsetof(CPUPPCState, vscr_sat), \
1216 avr_full_offset(rA(ctx->opcode)), \
1217 avr_full_offset(rB(ctx->opcode)), \
1221 GEN_VXFORM_SAT(vaddubs, MO_8, add, usadd, 0, 8);
1222 GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \
1223 vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800)
1224 GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9);
1225 GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \
1226 vmul10euq, PPC_NONE, PPC2_ISA300)
1227 GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10);
1228 GEN_VXFORM_SAT(vaddsbs, MO_8, add, ssadd, 0, 12);
1229 GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13);
1230 GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14);
1231 GEN_VXFORM_SAT(vsububs, MO_8, sub, ussub, 0, 24);
1232 GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25);
1233 GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);
1234 GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28);
1235 GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);
1236 GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);
1237 GEN_VXFORM(vadduqm, 0, 4);
1238 GEN_VXFORM(vaddcuq, 0, 5);
1239 GEN_VXFORM3(vaddeuqm, 30, 0);
1240 GEN_VXFORM3(vaddecuq, 30, 0);
1241 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
1242 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
1243 GEN_VXFORM(vsubuqm, 0, 20);
1244 GEN_VXFORM(vsubcuq, 0, 21);
1245 GEN_VXFORM3(vsubeuqm, 31, 0);
1246 GEN_VXFORM3(vsubecuq, 31, 0);
1247 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
1248 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
1249 GEN_VXFORM_TRANS(vsl, 2, 7);
1250 GEN_VXFORM_TRANS(vsr, 2, 11);
1251 GEN_VXFORM_ENV(vpkuhum, 7, 0);
1252 GEN_VXFORM_ENV(vpkuwum, 7, 1);
1253 GEN_VXFORM_ENV(vpkudum, 7, 17);
1254 GEN_VXFORM_ENV(vpkuhus, 7, 2);
1255 GEN_VXFORM_ENV(vpkuwus, 7, 3);
1256 GEN_VXFORM_ENV(vpkudus, 7, 19);
1257 GEN_VXFORM_ENV(vpkshus, 7, 4);
1258 GEN_VXFORM_ENV(vpkswus, 7, 5);
1259 GEN_VXFORM_ENV(vpksdus, 7, 21);
1260 GEN_VXFORM_ENV(vpkshss, 7, 6);
1261 GEN_VXFORM_ENV(vpkswss, 7, 7);
1262 GEN_VXFORM_ENV(vpksdss, 7, 23);
1263 GEN_VXFORM(vpkpx, 7, 12);
1264 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
1265 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
1266 GEN_VXFORM_ENV(vsum4shs, 4, 25);
1267 GEN_VXFORM_ENV(vsum2sws, 4, 26);
1268 GEN_VXFORM_ENV(vsumsws, 4, 30);
1269 GEN_VXFORM_ENV(vaddfp, 5, 0);
1270 GEN_VXFORM_ENV(vsubfp, 5, 1);
1271 GEN_VXFORM_ENV(vmaxfp, 5, 16);
1272 GEN_VXFORM_ENV(vminfp, 5, 17);
1273 GEN_VXFORM_HETRO(vextublx, 6, 24)
1274 GEN_VXFORM_HETRO(vextuhlx, 6, 25)
1275 GEN_VXFORM_HETRO(vextuwlx, 6, 26)
1276 GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
1277 vextuwlx, PPC_NONE, PPC2_ISA300)
1278 GEN_VXFORM_HETRO(vextubrx, 6, 28)
1279 GEN_VXFORM_HETRO(vextuhrx, 6, 29)
1280 GEN_VXFORM_HETRO(vextuwrx, 6, 30)
1281 GEN_VXFORM_TRANS(lvsl, 6, 31)
1282 GEN_VXFORM_TRANS(lvsr, 6, 32)
1283 GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207,
1284 vextuwrx, PPC_NONE, PPC2_ISA300)
1286 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
1287 static void glue(gen_, name)(DisasContext *ctx) \
1289 TCGv_ptr ra, rb, rd; \
1290 if (unlikely(!ctx->altivec_enabled)) { \
1291 gen_exception(ctx, POWERPC_EXCP_VPU); \
1294 ra = gen_avr_ptr(rA(ctx->opcode)); \
1295 rb = gen_avr_ptr(rB(ctx->opcode)); \
1296 rd = gen_avr_ptr(rD(ctx->opcode)); \
1297 gen_helper_##opname(cpu_env, rd, ra, rb); \
1298 tcg_temp_free_ptr(ra); \
1299 tcg_temp_free_ptr(rb); \
1300 tcg_temp_free_ptr(rd); \
1303 #define GEN_VXRFORM(name, opc2, opc3) \
1304 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
1305 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
1308 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
1309 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
1310 * come from different versions of the ISA, so we must also support a
1311 * pair of flags for each instruction.
1313 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
1314 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
1316 if ((Rc(ctx->opcode) == 0) && \
1317 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
1318 if (Rc21(ctx->opcode) == 0) { \
1321 gen_##name0##_(ctx); \
1323 } else if ((Rc(ctx->opcode) == 1) && \
1324 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
1325 if (Rc21(ctx->opcode) == 0) { \
1328 gen_##name1##_(ctx); \
1331 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
1335 static void do_vcmp_rc(int vrt)
1337 TCGv_i64 tmp, set, clr;
1339 tmp = tcg_temp_new_i64();
1340 set = tcg_temp_new_i64();
1341 clr = tcg_temp_new_i64();
1343 get_avr64(tmp, vrt, true);
1344 tcg_gen_mov_i64(set, tmp);
1345 get_avr64(tmp, vrt, false);
1346 tcg_gen_or_i64(clr, set, tmp);
1347 tcg_gen_and_i64(set, set, tmp);
1349 tcg_gen_setcondi_i64(TCG_COND_EQ, clr, clr, 0);
1350 tcg_gen_shli_i64(clr, clr, 1);
1352 tcg_gen_setcondi_i64(TCG_COND_EQ, set, set, -1);
1353 tcg_gen_shli_i64(set, set, 3);
1355 tcg_gen_or_i64(tmp, set, clr);
1356 tcg_gen_extrl_i64_i32(cpu_crf[6], tmp);
1358 tcg_temp_free_i64(tmp);
1359 tcg_temp_free_i64(set);
1360 tcg_temp_free_i64(clr);
1363 static bool do_vcmp(DisasContext *ctx, arg_VC *a, TCGCond cond, int vece)
1365 REQUIRE_VECTOR(ctx);
1367 tcg_gen_gvec_cmp(cond, vece, avr_full_offset(a->vrt),
1368 avr_full_offset(a->vra), avr_full_offset(a->vrb), 16, 16);
1377 TRANS_FLAGS(ALTIVEC, VCMPEQUB, do_vcmp, TCG_COND_EQ, MO_8)
1378 TRANS_FLAGS(ALTIVEC, VCMPEQUH, do_vcmp, TCG_COND_EQ, MO_16)
1379 TRANS_FLAGS(ALTIVEC, VCMPEQUW, do_vcmp, TCG_COND_EQ, MO_32)
1380 TRANS_FLAGS2(ALTIVEC_207, VCMPEQUD, do_vcmp, TCG_COND_EQ, MO_64)
1382 TRANS_FLAGS(ALTIVEC, VCMPGTSB, do_vcmp, TCG_COND_GT, MO_8)
1383 TRANS_FLAGS(ALTIVEC, VCMPGTSH, do_vcmp, TCG_COND_GT, MO_16)
1384 TRANS_FLAGS(ALTIVEC, VCMPGTSW, do_vcmp, TCG_COND_GT, MO_32)
1385 TRANS_FLAGS2(ALTIVEC_207, VCMPGTSD, do_vcmp, TCG_COND_GT, MO_64)
1386 TRANS_FLAGS(ALTIVEC, VCMPGTUB, do_vcmp, TCG_COND_GTU, MO_8)
1387 TRANS_FLAGS(ALTIVEC, VCMPGTUH, do_vcmp, TCG_COND_GTU, MO_16)
1388 TRANS_FLAGS(ALTIVEC, VCMPGTUW, do_vcmp, TCG_COND_GTU, MO_32)
1389 TRANS_FLAGS2(ALTIVEC_207, VCMPGTUD, do_vcmp, TCG_COND_GTU, MO_64)
1391 TRANS_FLAGS2(ISA300, VCMPNEB, do_vcmp, TCG_COND_NE, MO_8)
1392 TRANS_FLAGS2(ISA300, VCMPNEH, do_vcmp, TCG_COND_NE, MO_16)
1393 TRANS_FLAGS2(ISA300, VCMPNEW, do_vcmp, TCG_COND_NE, MO_32)
1395 static void gen_vcmpnez_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
1397 TCGv_vec t0, t1, zero;
1399 t0 = tcg_temp_new_vec_matching(t);
1400 t1 = tcg_temp_new_vec_matching(t);
1401 zero = tcg_constant_vec_matching(t, vece, 0);
1403 tcg_gen_cmp_vec(TCG_COND_EQ, vece, t0, a, zero);
1404 tcg_gen_cmp_vec(TCG_COND_EQ, vece, t1, b, zero);
1405 tcg_gen_cmp_vec(TCG_COND_NE, vece, t, a, b);
1407 tcg_gen_or_vec(vece, t, t, t0);
1408 tcg_gen_or_vec(vece, t, t, t1);
1410 tcg_temp_free_vec(t0);
1411 tcg_temp_free_vec(t1);
1414 static bool do_vcmpnez(DisasContext *ctx, arg_VC *a, int vece)
1416 static const TCGOpcode vecop_list[] = {
1419 static const GVecGen3 ops[3] = {
1421 .fniv = gen_vcmpnez_vec,
1422 .fno = gen_helper_VCMPNEZB,
1423 .opt_opc = vecop_list,
1427 .fniv = gen_vcmpnez_vec,
1428 .fno = gen_helper_VCMPNEZH,
1429 .opt_opc = vecop_list,
1433 .fniv = gen_vcmpnez_vec,
1434 .fno = gen_helper_VCMPNEZW,
1435 .opt_opc = vecop_list,
1440 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
1441 REQUIRE_VECTOR(ctx);
1443 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
1444 avr_full_offset(a->vrb), 16, 16, &ops[vece]);
1453 TRANS(VCMPNEZB, do_vcmpnez, MO_8)
1454 TRANS(VCMPNEZH, do_vcmpnez, MO_16)
1455 TRANS(VCMPNEZW, do_vcmpnez, MO_32)
1457 static bool trans_VCMPEQUQ(DisasContext *ctx, arg_VC *a)
1459 TCGv_i64 t0, t1, t2;
1461 t0 = tcg_temp_new_i64();
1462 t1 = tcg_temp_new_i64();
1463 t2 = tcg_temp_new_i64();
1465 get_avr64(t0, a->vra, true);
1466 get_avr64(t1, a->vrb, true);
1467 tcg_gen_xor_i64(t2, t0, t1);
1469 get_avr64(t0, a->vra, false);
1470 get_avr64(t1, a->vrb, false);
1471 tcg_gen_xor_i64(t1, t0, t1);
1473 tcg_gen_or_i64(t1, t1, t2);
1474 tcg_gen_setcondi_i64(TCG_COND_EQ, t1, t1, 0);
1475 tcg_gen_neg_i64(t1, t1);
1477 set_avr64(a->vrt, t1, true);
1478 set_avr64(a->vrt, t1, false);
1481 tcg_gen_extrl_i64_i32(cpu_crf[6], t1);
1482 tcg_gen_andi_i32(cpu_crf[6], cpu_crf[6], 0xa);
1483 tcg_gen_xori_i32(cpu_crf[6], cpu_crf[6], 0x2);
1486 tcg_temp_free_i64(t0);
1487 tcg_temp_free_i64(t1);
1488 tcg_temp_free_i64(t2);
1493 static bool do_vcmpgtq(DisasContext *ctx, arg_VC *a, bool sign)
1495 TCGv_i64 t0, t1, t2;
1497 t0 = tcg_temp_new_i64();
1498 t1 = tcg_temp_new_i64();
1499 t2 = tcg_temp_new_i64();
1501 get_avr64(t0, a->vra, false);
1502 get_avr64(t1, a->vrb, false);
1503 tcg_gen_setcond_i64(TCG_COND_GTU, t2, t0, t1);
1505 get_avr64(t0, a->vra, true);
1506 get_avr64(t1, a->vrb, true);
1507 tcg_gen_movcond_i64(TCG_COND_EQ, t2, t0, t1, t2, tcg_constant_i64(0));
1508 tcg_gen_setcond_i64(sign ? TCG_COND_GT : TCG_COND_GTU, t1, t0, t1);
1510 tcg_gen_or_i64(t1, t1, t2);
1511 tcg_gen_neg_i64(t1, t1);
1513 set_avr64(a->vrt, t1, true);
1514 set_avr64(a->vrt, t1, false);
1517 tcg_gen_extrl_i64_i32(cpu_crf[6], t1);
1518 tcg_gen_andi_i32(cpu_crf[6], cpu_crf[6], 0xa);
1519 tcg_gen_xori_i32(cpu_crf[6], cpu_crf[6], 0x2);
1522 tcg_temp_free_i64(t0);
1523 tcg_temp_free_i64(t1);
1524 tcg_temp_free_i64(t2);
1529 TRANS(VCMPGTSQ, do_vcmpgtq, true)
1530 TRANS(VCMPGTUQ, do_vcmpgtq, false)
1532 static bool do_vcmpq(DisasContext *ctx, arg_VX_bf *a, bool sign)
1535 TCGLabel *gt, *lt, *done;
1537 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1538 REQUIRE_VECTOR(ctx);
1540 vra = tcg_temp_local_new_i64();
1541 vrb = tcg_temp_local_new_i64();
1542 gt = gen_new_label();
1543 lt = gen_new_label();
1544 done = gen_new_label();
1546 get_avr64(vra, a->vra, true);
1547 get_avr64(vrb, a->vrb, true);
1548 tcg_gen_brcond_i64((sign ? TCG_COND_GT : TCG_COND_GTU), vra, vrb, gt);
1549 tcg_gen_brcond_i64((sign ? TCG_COND_LT : TCG_COND_LTU), vra, vrb, lt);
1551 get_avr64(vra, a->vra, false);
1552 get_avr64(vrb, a->vrb, false);
1553 tcg_gen_brcond_i64(TCG_COND_GTU, vra, vrb, gt);
1554 tcg_gen_brcond_i64(TCG_COND_LTU, vra, vrb, lt);
1556 tcg_gen_movi_i32(cpu_crf[a->bf], CRF_EQ);
1560 tcg_gen_movi_i32(cpu_crf[a->bf], CRF_GT);
1564 tcg_gen_movi_i32(cpu_crf[a->bf], CRF_LT);
1567 gen_set_label(done);
1568 tcg_temp_free_i64(vra);
1569 tcg_temp_free_i64(vrb);
1574 TRANS(VCMPSQ, do_vcmpq, true)
1575 TRANS(VCMPUQ, do_vcmpq, false)
1577 GEN_VXRFORM(vcmpeqfp, 3, 3)
1578 GEN_VXRFORM(vcmpgefp, 3, 7)
1579 GEN_VXRFORM(vcmpgtfp, 3, 11)
1580 GEN_VXRFORM(vcmpbfp, 3, 15)
1582 static void gen_vsplti(DisasContext *ctx, int vece)
1586 if (unlikely(!ctx->altivec_enabled)) {
1587 gen_exception(ctx, POWERPC_EXCP_VPU);
1591 simm = SIMM5(ctx->opcode);
1592 tcg_gen_gvec_dup_imm(vece, avr_full_offset(rD(ctx->opcode)), 16, 16, simm);
1595 #define GEN_VXFORM_VSPLTI(name, vece, opc2, opc3) \
1596 static void glue(gen_, name)(DisasContext *ctx) { gen_vsplti(ctx, vece); }
1598 GEN_VXFORM_VSPLTI(vspltisb, MO_8, 6, 12);
1599 GEN_VXFORM_VSPLTI(vspltish, MO_16, 6, 13);
1600 GEN_VXFORM_VSPLTI(vspltisw, MO_32, 6, 14);
1602 #define GEN_VXFORM_NOA(name, opc2, opc3) \
1603 static void glue(gen_, name)(DisasContext *ctx) \
1606 if (unlikely(!ctx->altivec_enabled)) { \
1607 gen_exception(ctx, POWERPC_EXCP_VPU); \
1610 rb = gen_avr_ptr(rB(ctx->opcode)); \
1611 rd = gen_avr_ptr(rD(ctx->opcode)); \
1612 gen_helper_##name(rd, rb); \
1613 tcg_temp_free_ptr(rb); \
1614 tcg_temp_free_ptr(rd); \
1617 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
1618 static void glue(gen_, name)(DisasContext *ctx) \
1622 if (unlikely(!ctx->altivec_enabled)) { \
1623 gen_exception(ctx, POWERPC_EXCP_VPU); \
1626 rb = gen_avr_ptr(rB(ctx->opcode)); \
1627 rd = gen_avr_ptr(rD(ctx->opcode)); \
1628 gen_helper_##name(cpu_env, rd, rb); \
1629 tcg_temp_free_ptr(rb); \
1630 tcg_temp_free_ptr(rd); \
1633 #define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \
1634 static void glue(gen_, name)(DisasContext *ctx) \
1637 if (unlikely(!ctx->altivec_enabled)) { \
1638 gen_exception(ctx, POWERPC_EXCP_VPU); \
1641 rb = gen_avr_ptr(rB(ctx->opcode)); \
1642 rd = gen_avr_ptr(rD(ctx->opcode)); \
1643 gen_helper_##name(rd, rb); \
1644 tcg_temp_free_ptr(rb); \
1645 tcg_temp_free_ptr(rd); \
1648 #define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \
1649 static void glue(gen_, name)(DisasContext *ctx) \
1652 if (unlikely(!ctx->altivec_enabled)) { \
1653 gen_exception(ctx, POWERPC_EXCP_VPU); \
1656 rb = gen_avr_ptr(rB(ctx->opcode)); \
1657 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \
1658 tcg_temp_free_ptr(rb); \
1660 GEN_VXFORM_NOA(vupkhsb, 7, 8);
1661 GEN_VXFORM_NOA(vupkhsh, 7, 9);
1662 GEN_VXFORM_NOA(vupkhsw, 7, 25);
1663 GEN_VXFORM_NOA(vupklsb, 7, 10);
1664 GEN_VXFORM_NOA(vupklsh, 7, 11);
1665 GEN_VXFORM_NOA(vupklsw, 7, 27);
1666 GEN_VXFORM_NOA(vupkhpx, 7, 13);
1667 GEN_VXFORM_NOA(vupklpx, 7, 15);
1668 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
1669 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
1670 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
1671 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
1672 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
1673 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
1674 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
1675 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
1676 GEN_VXFORM_NOA(vprtybw, 1, 24);
1677 GEN_VXFORM_NOA(vprtybd, 1, 24);
1678 GEN_VXFORM_NOA(vprtybq, 1, 24);
1680 static void gen_vsplt(DisasContext *ctx, int vece)
1682 int uimm, dofs, bofs;
1684 if (unlikely(!ctx->altivec_enabled)) {
1685 gen_exception(ctx, POWERPC_EXCP_VPU);
1689 uimm = UIMM5(ctx->opcode);
1690 bofs = avr_full_offset(rB(ctx->opcode));
1691 dofs = avr_full_offset(rD(ctx->opcode));
1693 /* Experimental testing shows that hardware masks the immediate. */
1694 bofs += (uimm << vece) & 15;
1695 #if !HOST_BIG_ENDIAN
1697 bofs &= ~((1 << vece) - 1);
1700 tcg_gen_gvec_dup_mem(vece, dofs, bofs, 16, 16);
1703 #define GEN_VXFORM_VSPLT(name, vece, opc2, opc3) \
1704 static void glue(gen_, name)(DisasContext *ctx) { gen_vsplt(ctx, vece); }
1706 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
1707 static void glue(gen_, name)(DisasContext *ctx) \
1712 if (unlikely(!ctx->altivec_enabled)) { \
1713 gen_exception(ctx, POWERPC_EXCP_VPU); \
1716 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
1717 rb = gen_avr_ptr(rB(ctx->opcode)); \
1718 rd = gen_avr_ptr(rD(ctx->opcode)); \
1719 gen_helper_##name(cpu_env, rd, rb, uimm); \
1720 tcg_temp_free_i32(uimm); \
1721 tcg_temp_free_ptr(rb); \
1722 tcg_temp_free_ptr(rd); \
1725 #define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \
1726 static void glue(gen_, name)(DisasContext *ctx) \
1729 uint8_t uimm = UIMM4(ctx->opcode); \
1731 if (unlikely(!ctx->altivec_enabled)) { \
1732 gen_exception(ctx, POWERPC_EXCP_VPU); \
1735 if (uimm > splat_max) { \
1738 t0 = tcg_temp_new_i32(); \
1739 tcg_gen_movi_i32(t0, uimm); \
1740 rb = gen_avr_ptr(rB(ctx->opcode)); \
1741 rd = gen_avr_ptr(rD(ctx->opcode)); \
1742 gen_helper_##name(rd, rb, t0); \
1743 tcg_temp_free_i32(t0); \
1744 tcg_temp_free_ptr(rb); \
1745 tcg_temp_free_ptr(rd); \
1748 GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8);
1749 GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9);
1750 GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10);
1751 GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);
1752 GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);
1753 GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);
1754 GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8);
1755 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
1756 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
1757 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
1758 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
1759 GEN_VXFORM_DUAL(vspltb, PPC_ALTIVEC, PPC_NONE,
1760 vextractub, PPC_NONE, PPC2_ISA300);
1761 GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
1762 vextractuh, PPC_NONE, PPC2_ISA300);
1763 GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
1764 vextractuw, PPC_NONE, PPC2_ISA300);
1766 static bool trans_VGNB(DisasContext *ctx, arg_VX_n *a)
1769 * Similar to do_vextractm, we'll use a sequence of mask-shift-or operations
1770 * to gather the bits. The masks can be created with
1772 * uint64_t mask(uint64_t n, uint64_t step)
1774 * uint64_t p = ((1UL << (1UL << step)) - 1UL) << ((n - 1UL) << step),
1775 * plen = n << step, m = 0;
1776 * for(int i = 0; i < 64/plen; i++) {
1778 * m = ror64(m, plen);
1780 * p >>= plen * DIV_ROUND_UP(64, plen) - 64;
1784 * But since there are few values of N, we'll use a lookup table to avoid
1785 * these calculations at runtime.
1787 static const uint64_t mask[6][5] = {
1789 0xAAAAAAAAAAAAAAAAULL, 0xccccccccccccccccULL, 0xf0f0f0f0f0f0f0f0ULL,
1790 0xff00ff00ff00ff00ULL, 0xffff0000ffff0000ULL
1793 0x9249249249249249ULL, 0xC30C30C30C30C30CULL, 0xF00F00F00F00F00FULL,
1794 0xFF0000FF0000FF00ULL, 0xFFFF00000000FFFFULL
1797 /* For N >= 4, some mask operations can be elided */
1798 0x8888888888888888ULL, 0, 0xf000f000f000f000ULL, 0,
1799 0xFFFF000000000000ULL
1802 0x8421084210842108ULL, 0, 0xF0000F0000F0000FULL, 0, 0
1805 0x8208208208208208ULL, 0, 0xF00000F00000F000ULL, 0, 0
1808 0x8102040810204081ULL, 0, 0xF000000F000000F0ULL, 0, 0
1812 int i, sh, nbits = DIV_ROUND_UP(64, a->n);
1813 TCGv_i64 hi, lo, t0, t1;
1815 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1816 REQUIRE_VECTOR(ctx);
1820 * "N can be any value between 2 and 7, inclusive." Otherwise, the
1821 * result is undefined, so we don't need to change RT. Also, N > 7 is
1822 * impossible since the immediate field is 3 bits only.
1827 hi = tcg_temp_new_i64();
1828 lo = tcg_temp_new_i64();
1829 t0 = tcg_temp_new_i64();
1830 t1 = tcg_temp_new_i64();
1832 get_avr64(hi, a->vrb, true);
1833 get_avr64(lo, a->vrb, false);
1835 /* Align the lower doubleword so we can use the same mask */
1836 tcg_gen_shli_i64(lo, lo, a->n * nbits - 64);
1839 * Starting from the most significant bit, gather every Nth bit with a
1840 * sequence of mask-shift-or operation. E.g.: for N=3
1841 * AxxBxxCxxDxxExxFxxGxxHxxIxxJxxKxxLxxMxxNxxOxxPxxQxxRxxSxxTxxUxxV
1843 * A..B..C..D..E..F..G..H..I..J..K..L..M..N..O..P..Q..R..S..T..U..V
1845 * .B..C..D..E..F..G..H..I..J..K..L..M..N..O..P..Q..R..S..T..U..V..
1847 * AB.BC.CD.DE.EF.FG.GH.HI.IJ.JK.KL.LM.MN.NO.OP.PQ.QR.RS.ST.TU.UV.V
1849 * AB....CD....EF....GH....IJ....KL....MN....OP....QR....ST....UV..
1851 * ..CD....EF....GH....IJ....KL....MN....OP....QR....ST....UV......
1853 * ABCD..CDEF..EFGH..GHIJ..IJKL..KLMN..MNOP..OPQR..QRST..STUV..UV..
1854 * & rep(0b111100000000)
1855 * ABCD........EFGH........IJKL........MNOP........QRST........UV..
1857 * ....EFGH........IJKL........MNOP........QRST........UV..........
1859 * ABCDEFGH....EFGHIJKL....IJKLMNOP....MNOPQRST....QRSTUV......UV..
1860 * & rep(0b111111110000000000000000)
1861 * ABCDEFGH................IJKLMNOP................QRSTUV..........
1863 * ........IJKLMNOP................QRSTUV..........................
1865 * ABCDEFGHIJKLMNOP........IJKLMNOPQRSTUV..........QRSTUV..........
1866 * & rep(0b111111111111111100000000000000000000000000000000)
1867 * ABCDEFGHIJKLMNOP................................QRSTUV..........
1869 * ................QRSTUV..........................................
1871 * ABCDEFGHIJKLMNOPQRSTUV..........................QRSTUV..........
1873 for (i = 0, sh = a->n - 1; i < 5; i++, sh <<= 1) {
1874 m = mask[a->n - 2][i];
1876 tcg_gen_andi_i64(hi, hi, m);
1877 tcg_gen_andi_i64(lo, lo, m);
1880 tcg_gen_shli_i64(t0, hi, sh);
1881 tcg_gen_shli_i64(t1, lo, sh);
1882 tcg_gen_or_i64(hi, t0, hi);
1883 tcg_gen_or_i64(lo, t1, lo);
1887 tcg_gen_andi_i64(hi, hi, ~(~0ULL >> nbits));
1888 tcg_gen_andi_i64(lo, lo, ~(~0ULL >> nbits));
1889 tcg_gen_shri_i64(lo, lo, nbits);
1890 tcg_gen_or_i64(hi, hi, lo);
1891 tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], hi);
1893 tcg_temp_free_i64(hi);
1894 tcg_temp_free_i64(lo);
1895 tcg_temp_free_i64(t0);
1896 tcg_temp_free_i64(t1);
1901 static bool do_vextdx(DisasContext *ctx, arg_VA *a, int size, bool right,
1902 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv))
1904 TCGv_ptr vrt, vra, vrb;
1907 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1908 REQUIRE_VECTOR(ctx);
1910 vrt = gen_avr_ptr(a->vrt);
1911 vra = gen_avr_ptr(a->vra);
1912 vrb = gen_avr_ptr(a->vrb);
1913 rc = tcg_temp_new();
1915 tcg_gen_andi_tl(rc, cpu_gpr[a->rc], 0x1F);
1917 tcg_gen_subfi_tl(rc, 32 - size, rc);
1919 gen_helper(cpu_env, vrt, vra, vrb, rc);
1921 tcg_temp_free_ptr(vrt);
1922 tcg_temp_free_ptr(vra);
1923 tcg_temp_free_ptr(vrb);
1928 TRANS(VEXTDUBVLX, do_vextdx, 1, false, gen_helper_VEXTDUBVLX)
1929 TRANS(VEXTDUHVLX, do_vextdx, 2, false, gen_helper_VEXTDUHVLX)
1930 TRANS(VEXTDUWVLX, do_vextdx, 4, false, gen_helper_VEXTDUWVLX)
1931 TRANS(VEXTDDVLX, do_vextdx, 8, false, gen_helper_VEXTDDVLX)
1933 TRANS(VEXTDUBVRX, do_vextdx, 1, true, gen_helper_VEXTDUBVLX)
1934 TRANS(VEXTDUHVRX, do_vextdx, 2, true, gen_helper_VEXTDUHVLX)
1935 TRANS(VEXTDUWVRX, do_vextdx, 4, true, gen_helper_VEXTDUWVLX)
1936 TRANS(VEXTDDVRX, do_vextdx, 8, true, gen_helper_VEXTDDVLX)
1938 static bool do_vinsx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
1939 TCGv_i64 rb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1944 t = gen_avr_ptr(vrt);
1945 idx = tcg_temp_new();
1947 tcg_gen_andi_tl(idx, ra, 0xF);
1949 tcg_gen_subfi_tl(idx, 16 - size, idx);
1952 gen_helper(cpu_env, t, rb, idx);
1954 tcg_temp_free_ptr(t);
1960 static bool do_vinsvx(DisasContext *ctx, int vrt, int size, bool right, TCGv ra,
1961 int vrb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1966 val = tcg_temp_new_i64();
1967 get_avr64(val, vrb, true);
1968 ok = do_vinsx(ctx, vrt, size, right, ra, val, gen_helper);
1970 tcg_temp_free_i64(val);
1974 static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
1975 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1980 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1981 REQUIRE_VECTOR(ctx);
1983 val = tcg_temp_new_i64();
1984 tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]);
1986 ok = do_vinsx(ctx, a->vrt, size, right, cpu_gpr[a->vra], val, gen_helper);
1988 tcg_temp_free_i64(val);
1992 static bool do_vinsvx_VX(DisasContext *ctx, arg_VX *a, int size, bool right,
1993 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
1995 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
1996 REQUIRE_VECTOR(ctx);
1998 return do_vinsvx(ctx, a->vrt, size, right, cpu_gpr[a->vra], a->vrb,
2002 static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
2003 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
2008 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2009 REQUIRE_VECTOR(ctx);
2011 if (a->uim > (16 - size)) {
2013 * PowerISA v3.1 says that the resulting value is undefined in this
2014 * case, so just log a guest error and leave VRT unchanged. The
2015 * real hardware would do a partial insert, e.g. if VRT is zeroed and
2016 * RB is 0x12345678, executing "vinsw VRT,RB,14" results in
2017 * VRT = 0x0000...00001234, but we don't bother to reproduce this
2018 * behavior as software shouldn't rely on it.
2020 qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINS* at"
2021 " 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
2026 val = tcg_temp_new_i64();
2027 tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]);
2029 ok = do_vinsx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), val,
2032 tcg_temp_free_i64(val);
2036 static bool do_vinsert_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size,
2037 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv))
2039 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
2040 REQUIRE_VECTOR(ctx);
2042 if (a->uim > (16 - size)) {
2043 qemu_log_mask(LOG_GUEST_ERROR, "Invalid index for VINSERT* at"
2044 " 0x" TARGET_FMT_lx ", UIM = %d > %d\n", ctx->cia, a->uim,
2049 return do_vinsvx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), a->vrb,
2053 TRANS(VINSBLX, do_vinsx_VX, 1, false, gen_helper_VINSBLX)
2054 TRANS(VINSHLX, do_vinsx_VX, 2, false, gen_helper_VINSHLX)
2055 TRANS(VINSWLX, do_vinsx_VX, 4, false, gen_helper_VINSWLX)
2056 TRANS(VINSDLX, do_vinsx_VX, 8, false, gen_helper_VINSDLX)
2058 TRANS(VINSBRX, do_vinsx_VX, 1, true, gen_helper_VINSBLX)
2059 TRANS(VINSHRX, do_vinsx_VX, 2, true, gen_helper_VINSHLX)
2060 TRANS(VINSWRX, do_vinsx_VX, 4, true, gen_helper_VINSWLX)
2061 TRANS(VINSDRX, do_vinsx_VX, 8, true, gen_helper_VINSDLX)
2063 TRANS(VINSW, do_vins_VX_uim4, 4, gen_helper_VINSWLX)
2064 TRANS(VINSD, do_vins_VX_uim4, 8, gen_helper_VINSDLX)
2066 TRANS(VINSBVLX, do_vinsvx_VX, 1, false, gen_helper_VINSBLX)
2067 TRANS(VINSHVLX, do_vinsvx_VX, 2, false, gen_helper_VINSHLX)
2068 TRANS(VINSWVLX, do_vinsvx_VX, 4, false, gen_helper_VINSWLX)
2070 TRANS(VINSBVRX, do_vinsvx_VX, 1, true, gen_helper_VINSBLX)
2071 TRANS(VINSHVRX, do_vinsvx_VX, 2, true, gen_helper_VINSHLX)
2072 TRANS(VINSWVRX, do_vinsvx_VX, 4, true, gen_helper_VINSWLX)
2074 TRANS(VINSERTB, do_vinsert_VX_uim4, 1, gen_helper_VINSBLX)
2075 TRANS(VINSERTH, do_vinsert_VX_uim4, 2, gen_helper_VINSHLX)
2076 TRANS(VINSERTW, do_vinsert_VX_uim4, 4, gen_helper_VINSWLX)
2077 TRANS(VINSERTD, do_vinsert_VX_uim4, 8, gen_helper_VINSDLX)
2079 static void gen_vsldoi(DisasContext *ctx)
2081 TCGv_ptr ra, rb, rd;
2083 if (unlikely(!ctx->altivec_enabled)) {
2084 gen_exception(ctx, POWERPC_EXCP_VPU);
2087 ra = gen_avr_ptr(rA(ctx->opcode));
2088 rb = gen_avr_ptr(rB(ctx->opcode));
2089 rd = gen_avr_ptr(rD(ctx->opcode));
2090 sh = tcg_const_i32(VSH(ctx->opcode));
2091 gen_helper_vsldoi(rd, ra, rb, sh);
2092 tcg_temp_free_ptr(ra);
2093 tcg_temp_free_ptr(rb);
2094 tcg_temp_free_ptr(rd);
2095 tcg_temp_free_i32(sh);
2098 static bool trans_VSLDBI(DisasContext *ctx, arg_VN *a)
2100 TCGv_i64 t0, t1, t2;
2102 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2103 REQUIRE_VECTOR(ctx);
2105 t0 = tcg_temp_new_i64();
2106 t1 = tcg_temp_new_i64();
2108 get_avr64(t0, a->vra, true);
2109 get_avr64(t1, a->vra, false);
2112 t2 = tcg_temp_new_i64();
2114 get_avr64(t2, a->vrb, true);
2116 tcg_gen_extract2_i64(t0, t1, t0, 64 - a->sh);
2117 tcg_gen_extract2_i64(t1, t2, t1, 64 - a->sh);
2119 tcg_temp_free_i64(t2);
2122 set_avr64(a->vrt, t0, true);
2123 set_avr64(a->vrt, t1, false);
2125 tcg_temp_free_i64(t0);
2126 tcg_temp_free_i64(t1);
2131 static bool trans_VSRDBI(DisasContext *ctx, arg_VN *a)
2133 TCGv_i64 t2, t1, t0;
2135 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2136 REQUIRE_VECTOR(ctx);
2138 t0 = tcg_temp_new_i64();
2139 t1 = tcg_temp_new_i64();
2141 get_avr64(t0, a->vrb, false);
2142 get_avr64(t1, a->vrb, true);
2145 t2 = tcg_temp_new_i64();
2147 get_avr64(t2, a->vra, false);
2149 tcg_gen_extract2_i64(t0, t0, t1, a->sh);
2150 tcg_gen_extract2_i64(t1, t1, t2, a->sh);
2152 tcg_temp_free_i64(t2);
2155 set_avr64(a->vrt, t0, false);
2156 set_avr64(a->vrt, t1, true);
2158 tcg_temp_free_i64(t0);
2159 tcg_temp_free_i64(t1);
2164 static bool do_vexpand(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
2166 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2167 REQUIRE_VECTOR(ctx);
2169 tcg_gen_gvec_sari(vece, avr_full_offset(a->vrt), avr_full_offset(a->vrb),
2170 (8 << vece) - 1, 16, 16);
2175 TRANS(VEXPANDBM, do_vexpand, MO_8)
2176 TRANS(VEXPANDHM, do_vexpand, MO_16)
2177 TRANS(VEXPANDWM, do_vexpand, MO_32)
2178 TRANS(VEXPANDDM, do_vexpand, MO_64)
2180 static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a)
2184 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2185 REQUIRE_VECTOR(ctx);
2187 tmp = tcg_temp_new_i64();
2189 get_avr64(tmp, a->vrb, true);
2190 tcg_gen_sari_i64(tmp, tmp, 63);
2191 set_avr64(a->vrt, tmp, false);
2192 set_avr64(a->vrt, tmp, true);
2194 tcg_temp_free_i64(tmp);
2198 static bool do_vextractm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
2200 const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece,
2201 mask = dup_const(vece, 1 << (elem_width - 1));
2203 TCGv_i64 lo, hi, t0, t1;
2205 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2206 REQUIRE_VECTOR(ctx);
2208 hi = tcg_temp_new_i64();
2209 lo = tcg_temp_new_i64();
2210 t0 = tcg_temp_new_i64();
2211 t1 = tcg_temp_new_i64();
2213 get_avr64(lo, a->vrb, false);
2214 get_avr64(hi, a->vrb, true);
2216 tcg_gen_andi_i64(lo, lo, mask);
2217 tcg_gen_andi_i64(hi, hi, mask);
2220 * Gather the most significant bit of each element in the highest element
2221 * element. E.g. for bytes:
2222 * aXXXXXXXbXXXXXXXcXXXXXXXdXXXXXXXeXXXXXXXfXXXXXXXgXXXXXXXhXXXXXXX
2223 * & dup(1 << (elem_width - 1))
2224 * a0000000b0000000c0000000d0000000e0000000f0000000g0000000h0000000
2226 * 0000e0000000f0000000g0000000h00000000000000000000000000000000000
2228 * a000e000b000f000c000g000d000h000e0000000f0000000g0000000h0000000
2230 * 00c000g000d000h000e0000000f0000000g0000000h000000000000000000000
2232 * a0c0e0g0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h0000000
2234 * 0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h00000000000000
2236 * abcdefghbcdefgh0cdefgh00defgh000efgh0000fgh00000gh000000h0000000
2238 for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) {
2239 tcg_gen_shli_i64(t0, hi, j - i);
2240 tcg_gen_shli_i64(t1, lo, j - i);
2241 tcg_gen_or_i64(hi, hi, t0);
2242 tcg_gen_or_i64(lo, lo, t1);
2245 tcg_gen_shri_i64(hi, hi, 64 - elem_count_half);
2246 tcg_gen_extract2_i64(lo, lo, hi, 64 - elem_count_half);
2247 tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], lo);
2249 tcg_temp_free_i64(hi);
2250 tcg_temp_free_i64(lo);
2251 tcg_temp_free_i64(t0);
2252 tcg_temp_free_i64(t1);
2257 TRANS(VEXTRACTBM, do_vextractm, MO_8)
2258 TRANS(VEXTRACTHM, do_vextractm, MO_16)
2259 TRANS(VEXTRACTWM, do_vextractm, MO_32)
2260 TRANS(VEXTRACTDM, do_vextractm, MO_64)
2262 static bool trans_VEXTRACTQM(DisasContext *ctx, arg_VX_tb *a)
2266 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2267 REQUIRE_VECTOR(ctx);
2269 tmp = tcg_temp_new_i64();
2271 get_avr64(tmp, a->vrb, true);
2272 tcg_gen_shri_i64(tmp, tmp, 63);
2273 tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], tmp);
2275 tcg_temp_free_i64(tmp);
2280 static bool do_mtvsrm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
2282 const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece;
2285 TCGv_i64 hi, lo, t0, t1;
2287 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2288 REQUIRE_VECTOR(ctx);
2290 hi = tcg_temp_new_i64();
2291 lo = tcg_temp_new_i64();
2292 t0 = tcg_temp_new_i64();
2293 t1 = tcg_temp_new_i64();
2295 tcg_gen_extu_tl_i64(t0, cpu_gpr[a->vrb]);
2296 tcg_gen_extract_i64(hi, t0, elem_count_half, elem_count_half);
2297 tcg_gen_extract_i64(lo, t0, 0, elem_count_half);
2300 * Spread the bits into their respective elements.
2302 * 00000000000000000000000000000000000000000000000000000000abcdefgh
2304 * 0000000000000000000000000000abcdefgh0000000000000000000000000000
2306 * 0000000000000000000000000000abcdefgh00000000000000000000abcdefgh
2308 * 00000000000000abcdefgh00000000000000000000abcdefgh00000000000000
2310 * 00000000000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh
2312 * 0000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh0000000
2314 * 0000000abcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgh
2316 * 0000000a0000000b0000000c0000000d0000000e0000000f0000000g0000000h
2318 * aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh
2320 for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) {
2321 tcg_gen_shli_i64(t0, hi, j - i);
2322 tcg_gen_shli_i64(t1, lo, j - i);
2323 tcg_gen_or_i64(hi, hi, t0);
2324 tcg_gen_or_i64(lo, lo, t1);
2327 c = dup_const(vece, 1);
2328 tcg_gen_andi_i64(hi, hi, c);
2329 tcg_gen_andi_i64(lo, lo, c);
2331 c = MAKE_64BIT_MASK(0, elem_width);
2332 tcg_gen_muli_i64(hi, hi, c);
2333 tcg_gen_muli_i64(lo, lo, c);
2335 set_avr64(a->vrt, lo, false);
2336 set_avr64(a->vrt, hi, true);
2338 tcg_temp_free_i64(hi);
2339 tcg_temp_free_i64(lo);
2340 tcg_temp_free_i64(t0);
2341 tcg_temp_free_i64(t1);
2346 TRANS(MTVSRBM, do_mtvsrm, MO_8)
2347 TRANS(MTVSRHM, do_mtvsrm, MO_16)
2348 TRANS(MTVSRWM, do_mtvsrm, MO_32)
2349 TRANS(MTVSRDM, do_mtvsrm, MO_64)
2351 static bool trans_MTVSRQM(DisasContext *ctx, arg_VX_tb *a)
2355 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2356 REQUIRE_VECTOR(ctx);
2358 tmp = tcg_temp_new_i64();
2360 tcg_gen_ext_tl_i64(tmp, cpu_gpr[a->vrb]);
2361 tcg_gen_sextract_i64(tmp, tmp, 0, 1);
2362 set_avr64(a->vrt, tmp, false);
2363 set_avr64(a->vrt, tmp, true);
2365 tcg_temp_free_i64(tmp);
2370 static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a)
2372 const uint64_t mask = dup_const(MO_8, 1);
2375 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2376 REQUIRE_VECTOR(ctx);
2378 hi = extract16(a->b, 8, 8);
2379 lo = extract16(a->b, 0, 8);
2381 for (int i = 4, j = 32; i > 0; i >>= 1, j >>= 1) {
2382 hi |= hi << (j - i);
2383 lo |= lo << (j - i);
2386 hi = (hi & mask) * 0xFF;
2387 lo = (lo & mask) * 0xFF;
2389 set_avr64(a->vrt, tcg_constant_i64(hi), true);
2390 set_avr64(a->vrt, tcg_constant_i64(lo), false);
2395 static bool do_vcntmb(DisasContext *ctx, arg_VX_mp *a, int vece)
2397 TCGv_i64 rt, vrb, mask;
2398 rt = tcg_const_i64(0);
2399 vrb = tcg_temp_new_i64();
2400 mask = tcg_constant_i64(dup_const(vece, 1ULL << ((8 << vece) - 1)));
2402 for (int i = 0; i < 2; i++) {
2403 get_avr64(vrb, a->vrb, i);
2405 tcg_gen_and_i64(vrb, mask, vrb);
2407 tcg_gen_andc_i64(vrb, mask, vrb);
2409 tcg_gen_ctpop_i64(vrb, vrb);
2410 tcg_gen_add_i64(rt, rt, vrb);
2413 tcg_gen_shli_i64(rt, rt, TARGET_LONG_BITS - 8 + vece);
2414 tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], rt);
2416 tcg_temp_free_i64(vrb);
2417 tcg_temp_free_i64(rt);
2422 TRANS(VCNTMBB, do_vcntmb, MO_8)
2423 TRANS(VCNTMBH, do_vcntmb, MO_16)
2424 TRANS(VCNTMBW, do_vcntmb, MO_32)
2425 TRANS(VCNTMBD, do_vcntmb, MO_64)
2427 static bool do_vstri(DisasContext *ctx, arg_VX_tb_rc *a,
2428 void (*gen_helper)(TCGv_i32, TCGv_ptr, TCGv_ptr))
2432 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2433 REQUIRE_VECTOR(ctx);
2435 vrt = gen_avr_ptr(a->vrt);
2436 vrb = gen_avr_ptr(a->vrb);
2439 gen_helper(cpu_crf[6], vrt, vrb);
2441 TCGv_i32 discard = tcg_temp_new_i32();
2442 gen_helper(discard, vrt, vrb);
2443 tcg_temp_free_i32(discard);
2446 tcg_temp_free_ptr(vrt);
2447 tcg_temp_free_ptr(vrb);
2452 TRANS(VSTRIBL, do_vstri, gen_helper_VSTRIBL)
2453 TRANS(VSTRIBR, do_vstri, gen_helper_VSTRIBR)
2454 TRANS(VSTRIHL, do_vstri, gen_helper_VSTRIHL)
2455 TRANS(VSTRIHR, do_vstri, gen_helper_VSTRIHR)
2457 static bool do_vclrb(DisasContext *ctx, arg_VX *a, bool right)
2459 TCGv_i64 rb, mh, ml, tmp,
2460 ones = tcg_constant_i64(-1),
2461 zero = tcg_constant_i64(0);
2463 rb = tcg_temp_new_i64();
2464 mh = tcg_temp_new_i64();
2465 ml = tcg_temp_new_i64();
2466 tmp = tcg_temp_new_i64();
2468 tcg_gen_extu_tl_i64(rb, cpu_gpr[a->vrb]);
2469 tcg_gen_andi_i64(tmp, rb, 7);
2470 tcg_gen_shli_i64(tmp, tmp, 3);
2472 tcg_gen_shr_i64(tmp, ones, tmp);
2474 tcg_gen_shl_i64(tmp, ones, tmp);
2476 tcg_gen_not_i64(tmp, tmp);
2479 tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(8),
2481 tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(8),
2483 tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(16),
2486 tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(8),
2488 tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(8),
2490 tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(16),
2494 get_avr64(tmp, a->vra, true);
2495 tcg_gen_and_i64(tmp, tmp, mh);
2496 set_avr64(a->vrt, tmp, true);
2498 get_avr64(tmp, a->vra, false);
2499 tcg_gen_and_i64(tmp, tmp, ml);
2500 set_avr64(a->vrt, tmp, false);
2502 tcg_temp_free_i64(rb);
2503 tcg_temp_free_i64(mh);
2504 tcg_temp_free_i64(ml);
2505 tcg_temp_free_i64(tmp);
2510 TRANS(VCLRLB, do_vclrb, false)
2511 TRANS(VCLRRB, do_vclrb, true)
2513 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
2514 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
2516 TCGv_ptr ra, rb, rc, rd; \
2517 if (unlikely(!ctx->altivec_enabled)) { \
2518 gen_exception(ctx, POWERPC_EXCP_VPU); \
2521 ra = gen_avr_ptr(rA(ctx->opcode)); \
2522 rb = gen_avr_ptr(rB(ctx->opcode)); \
2523 rc = gen_avr_ptr(rC(ctx->opcode)); \
2524 rd = gen_avr_ptr(rD(ctx->opcode)); \
2525 if (Rc(ctx->opcode)) { \
2526 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
2528 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
2530 tcg_temp_free_ptr(ra); \
2531 tcg_temp_free_ptr(rb); \
2532 tcg_temp_free_ptr(rc); \
2533 tcg_temp_free_ptr(rd); \
2536 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
2538 static void gen_vmladduhm(DisasContext *ctx)
2540 TCGv_ptr ra, rb, rc, rd;
2541 if (unlikely(!ctx->altivec_enabled)) {
2542 gen_exception(ctx, POWERPC_EXCP_VPU);
2545 ra = gen_avr_ptr(rA(ctx->opcode));
2546 rb = gen_avr_ptr(rB(ctx->opcode));
2547 rc = gen_avr_ptr(rC(ctx->opcode));
2548 rd = gen_avr_ptr(rD(ctx->opcode));
2549 gen_helper_vmladduhm(rd, ra, rb, rc);
2550 tcg_temp_free_ptr(ra);
2551 tcg_temp_free_ptr(rb);
2552 tcg_temp_free_ptr(rc);
2553 tcg_temp_free_ptr(rd);
2556 static bool do_va_helper(DisasContext *ctx, arg_VA *a,
2557 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
2559 TCGv_ptr vrt, vra, vrb, vrc;
2560 REQUIRE_VECTOR(ctx);
2562 vrt = gen_avr_ptr(a->vrt);
2563 vra = gen_avr_ptr(a->vra);
2564 vrb = gen_avr_ptr(a->vrb);
2565 vrc = gen_avr_ptr(a->rc);
2566 gen_helper(vrt, vra, vrb, vrc);
2567 tcg_temp_free_ptr(vrt);
2568 tcg_temp_free_ptr(vra);
2569 tcg_temp_free_ptr(vrb);
2570 tcg_temp_free_ptr(vrc);
2575 TRANS_FLAGS(ALTIVEC, VPERM, do_va_helper, gen_helper_VPERM)
2576 TRANS_FLAGS2(ISA300, VPERMR, do_va_helper, gen_helper_VPERMR)
2578 static bool trans_VSEL(DisasContext *ctx, arg_VA *a)
2580 REQUIRE_INSNS_FLAGS(ctx, ALTIVEC);
2581 REQUIRE_VECTOR(ctx);
2583 tcg_gen_gvec_bitsel(MO_64, avr_full_offset(a->vrt), avr_full_offset(a->rc),
2584 avr_full_offset(a->vrb), avr_full_offset(a->vra),
2590 TRANS_FLAGS(ALTIVEC, VMSUMUBM, do_va_helper, gen_helper_VMSUMUBM)
2591 TRANS_FLAGS(ALTIVEC, VMSUMMBM, do_va_helper, gen_helper_VMSUMMBM)
2592 TRANS_FLAGS(ALTIVEC, VMSUMSHM, do_va_helper, gen_helper_VMSUMSHM)
2593 TRANS_FLAGS(ALTIVEC, VMSUMUHM, do_va_helper, gen_helper_VMSUMUHM)
2595 static bool do_va_env_helper(DisasContext *ctx, arg_VA *a,
2596 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
2598 TCGv_ptr vrt, vra, vrb, vrc;
2599 REQUIRE_VECTOR(ctx);
2601 vrt = gen_avr_ptr(a->vrt);
2602 vra = gen_avr_ptr(a->vra);
2603 vrb = gen_avr_ptr(a->vrb);
2604 vrc = gen_avr_ptr(a->rc);
2605 gen_helper(cpu_env, vrt, vra, vrb, vrc);
2606 tcg_temp_free_ptr(vrt);
2607 tcg_temp_free_ptr(vra);
2608 tcg_temp_free_ptr(vrb);
2609 tcg_temp_free_ptr(vrc);
2614 TRANS_FLAGS(ALTIVEC, VMSUMUHS, do_va_env_helper, gen_helper_VMSUMUHS)
2615 TRANS_FLAGS(ALTIVEC, VMSUMSHS, do_va_env_helper, gen_helper_VMSUMSHS)
2617 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
2619 GEN_VXFORM_NOA(vclzb, 1, 28)
2620 GEN_VXFORM_NOA(vclzh, 1, 29)
2621 GEN_VXFORM_TRANS(vclzw, 1, 30)
2622 GEN_VXFORM_TRANS(vclzd, 1, 31)
2623 GEN_VXFORM_NOA_2(vnegw, 1, 24, 6)
2624 GEN_VXFORM_NOA_2(vnegd, 1, 24, 7)
2626 static void gen_vexts_i64(TCGv_i64 t, TCGv_i64 b, int64_t s)
2628 tcg_gen_sextract_i64(t, b, 0, 64 - s);
2631 static void gen_vexts_i32(TCGv_i32 t, TCGv_i32 b, int32_t s)
2633 tcg_gen_sextract_i32(t, b, 0, 32 - s);
2636 static void gen_vexts_vec(unsigned vece, TCGv_vec t, TCGv_vec b, int64_t s)
2638 tcg_gen_shli_vec(vece, t, b, s);
2639 tcg_gen_sari_vec(vece, t, t, s);
2642 static bool do_vexts(DisasContext *ctx, arg_VX_tb *a, unsigned vece, int64_t s)
2644 static const TCGOpcode vecop_list[] = {
2645 INDEX_op_shli_vec, INDEX_op_sari_vec, 0
2648 static const GVecGen2i op[2] = {
2650 .fni4 = gen_vexts_i32,
2651 .fniv = gen_vexts_vec,
2652 .opt_opc = vecop_list,
2656 .fni8 = gen_vexts_i64,
2657 .fniv = gen_vexts_vec,
2658 .opt_opc = vecop_list,
2663 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
2664 REQUIRE_VECTOR(ctx);
2666 tcg_gen_gvec_2i(avr_full_offset(a->vrt), avr_full_offset(a->vrb),
2667 16, 16, s, &op[vece - MO_32]);
2672 TRANS(VEXTSB2W, do_vexts, MO_32, 24);
2673 TRANS(VEXTSH2W, do_vexts, MO_32, 16);
2674 TRANS(VEXTSB2D, do_vexts, MO_64, 56);
2675 TRANS(VEXTSH2D, do_vexts, MO_64, 48);
2676 TRANS(VEXTSW2D, do_vexts, MO_64, 32);
2678 static bool trans_VEXTSD2Q(DisasContext *ctx, arg_VX_tb *a)
2682 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2683 REQUIRE_VECTOR(ctx);
2685 tmp = tcg_temp_new_i64();
2687 get_avr64(tmp, a->vrb, false);
2688 set_avr64(a->vrt, tmp, false);
2689 tcg_gen_sari_i64(tmp, tmp, 63);
2690 set_avr64(a->vrt, tmp, true);
2692 tcg_temp_free_i64(tmp);
2696 GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
2697 GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
2698 GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
2699 GEN_VXFORM_NOA_2(vctzd, 1, 24, 31)
2700 GEN_VXFORM_NOA_3(vclzlsbb, 1, 24, 0)
2701 GEN_VXFORM_NOA_3(vctzlsbb, 1, 24, 1)
2702 GEN_VXFORM_NOA(vpopcntb, 1, 28)
2703 GEN_VXFORM_NOA(vpopcnth, 1, 29)
2704 GEN_VXFORM_NOA(vpopcntw, 1, 30)
2705 GEN_VXFORM_NOA(vpopcntd, 1, 31)
2706 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
2707 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
2708 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
2709 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
2710 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
2711 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
2712 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
2713 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
2714 GEN_VXFORM(vbpermd, 6, 23);
2715 GEN_VXFORM(vbpermq, 6, 21);
2716 GEN_VXFORM_TRANS(vgbbd, 6, 20);
2717 GEN_VXFORM(vpmsumb, 4, 16)
2718 GEN_VXFORM(vpmsumh, 4, 17)
2719 GEN_VXFORM(vpmsumw, 4, 18)
2720 GEN_VXFORM(vpmsumd, 4, 19)
2722 #define GEN_BCD(op) \
2723 static void gen_##op(DisasContext *ctx) \
2725 TCGv_ptr ra, rb, rd; \
2728 if (unlikely(!ctx->altivec_enabled)) { \
2729 gen_exception(ctx, POWERPC_EXCP_VPU); \
2733 ra = gen_avr_ptr(rA(ctx->opcode)); \
2734 rb = gen_avr_ptr(rB(ctx->opcode)); \
2735 rd = gen_avr_ptr(rD(ctx->opcode)); \
2737 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
2739 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
2741 tcg_temp_free_ptr(ra); \
2742 tcg_temp_free_ptr(rb); \
2743 tcg_temp_free_ptr(rd); \
2744 tcg_temp_free_i32(ps); \
2747 #define GEN_BCD2(op) \
2748 static void gen_##op(DisasContext *ctx) \
2753 if (unlikely(!ctx->altivec_enabled)) { \
2754 gen_exception(ctx, POWERPC_EXCP_VPU); \
2758 rb = gen_avr_ptr(rB(ctx->opcode)); \
2759 rd = gen_avr_ptr(rD(ctx->opcode)); \
2761 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
2763 gen_helper_##op(cpu_crf[6], rd, rb, ps); \
2765 tcg_temp_free_ptr(rb); \
2766 tcg_temp_free_ptr(rd); \
2767 tcg_temp_free_i32(ps); \
2786 static void gen_xpnd04_1(DisasContext *ctx)
2788 switch (opc4(ctx->opcode)) {
2816 static void gen_xpnd04_2(DisasContext *ctx)
2818 switch (opc4(ctx->opcode)) {
2844 GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \
2845 xpnd04_1, PPC_NONE, PPC2_ISA300)
2846 GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \
2847 xpnd04_2, PPC_NONE, PPC2_ISA300)
2849 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
2850 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
2851 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
2852 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
2853 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
2854 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
2855 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
2856 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
2857 GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \
2858 bcdcpsgn, PPC_NONE, PPC2_ISA300)
2859 GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
2860 bcds, PPC_NONE, PPC2_ISA300)
2861 GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
2862 bcdus, PPC_NONE, PPC2_ISA300)
2863 GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
2864 bcdtrunc, PPC_NONE, PPC2_ISA300)
2865 GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
2866 bcdtrunc, PPC_NONE, PPC2_ISA300)
2867 GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \
2868 bcdutrunc, PPC_NONE, PPC2_ISA300)
2871 static void gen_vsbox(DisasContext *ctx)
2874 if (unlikely(!ctx->altivec_enabled)) {
2875 gen_exception(ctx, POWERPC_EXCP_VPU);
2878 ra = gen_avr_ptr(rA(ctx->opcode));
2879 rd = gen_avr_ptr(rD(ctx->opcode));
2880 gen_helper_vsbox(rd, ra);
2881 tcg_temp_free_ptr(ra);
2882 tcg_temp_free_ptr(rd);
2885 GEN_VXFORM(vcipher, 4, 20)
2886 GEN_VXFORM(vcipherlast, 4, 20)
2887 GEN_VXFORM(vncipher, 4, 21)
2888 GEN_VXFORM(vncipherlast, 4, 21)
2890 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
2891 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
2892 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
2893 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
2895 #define VSHASIGMA(op) \
2896 static void gen_##op(DisasContext *ctx) \
2900 if (unlikely(!ctx->altivec_enabled)) { \
2901 gen_exception(ctx, POWERPC_EXCP_VPU); \
2904 ra = gen_avr_ptr(rA(ctx->opcode)); \
2905 rd = gen_avr_ptr(rD(ctx->opcode)); \
2906 st_six = tcg_const_i32(rB(ctx->opcode)); \
2907 gen_helper_##op(rd, ra, st_six); \
2908 tcg_temp_free_ptr(ra); \
2909 tcg_temp_free_ptr(rd); \
2910 tcg_temp_free_i32(st_six); \
2913 VSHASIGMA(vshasigmaw)
2914 VSHASIGMA(vshasigmad)
2916 GEN_VXFORM3(vpermxor, 22, 0xFF)
2917 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
2918 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
2920 static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
2922 static const GVecGen3 g = {
2923 .fni8 = gen_helper_CFUGED,
2927 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2928 REQUIRE_VECTOR(ctx);
2930 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2931 avr_full_offset(a->vrb), 16, 16, &g);
2936 static bool trans_VCLZDM(DisasContext *ctx, arg_VX *a)
2938 static const GVecGen3i g = {
2943 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2944 REQUIRE_VECTOR(ctx);
2946 tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2947 avr_full_offset(a->vrb), 16, 16, false, &g);
2952 static bool trans_VCTZDM(DisasContext *ctx, arg_VX *a)
2954 static const GVecGen3i g = {
2959 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2960 REQUIRE_VECTOR(ctx);
2962 tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2963 avr_full_offset(a->vrb), 16, 16, true, &g);
2968 static bool trans_VPDEPD(DisasContext *ctx, arg_VX *a)
2970 static const GVecGen3 g = {
2971 .fni8 = gen_helper_PDEPD,
2975 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2976 REQUIRE_VECTOR(ctx);
2978 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2979 avr_full_offset(a->vrb), 16, 16, &g);
2984 static bool trans_VPEXTD(DisasContext *ctx, arg_VX *a)
2986 static const GVecGen3 g = {
2987 .fni8 = gen_helper_PEXTD,
2991 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
2992 REQUIRE_VECTOR(ctx);
2994 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
2995 avr_full_offset(a->vrb), 16, 16, &g);
3000 static bool trans_VMSUMUDM(DisasContext *ctx, arg_VA *a)
3002 TCGv_i64 rl, rh, src1, src2;
3005 REQUIRE_INSNS_FLAGS2(ctx, ISA300);
3006 REQUIRE_VECTOR(ctx);
3008 rh = tcg_temp_new_i64();
3009 rl = tcg_temp_new_i64();
3010 src1 = tcg_temp_new_i64();
3011 src2 = tcg_temp_new_i64();
3013 get_avr64(rl, a->rc, false);
3014 get_avr64(rh, a->rc, true);
3016 for (dw = 0; dw < 2; dw++) {
3017 get_avr64(src1, a->vra, dw);
3018 get_avr64(src2, a->vrb, dw);
3019 tcg_gen_mulu2_i64(src1, src2, src1, src2);
3020 tcg_gen_add2_i64(rl, rh, rl, rh, src1, src2);
3023 set_avr64(a->vrt, rl, false);
3024 set_avr64(a->vrt, rh, true);
3026 tcg_temp_free_i64(rl);
3027 tcg_temp_free_i64(rh);
3028 tcg_temp_free_i64(src1);
3029 tcg_temp_free_i64(src2);
3034 static bool trans_VMSUMCUD(DisasContext *ctx, arg_VA *a)
3036 TCGv_i64 tmp0, tmp1, prod1h, prod1l, prod0h, prod0l, zero;
3038 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
3039 REQUIRE_VECTOR(ctx);
3041 tmp0 = tcg_temp_new_i64();
3042 tmp1 = tcg_temp_new_i64();
3043 prod1h = tcg_temp_new_i64();
3044 prod1l = tcg_temp_new_i64();
3045 prod0h = tcg_temp_new_i64();
3046 prod0l = tcg_temp_new_i64();
3047 zero = tcg_constant_i64(0);
3049 /* prod1 = vsr[vra+32].dw[1] * vsr[vrb+32].dw[1] */
3050 get_avr64(tmp0, a->vra, false);
3051 get_avr64(tmp1, a->vrb, false);
3052 tcg_gen_mulu2_i64(prod1l, prod1h, tmp0, tmp1);
3054 /* prod0 = vsr[vra+32].dw[0] * vsr[vrb+32].dw[0] */
3055 get_avr64(tmp0, a->vra, true);
3056 get_avr64(tmp1, a->vrb, true);
3057 tcg_gen_mulu2_i64(prod0l, prod0h, tmp0, tmp1);
3059 /* Sum lower 64-bits elements */
3060 get_avr64(tmp1, a->rc, false);
3061 tcg_gen_add2_i64(tmp1, tmp0, tmp1, zero, prod1l, zero);
3062 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod0l, zero);
3065 * Discard lower 64-bits, leaving the carry into bit 64.
3066 * Then sum the higher 64-bit elements.
3068 get_avr64(tmp1, a->rc, true);
3069 tcg_gen_add2_i64(tmp1, tmp0, tmp0, zero, tmp1, zero);
3070 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod1h, zero);
3071 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod0h, zero);
3073 /* Discard 64 more bits to complete the CHOP128(temp >> 128) */
3074 set_avr64(a->vrt, tmp0, false);
3075 set_avr64(a->vrt, zero, true);
3077 tcg_temp_free_i64(tmp0);
3078 tcg_temp_free_i64(tmp1);
3079 tcg_temp_free_i64(prod1h);
3080 tcg_temp_free_i64(prod1l);
3081 tcg_temp_free_i64(prod0h);
3082 tcg_temp_free_i64(prod0l);
3087 static bool do_vx_helper(DisasContext *ctx, arg_VX *a,
3088 void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr))
3090 TCGv_ptr ra, rb, rd;
3091 REQUIRE_VECTOR(ctx);
3093 ra = gen_avr_ptr(a->vra);
3094 rb = gen_avr_ptr(a->vrb);
3095 rd = gen_avr_ptr(a->vrt);
3096 gen_helper(rd, ra, rb);
3097 tcg_temp_free_ptr(ra);
3098 tcg_temp_free_ptr(rb);
3099 tcg_temp_free_ptr(rd);
3104 static bool do_vx_vmuleo(DisasContext *ctx, arg_VX *a, bool even,
3105 void (*gen_mul)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
3107 TCGv_i64 vra, vrb, vrt0, vrt1;
3108 REQUIRE_VECTOR(ctx);
3110 vra = tcg_temp_new_i64();
3111 vrb = tcg_temp_new_i64();
3112 vrt0 = tcg_temp_new_i64();
3113 vrt1 = tcg_temp_new_i64();
3115 get_avr64(vra, a->vra, even);
3116 get_avr64(vrb, a->vrb, even);
3117 gen_mul(vrt0, vrt1, vra, vrb);
3118 set_avr64(a->vrt, vrt0, false);
3119 set_avr64(a->vrt, vrt1, true);
3121 tcg_temp_free_i64(vra);
3122 tcg_temp_free_i64(vrb);
3123 tcg_temp_free_i64(vrt0);
3124 tcg_temp_free_i64(vrt1);
3129 static bool trans_VMULLD(DisasContext *ctx, arg_VX *a)
3131 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
3132 REQUIRE_VECTOR(ctx);
3134 tcg_gen_gvec_mul(MO_64, avr_full_offset(a->vrt), avr_full_offset(a->vra),
3135 avr_full_offset(a->vrb), 16, 16);
3140 TRANS_FLAGS(ALTIVEC, VMULESB, do_vx_helper, gen_helper_VMULESB)
3141 TRANS_FLAGS(ALTIVEC, VMULOSB, do_vx_helper, gen_helper_VMULOSB)
3142 TRANS_FLAGS(ALTIVEC, VMULEUB, do_vx_helper, gen_helper_VMULEUB)
3143 TRANS_FLAGS(ALTIVEC, VMULOUB, do_vx_helper, gen_helper_VMULOUB)
3144 TRANS_FLAGS(ALTIVEC, VMULESH, do_vx_helper, gen_helper_VMULESH)
3145 TRANS_FLAGS(ALTIVEC, VMULOSH, do_vx_helper, gen_helper_VMULOSH)
3146 TRANS_FLAGS(ALTIVEC, VMULEUH, do_vx_helper, gen_helper_VMULEUH)
3147 TRANS_FLAGS(ALTIVEC, VMULOUH, do_vx_helper, gen_helper_VMULOUH)
3148 TRANS_FLAGS2(ALTIVEC_207, VMULESW, do_vx_helper, gen_helper_VMULESW)
3149 TRANS_FLAGS2(ALTIVEC_207, VMULOSW, do_vx_helper, gen_helper_VMULOSW)
3150 TRANS_FLAGS2(ALTIVEC_207, VMULEUW, do_vx_helper, gen_helper_VMULEUW)
3151 TRANS_FLAGS2(ALTIVEC_207, VMULOUW, do_vx_helper, gen_helper_VMULOUW)
3152 TRANS_FLAGS2(ISA310, VMULESD, do_vx_vmuleo, true , tcg_gen_muls2_i64)
3153 TRANS_FLAGS2(ISA310, VMULOSD, do_vx_vmuleo, false, tcg_gen_muls2_i64)
3154 TRANS_FLAGS2(ISA310, VMULEUD, do_vx_vmuleo, true , tcg_gen_mulu2_i64)
3155 TRANS_FLAGS2(ISA310, VMULOUD, do_vx_vmuleo, false, tcg_gen_mulu2_i64)
3157 static void do_vx_vmulhw_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, bool sign)
3159 TCGv_i64 hh, lh, temp;
3161 hh = tcg_temp_new_i64();
3162 lh = tcg_temp_new_i64();
3163 temp = tcg_temp_new_i64();
3166 tcg_gen_ext32s_i64(lh, a);
3167 tcg_gen_ext32s_i64(temp, b);
3169 tcg_gen_ext32u_i64(lh, a);
3170 tcg_gen_ext32u_i64(temp, b);
3172 tcg_gen_mul_i64(lh, lh, temp);
3175 tcg_gen_sari_i64(hh, a, 32);
3176 tcg_gen_sari_i64(temp, b, 32);
3178 tcg_gen_shri_i64(hh, a, 32);
3179 tcg_gen_shri_i64(temp, b, 32);
3181 tcg_gen_mul_i64(hh, hh, temp);
3183 tcg_gen_shri_i64(lh, lh, 32);
3184 tcg_gen_deposit_i64(t, hh, lh, 0, 32);
3186 tcg_temp_free_i64(hh);
3187 tcg_temp_free_i64(lh);
3188 tcg_temp_free_i64(temp);
3191 static void do_vx_vmulhd_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, bool sign)
3195 tlow = tcg_temp_new_i64();
3197 tcg_gen_muls2_i64(tlow, t, a, b);
3199 tcg_gen_mulu2_i64(tlow, t, a, b);
3202 tcg_temp_free_i64(tlow);
3205 static bool do_vx_mulh(DisasContext *ctx, arg_VX *a, bool sign,
3206 void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, bool))
3208 REQUIRE_INSNS_FLAGS2(ctx, ISA310);
3209 REQUIRE_VECTOR(ctx);
3211 TCGv_i64 vra, vrb, vrt;
3214 vra = tcg_temp_new_i64();
3215 vrb = tcg_temp_new_i64();
3216 vrt = tcg_temp_new_i64();
3218 for (i = 0; i < 2; i++) {
3219 get_avr64(vra, a->vra, i);
3220 get_avr64(vrb, a->vrb, i);
3221 get_avr64(vrt, a->vrt, i);
3223 func(vrt, vra, vrb, sign);
3225 set_avr64(a->vrt, vrt, i);
3228 tcg_temp_free_i64(vra);
3229 tcg_temp_free_i64(vrb);
3230 tcg_temp_free_i64(vrt);
3236 TRANS(VMULHSW, do_vx_mulh, true , do_vx_vmulhw_i64)
3237 TRANS(VMULHSD, do_vx_mulh, true , do_vx_vmulhd_i64)
3238 TRANS(VMULHUW, do_vx_mulh, false, do_vx_vmulhw_i64)
3239 TRANS(VMULHUD, do_vx_mulh, false, do_vx_vmulhd_i64)
3241 static bool do_vdiv_vmod(DisasContext *ctx, arg_VX *a, const int vece,
3242 void (*func_32)(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b),
3243 void (*func_64)(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b))
3245 const GVecGen3 op = {
3251 REQUIRE_VECTOR(ctx);
3253 tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
3254 avr_full_offset(a->vrb), 16, 16, &op);
3259 #define DIVU32(NAME, DIV) \
3260 static void NAME(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b) \
3262 TCGv_i32 zero = tcg_constant_i32(0); \
3263 TCGv_i32 one = tcg_constant_i32(1); \
3264 tcg_gen_movcond_i32(TCG_COND_EQ, b, b, zero, one, b); \
3268 #define DIVS32(NAME, DIV) \
3269 static void NAME(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b) \
3271 TCGv_i32 t0 = tcg_temp_new_i32(); \
3272 TCGv_i32 t1 = tcg_temp_new_i32(); \
3273 tcg_gen_setcondi_i32(TCG_COND_EQ, t0, a, INT32_MIN); \
3274 tcg_gen_setcondi_i32(TCG_COND_EQ, t1, b, -1); \
3275 tcg_gen_and_i32(t0, t0, t1); \
3276 tcg_gen_setcondi_i32(TCG_COND_EQ, t1, b, 0); \
3277 tcg_gen_or_i32(t0, t0, t1); \
3278 tcg_gen_movi_i32(t1, 0); \
3279 tcg_gen_movcond_i32(TCG_COND_NE, b, t0, t1, t0, b); \
3281 tcg_temp_free_i32(t0); \
3282 tcg_temp_free_i32(t1); \
3285 #define DIVU64(NAME, DIV) \
3286 static void NAME(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b) \
3288 TCGv_i64 zero = tcg_constant_i64(0); \
3289 TCGv_i64 one = tcg_constant_i64(1); \
3290 tcg_gen_movcond_i64(TCG_COND_EQ, b, b, zero, one, b); \
3294 #define DIVS64(NAME, DIV) \
3295 static void NAME(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b) \
3297 TCGv_i64 t0 = tcg_temp_new_i64(); \
3298 TCGv_i64 t1 = tcg_temp_new_i64(); \
3299 tcg_gen_setcondi_i64(TCG_COND_EQ, t0, a, INT64_MIN); \
3300 tcg_gen_setcondi_i64(TCG_COND_EQ, t1, b, -1); \
3301 tcg_gen_and_i64(t0, t0, t1); \
3302 tcg_gen_setcondi_i64(TCG_COND_EQ, t1, b, 0); \
3303 tcg_gen_or_i64(t0, t0, t1); \
3304 tcg_gen_movi_i64(t1, 0); \
3305 tcg_gen_movcond_i64(TCG_COND_NE, b, t0, t1, t0, b); \
3307 tcg_temp_free_i64(t0); \
3308 tcg_temp_free_i64(t1); \
3311 DIVS32(do_divsw, tcg_gen_div_i32)
3312 DIVU32(do_divuw, tcg_gen_divu_i32)
3313 DIVS64(do_divsd, tcg_gen_div_i64)
3314 DIVU64(do_divud, tcg_gen_divu_i64)
3316 TRANS_FLAGS2(ISA310, VDIVSW, do_vdiv_vmod, MO_32, do_divsw, NULL)
3317 TRANS_FLAGS2(ISA310, VDIVUW, do_vdiv_vmod, MO_32, do_divuw, NULL)
3318 TRANS_FLAGS2(ISA310, VDIVSD, do_vdiv_vmod, MO_64, NULL, do_divsd)
3319 TRANS_FLAGS2(ISA310, VDIVUD, do_vdiv_vmod, MO_64, NULL, do_divud)
3320 TRANS_FLAGS2(ISA310, VDIVSQ, do_vx_helper, gen_helper_VDIVSQ)
3321 TRANS_FLAGS2(ISA310, VDIVUQ, do_vx_helper, gen_helper_VDIVUQ)
3323 static void do_dives_i32(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)
3325 TCGv_i64 val1, val2;
3327 val1 = tcg_temp_new_i64();
3328 val2 = tcg_temp_new_i64();
3330 tcg_gen_ext_i32_i64(val1, a);
3331 tcg_gen_ext_i32_i64(val2, b);
3334 tcg_gen_shli_i64(val1, val1, 32);
3335 tcg_gen_div_i64(val1, val1, val2);
3337 /* if quotient doesn't fit in 32 bits the result is undefined */
3338 tcg_gen_extrl_i64_i32(t, val1);
3340 tcg_temp_free_i64(val1);
3341 tcg_temp_free_i64(val2);
3344 static void do_diveu_i32(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)
3346 TCGv_i64 val1, val2;
3348 val1 = tcg_temp_new_i64();
3349 val2 = tcg_temp_new_i64();
3351 tcg_gen_extu_i32_i64(val1, a);
3352 tcg_gen_extu_i32_i64(val2, b);
3355 tcg_gen_shli_i64(val1, val1, 32);
3356 tcg_gen_divu_i64(val1, val1, val2);
3358 /* if quotient doesn't fit in 32 bits the result is undefined */
3359 tcg_gen_extrl_i64_i32(t, val1);
3361 tcg_temp_free_i64(val1);
3362 tcg_temp_free_i64(val2);
3365 DIVS32(do_divesw, do_dives_i32)
3366 DIVU32(do_diveuw, do_diveu_i32)
3368 TRANS_FLAGS2(ISA310, VDIVESW, do_vdiv_vmod, MO_32, do_divesw, NULL)
3369 TRANS_FLAGS2(ISA310, VDIVEUW, do_vdiv_vmod, MO_32, do_diveuw, NULL)
3370 TRANS_FLAGS2(ISA310, VDIVESD, do_vx_helper, gen_helper_VDIVESD)
3371 TRANS_FLAGS2(ISA310, VDIVEUD, do_vx_helper, gen_helper_VDIVEUD)
3372 TRANS_FLAGS2(ISA310, VDIVESQ, do_vx_helper, gen_helper_VDIVESQ)
3373 TRANS_FLAGS2(ISA310, VDIVEUQ, do_vx_helper, gen_helper_VDIVEUQ)
3385 #undef GEN_VX_LOGICAL
3386 #undef GEN_VX_LOGICAL_207
3388 #undef GEN_VXFORM_207
3389 #undef GEN_VXFORM_DUAL
3390 #undef GEN_VXRFORM_DUAL
3393 #undef GEN_VXFORM_VSPLTI
3394 #undef GEN_VXFORM_NOA
3395 #undef GEN_VXFORM_UIMM
3396 #undef GEN_VAFORM_PAIRED