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Fix regression introduced by -machine accel=
[qemu.git] / hw / usb-ehci.c
blobf63519ecf949ee5316623aa09256d7db79b2bc6b
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 *
24 * TODO:
25 * o Downstream port handoff
26 */
27
28 #include "hw.h"
29 #include "qemu-timer.h"
30 #include "usb.h"
31 #include "pci.h"
32 #include "monitor.h"
33
34 #define EHCI_DEBUG 0
35 #define STATE_DEBUG 0 /* state transitions */
36
37 #if EHCI_DEBUG || STATE_DEBUG
38 #define DPRINTF printf
39 #else
40 #define DPRINTF(...)
41 #endif
42
43 #if STATE_DEBUG
44 #define DPRINTF_ST DPRINTF
45 #else
46 #define DPRINTF_ST(...)
47 #endif
48
49 /* internal processing - reset HC to try and recover */
50 #define USB_RET_PROCERR (-99)
51
52 #define MMIO_SIZE 0x1000
53
54 /* Capability Registers Base Address - section 2.2 */
55 #define CAPREGBASE 0x0000
56 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
57 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
58 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
59 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
60 #define EECP HCCPARAMS + 1
61 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
62 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
63
64 #define OPREGBASE 0x0020 // Operational Registers Base Address
65
66 #define USBCMD OPREGBASE + 0x0000
67 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
68 #define USBCMD_HCRESET (1 << 1) // HC Reset
69 #define USBCMD_FLS (3 << 2) // Frame List Size
70 #define USBCMD_FLS_SH 2 // Frame List Size Shift
71 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
72 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
73 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
74 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
75 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
76 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
77 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
78 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
79
80 #define USBSTS OPREGBASE + 0x0004
81 #define USBSTS_RO_MASK 0x0000003f
82 #define USBSTS_INT (1 << 0) // USB Interrupt
83 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
84 #define USBSTS_PCD (1 << 2) // Port Change Detect
85 #define USBSTS_FLR (1 << 3) // Frame List Rollover
86 #define USBSTS_HSE (1 << 4) // Host System Error
87 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
88 #define USBSTS_HALT (1 << 12) // HC Halted
89 #define USBSTS_REC (1 << 13) // Reclamation
90 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
91 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
92
93 /*
94 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
95 * so no need to redefine here.
96 */
97 #define USBINTR OPREGBASE + 0x0008
98 #define USBINTR_MASK 0x0000003f
99
100 #define FRINDEX OPREGBASE + 0x000c
101 #define CTRLDSSEGMENT OPREGBASE + 0x0010
102 #define PERIODICLISTBASE OPREGBASE + 0x0014
103 #define ASYNCLISTADDR OPREGBASE + 0x0018
104 #define ASYNCLISTADDR_MASK 0xffffffe0
105
106 #define CONFIGFLAG OPREGBASE + 0x0040
107
108 #define PORTSC (OPREGBASE + 0x0044)
109 #define PORTSC_BEGIN PORTSC
110 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
111 /*
112 * Bits that are reserverd or are read-only are masked out of values
113 * written to us by software
114 */
115 #define PORTSC_RO_MASK 0x007021c5
116 #define PORTSC_RWC_MASK 0x0000002a
117 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
118 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
119 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
120 #define PORTSC_PTC (15 << 16) // Port Test Control
121 #define PORTSC_PTC_SH 16 // Port Test Control shift
122 #define PORTSC_PIC (3 << 14) // Port Indicator Control
123 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
124 #define PORTSC_POWNER (1 << 13) // Port Owner
125 #define PORTSC_PPOWER (1 << 12) // Port Power
126 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
127 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
128 #define PORTSC_PRESET (1 << 8) // Port Reset
129 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
130 #define PORTSC_FPRES (1 << 6) // Force Port Resume
131 #define PORTSC_OCC (1 << 5) // Over Current Change
132 #define PORTSC_OCA (1 << 4) // Over Current Active
133 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
134 #define PORTSC_PED (1 << 2) // Port Enable/Disable
135 #define PORTSC_CSC (1 << 1) // Connect Status Change
136 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
137
138 #define FRAME_TIMER_FREQ 1000
139 #define FRAME_TIMER_USEC (1000000 / FRAME_TIMER_FREQ)
140
141 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
142 #define NB_PORTS 4 // Number of downstream ports
143 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
144 #define MAX_ITERATIONS 20 // Max number of QH before we break the loop
145 #define MAX_QH 100 // Max allowable queue heads in a chain
146
147 /* Internal periodic / asynchronous schedule state machine states
148 */
149 typedef enum {
150 EST_INACTIVE = 1000,
151 EST_ACTIVE,
152 EST_EXECUTING,
153 EST_SLEEPING,
154 /* The following states are internal to the state machine function
155 */
156 EST_WAITLISTHEAD,
157 EST_FETCHENTRY,
158 EST_FETCHQH,
159 EST_FETCHITD,
160 EST_ADVANCEQUEUE,
161 EST_FETCHQTD,
162 EST_EXECUTE,
163 EST_WRITEBACK,
164 EST_HORIZONTALQH
165 } EHCI_STATES;
166
167 /* macros for accessing fields within next link pointer entry */
168 #define NLPTR_GET(x) ((x) & 0xffffffe0)
169 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
170 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
171
172 /* link pointer types */
173 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
174 #define NLPTR_TYPE_QH 1 // queue head
175 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
176 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
177
178
179 /* EHCI spec version 1.0 Section 3.3
180 */
181 typedef struct EHCIitd {
182 uint32_t next;
183
184 uint32_t transact[8];
185 #define ITD_XACT_ACTIVE (1 << 31)
186 #define ITD_XACT_DBERROR (1 << 30)
187 #define ITD_XACT_BABBLE (1 << 29)
188 #define ITD_XACT_XACTERR (1 << 28)
189 #define ITD_XACT_LENGTH_MASK 0x0fff0000
190 #define ITD_XACT_LENGTH_SH 16
191 #define ITD_XACT_IOC (1 << 15)
192 #define ITD_XACT_PGSEL_MASK 0x00007000
193 #define ITD_XACT_PGSEL_SH 12
194 #define ITD_XACT_OFFSET_MASK 0x00000fff
195
196 uint32_t bufptr[7];
197 #define ITD_BUFPTR_MASK 0xfffff000
198 #define ITD_BUFPTR_SH 12
199 #define ITD_BUFPTR_EP_MASK 0x00000f00
200 #define ITD_BUFPTR_EP_SH 8
201 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
202 #define ITD_BUFPTR_DEVADDR_SH 0
203 #define ITD_BUFPTR_DIRECTION (1 << 11)
204 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
205 #define ITD_BUFPTR_MAXPKT_SH 0
206 #define ITD_BUFPTR_MULT_MASK 0x00000003
207 } EHCIitd;
208
209 /* EHCI spec version 1.0 Section 3.4
210 */
211 typedef struct EHCIsitd {
212 uint32_t next; // Standard next link pointer
213 uint32_t epchar;
214 #define SITD_EPCHAR_IO (1 << 31)
215 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
216 #define SITD_EPCHAR_PORTNUM_SH 24
217 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
218 #define SITD_EPCHAR_HUBADDR_SH 16
219 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
220 #define SITD_EPCHAR_EPNUM_SH 8
221 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
222
223 uint32_t uframe;
224 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
225 #define SITD_UFRAME_CMASK_SH 8
226 #define SITD_UFRAME_SMASK_MASK 0x000000ff
227
228 uint32_t results;
229 #define SITD_RESULTS_IOC (1 << 31)
230 #define SITD_RESULTS_PGSEL (1 << 30)
231 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
232 #define SITD_RESULTS_TYBYTES_SH 16
233 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
234 #define SITD_RESULTS_CPROGMASK_SH 8
235 #define SITD_RESULTS_ACTIVE (1 << 7)
236 #define SITD_RESULTS_ERR (1 << 6)
237 #define SITD_RESULTS_DBERR (1 << 5)
238 #define SITD_RESULTS_BABBLE (1 << 4)
239 #define SITD_RESULTS_XACTERR (1 << 3)
240 #define SITD_RESULTS_MISSEDUF (1 << 2)
241 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
242
243 uint32_t bufptr[2];
244 #define SITD_BUFPTR_MASK 0xfffff000
245 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
246 #define SITD_BUFPTR_TPOS_MASK 0x00000018
247 #define SITD_BUFPTR_TPOS_SH 3
248 #define SITD_BUFPTR_TCNT_MASK 0x00000007
249
250 uint32_t backptr; // Standard next link pointer
251 } EHCIsitd;
252
253 /* EHCI spec version 1.0 Section 3.5
254 */
255 typedef struct EHCIqtd {
256 uint32_t next; // Standard next link pointer
257 uint32_t altnext; // Standard next link pointer
258 uint32_t token;
259 #define QTD_TOKEN_DTOGGLE (1 << 31)
260 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
261 #define QTD_TOKEN_TBYTES_SH 16
262 #define QTD_TOKEN_IOC (1 << 15)
263 #define QTD_TOKEN_CPAGE_MASK 0x00007000
264 #define QTD_TOKEN_CPAGE_SH 12
265 #define QTD_TOKEN_CERR_MASK 0x00000c00
266 #define QTD_TOKEN_CERR_SH 10
267 #define QTD_TOKEN_PID_MASK 0x00000300
268 #define QTD_TOKEN_PID_SH 8
269 #define QTD_TOKEN_ACTIVE (1 << 7)
270 #define QTD_TOKEN_HALT (1 << 6)
271 #define QTD_TOKEN_DBERR (1 << 5)
272 #define QTD_TOKEN_BABBLE (1 << 4)
273 #define QTD_TOKEN_XACTERR (1 << 3)
274 #define QTD_TOKEN_MISSEDUF (1 << 2)
275 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
276 #define QTD_TOKEN_PING (1 << 0)
277
278 uint32_t bufptr[5]; // Standard buffer pointer
279 #define QTD_BUFPTR_MASK 0xfffff000
280 } EHCIqtd;
281
282 /* EHCI spec version 1.0 Section 3.6
283 */
284 typedef struct EHCIqh {
285 uint32_t next; // Standard next link pointer
286
287 /* endpoint characteristics */
288 uint32_t epchar;
289 #define QH_EPCHAR_RL_MASK 0xf0000000
290 #define QH_EPCHAR_RL_SH 28
291 #define QH_EPCHAR_C (1 << 27)
292 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
293 #define QH_EPCHAR_MPLEN_SH 16
294 #define QH_EPCHAR_H (1 << 15)
295 #define QH_EPCHAR_DTC (1 << 14)
296 #define QH_EPCHAR_EPS_MASK 0x00003000
297 #define QH_EPCHAR_EPS_SH 12
298 #define EHCI_QH_EPS_FULL 0
299 #define EHCI_QH_EPS_LOW 1
300 #define EHCI_QH_EPS_HIGH 2
301 #define EHCI_QH_EPS_RESERVED 3
302
303 #define QH_EPCHAR_EP_MASK 0x00000f00
304 #define QH_EPCHAR_EP_SH 8
305 #define QH_EPCHAR_I (1 << 7)
306 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
307 #define QH_EPCHAR_DEVADDR_SH 0
308
309 /* endpoint capabilities */
310 uint32_t epcap;
311 #define QH_EPCAP_MULT_MASK 0xc0000000
312 #define QH_EPCAP_MULT_SH 30
313 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
314 #define QH_EPCAP_PORTNUM_SH 23
315 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
316 #define QH_EPCAP_HUBADDR_SH 16
317 #define QH_EPCAP_CMASK_MASK 0x0000ff00
318 #define QH_EPCAP_CMASK_SH 8
319 #define QH_EPCAP_SMASK_MASK 0x000000ff
320 #define QH_EPCAP_SMASK_SH 0
321
322 uint32_t current_qtd; // Standard next link pointer
323 uint32_t next_qtd; // Standard next link pointer
324 uint32_t altnext_qtd;
325 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
326 #define QH_ALTNEXT_NAKCNT_SH 1
327
328 uint32_t token; // Same as QTD token
329 uint32_t bufptr[5]; // Standard buffer pointer
330 #define BUFPTR_CPROGMASK_MASK 0x000000ff
331 #define BUFPTR_FRAMETAG_MASK 0x0000001f
332 #define BUFPTR_SBYTES_MASK 0x00000fe0
333 #define BUFPTR_SBYTES_SH 5
334 } EHCIqh;
335
336 /* EHCI spec version 1.0 Section 3.7
337 */
338 typedef struct EHCIfstn {
339 uint32_t next; // Standard next link pointer
340 uint32_t backptr; // Standard next link pointer
341 } EHCIfstn;
342
343 typedef struct {
344 PCIDevice dev;
345 qemu_irq irq;
346 target_phys_addr_t mem_base;
347 int mem;
348 int num_ports;
349 /*
350 * EHCI spec version 1.0 Section 2.3
351 * Host Controller Operational Registers
352 */
353 union {
354 uint8_t mmio[MMIO_SIZE];
355 struct {
356 uint8_t cap[OPREGBASE];
357 uint32_t usbcmd;
358 uint32_t usbsts;
359 uint32_t usbintr;
360 uint32_t frindex;
361 uint32_t ctrldssegment;
362 uint32_t periodiclistbase;
363 uint32_t asynclistaddr;
364 uint32_t notused[9];
365 uint32_t configflag;
366 uint32_t portsc[NB_PORTS];
367 };
368 };
369 /*
370 * Internal states, shadow registers, etc
371 */
372 uint32_t sofv;
373 QEMUTimer *frame_timer;
374 int attach_poll_counter;
375 int astate; // Current state in asynchronous schedule
376 int pstate; // Current state in periodic schedule
377 USBPort ports[NB_PORTS];
378 uint8_t buffer[BUFF_SIZE];
379 uint32_t usbsts_pending;
380
381 /* cached data from guest - needs to be flushed
382 * when guest removes an entry (doorbell, handshake sequence)
383 */
384 EHCIqh qh; // copy of current QH (being worked on)
385 uint32_t qhaddr; // address QH read from
386
387 EHCIqtd qtd; // copy of current QTD (being worked on)
388 uint32_t qtdaddr; // address QTD read from
389
390 uint32_t itdaddr; // current ITD
391
392 uint32_t fetch_addr; // which address to look at next
393
394 USBBus bus;
395 USBPacket usb_packet;
396 int async_complete;
397 uint32_t tbytes;
398 int pid;
399 int exec_status;
400 int isoch_pause;
401 uint32_t last_run_usec;
402 uint32_t frame_end_usec;
403 } EHCIState;
404
405 #define SET_LAST_RUN_CLOCK(s) \
406 (s)->last_run_usec = qemu_get_clock_ns(vm_clock) / 1000;
407
408 /* nifty macros from Arnon's EHCI version */
409 #define get_field(data, field) \
410 (((data) & field##_MASK) >> field##_SH)
411
412 #define set_field(data, newval, field) do { \
413 uint32_t val = *data; \
414 val &= ~ field##_MASK; \
415 val |= ((newval) << field##_SH) & field##_MASK; \
416 *data = val; \
417 } while(0)
418
419
420 #if EHCI_DEBUG
421 static const char *addr2str(unsigned addr)
422 {
423 const char *r = " unknown";
424 const char *n[] = {
425 [ CAPLENGTH ] = " CAPLENGTH",
426 [ HCIVERSION ] = "HCIVERSION",
427 [ HCSPARAMS ] = " HCSPARAMS",
428 [ HCCPARAMS ] = " HCCPARAMS",
429 [ USBCMD ] = " COMMAND",
430 [ USBSTS ] = " STATUS",
431 [ USBINTR ] = " INTERRUPT",
432 [ FRINDEX ] = " FRAME IDX",
433 [ PERIODICLISTBASE ] = "P-LIST BASE",
434 [ ASYNCLISTADDR ] = "A-LIST ADDR",
435 [ PORTSC_BEGIN ...
436 PORTSC_END ] = "PORT STATUS",
437 [ CONFIGFLAG ] = "CONFIG FLAG",
438 };
439
440 if (addr < ARRAY_SIZE(n) && n[addr] != NULL) {
441 return n[addr];
442 } else {
443 return r;
444 }
445 }
446 #endif
447
448
449 static inline void ehci_set_interrupt(EHCIState *s, int intr)
450 {
451 int level = 0;
452
453 // TODO honour interrupt threshold requests
454
455 s->usbsts |= intr;
456
457 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
458 level = 1;
459 }
460
461 qemu_set_irq(s->irq, level);
462 }
463
464 static inline void ehci_record_interrupt(EHCIState *s, int intr)
465 {
466 s->usbsts_pending |= intr;
467 }
468
469 static inline void ehci_commit_interrupt(EHCIState *s)
470 {
471 if (!s->usbsts_pending) {
472 return;
473 }
474 ehci_set_interrupt(s, s->usbsts_pending);
475 s->usbsts_pending = 0;
476 }
477
478 /* Attach or detach a device on root hub */
479
480 static void ehci_attach(USBPort *port)
481 {
482 EHCIState *s = port->opaque;
483 uint32_t *portsc = &s->portsc[port->index];
484
485 DPRINTF("ehci_attach invoked for index %d, portsc 0x%x, desc %s\n",
486 port->index, *portsc, port->dev->product_desc);
487
488 *portsc |= PORTSC_CONNECT;
489 *portsc |= PORTSC_CSC;
490
491 /*
492 * If a high speed device is attached then we own this port(indicated
493 * by zero in the PORTSC_POWNER bit field) so set the status bit
494 * and set an interrupt if enabled.
495 */
496 if ( !(*portsc & PORTSC_POWNER)) {
497 ehci_set_interrupt(s, USBSTS_PCD);
498 }
499 }
500
501 static void ehci_detach(USBPort *port)
502 {
503 EHCIState *s = port->opaque;
504 uint32_t *portsc = &s->portsc[port->index];
505
506 DPRINTF("ehci_attach invoked for index %d, portsc 0x%x\n",
507 port->index, *portsc);
508
509 *portsc &= ~PORTSC_CONNECT;
510 *portsc |= PORTSC_CSC;
511
512 /*
513 * If a high speed device is attached then we own this port(indicated
514 * by zero in the PORTSC_POWNER bit field) so set the status bit
515 * and set an interrupt if enabled.
516 */
517 if ( !(*portsc & PORTSC_POWNER)) {
518 ehci_set_interrupt(s, USBSTS_PCD);
519 }
520 }
521
522 /* 4.1 host controller initialization */
523 static void ehci_reset(void *opaque)
524 {
525 EHCIState *s = opaque;
526 uint8_t *pci_conf;
527 int i;
528
529 pci_conf = s->dev.config;
530
531 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
532
533 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
534 s->usbsts = USBSTS_HALT;
535
536 s->astate = EST_INACTIVE;
537 s->pstate = EST_INACTIVE;
538 s->async_complete = 0;
539 s->isoch_pause = -1;
540 s->attach_poll_counter = 0;
541
542 for(i = 0; i < NB_PORTS; i++) {
543 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
544
545 if (s->ports[i].dev) {
546 usb_attach(&s->ports[i], s->ports[i].dev);
547 }
548 }
549 }
550
551 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
552 {
553 EHCIState *s = ptr;
554 uint32_t val;
555
556 val = s->mmio[addr];
557
558 return val;
559 }
560
561 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
562 {
563 EHCIState *s = ptr;
564 uint32_t val;
565
566 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
567
568 return val;
569 }
570
571 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
572 {
573 EHCIState *s = ptr;
574 uint32_t val;
575
576 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
577 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
578
579 return val;
580 }
581
582 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
583 {
584 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
585 exit(1);
586 }
587
588 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
589 {
590 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
591 exit(1);
592 }
593
594 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
595 {
596 uint32_t *portsc = &s->portsc[port];
597 int rwc;
598 USBDevice *dev = s->ports[port].dev;
599
600 DPRINTF("port_status_write: "
601 "PORTSC (port %d) curr %08X new %08X rw-clear %08X rw %08X\n",
602 port, *portsc, val, (val & PORTSC_RWC_MASK), val & PORTSC_RO_MASK);
603
604 rwc = val & PORTSC_RWC_MASK;
605 val &= PORTSC_RO_MASK;
606
607 // handle_read_write_clear(&val, portsc, PORTSC_PEDC | PORTSC_CSC);
608
609 *portsc &= ~rwc;
610
611 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
612 DPRINTF("port_status_write: USBTRAN Port %d reset begin\n", port);
613 }
614
615 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
616 DPRINTF("port_status_write: USBTRAN Port %d reset done\n", port);
617 usb_attach(&s->ports[port], dev);
618
619 // TODO how to handle reset of ports with no device
620 if (dev) {
621 usb_send_msg(dev, USB_MSG_RESET);
622 }
623
624 if (s->ports[port].dev) {
625 DPRINTF("port_status_write: "
626 "Device was connected before reset, clearing CSC bit\n");
627 *portsc &= ~PORTSC_CSC;
628 }
629
630 /* Table 2.16 Set the enable bit(and enable bit change) to indicate
631 * to SW that this port has a high speed device attached
632 *
633 * TODO - when to disable?
634 */
635 val |= PORTSC_PED;
636 val |= PORTSC_PEDC;
637 }
638
639 *portsc &= ~PORTSC_RO_MASK;
640 *portsc |= val;
641 DPRINTF("port_status_write: Port %d status set to 0x%08x\n", port, *portsc);
642 }
643
644 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
645 {
646 EHCIState *s = ptr;
647 int i;
648 #if EHCI_DEBUG
649 const char *str;
650 #endif
651
652 /* Only aligned reads are allowed on OHCI */
653 if (addr & 3) {
654 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
655 TARGET_FMT_plx "\n", addr);
656 return;
657 }
658
659 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
660 handle_port_status_write(s, (addr-PORTSC)/4, val);
661 return;
662 }
663
664 if (addr < OPREGBASE) {
665 fprintf(stderr, "usb-ehci: write attempt to read-only register"
666 TARGET_FMT_plx "\n", addr);
667 return;
668 }
669
670
671 /* Do any register specific pre-write processing here. */
672 #if EHCI_DEBUG
673 str = addr2str((unsigned) addr);
674 #endif
675 switch(addr) {
676 case USBCMD:
677 DPRINTF("ehci_mem_writel: USBCMD val=0x%08X, current cmd=0x%08X\n",
678 val, s->usbcmd);
679
680 if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
681 DPRINTF("ehci_mem_writel: %s run, clear halt\n", str);
682 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
683 SET_LAST_RUN_CLOCK(s);
684 s->usbsts &= ~USBSTS_HALT;
685 }
686
687 if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
688 DPRINTF(" ** STOP **\n");
689 qemu_del_timer(s->frame_timer);
690 // TODO - should finish out some stuff before setting halt
691 s->usbsts |= USBSTS_HALT;
692 }
693
694 if (val & USBCMD_HCRESET) {
695 DPRINTF("ehci_mem_writel: %s run, resetting\n", str);
696 ehci_reset(s);
697 val &= ~USBCMD_HCRESET;
698 }
699
700 /* not supporting dynamic frame list size at the moment */
701 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
702 fprintf(stderr, "attempt to set frame list size -- value %d\n",
703 val & USBCMD_FLS);
704 val &= ~USBCMD_FLS;
705 }
706 #if EHCI_DEBUG
707 if ((val & USBCMD_PSE) && !(s->usbcmd & USBCMD_PSE)) {
708 DPRINTF("periodic scheduling enabled\n");
709 }
710 if (!(val & USBCMD_PSE) && (s->usbcmd & USBCMD_PSE)) {
711 DPRINTF("periodic scheduling disabled\n");
712 }
713 if ((val & USBCMD_ASE) && !(s->usbcmd & USBCMD_ASE)) {
714 DPRINTF("asynchronous scheduling enabled\n");
715 }
716 if (!(val & USBCMD_ASE) && (s->usbcmd & USBCMD_ASE)) {
717 DPRINTF("asynchronous scheduling disabled\n");
718 }
719 if ((val & USBCMD_IAAD) && !(s->usbcmd & USBCMD_IAAD)) {
720 DPRINTF("doorbell request received\n");
721 }
722 if ((val & USBCMD_LHCR) && !(s->usbcmd & USBCMD_LHCR)) {
723 DPRINTF("light host controller reset received\n");
724 }
725 if ((val & USBCMD_ITC) != (s->usbcmd & USBCMD_ITC)) {
726 DPRINTF("interrupt threshold control set to %x\n",
727 (val & USBCMD_ITC)>>USBCMD_ITC_SH);
728 }
729 #endif
730 break;
731
732
733 case USBSTS:
734 val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO
735 DPRINTF("ehci_mem_writel: %s RWC set to 0x%08X\n", str, val);
736
737 val = (s->usbsts &= ~val); // bits 0 thru 5 are R/WC
738
739 DPRINTF("ehci_mem_writel: %s updating interrupt condition\n", str);
740 ehci_set_interrupt(s, 0);
741 break;
742
743
744 case USBINTR:
745 val &= USBINTR_MASK;
746 DPRINTF("ehci_mem_writel: %s set to 0x%08X\n", str, val);
747 break;
748
749 case FRINDEX:
750 s->sofv = val >> 3;
751 DPRINTF("ehci_mem_writel: %s set to 0x%08X\n", str, val);
752 break;
753
754 case CONFIGFLAG:
755 DPRINTF("ehci_mem_writel: %s set to 0x%08X\n", str, val);
756 val &= 0x1;
757 if (val) {
758 for(i = 0; i < NB_PORTS; i++)
759 s->portsc[i] &= ~PORTSC_POWNER;
760 }
761 break;
762
763 case PERIODICLISTBASE:
764 if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
765 fprintf(stderr,
766 "ehci: PERIODIC list base register set while periodic schedule\n"
767 " is enabled and HC is enabled\n");
768 }
769 DPRINTF("ehci_mem_writel: P-LIST BASE set to 0x%08X\n", val);
770 break;
771
772 case ASYNCLISTADDR:
773 if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
774 fprintf(stderr,
775 "ehci: ASYNC list address register set while async schedule\n"
776 " is enabled and HC is enabled\n");
777 }
778 DPRINTF("ehci_mem_writel: A-LIST ADDR set to 0x%08X\n", val);
779 break;
780 }
781
782 *(uint32_t *)(&s->mmio[addr]) = val;
783 }
784
785
786 // TODO : Put in common header file, duplication from usb-ohci.c
787
788 /* Get an array of dwords from main memory */
789 static inline int get_dwords(uint32_t addr, uint32_t *buf, int num)
790 {
791 int i;
792
793 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
794 cpu_physical_memory_rw(addr,(uint8_t *)buf, sizeof(*buf), 0);
795 *buf = le32_to_cpu(*buf);
796 }
797
798 return 1;
799 }
800
801 /* Put an array of dwords in to main memory */
802 static inline int put_dwords(uint32_t addr, uint32_t *buf, int num)
803 {
804 int i;
805
806 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
807 uint32_t tmp = cpu_to_le32(*buf);
808 cpu_physical_memory_rw(addr,(uint8_t *)&tmp, sizeof(tmp), 1);
809 }
810
811 return 1;
812 }
813
814 // 4.10.2
815
816 static int ehci_qh_do_overlay(EHCIState *ehci, EHCIqh *qh, EHCIqtd *qtd)
817 {
818 int i;
819 int dtoggle;
820 int ping;
821 int eps;
822 int reload;
823
824 // remember values in fields to preserve in qh after overlay
825
826 dtoggle = qh->token & QTD_TOKEN_DTOGGLE;
827 ping = qh->token & QTD_TOKEN_PING;
828
829 DPRINTF("setting qh.current from %08X to 0x%08X\n", qh->current_qtd,
830 ehci->qtdaddr);
831 qh->current_qtd = ehci->qtdaddr;
832 qh->next_qtd = qtd->next;
833 qh->altnext_qtd = qtd->altnext;
834 qh->token = qtd->token;
835
836
837 eps = get_field(qh->epchar, QH_EPCHAR_EPS);
838 if (eps == EHCI_QH_EPS_HIGH) {
839 qh->token &= ~QTD_TOKEN_PING;
840 qh->token |= ping;
841 }
842
843 reload = get_field(qh->epchar, QH_EPCHAR_RL);
844 set_field(&qh->altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
845
846 for (i = 0; i < 5; i++) {
847 qh->bufptr[i] = qtd->bufptr[i];
848 }
849
850 if (!(qh->epchar & QH_EPCHAR_DTC)) {
851 // preserve QH DT bit
852 qh->token &= ~QTD_TOKEN_DTOGGLE;
853 qh->token |= dtoggle;
854 }
855
856 qh->bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
857 qh->bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
858
859 put_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
860
861 return 0;
862 }
863
864 static int ehci_buffer_rw(uint8_t *buffer, EHCIqh *qh, int bytes, int rw)
865 {
866 int bufpos = 0;
867 int cpage, offset;
868 uint32_t head;
869 uint32_t tail;
870
871
872 if (!bytes) {
873 return 0;
874 }
875
876 cpage = get_field(qh->token, QTD_TOKEN_CPAGE);
877 if (cpage > 4) {
878 fprintf(stderr, "cpage out of range (%d)\n", cpage);
879 return USB_RET_PROCERR;
880 }
881
882 offset = qh->bufptr[0] & ~QTD_BUFPTR_MASK;
883 DPRINTF("ehci_buffer_rw: %sing %d bytes %08x cpage %d offset %d\n",
884 rw ? "writ" : "read", bytes, qh->bufptr[0], cpage, offset);
885
886 do {
887 /* start and end of this page */
888 head = qh->bufptr[cpage] & QTD_BUFPTR_MASK;
889 tail = head + ~QTD_BUFPTR_MASK + 1;
890 /* add offset into page */
891 head |= offset;
892
893 if (bytes <= (tail - head)) {
894 tail = head + bytes;
895 }
896
897 DPRINTF("DATA %s cpage:%d head:%08X tail:%08X target:%08X\n",
898 rw ? "WRITE" : "READ ", cpage, head, tail, bufpos);
899
900 cpu_physical_memory_rw(head, &buffer[bufpos], tail - head, rw);
901
902 bufpos += (tail - head);
903 bytes -= (tail - head);
904
905 if (bytes > 0) {
906 cpage++;
907 offset = 0;
908 }
909 } while (bytes > 0);
910
911 /* save cpage */
912 set_field(&qh->token, cpage, QTD_TOKEN_CPAGE);
913
914 /* save offset into cpage */
915 offset = tail - head;
916 qh->bufptr[0] &= ~QTD_BUFPTR_MASK;
917 qh->bufptr[0] |= offset;
918
919 return 0;
920 }
921
922 static void ehci_async_complete_packet(USBDevice *dev, USBPacket *packet)
923 {
924 EHCIState *ehci = container_of(packet, EHCIState, usb_packet);
925
926 DPRINTF("Async packet complete\n");
927 ehci->async_complete = 1;
928 ehci->exec_status = packet->len;
929 }
930
931 static int ehci_execute_complete(EHCIState *ehci, EHCIqh *qh, int ret)
932 {
933 int c_err, reload;
934
935 if (ret == USB_RET_ASYNC && !ehci->async_complete) {
936 DPRINTF("not done yet\n");
937 return ret;
938 }
939
940 ehci->async_complete = 0;
941
942 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
943 ehci->qhaddr, qh->next, ehci->qtdaddr, ret);
944
945 if (ret < 0) {
946 err:
947 /* TO-DO: put this is in a function that can be invoked below as well */
948 c_err = get_field(qh->token, QTD_TOKEN_CERR);
949 c_err--;
950 set_field(&qh->token, c_err, QTD_TOKEN_CERR);
951
952 switch(ret) {
953 case USB_RET_NODEV:
954 fprintf(stderr, "USB no device\n");
955 break;
956 case USB_RET_STALL:
957 fprintf(stderr, "USB stall\n");
958 qh->token |= QTD_TOKEN_HALT;
959 ehci_record_interrupt(ehci, USBSTS_ERRINT);
960 break;
961 case USB_RET_NAK:
962 /* 4.10.3 */
963 reload = get_field(qh->epchar, QH_EPCHAR_RL);
964 if ((ehci->pid == USB_TOKEN_IN) && reload) {
965 int nakcnt = get_field(qh->altnext_qtd, QH_ALTNEXT_NAKCNT);
966 nakcnt--;
967 set_field(&qh->altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
968 } else if (!reload) {
969 return USB_RET_NAK;
970 }
971 break;
972 case USB_RET_BABBLE:
973 fprintf(stderr, "USB babble TODO\n");
974 qh->token |= QTD_TOKEN_BABBLE;
975 ehci_record_interrupt(ehci, USBSTS_ERRINT);
976 break;
977 default:
978 fprintf(stderr, "USB invalid response %d to handle\n", ret);
979 /* TO-DO: transaction error */
980 ret = USB_RET_PROCERR;
981 break;
982 }
983 } else {
984 // DPRINTF("Short packet condition\n");
985 // TODO check 4.12 for splits
986
987 if ((ret > ehci->tbytes) && (ehci->pid == USB_TOKEN_IN)) {
988 ret = USB_RET_BABBLE;
989 goto err;
990 }
991
992 if (ehci->tbytes && ehci->pid == USB_TOKEN_IN) {
993 if (ehci_buffer_rw(ehci->buffer, qh, ret, 1) != 0) {
994 return USB_RET_PROCERR;
995 }
996 ehci->tbytes -= ret;
997 } else {
998 ehci->tbytes = 0;
999 }
1000
1001 DPRINTF("updating tbytes to %d\n", ehci->tbytes);
1002 set_field(&qh->token, ehci->tbytes, QTD_TOKEN_TBYTES);
1003 }
1004
1005 qh->token ^= QTD_TOKEN_DTOGGLE;
1006 qh->token &= ~QTD_TOKEN_ACTIVE;
1007
1008 if ((ret >= 0) && (qh->token & QTD_TOKEN_IOC)) {
1009 ehci_record_interrupt(ehci, USBSTS_INT);
1010 }
1011
1012 return ret;
1013 }
1014
1015 // 4.10.3
1016
1017 static int ehci_execute(EHCIState *ehci, EHCIqh *qh)
1018 {
1019 USBPort *port;
1020 USBDevice *dev;
1021 int ret;
1022 int i;
1023 int endp;
1024 int devadr;
1025
1026 if ( !(qh->token & QTD_TOKEN_ACTIVE)) {
1027 fprintf(stderr, "Attempting to execute inactive QH\n");
1028 return USB_RET_PROCERR;
1029 }
1030
1031 ehci->tbytes = (qh->token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1032 if (ehci->tbytes > BUFF_SIZE) {
1033 fprintf(stderr, "Request for more bytes than allowed\n");
1034 return USB_RET_PROCERR;
1035 }
1036
1037 ehci->pid = (qh->token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1038 switch(ehci->pid) {
1039 case 0: ehci->pid = USB_TOKEN_OUT; break;
1040 case 1: ehci->pid = USB_TOKEN_IN; break;
1041 case 2: ehci->pid = USB_TOKEN_SETUP; break;
1042 default: fprintf(stderr, "bad token\n"); break;
1043 }
1044
1045 if ((ehci->tbytes && ehci->pid != USB_TOKEN_IN) &&
1046 (ehci_buffer_rw(ehci->buffer, qh, ehci->tbytes, 0) != 0)) {
1047 return USB_RET_PROCERR;
1048 }
1049
1050 endp = get_field(qh->epchar, QH_EPCHAR_EP);
1051 devadr = get_field(qh->epchar, QH_EPCHAR_DEVADDR);
1052
1053 ret = USB_RET_NODEV;
1054
1055 // TO-DO: associating device with ehci port
1056 for(i = 0; i < NB_PORTS; i++) {
1057 port = &ehci->ports[i];
1058 dev = port->dev;
1059
1060 // TODO sometime we will also need to check if we are the port owner
1061
1062 if (!(ehci->portsc[i] &(PORTSC_CONNECT))) {
1063 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1064 i, ehci->portsc[i]);
1065 continue;
1066 }
1067
1068 ehci->usb_packet.pid = ehci->pid;
1069 ehci->usb_packet.devaddr = devadr;
1070 ehci->usb_packet.devep = endp;
1071 ehci->usb_packet.data = ehci->buffer;
1072 ehci->usb_packet.len = ehci->tbytes;
1073
1074 ret = usb_handle_packet(dev, &ehci->usb_packet);
1075
1076 DPRINTF("submit: qh %x next %x qtd %x pid %x len %d (total %d) endp %x ret %d\n",
1077 ehci->qhaddr, qh->next, ehci->qtdaddr, ehci->pid,
1078 ehci->usb_packet.len, ehci->tbytes, endp, ret);
1079
1080 if (ret != USB_RET_NODEV) {
1081 break;
1082 }
1083 }
1084
1085 if (ret > BUFF_SIZE) {
1086 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1087 return USB_RET_PROCERR;
1088 }
1089
1090 if (ret == USB_RET_ASYNC) {
1091 ehci->async_complete = 0;
1092 }
1093
1094 return ret;
1095 }
1096
1097 /* 4.7.2
1098 */
1099
1100 static int ehci_process_itd(EHCIState *ehci,
1101 EHCIitd *itd)
1102 {
1103 USBPort *port;
1104 USBDevice *dev;
1105 int ret;
1106 int i, j;
1107 int ptr;
1108 int pid;
1109 int pg;
1110 int len;
1111 int dir;
1112 int devadr;
1113 int endp;
1114 int maxpkt;
1115
1116 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1117 devadr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1118 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1119 maxpkt = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1120
1121 for(i = 0; i < 8; i++) {
1122 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1123 DPRINTF("ISOCHRONOUS active for frame %d, interval %d\n",
1124 ehci->frindex >> 3, i);
1125
1126 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1127 ptr = (itd->bufptr[pg] & ITD_BUFPTR_MASK) |
1128 (itd->transact[i] & ITD_XACT_OFFSET_MASK);
1129 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1130
1131 if (len > BUFF_SIZE) {
1132 return USB_RET_PROCERR;
1133 }
1134
1135 DPRINTF("ISOCH: buffer %08X len %d\n", ptr, len);
1136
1137 if (!dir) {
1138 cpu_physical_memory_rw(ptr, &ehci->buffer[0], len, 0);
1139 pid = USB_TOKEN_OUT;
1140 } else
1141 pid = USB_TOKEN_IN;
1142
1143 ret = USB_RET_NODEV;
1144
1145 for (j = 0; j < NB_PORTS; j++) {
1146 port = &ehci->ports[j];
1147 dev = port->dev;
1148
1149 // TODO sometime we will also need to check if we are the port owner
1150
1151 if (!(ehci->portsc[j] &(PORTSC_CONNECT))) {
1152 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1153 j, ehci->portsc[j]);
1154 continue;
1155 }
1156
1157 ehci->usb_packet.pid = ehci->pid;
1158 ehci->usb_packet.devaddr = devadr;
1159 ehci->usb_packet.devep = endp;
1160 ehci->usb_packet.data = ehci->buffer;
1161 ehci->usb_packet.len = len;
1162
1163 DPRINTF("calling usb_handle_packet\n");
1164 ret = usb_handle_packet(dev, &ehci->usb_packet);
1165
1166 if (ret != USB_RET_NODEV) {
1167 break;
1168 }
1169 }
1170
1171 /* In isoch, there is no facility to indicate a NAK so let's
1172 * instead just complete a zero-byte transaction. Setting
1173 * DBERR seems too draconian.
1174 */
1175
1176 if (ret == USB_RET_NAK) {
1177 if (ehci->isoch_pause > 0) {
1178 DPRINTF("ISOCH: received a NAK but paused so returning\n");
1179 ehci->isoch_pause--;
1180 return 0;
1181 } else if (ehci->isoch_pause == -1) {
1182 DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n");
1183 // Pause frindex for up to 50 msec waiting for data from
1184 // remote
1185 ehci->isoch_pause = 50;
1186 return 0;
1187 } else {
1188 DPRINTF("ISOCH: isoch pause timeout! return 0\n");
1189 ret = 0;
1190 }
1191 } else {
1192 DPRINTF("ISOCH: received ACK, clearing pause\n");
1193 ehci->isoch_pause = -1;
1194 }
1195
1196 if (ret >= 0) {
1197 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1198
1199 if (itd->transact[i] & ITD_XACT_IOC) {
1200 ehci_record_interrupt(ehci, USBSTS_INT);
1201 }
1202 }
1203
1204 if (ret >= 0 && dir) {
1205 cpu_physical_memory_rw(ptr, &ehci->buffer[0], len, 1);
1206
1207 if (ret != len) {
1208 DPRINTF("ISOCH IN expected %d, got %d\n",
1209 len, ret);
1210 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1211 }
1212 }
1213 }
1214 }
1215 return 0;
1216 }
1217
1218 /* This state is the entry point for asynchronous schedule
1219 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1220 */
1221 static int ehci_state_waitlisthead(EHCIState *ehci, int async, int *state)
1222 {
1223 EHCIqh *qh = &ehci->qh;
1224 int i = 0;
1225 int again = 0;
1226 uint32_t entry = ehci->asynclistaddr;
1227
1228 /* set reclamation flag at start event (4.8.6) */
1229 if (async) {
1230 ehci->usbsts |= USBSTS_REC;
1231 }
1232
1233 /* Find the head of the list (4.9.1.1) */
1234 for(i = 0; i < MAX_QH; i++) {
1235 get_dwords(NLPTR_GET(entry), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
1236
1237 if (qh->epchar & QH_EPCHAR_H) {
1238 DPRINTF_ST("WAITLISTHEAD: QH %08X is the HEAD of the list\n",
1239 entry);
1240 if (async) {
1241 entry |= (NLPTR_TYPE_QH << 1);
1242 }
1243
1244 ehci->fetch_addr = entry;
1245 *state = EST_FETCHENTRY;
1246 again = 1;
1247 goto out;
1248 }
1249
1250 DPRINTF_ST("WAITLISTHEAD: QH %08X is NOT the HEAD of the list\n",
1251 entry);
1252 entry = qh->next;
1253 if (entry == ehci->asynclistaddr) {
1254 DPRINTF("WAITLISTHEAD: reached beginning of QH list\n");
1255 break;
1256 }
1257 }
1258
1259 /* no head found for list. */
1260
1261 *state = EST_ACTIVE;
1262
1263 out:
1264 return again;
1265 }
1266
1267
1268 /* This state is the entry point for periodic schedule processing as
1269 * well as being a continuation state for async processing.
1270 */
1271 static int ehci_state_fetchentry(EHCIState *ehci, int async, int *state)
1272 {
1273 int again = 0;
1274 uint32_t entry = ehci->fetch_addr;
1275
1276 #if EHCI_DEBUG == 0
1277 if (qemu_get_clock_ns(vm_clock) / 1000 >= ehci->frame_end_usec) {
1278 if (async) {
1279 DPRINTF("FETCHENTRY: FRAME timer elapsed, exit state machine\n");
1280 goto out;
1281 } else {
1282 DPRINTF("FETCHENTRY: WARNING "
1283 "- frame timer elapsed during periodic\n");
1284 }
1285 }
1286 #endif
1287 if (entry < 0x1000) {
1288 DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry);
1289 *state = EST_ACTIVE;
1290 goto out;
1291 }
1292
1293 /* section 4.8, only QH in async schedule */
1294 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1295 fprintf(stderr, "non queue head request in async schedule\n");
1296 return -1;
1297 }
1298
1299 switch (NLPTR_TYPE_GET(entry)) {
1300 case NLPTR_TYPE_QH:
1301 DPRINTF_ST("FETCHENTRY: entry %X is a Queue Head\n", entry);
1302 *state = EST_FETCHQH;
1303 ehci->qhaddr = entry;
1304 again = 1;
1305 break;
1306
1307 case NLPTR_TYPE_ITD:
1308 DPRINTF_ST("FETCHENTRY: entry %X is an ITD\n", entry);
1309 *state = EST_FETCHITD;
1310 ehci->itdaddr = entry;
1311 again = 1;
1312 break;
1313
1314 default:
1315 // TODO: handle siTD and FSTN types
1316 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1317 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1318 return -1;
1319 }
1320
1321 out:
1322 return again;
1323 }
1324
1325 static int ehci_state_fetchqh(EHCIState *ehci, int async, int *state)
1326 {
1327 EHCIqh *qh = &ehci->qh;
1328 int reload;
1329 int again = 0;
1330
1331 get_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
1332
1333 if (async && (qh->epchar & QH_EPCHAR_H)) {
1334
1335 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1336 if (ehci->usbsts & USBSTS_REC) {
1337 ehci->usbsts &= ~USBSTS_REC;
1338 } else {
1339 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1340 " - done processing\n", ehci->qhaddr);
1341 *state = EST_ACTIVE;
1342 goto out;
1343 }
1344 }
1345
1346 #if EHCI_DEBUG
1347 if (ehci->qhaddr != qh->next) {
1348 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1349 ehci->qhaddr,
1350 qh->epchar & QH_EPCHAR_H,
1351 qh->token & QTD_TOKEN_HALT,
1352 qh->token & QTD_TOKEN_ACTIVE,
1353 qh->next);
1354 }
1355 #endif
1356
1357 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1358 if (reload) {
1359 DPRINTF_ST("FETCHQH: reloading nakcnt to %d\n", reload);
1360 set_field(&qh->altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1361 }
1362
1363 if (qh->token & QTD_TOKEN_HALT) {
1364 DPRINTF_ST("FETCHQH: QH Halted, go horizontal\n");
1365 *state = EST_HORIZONTALQH;
1366 again = 1;
1367
1368 } else if ((qh->token & QTD_TOKEN_ACTIVE) && (qh->current_qtd > 0x1000)) {
1369 DPRINTF_ST("FETCHQH: Active, !Halt, execute - fetch qTD\n");
1370 ehci->qtdaddr = qh->current_qtd;
1371 *state = EST_FETCHQTD;
1372 again = 1;
1373
1374 } else {
1375 /* EHCI spec version 1.0 Section 4.10.2 */
1376 DPRINTF_ST("FETCHQH: !Active, !Halt, advance queue\n");
1377 *state = EST_ADVANCEQUEUE;
1378 again = 1;
1379 }
1380
1381 out:
1382 return again;
1383 }
1384
1385 static int ehci_state_fetchitd(EHCIState *ehci, int async, int *state)
1386 {
1387 EHCIitd itd;
1388
1389 get_dwords(NLPTR_GET(ehci->itdaddr),(uint32_t *) &itd,
1390 sizeof(EHCIitd) >> 2);
1391 DPRINTF_ST("FETCHITD: Fetched ITD at address %08X " "(next is %08X)\n",
1392 ehci->itdaddr, itd.next);
1393
1394 if (ehci_process_itd(ehci, &itd) != 0) {
1395 return -1;
1396 }
1397
1398 put_dwords(NLPTR_GET(ehci->itdaddr), (uint32_t *) &itd,
1399 sizeof(EHCIitd) >> 2);
1400 ehci->fetch_addr = itd.next;
1401 *state = EST_FETCHENTRY;
1402
1403 return 1;
1404 }
1405
1406 /* Section 4.10.2 - paragraph 3 */
1407 static int ehci_state_advqueue(EHCIState *ehci, int async, int *state)
1408 {
1409 #if 0
1410 /* TO-DO: 4.10.2 - paragraph 2
1411 * if I-bit is set to 1 and QH is not active
1412 * go to horizontal QH
1413 */
1414 if (I-bit set) {
1415 *state = EST_HORIZONTALQH;
1416 goto out;
1417 }
1418 #endif
1419
1420 /*
1421 * want data and alt-next qTD is valid
1422 */
1423 if (((ehci->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1424 (ehci->qh.altnext_qtd > 0x1000) &&
1425 (NLPTR_TBIT(ehci->qh.altnext_qtd) == 0)) {
1426 DPRINTF_ST("ADVQUEUE: goto alt next qTD. "
1427 "curr 0x%08x next 0x%08x alt 0x%08x (next qh %x)\n",
1428 ehci->qh.current_qtd, ehci->qh.altnext_qtd,
1429 ehci->qh.next_qtd, ehci->qh.next);
1430 ehci->qtdaddr = ehci->qh.altnext_qtd;
1431 *state = EST_FETCHQTD;
1432
1433 /*
1434 * next qTD is valid
1435 */
1436 } else if ((ehci->qh.next_qtd > 0x1000) &&
1437 (NLPTR_TBIT(ehci->qh.next_qtd) == 0)) {
1438 DPRINTF_ST("ADVQUEUE: next qTD. "
1439 "curr 0x%08x next 0x%08x alt 0x%08x (next qh %x)\n",
1440 ehci->qh.current_qtd, ehci->qh.altnext_qtd,
1441 ehci->qh.next_qtd, ehci->qh.next);
1442 ehci->qtdaddr = ehci->qh.next_qtd;
1443 *state = EST_FETCHQTD;
1444
1445 /*
1446 * no valid qTD, try next QH
1447 */
1448 } else {
1449 DPRINTF_ST("ADVQUEUE: go to horizontal QH\n");
1450 *state = EST_HORIZONTALQH;
1451 }
1452
1453 return 1;
1454 }
1455
1456 /* Section 4.10.2 - paragraph 4 */
1457 static int ehci_state_fetchqtd(EHCIState *ehci, int async, int *state)
1458 {
1459 EHCIqtd *qtd = &ehci->qtd;
1460 int again = 0;
1461
1462 get_dwords(NLPTR_GET(ehci->qtdaddr),(uint32_t *) qtd, sizeof(EHCIqtd) >> 2);
1463
1464 if (qtd->token & QTD_TOKEN_ACTIVE) {
1465 *state = EST_EXECUTE;
1466 again = 1;
1467 } else {
1468 *state = EST_HORIZONTALQH;
1469 again = 1;
1470 }
1471
1472 return again;
1473 }
1474
1475 static int ehci_state_horizqh(EHCIState *ehci, int async, int *state)
1476 {
1477 int again = 0;
1478
1479 if (ehci->fetch_addr != ehci->qh.next) {
1480 ehci->fetch_addr = ehci->qh.next;
1481 *state = EST_FETCHENTRY;
1482 again = 1;
1483 } else {
1484 *state = EST_ACTIVE;
1485 }
1486
1487 return again;
1488 }
1489
1490 static int ehci_state_execute(EHCIState *ehci, int async, int *state)
1491 {
1492 EHCIqh *qh = &ehci->qh;
1493 EHCIqtd *qtd = &ehci->qtd;
1494 int again = 0;
1495 int reload, nakcnt;
1496 int smask;
1497
1498 if (async) {
1499 DPRINTF_ST(">>>>> ASYNC STATE MACHINE execute QH 0x%08x, QTD 0x%08x\n",
1500 ehci->qhaddr, ehci->qtdaddr);
1501 } else {
1502 DPRINTF_ST(">>>>> PERIODIC STATE MACHINE execute\n");
1503 }
1504
1505 if (ehci_qh_do_overlay(ehci, qh, qtd) != 0) {
1506 return -1;
1507 }
1508
1509 smask = get_field(qh->epcap, QH_EPCAP_SMASK);
1510
1511 if (!smask) {
1512 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1513 nakcnt = get_field(qh->altnext_qtd, QH_ALTNEXT_NAKCNT);
1514 if (reload && !nakcnt) {
1515 DPRINTF_ST("EXECUTE: RL != 0 but NakCnt == 0 -- no execute\n");
1516 *state = EST_HORIZONTALQH;
1517 again = 1;
1518 goto out;
1519 }
1520 }
1521
1522 // TODO verify enough time remains in the uframe as in 4.4.1.1
1523 // TODO write back ptr to async list when done or out of time
1524 // TODO Windows does not seem to ever set the MULT field
1525
1526 if (!async) {
1527 int transactCtr = get_field(qh->epcap, QH_EPCAP_MULT);
1528 if (!transactCtr) {
1529 DPRINTF("ZERO transactctr for int qh, go HORIZ\n");
1530 *state = EST_HORIZONTALQH;
1531 again = 1;
1532 goto out;
1533 }
1534 }
1535
1536 if (async) {
1537 ehci->usbsts |= USBSTS_REC;
1538 }
1539
1540 ehci->exec_status = ehci_execute(ehci, qh);
1541 if (ehci->exec_status == USB_RET_PROCERR) {
1542 again = -1;
1543 goto out;
1544 }
1545 *state = EST_EXECUTING;
1546
1547 if (ehci->exec_status != USB_RET_ASYNC) {
1548 again = 1;
1549 }
1550
1551 out:
1552 return again;
1553 }
1554
1555 static int ehci_state_executing(EHCIState *ehci, int async, int *state)
1556 {
1557 EHCIqh *qh = &ehci->qh;
1558 int again = 0;
1559 int reload, nakcnt;
1560
1561 ehci->exec_status = ehci_execute_complete(ehci, qh, ehci->exec_status);
1562 if (ehci->exec_status == USB_RET_ASYNC) {
1563 goto out;
1564 }
1565 if (ehci->exec_status == USB_RET_PROCERR) {
1566 again = -1;
1567 goto out;
1568 }
1569
1570 // 4.10.3
1571 if (!async) {
1572 int transactCtr = get_field(qh->epcap, QH_EPCAP_MULT);
1573 transactCtr--;
1574 set_field(&qh->epcap, transactCtr, QH_EPCAP_MULT);
1575 // 4.10.3, bottom of page 82, should exit this state when transaction
1576 // counter decrements to 0
1577 }
1578
1579
1580 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1581 if (reload) {
1582 nakcnt = get_field(qh->altnext_qtd, QH_ALTNEXT_NAKCNT);
1583 if (ehci->exec_status == USB_RET_NAK) {
1584 if (nakcnt) {
1585 nakcnt--;
1586 }
1587 DPRINTF_ST("EXECUTING: Nak occured and RL != 0, dec NakCnt to %d\n",
1588 nakcnt);
1589 } else {
1590 nakcnt = reload;
1591 DPRINTF_ST("EXECUTING: Nak didn't occur, reloading to %d\n",
1592 nakcnt);
1593 }
1594 set_field(&qh->altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1595 }
1596
1597 /*
1598 * Write the qh back to guest physical memory. This step isn't
1599 * in the EHCI spec but we need to do it since we don't share
1600 * physical memory with our guest VM.
1601 */
1602
1603 DPRINTF("EXECUTING: write QH to VM memory: qhaddr 0x%x, next 0x%x\n",
1604 ehci->qhaddr, qh->next);
1605 put_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
1606
1607 /* 4.10.5 */
1608 if ((ehci->exec_status == USB_RET_NAK) || (qh->token & QTD_TOKEN_ACTIVE)) {
1609 *state = EST_HORIZONTALQH;
1610 } else {
1611 *state = EST_WRITEBACK;
1612 }
1613
1614 again = 1;
1615
1616 out:
1617 return again;
1618 }
1619
1620
1621 static int ehci_state_writeback(EHCIState *ehci, int async, int *state)
1622 {
1623 EHCIqh *qh = &ehci->qh;
1624 int again = 0;
1625
1626 /* Write back the QTD from the QH area */
1627 DPRINTF_ST("WRITEBACK: write QTD to VM memory\n");
1628 put_dwords(NLPTR_GET(ehci->qtdaddr),(uint32_t *) &qh->next_qtd,
1629 sizeof(EHCIqtd) >> 2);
1630
1631 /* TODO confirm next state. For now, keep going if async
1632 * but stop after one qtd if periodic
1633 */
1634 //if (async) {
1635 *state = EST_ADVANCEQUEUE;
1636 again = 1;
1637 //} else {
1638 // *state = EST_ACTIVE;
1639 //}
1640 return again;
1641 }
1642
1643 /*
1644 * This is the state machine that is common to both async and periodic
1645 */
1646
1647 static int ehci_advance_state(EHCIState *ehci,
1648 int async,
1649 int state)
1650 {
1651 int again;
1652 int iter = 0;
1653
1654 do {
1655 if (state == EST_FETCHQH) {
1656 iter++;
1657 /* if we are roaming a lot of QH without executing a qTD
1658 * something is wrong with the linked list. TO-DO: why is
1659 * this hack needed?
1660 */
1661 if (iter > MAX_ITERATIONS) {
1662 DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n");
1663 state = EST_ACTIVE;
1664 break;
1665 }
1666 }
1667 switch(state) {
1668 case EST_WAITLISTHEAD:
1669 again = ehci_state_waitlisthead(ehci, async, &state);
1670 break;
1671
1672 case EST_FETCHENTRY:
1673 again = ehci_state_fetchentry(ehci, async, &state);
1674 break;
1675
1676 case EST_FETCHQH:
1677 again = ehci_state_fetchqh(ehci, async, &state);
1678 break;
1679
1680 case EST_FETCHITD:
1681 again = ehci_state_fetchitd(ehci, async, &state);
1682 break;
1683
1684 case EST_ADVANCEQUEUE:
1685 again = ehci_state_advqueue(ehci, async, &state);
1686 break;
1687
1688 case EST_FETCHQTD:
1689 again = ehci_state_fetchqtd(ehci, async, &state);
1690 break;
1691
1692 case EST_HORIZONTALQH:
1693 again = ehci_state_horizqh(ehci, async, &state);
1694 break;
1695
1696 case EST_EXECUTE:
1697 iter = 0;
1698 again = ehci_state_execute(ehci, async, &state);
1699 break;
1700
1701 case EST_EXECUTING:
1702 again = ehci_state_executing(ehci, async, &state);
1703 break;
1704
1705 case EST_WRITEBACK:
1706 again = ehci_state_writeback(ehci, async, &state);
1707 break;
1708
1709 default:
1710 fprintf(stderr, "Bad state!\n");
1711 again = -1;
1712 break;
1713 }
1714
1715 if (again < 0) {
1716 fprintf(stderr, "processing error - resetting ehci HC\n");
1717 ehci_reset(ehci);
1718 again = 0;
1719 }
1720 }
1721 while (again);
1722
1723 ehci_commit_interrupt(ehci);
1724 return state;
1725 }
1726
1727 static void ehci_advance_async_state(EHCIState *ehci)
1728 {
1729 EHCIqh qh;
1730 int state = ehci->astate;
1731
1732 switch(state) {
1733 case EST_INACTIVE:
1734 if (!(ehci->usbcmd & USBCMD_ASE)) {
1735 break;
1736 }
1737 ehci->usbsts |= USBSTS_ASS;
1738 ehci->astate = EST_ACTIVE;
1739 // No break, fall through to ACTIVE
1740
1741 case EST_ACTIVE:
1742 if ( !(ehci->usbcmd & USBCMD_ASE)) {
1743 ehci->usbsts &= ~USBSTS_ASS;
1744 ehci->astate = EST_INACTIVE;
1745 break;
1746 }
1747
1748 /* If the doorbell is set, the guest wants to make a change to the
1749 * schedule. The host controller needs to release cached data.
1750 * (section 4.8.2)
1751 */
1752 if (ehci->usbcmd & USBCMD_IAAD) {
1753 DPRINTF("ASYNC: doorbell request acknowledged\n");
1754 ehci->usbcmd &= ~USBCMD_IAAD;
1755 ehci_set_interrupt(ehci, USBSTS_IAA);
1756 break;
1757 }
1758
1759 /* make sure guest has acknowledged */
1760 /* TO-DO: is this really needed? */
1761 if (ehci->usbsts & USBSTS_IAA) {
1762 DPRINTF("IAA status bit still set.\n");
1763 break;
1764 }
1765
1766 DPRINTF_ST("ASYNC: waiting for listhead, starting at %08x\n",
1767 ehci->asynclistaddr);
1768 /* check that address register has been set */
1769 if (ehci->asynclistaddr == 0) {
1770 break;
1771 }
1772
1773 state = EST_WAITLISTHEAD;
1774 /* fall through */
1775
1776 case EST_FETCHENTRY:
1777 /* fall through */
1778
1779 case EST_EXECUTING:
1780 get_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) &qh,
1781 sizeof(EHCIqh) >> 2);
1782 ehci->astate = ehci_advance_state(ehci, 1, state);
1783 break;
1784
1785 default:
1786 /* this should only be due to a developer mistake */
1787 fprintf(stderr, "ehci: Bad asynchronous state %d. "
1788 "Resetting to active\n", ehci->astate);
1789 ehci->astate = EST_ACTIVE;
1790 }
1791 }
1792
1793 static void ehci_advance_periodic_state(EHCIState *ehci)
1794 {
1795 uint32_t entry;
1796 uint32_t list;
1797
1798 // 4.6
1799
1800 switch(ehci->pstate) {
1801 case EST_INACTIVE:
1802 if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) {
1803 DPRINTF("PERIODIC going active\n");
1804 ehci->usbsts |= USBSTS_PSS;
1805 ehci->pstate = EST_ACTIVE;
1806 // No break, fall through to ACTIVE
1807 } else
1808 break;
1809
1810 case EST_ACTIVE:
1811 if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) {
1812 DPRINTF("PERIODIC going inactive\n");
1813 ehci->usbsts &= ~USBSTS_PSS;
1814 ehci->pstate = EST_INACTIVE;
1815 break;
1816 }
1817
1818 list = ehci->periodiclistbase & 0xfffff000;
1819 /* check that register has been set */
1820 if (list == 0) {
1821 break;
1822 }
1823 list |= ((ehci->frindex & 0x1ff8) >> 1);
1824
1825 cpu_physical_memory_rw(list, (uint8_t *) &entry, sizeof entry, 0);
1826 entry = le32_to_cpu(entry);
1827
1828 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
1829 ehci->frindex / 8, list, entry);
1830 ehci->fetch_addr = entry;
1831 ehci->pstate = ehci_advance_state(ehci, 0, EST_FETCHENTRY);
1832 break;
1833
1834 case EST_EXECUTING:
1835 DPRINTF("PERIODIC state adv for executing\n");
1836 ehci->pstate = ehci_advance_state(ehci, 0, EST_EXECUTING);
1837 break;
1838
1839 default:
1840 /* this should only be due to a developer mistake */
1841 fprintf(stderr, "ehci: Bad periodic state %d. "
1842 "Resetting to active\n", ehci->pstate);
1843 ehci->pstate = EST_ACTIVE;
1844 }
1845 }
1846
1847 static void ehci_frame_timer(void *opaque)
1848 {
1849 EHCIState *ehci = opaque;
1850 int64_t expire_time, t_now;
1851 int usec_elapsed;
1852 int frames;
1853 int usec_now;
1854 int i;
1855 int skipped_frames = 0;
1856
1857
1858 t_now = qemu_get_clock_ns(vm_clock);
1859 expire_time = t_now + (get_ticks_per_sec() / FRAME_TIMER_FREQ);
1860 if (expire_time == t_now) {
1861 expire_time++;
1862 }
1863
1864 usec_now = t_now / 1000;
1865 usec_elapsed = usec_now - ehci->last_run_usec;
1866 frames = usec_elapsed / FRAME_TIMER_USEC;
1867 ehci->frame_end_usec = usec_now + FRAME_TIMER_USEC - 10;
1868
1869 for (i = 0; i < frames; i++) {
1870 if ( !(ehci->usbsts & USBSTS_HALT)) {
1871 if (ehci->isoch_pause <= 0) {
1872 ehci->frindex += 8;
1873 }
1874
1875 if (ehci->frindex > 0x00001fff) {
1876 ehci->frindex = 0;
1877 ehci_set_interrupt(ehci, USBSTS_FLR);
1878 }
1879
1880 ehci->sofv = (ehci->frindex - 1) >> 3;
1881 ehci->sofv &= 0x000003ff;
1882 }
1883
1884 if (frames - i > 10) {
1885 skipped_frames++;
1886 } else {
1887 // TODO could this cause periodic frames to get skipped if async
1888 // active?
1889 if (ehci->astate != EST_EXECUTING) {
1890 ehci_advance_periodic_state(ehci);
1891 }
1892 }
1893
1894 ehci->last_run_usec += FRAME_TIMER_USEC;
1895 }
1896
1897 #if 0
1898 if (skipped_frames) {
1899 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
1900 }
1901 #endif
1902
1903 /* Async is not inside loop since it executes everything it can once
1904 * called
1905 */
1906 if (ehci->pstate != EST_EXECUTING) {
1907 ehci_advance_async_state(ehci);
1908 }
1909
1910 qemu_mod_timer(ehci->frame_timer, expire_time);
1911 }
1912
1913 static CPUReadMemoryFunc *ehci_readfn[3]={
1914 ehci_mem_readb,
1915 ehci_mem_readw,
1916 ehci_mem_readl
1917 };
1918
1919 static CPUWriteMemoryFunc *ehci_writefn[3]={
1920 ehci_mem_writeb,
1921 ehci_mem_writew,
1922 ehci_mem_writel
1923 };
1924
1925 static void ehci_map(PCIDevice *pci_dev, int region_num,
1926 pcibus_t addr, pcibus_t size, int type)
1927 {
1928 EHCIState *s =(EHCIState *)pci_dev;
1929
1930 DPRINTF("ehci_map: region %d, addr %08" PRIx64 ", size %" PRId64 ", s->mem %08X\n",
1931 region_num, addr, size, s->mem);
1932 s->mem_base = addr;
1933 cpu_register_physical_memory(addr, size, s->mem);
1934 }
1935
1936 static int usb_ehci_initfn(PCIDevice *dev);
1937
1938 static USBPortOps ehci_port_ops = {
1939 .attach = ehci_attach,
1940 .detach = ehci_detach,
1941 .complete = ehci_async_complete_packet,
1942 };
1943
1944 static PCIDeviceInfo ehci_info = {
1945 .qdev.name = "usb-ehci",
1946 .qdev.size = sizeof(EHCIState),
1947 .init = usb_ehci_initfn,
1948 };
1949
1950 static int usb_ehci_initfn(PCIDevice *dev)
1951 {
1952 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
1953 uint8_t *pci_conf = s->dev.config;
1954 int i;
1955
1956 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
1957 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82801D);
1958 pci_set_byte(&pci_conf[PCI_REVISION_ID], 0x10);
1959 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
1960 pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB);
1961 pci_set_byte(&pci_conf[PCI_HEADER_TYPE], PCI_HEADER_TYPE_NORMAL);
1962
1963 /* capabilities pointer */
1964 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
1965 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
1966
1967 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); // interrupt pin 3
1968 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
1969 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
1970
1971 // pci_conf[0x50] = 0x01; // power management caps
1972
1973 pci_set_byte(&pci_conf[0x60], 0x20); // spec release number (2.1.4)
1974 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
1975 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
1976
1977 pci_conf[0x64] = 0x00;
1978 pci_conf[0x65] = 0x00;
1979 pci_conf[0x66] = 0x00;
1980 pci_conf[0x67] = 0x00;
1981 pci_conf[0x68] = 0x01;
1982 pci_conf[0x69] = 0x00;
1983 pci_conf[0x6a] = 0x00;
1984 pci_conf[0x6b] = 0x00; // USBLEGSUP
1985 pci_conf[0x6c] = 0x00;
1986 pci_conf[0x6d] = 0x00;
1987 pci_conf[0x6e] = 0x00;
1988 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
1989
1990 // 2.2 host controller interface version
1991 s->mmio[0x00] = (uint8_t) OPREGBASE;
1992 s->mmio[0x01] = 0x00;
1993 s->mmio[0x02] = 0x00;
1994 s->mmio[0x03] = 0x01; // HC version
1995 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
1996 s->mmio[0x05] = 0x00; // No companion ports at present
1997 s->mmio[0x06] = 0x00;
1998 s->mmio[0x07] = 0x00;
1999 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2000 s->mmio[0x09] = 0x68; // EECP
2001 s->mmio[0x0a] = 0x00;
2002 s->mmio[0x0b] = 0x00;
2003
2004 s->irq = s->dev.irq[3];
2005
2006 usb_bus_new(&s->bus, &s->dev.qdev);
2007 for(i = 0; i < NB_PORTS; i++) {
2008 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2009 USB_SPEED_MASK_HIGH);
2010 usb_port_location(&s->ports[i], NULL, i+1);
2011 s->ports[i].dev = 0;
2012 }
2013
2014 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2015
2016 qemu_register_reset(ehci_reset, s);
2017
2018 s->mem = cpu_register_io_memory(ehci_readfn, ehci_writefn, s,
2019 DEVICE_LITTLE_ENDIAN);
2020
2021 pci_register_bar(&s->dev, 0, MMIO_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
2022 ehci_map);
2023
2024 fprintf(stderr, "*** EHCI support is under development ***\n");
2025
2026 return 0;
2027 }
2028
2029 static void ehci_register(void)
2030 {
2031 pci_qdev_register(&ehci_info);
2032 }
2033 device_init(ehci_register);
2034
2035 /*
2036 * vim: expandtab ts=4
2037 */
QEmu