hw/pci-host/gpex-acpi.c

   1 #include "qemu/osdep.h"
   2 #include "hw/acpi/aml-build.h"
   3 #include "hw/pci-host/gpex.h"
   4
   5 static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq)
   6 {
   7     Aml *method, *crs;
   8     int i, slot_no;
   9
  10     /* Declare the PCI Routing Table. */
  11     Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS);
  12     for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) {
  13         for (i = 0; i < PCI_NUM_PINS; i++) {
  14             int gsi = (i + slot_no) % PCI_NUM_PINS;
  15             Aml *pkg = aml_package(4);
  16             aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF));
  17             aml_append(pkg, aml_int(i));
  18             aml_append(pkg, aml_name("GSI%d", gsi));
  19             aml_append(pkg, aml_int(0));
  20             aml_append(rt_pkg, pkg);
  21         }
  22     }
  23     aml_append(dev, aml_name_decl("_PRT", rt_pkg));
  24
  25     /* Create GSI link device */
  26     for (i = 0; i < PCI_NUM_PINS; i++) {
  27         uint32_t irqs = irq + i;
  28         Aml *dev_gsi = aml_device("GSI%d", i);
  29         aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
  30         aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i)));
  31         crs = aml_resource_template();
  32         aml_append(crs,
  33                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
  34                                  AML_EXCLUSIVE, &irqs, 1));
  35         aml_append(dev_gsi, aml_name_decl("_PRS", crs));
  36         crs = aml_resource_template();
  37         aml_append(crs,
  38                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
  39                                  AML_EXCLUSIVE, &irqs, 1));
  40         aml_append(dev_gsi, aml_name_decl("_CRS", crs));
  41         method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
  42         aml_append(dev_gsi, method);
  43         aml_append(dev, dev_gsi);
  44     }
  45 }
  46
  47 static void acpi_dsdt_add_pci_osc(Aml *dev)
  48 {
  49     Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf;
  50
  51     /* Declare an _OSC (OS Control Handoff) method */
  52     aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
  53     aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
  54     method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
  55     aml_append(method,
  56         aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
  57
  58     /* PCI Firmware Specification 3.0
  59      * 4.5.1. _OSC Interface for PCI Host Bridge Devices
  60      * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
  61      * identified by the Universal Unique IDentifier (UUID)
  62      * 33DB4D5B-1FF7-401C-9657-7441C03DD766
  63      */
  64     UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
  65     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
  66     aml_append(ifctx,
  67         aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
  68     aml_append(ifctx,
  69         aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
  70     aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
  71     aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
  72
  73     /*
  74      * Allow OS control for all 5 features:
  75      * PCIeHotplug SHPCHotplug PME AER PCIeCapability.
  76      */
  77     aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F),
  78                               aml_name("CTRL")));
  79
  80     ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
  81     aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08),
  82                               aml_name("CDW1")));
  83     aml_append(ifctx, ifctx1);
  84
  85     ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
  86     aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10),
  87                               aml_name("CDW1")));
  88     aml_append(ifctx, ifctx1);
  89
  90     aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
  91     aml_append(ifctx, aml_return(aml_arg(3)));
  92     aml_append(method, ifctx);
  93
  94     elsectx = aml_else();
  95     aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4),
  96                                aml_name("CDW1")));
  97     aml_append(elsectx, aml_return(aml_arg(3)));
  98     aml_append(method, elsectx);
  99     aml_append(dev, method);
 100
 101     method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
 102
 103     /* PCI Firmware Specification 3.0
 104      * 4.6.1. _DSM for PCI Express Slot Information
 105      * The UUID in _DSM in this context is
 106      * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
 107      */
 108     UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
 109     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
 110     ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
 111     uint8_t byte_list[1] = {1};
 112     buf = aml_buffer(1, byte_list);
 113     aml_append(ifctx1, aml_return(buf));
 114     aml_append(ifctx, ifctx1);
 115     aml_append(method, ifctx);
 116
 117     byte_list[0] = 0;
 118     buf = aml_buffer(1, byte_list);
 119     aml_append(method, aml_return(buf));
 120     aml_append(dev, method);
 121 }
 122
 123 void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
 124 {
 125     int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN;
 126     Aml *method, *crs, *dev, *rbuf;
 127
 128     dev = aml_device("%s", "PCI0");
 129     aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
 130     aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
 131     aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
 132     aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
 133     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 134     aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
 135     aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
 136
 137     acpi_dsdt_add_pci_route_table(dev, cfg->irq);
 138
 139     method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
 140     aml_append(method, aml_return(aml_int(cfg->ecam.base)));
 141     aml_append(dev, method);
 142
 143     rbuf = aml_resource_template();
 144     aml_append(rbuf,
 145         aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
 146                             0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
 147                             nr_pcie_buses));
 148     if (cfg->mmio32.size) {
 149         aml_append(rbuf,
 150                    aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 151                                     AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
 152                                     cfg->mmio32.base,
 153                                     cfg->mmio32.base + cfg->mmio32.size - 1,
 154                                     0x0000,
 155                                     cfg->mmio32.size));
 156     }
 157     if (cfg->pio.size) {
 158         aml_append(rbuf,
 159                    aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
 160                                 AML_ENTIRE_RANGE, 0x0000, 0x0000,
 161                                 cfg->pio.size - 1,
 162                                 cfg->pio.base,
 163                                 cfg->pio.size));
 164     }
 165     if (cfg->mmio64.size) {
 166         aml_append(rbuf,
 167                    aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 168                                     AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
 169                                     cfg->mmio64.base,
 170                                     cfg->mmio64.base + cfg->mmio64.size - 1,
 171                                     0x0000,
 172                                     cfg->mmio64.size));
 173     }
 174     aml_append(dev, aml_name_decl("_CRS", rbuf));
 175
 176     acpi_dsdt_add_pci_osc(dev);
 177
 178     Aml *dev_res0 = aml_device("%s", "RES0");
 179     aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
 180     crs = aml_resource_template();
 181     aml_append(crs,
 182         aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 183                          AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
 184                          cfg->ecam.base,
 185                          cfg->ecam.base + cfg->ecam.size - 1,
 186                          0x0000,
 187                          cfg->ecam.size));
 188     aml_append(dev_res0, aml_name_decl("_CRS", crs));
 189     aml_append(dev, dev_res0);
 190     aml_append(scope, dev);
 191 }