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target-sh4: implement flush-to-zero
[qemu.git] / hw / qxl.c
blob207aa63f90c81ce2dd849c6fceb9e01e449167b2
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include <pthread.h>
22
23 #include "qemu-common.h"
24 #include "qemu-timer.h"
25 #include "qemu-queue.h"
26 #include "monitor.h"
27 #include "sysemu.h"
28
29 #include "qxl.h"
30
31 #undef SPICE_RING_PROD_ITEM
32 #define SPICE_RING_PROD_ITEM(r, ret) { \
33 typeof(r) start = r; \
34 typeof(r) end = r + 1; \
35 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
36 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
37 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
38 abort(); \
39 } \
40 ret = &m_item->el; \
41 }
42
43 #undef SPICE_RING_CONS_ITEM
44 #define SPICE_RING_CONS_ITEM(r, ret) { \
45 typeof(r) start = r; \
46 typeof(r) end = r + 1; \
47 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
48 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
49 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
50 abort(); \
51 } \
52 ret = &m_item->el; \
53 }
54
55 #undef ALIGN
56 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
57
58 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
59
60 #define QXL_MODE(_x, _y, _b, _o) \
61 { .x_res = _x, \
62 .y_res = _y, \
63 .bits = _b, \
64 .stride = (_x) * (_b) / 8, \
65 .x_mili = PIXEL_SIZE * (_x), \
66 .y_mili = PIXEL_SIZE * (_y), \
67 .orientation = _o, \
68 }
69
70 #define QXL_MODE_16_32(x_res, y_res, orientation) \
71 QXL_MODE(x_res, y_res, 16, orientation), \
72 QXL_MODE(x_res, y_res, 32, orientation)
73
74 #define QXL_MODE_EX(x_res, y_res) \
75 QXL_MODE_16_32(x_res, y_res, 0), \
76 QXL_MODE_16_32(y_res, x_res, 1), \
77 QXL_MODE_16_32(x_res, y_res, 2), \
78 QXL_MODE_16_32(y_res, x_res, 3)
79
80 static QXLMode qxl_modes[] = {
81 QXL_MODE_EX(640, 480),
82 QXL_MODE_EX(800, 480),
83 QXL_MODE_EX(800, 600),
84 QXL_MODE_EX(832, 624),
85 QXL_MODE_EX(960, 640),
86 QXL_MODE_EX(1024, 600),
87 QXL_MODE_EX(1024, 768),
88 QXL_MODE_EX(1152, 864),
89 QXL_MODE_EX(1152, 870),
90 QXL_MODE_EX(1280, 720),
91 QXL_MODE_EX(1280, 760),
92 QXL_MODE_EX(1280, 768),
93 QXL_MODE_EX(1280, 800),
94 QXL_MODE_EX(1280, 960),
95 QXL_MODE_EX(1280, 1024),
96 QXL_MODE_EX(1360, 768),
97 QXL_MODE_EX(1366, 768),
98 QXL_MODE_EX(1400, 1050),
99 QXL_MODE_EX(1440, 900),
100 QXL_MODE_EX(1600, 900),
101 QXL_MODE_EX(1600, 1200),
102 QXL_MODE_EX(1680, 1050),
103 QXL_MODE_EX(1920, 1080),
104 #if VGA_RAM_SIZE >= (16 * 1024 * 1024)
105 /* these modes need more than 8 MB video memory */
106 QXL_MODE_EX(1920, 1200),
107 QXL_MODE_EX(1920, 1440),
108 QXL_MODE_EX(2048, 1536),
109 QXL_MODE_EX(2560, 1440),
110 QXL_MODE_EX(2560, 1600),
111 #endif
112 #if VGA_RAM_SIZE >= (32 * 1024 * 1024)
113 /* these modes need more than 16 MB video memory */
114 QXL_MODE_EX(2560, 2048),
115 QXL_MODE_EX(2800, 2100),
116 QXL_MODE_EX(3200, 2400),
117 #endif
118 };
119
120 static PCIQXLDevice *qxl0;
121
122 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
123 static void qxl_destroy_primary(PCIQXLDevice *d);
124 static void qxl_reset_memslots(PCIQXLDevice *d);
125 static void qxl_reset_surfaces(PCIQXLDevice *d);
126 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
127
128 static inline uint32_t msb_mask(uint32_t val)
129 {
130 uint32_t mask;
131
132 do {
133 mask = ~(val - 1) & val;
134 val &= ~mask;
135 } while (mask < val);
136
137 return mask;
138 }
139
140 static ram_addr_t qxl_rom_size(void)
141 {
142 uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes);
143 rom_size = MAX(rom_size, TARGET_PAGE_SIZE);
144 rom_size = msb_mask(rom_size * 2 - 1);
145 return rom_size;
146 }
147
148 static void init_qxl_rom(PCIQXLDevice *d)
149 {
150 QXLRom *rom = qemu_get_ram_ptr(d->rom_offset);
151 QXLModes *modes = (QXLModes *)(rom + 1);
152 uint32_t ram_header_size;
153 uint32_t surface0_area_size;
154 uint32_t num_pages;
155 uint32_t fb, maxfb = 0;
156 int i;
157
158 memset(rom, 0, d->rom_size);
159
160 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
161 rom->id = cpu_to_le32(d->id);
162 rom->log_level = cpu_to_le32(d->guestdebug);
163 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
164
165 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
166 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
167 rom->slots_start = 1;
168 rom->slots_end = NUM_MEMSLOTS - 1;
169 rom->n_surfaces = cpu_to_le32(NUM_SURFACES);
170
171 modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes));
172 for (i = 0; i < modes->n_modes; i++) {
173 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
174 if (maxfb < fb) {
175 maxfb = fb;
176 }
177 modes->modes[i].id = cpu_to_le32(i);
178 modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res);
179 modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res);
180 modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits);
181 modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride);
182 modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
183 modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
184 modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation);
185 }
186 if (maxfb < VGA_RAM_SIZE && d->id == 0)
187 maxfb = VGA_RAM_SIZE;
188
189 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
190 surface0_area_size = ALIGN(maxfb, 4096);
191 num_pages = d->vga.vram_size;
192 num_pages -= ram_header_size;
193 num_pages -= surface0_area_size;
194 num_pages = num_pages / TARGET_PAGE_SIZE;
195
196 rom->draw_area_offset = cpu_to_le32(0);
197 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
198 rom->pages_offset = cpu_to_le32(surface0_area_size);
199 rom->num_pages = cpu_to_le32(num_pages);
200 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
201
202 d->shadow_rom = *rom;
203 d->rom = rom;
204 d->modes = modes;
205 }
206
207 static void init_qxl_ram(PCIQXLDevice *d)
208 {
209 uint8_t *buf;
210 uint64_t *item;
211
212 buf = d->vga.vram_ptr;
213 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
214 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
215 d->ram->int_pending = cpu_to_le32(0);
216 d->ram->int_mask = cpu_to_le32(0);
217 SPICE_RING_INIT(&d->ram->cmd_ring);
218 SPICE_RING_INIT(&d->ram->cursor_ring);
219 SPICE_RING_INIT(&d->ram->release_ring);
220 SPICE_RING_PROD_ITEM(&d->ram->release_ring, item);
221 *item = 0;
222 qxl_ring_set_dirty(d);
223 }
224
225 /* can be called from spice server thread context */
226 static void qxl_set_dirty(ram_addr_t addr, ram_addr_t end)
227 {
228 while (addr < end) {
229 cpu_physical_memory_set_dirty(addr);
230 addr += TARGET_PAGE_SIZE;
231 }
232 }
233
234 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
235 {
236 ram_addr_t addr = qxl->rom_offset;
237 qxl_set_dirty(addr, addr + qxl->rom_size);
238 }
239
240 /* called from spice server thread context only */
241 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
242 {
243 ram_addr_t addr = qxl->vga.vram_offset;
244 void *base = qxl->vga.vram_ptr;
245 intptr_t offset;
246
247 offset = ptr - base;
248 offset &= ~(TARGET_PAGE_SIZE-1);
249 assert(offset < qxl->vga.vram_size);
250 qxl_set_dirty(addr + offset, addr + offset + TARGET_PAGE_SIZE);
251 }
252
253 /* can be called from spice server thread context */
254 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
255 {
256 ram_addr_t addr = qxl->vga.vram_offset + qxl->shadow_rom.ram_header_offset;
257 ram_addr_t end = qxl->vga.vram_offset + qxl->vga.vram_size;
258 qxl_set_dirty(addr, end);
259 }
260
261 /*
262 * keep track of some command state, for savevm/loadvm.
263 * called from spice server thread context only
264 */
265 static void qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
266 {
267 switch (le32_to_cpu(ext->cmd.type)) {
268 case QXL_CMD_SURFACE:
269 {
270 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
271 uint32_t id = le32_to_cpu(cmd->surface_id);
272 PANIC_ON(id >= NUM_SURFACES);
273 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
274 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
275 qxl->guest_surfaces.count++;
276 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
277 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
278 }
279 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
280 qxl->guest_surfaces.cmds[id] = 0;
281 qxl->guest_surfaces.count--;
282 }
283 break;
284 }
285 case QXL_CMD_CURSOR:
286 {
287 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
288 if (cmd->type == QXL_CURSOR_SET) {
289 qxl->guest_cursor = ext->cmd.data;
290 }
291 break;
292 }
293 }
294 }
295
296 /* spice display interface callbacks */
297
298 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
299 {
300 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
301
302 dprint(qxl, 1, "%s:\n", __FUNCTION__);
303 qxl->ssd.worker = qxl_worker;
304 }
305
306 static void interface_set_compression_level(QXLInstance *sin, int level)
307 {
308 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
309
310 dprint(qxl, 1, "%s: %d\n", __FUNCTION__, level);
311 qxl->shadow_rom.compression_level = cpu_to_le32(level);
312 qxl->rom->compression_level = cpu_to_le32(level);
313 qxl_rom_set_dirty(qxl);
314 }
315
316 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
317 {
318 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
319
320 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
321 qxl->rom->mm_clock = cpu_to_le32(mm_time);
322 qxl_rom_set_dirty(qxl);
323 }
324
325 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
326 {
327 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
328
329 dprint(qxl, 1, "%s:\n", __FUNCTION__);
330 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
331 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
332 info->num_memslots = NUM_MEMSLOTS;
333 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
334 info->internal_groupslot_id = 0;
335 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
336 info->n_surfaces = NUM_SURFACES;
337 }
338
339 /* called from spice server thread context only */
340 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
341 {
342 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
343 SimpleSpiceUpdate *update;
344 QXLCommandRing *ring;
345 QXLCommand *cmd;
346 int notify;
347
348 switch (qxl->mode) {
349 case QXL_MODE_VGA:
350 dprint(qxl, 2, "%s: vga\n", __FUNCTION__);
351 update = qemu_spice_create_update(&qxl->ssd);
352 if (update == NULL) {
353 return false;
354 }
355 *ext = update->ext;
356 qxl_log_command(qxl, "vga", ext);
357 return true;
358 case QXL_MODE_COMPAT:
359 case QXL_MODE_NATIVE:
360 case QXL_MODE_UNDEFINED:
361 dprint(qxl, 2, "%s: %s\n", __FUNCTION__,
362 qxl->cmdflags ? "compat" : "native");
363 ring = &qxl->ram->cmd_ring;
364 if (SPICE_RING_IS_EMPTY(ring)) {
365 return false;
366 }
367 SPICE_RING_CONS_ITEM(ring, cmd);
368 ext->cmd = *cmd;
369 ext->group_id = MEMSLOT_GROUP_GUEST;
370 ext->flags = qxl->cmdflags;
371 SPICE_RING_POP(ring, notify);
372 qxl_ring_set_dirty(qxl);
373 if (notify) {
374 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
375 }
376 qxl->guest_primary.commands++;
377 qxl_track_command(qxl, ext);
378 qxl_log_command(qxl, "cmd", ext);
379 return true;
380 default:
381 return false;
382 }
383 }
384
385 /* called from spice server thread context only */
386 static int interface_req_cmd_notification(QXLInstance *sin)
387 {
388 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
389 int wait = 1;
390
391 switch (qxl->mode) {
392 case QXL_MODE_COMPAT:
393 case QXL_MODE_NATIVE:
394 case QXL_MODE_UNDEFINED:
395 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
396 qxl_ring_set_dirty(qxl);
397 break;
398 default:
399 /* nothing */
400 break;
401 }
402 return wait;
403 }
404
405 /* called from spice server thread context only */
406 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
407 {
408 QXLReleaseRing *ring = &d->ram->release_ring;
409 uint64_t *item;
410 int notify;
411
412 #define QXL_FREE_BUNCH_SIZE 32
413
414 if (ring->prod - ring->cons + 1 == ring->num_items) {
415 /* ring full -- can't push */
416 return;
417 }
418 if (!flush && d->oom_running) {
419 /* collect everything from oom handler before pushing */
420 return;
421 }
422 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
423 /* collect a bit more before pushing */
424 return;
425 }
426
427 SPICE_RING_PUSH(ring, notify);
428 dprint(d, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
429 d->num_free_res, notify ? "yes" : "no",
430 ring->prod - ring->cons, ring->num_items,
431 ring->prod, ring->cons);
432 if (notify) {
433 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
434 }
435 SPICE_RING_PROD_ITEM(ring, item);
436 *item = 0;
437 d->num_free_res = 0;
438 d->last_release = NULL;
439 qxl_ring_set_dirty(d);
440 }
441
442 /* called from spice server thread context only */
443 static void interface_release_resource(QXLInstance *sin,
444 struct QXLReleaseInfoExt ext)
445 {
446 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
447 QXLReleaseRing *ring;
448 uint64_t *item, id;
449
450 if (ext.group_id == MEMSLOT_GROUP_HOST) {
451 /* host group -> vga mode update request */
452 qemu_spice_destroy_update(&qxl->ssd, (void*)ext.info->id);
453 return;
454 }
455
456 /*
457 * ext->info points into guest-visible memory
458 * pci bar 0, $command.release_info
459 */
460 ring = &qxl->ram->release_ring;
461 SPICE_RING_PROD_ITEM(ring, item);
462 if (*item == 0) {
463 /* stick head into the ring */
464 id = ext.info->id;
465 ext.info->next = 0;
466 qxl_ram_set_dirty(qxl, &ext.info->next);
467 *item = id;
468 qxl_ring_set_dirty(qxl);
469 } else {
470 /* append item to the list */
471 qxl->last_release->next = ext.info->id;
472 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
473 ext.info->next = 0;
474 qxl_ram_set_dirty(qxl, &ext.info->next);
475 }
476 qxl->last_release = ext.info;
477 qxl->num_free_res++;
478 dprint(qxl, 3, "%4d\r", qxl->num_free_res);
479 qxl_push_free_res(qxl, 0);
480 }
481
482 /* called from spice server thread context only */
483 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
484 {
485 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
486 QXLCursorRing *ring;
487 QXLCommand *cmd;
488 int notify;
489
490 switch (qxl->mode) {
491 case QXL_MODE_COMPAT:
492 case QXL_MODE_NATIVE:
493 case QXL_MODE_UNDEFINED:
494 ring = &qxl->ram->cursor_ring;
495 if (SPICE_RING_IS_EMPTY(ring)) {
496 return false;
497 }
498 SPICE_RING_CONS_ITEM(ring, cmd);
499 ext->cmd = *cmd;
500 ext->group_id = MEMSLOT_GROUP_GUEST;
501 ext->flags = qxl->cmdflags;
502 SPICE_RING_POP(ring, notify);
503 qxl_ring_set_dirty(qxl);
504 if (notify) {
505 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
506 }
507 qxl->guest_primary.commands++;
508 qxl_track_command(qxl, ext);
509 qxl_log_command(qxl, "csr", ext);
510 if (qxl->id == 0) {
511 qxl_render_cursor(qxl, ext);
512 }
513 return true;
514 default:
515 return false;
516 }
517 }
518
519 /* called from spice server thread context only */
520 static int interface_req_cursor_notification(QXLInstance *sin)
521 {
522 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
523 int wait = 1;
524
525 switch (qxl->mode) {
526 case QXL_MODE_COMPAT:
527 case QXL_MODE_NATIVE:
528 case QXL_MODE_UNDEFINED:
529 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
530 qxl_ring_set_dirty(qxl);
531 break;
532 default:
533 /* nothing */
534 break;
535 }
536 return wait;
537 }
538
539 /* called from spice server thread context */
540 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
541 {
542 fprintf(stderr, "%s: abort()\n", __FUNCTION__);
543 abort();
544 }
545
546 /* called from spice server thread context only */
547 static int interface_flush_resources(QXLInstance *sin)
548 {
549 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
550 int ret;
551
552 dprint(qxl, 1, "free: guest flush (have %d)\n", qxl->num_free_res);
553 ret = qxl->num_free_res;
554 if (ret) {
555 qxl_push_free_res(qxl, 1);
556 }
557 return ret;
558 }
559
560 static const QXLInterface qxl_interface = {
561 .base.type = SPICE_INTERFACE_QXL,
562 .base.description = "qxl gpu",
563 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
564 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
565
566 .attache_worker = interface_attach_worker,
567 .set_compression_level = interface_set_compression_level,
568 .set_mm_time = interface_set_mm_time,
569 .get_init_info = interface_get_init_info,
570
571 /* the callbacks below are called from spice server thread context */
572 .get_command = interface_get_command,
573 .req_cmd_notification = interface_req_cmd_notification,
574 .release_resource = interface_release_resource,
575 .get_cursor_command = interface_get_cursor_command,
576 .req_cursor_notification = interface_req_cursor_notification,
577 .notify_update = interface_notify_update,
578 .flush_resources = interface_flush_resources,
579 };
580
581 static void qxl_enter_vga_mode(PCIQXLDevice *d)
582 {
583 if (d->mode == QXL_MODE_VGA) {
584 return;
585 }
586 dprint(d, 1, "%s\n", __FUNCTION__);
587 qemu_spice_create_host_primary(&d->ssd);
588 d->mode = QXL_MODE_VGA;
589 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
590 }
591
592 static void qxl_exit_vga_mode(PCIQXLDevice *d)
593 {
594 if (d->mode != QXL_MODE_VGA) {
595 return;
596 }
597 dprint(d, 1, "%s\n", __FUNCTION__);
598 qxl_destroy_primary(d);
599 }
600
601 static void qxl_set_irq(PCIQXLDevice *d)
602 {
603 uint32_t pending = le32_to_cpu(d->ram->int_pending);
604 uint32_t mask = le32_to_cpu(d->ram->int_mask);
605 int level = !!(pending & mask);
606 qemu_set_irq(d->pci.irq[0], level);
607 qxl_ring_set_dirty(d);
608 }
609
610 static void qxl_write_config(PCIDevice *d, uint32_t address,
611 uint32_t val, int len)
612 {
613 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, d);
614 VGACommonState *vga = &qxl->vga;
615
616 vga_dirty_log_stop(vga);
617 pci_default_write_config(d, address, val, len);
618 if (vga->map_addr && qxl->pci.io_regions[0].addr == -1) {
619 vga->map_addr = 0;
620 }
621 vga_dirty_log_start(vga);
622 }
623
624 static void qxl_check_state(PCIQXLDevice *d)
625 {
626 QXLRam *ram = d->ram;
627
628 assert(SPICE_RING_IS_EMPTY(&ram->cmd_ring));
629 assert(SPICE_RING_IS_EMPTY(&ram->cursor_ring));
630 }
631
632 static void qxl_reset_state(PCIQXLDevice *d)
633 {
634 QXLRam *ram = d->ram;
635 QXLRom *rom = d->rom;
636
637 assert(SPICE_RING_IS_EMPTY(&ram->cmd_ring));
638 assert(SPICE_RING_IS_EMPTY(&ram->cursor_ring));
639 d->shadow_rom.update_id = cpu_to_le32(0);
640 *rom = d->shadow_rom;
641 qxl_rom_set_dirty(d);
642 init_qxl_ram(d);
643 d->num_free_res = 0;
644 d->last_release = NULL;
645 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
646 }
647
648 static void qxl_soft_reset(PCIQXLDevice *d)
649 {
650 dprint(d, 1, "%s:\n", __FUNCTION__);
651 qxl_check_state(d);
652
653 if (d->id == 0) {
654 qxl_enter_vga_mode(d);
655 } else {
656 d->mode = QXL_MODE_UNDEFINED;
657 }
658 }
659
660 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
661 {
662 dprint(d, 1, "%s: start%s\n", __FUNCTION__,
663 loadvm ? " (loadvm)" : "");
664
665 qemu_mutex_unlock_iothread();
666 d->ssd.worker->reset_cursor(d->ssd.worker);
667 d->ssd.worker->reset_image_cache(d->ssd.worker);
668 qemu_mutex_lock_iothread();
669 qxl_reset_surfaces(d);
670 qxl_reset_memslots(d);
671
672 /* pre loadvm reset must not touch QXLRam. This lives in
673 * device memory, is migrated together with RAM and thus
674 * already loaded at this point */
675 if (!loadvm) {
676 qxl_reset_state(d);
677 }
678 qemu_spice_create_host_memslot(&d->ssd);
679 qxl_soft_reset(d);
680
681 dprint(d, 1, "%s: done\n", __FUNCTION__);
682 }
683
684 static void qxl_reset_handler(DeviceState *dev)
685 {
686 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
687 qxl_hard_reset(d, 0);
688 }
689
690 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
691 {
692 VGACommonState *vga = opaque;
693 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
694
695 if (qxl->mode != QXL_MODE_VGA) {
696 dprint(qxl, 1, "%s\n", __FUNCTION__);
697 qxl_destroy_primary(qxl);
698 qxl_soft_reset(qxl);
699 }
700 vga_ioport_write(opaque, addr, val);
701 }
702
703 static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta)
704 {
705 static const int regions[] = {
706 QXL_RAM_RANGE_INDEX,
707 QXL_VRAM_RANGE_INDEX,
708 };
709 uint64_t guest_start;
710 uint64_t guest_end;
711 int pci_region;
712 pcibus_t pci_start;
713 pcibus_t pci_end;
714 intptr_t virt_start;
715 QXLDevMemSlot memslot;
716 int i;
717
718 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
719 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
720
721 dprint(d, 1, "%s: slot %d: guest phys 0x%" PRIx64 " - 0x%" PRIx64 "\n",
722 __FUNCTION__, slot_id,
723 guest_start, guest_end);
724
725 PANIC_ON(slot_id >= NUM_MEMSLOTS);
726 PANIC_ON(guest_start > guest_end);
727
728 for (i = 0; i < ARRAY_SIZE(regions); i++) {
729 pci_region = regions[i];
730 pci_start = d->pci.io_regions[pci_region].addr;
731 pci_end = pci_start + d->pci.io_regions[pci_region].size;
732 /* mapped? */
733 if (pci_start == -1) {
734 continue;
735 }
736 /* start address in range ? */
737 if (guest_start < pci_start || guest_start > pci_end) {
738 continue;
739 }
740 /* end address in range ? */
741 if (guest_end > pci_end) {
742 continue;
743 }
744 /* passed */
745 break;
746 }
747 PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */
748
749 switch (pci_region) {
750 case QXL_RAM_RANGE_INDEX:
751 virt_start = (intptr_t)qemu_get_ram_ptr(d->vga.vram_offset);
752 break;
753 case QXL_VRAM_RANGE_INDEX:
754 virt_start = (intptr_t)qemu_get_ram_ptr(d->vram_offset);
755 break;
756 default:
757 /* should not happen */
758 abort();
759 }
760
761 memslot.slot_id = slot_id;
762 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
763 memslot.virt_start = virt_start + (guest_start - pci_start);
764 memslot.virt_end = virt_start + (guest_end - pci_start);
765 memslot.addr_delta = memslot.virt_start - delta;
766 memslot.generation = d->rom->slot_generation = 0;
767 qxl_rom_set_dirty(d);
768
769 dprint(d, 1, "%s: slot %d: host virt 0x%" PRIx64 " - 0x%" PRIx64 "\n",
770 __FUNCTION__, memslot.slot_id,
771 memslot.virt_start, memslot.virt_end);
772
773 d->ssd.worker->add_memslot(d->ssd.worker, &memslot);
774 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
775 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
776 d->guest_slots[slot_id].delta = delta;
777 d->guest_slots[slot_id].active = 1;
778 }
779
780 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
781 {
782 dprint(d, 1, "%s: slot %d\n", __FUNCTION__, slot_id);
783 d->ssd.worker->del_memslot(d->ssd.worker, MEMSLOT_GROUP_HOST, slot_id);
784 d->guest_slots[slot_id].active = 0;
785 }
786
787 static void qxl_reset_memslots(PCIQXLDevice *d)
788 {
789 dprint(d, 1, "%s:\n", __FUNCTION__);
790 d->ssd.worker->reset_memslots(d->ssd.worker);
791 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
792 }
793
794 static void qxl_reset_surfaces(PCIQXLDevice *d)
795 {
796 dprint(d, 1, "%s:\n", __FUNCTION__);
797 d->mode = QXL_MODE_UNDEFINED;
798 qemu_mutex_unlock_iothread();
799 d->ssd.worker->destroy_surfaces(d->ssd.worker);
800 qemu_mutex_lock_iothread();
801 memset(&d->guest_surfaces.cmds, 0, sizeof(d->guest_surfaces.cmds));
802 }
803
804 /* called from spice server thread context only */
805 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
806 {
807 uint64_t phys = le64_to_cpu(pqxl);
808 uint32_t slot = (phys >> (64 - 8)) & 0xff;
809 uint64_t offset = phys & 0xffffffffffff;
810
811 switch (group_id) {
812 case MEMSLOT_GROUP_HOST:
813 return (void*)offset;
814 case MEMSLOT_GROUP_GUEST:
815 PANIC_ON(slot > NUM_MEMSLOTS);
816 PANIC_ON(!qxl->guest_slots[slot].active);
817 PANIC_ON(offset < qxl->guest_slots[slot].delta);
818 offset -= qxl->guest_slots[slot].delta;
819 PANIC_ON(offset > qxl->guest_slots[slot].size)
820 return qxl->guest_slots[slot].ptr + offset;
821 default:
822 PANIC_ON(1);
823 }
824 }
825
826 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm)
827 {
828 QXLDevSurfaceCreate surface;
829 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
830
831 assert(qxl->mode != QXL_MODE_NATIVE);
832 qxl_exit_vga_mode(qxl);
833
834 dprint(qxl, 1, "%s: %dx%d\n", __FUNCTION__,
835 le32_to_cpu(sc->width), le32_to_cpu(sc->height));
836
837 surface.format = le32_to_cpu(sc->format);
838 surface.height = le32_to_cpu(sc->height);
839 surface.mem = le64_to_cpu(sc->mem);
840 surface.position = le32_to_cpu(sc->position);
841 surface.stride = le32_to_cpu(sc->stride);
842 surface.width = le32_to_cpu(sc->width);
843 surface.type = le32_to_cpu(sc->type);
844 surface.flags = le32_to_cpu(sc->flags);
845
846 surface.mouse_mode = true;
847 surface.group_id = MEMSLOT_GROUP_GUEST;
848 if (loadvm) {
849 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
850 }
851
852 qxl->mode = QXL_MODE_NATIVE;
853 qxl->cmdflags = 0;
854 qxl->ssd.worker->create_primary_surface(qxl->ssd.worker, 0, &surface);
855
856 /* for local rendering */
857 qxl_render_resize(qxl);
858 }
859
860 static void qxl_destroy_primary(PCIQXLDevice *d)
861 {
862 if (d->mode == QXL_MODE_UNDEFINED) {
863 return;
864 }
865
866 dprint(d, 1, "%s\n", __FUNCTION__);
867
868 d->mode = QXL_MODE_UNDEFINED;
869 d->ssd.worker->destroy_primary_surface(d->ssd.worker, 0);
870 }
871
872 static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
873 {
874 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
875 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
876 QXLMode *mode = d->modes->modes + modenr;
877 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
878 QXLMemSlot slot = {
879 .mem_start = start,
880 .mem_end = end
881 };
882 QXLSurfaceCreate surface = {
883 .width = mode->x_res,
884 .height = mode->y_res,
885 .stride = -mode->x_res * 4,
886 .format = SPICE_SURFACE_FMT_32_xRGB,
887 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
888 .mouse_mode = true,
889 .mem = devmem + d->shadow_rom.draw_area_offset,
890 };
891
892 dprint(d, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%lx ]\n", __FUNCTION__,
893 modenr, mode->x_res, mode->y_res, mode->bits, devmem);
894 if (!loadvm) {
895 qxl_hard_reset(d, 0);
896 }
897
898 d->guest_slots[0].slot = slot;
899 qxl_add_memslot(d, 0, devmem);
900
901 d->guest_primary.surface = surface;
902 qxl_create_guest_primary(d, 0);
903
904 d->mode = QXL_MODE_COMPAT;
905 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
906 #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
907 if (mode->bits == 16) {
908 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
909 }
910 #endif
911 d->shadow_rom.mode = cpu_to_le32(modenr);
912 d->rom->mode = cpu_to_le32(modenr);
913 qxl_rom_set_dirty(d);
914 }
915
916 static void ioport_write(void *opaque, uint32_t addr, uint32_t val)
917 {
918 PCIQXLDevice *d = opaque;
919 uint32_t io_port = addr - d->io_base;
920
921 switch (io_port) {
922 case QXL_IO_RESET:
923 case QXL_IO_SET_MODE:
924 case QXL_IO_MEMSLOT_ADD:
925 case QXL_IO_MEMSLOT_DEL:
926 case QXL_IO_CREATE_PRIMARY:
927 break;
928 default:
929 if (d->mode == QXL_MODE_NATIVE || d->mode == QXL_MODE_COMPAT)
930 break;
931 dprint(d, 1, "%s: unexpected port 0x%x in vga mode\n", __FUNCTION__, io_port);
932 return;
933 }
934
935 switch (io_port) {
936 case QXL_IO_UPDATE_AREA:
937 {
938 QXLRect update = d->ram->update_area;
939 qemu_mutex_unlock_iothread();
940 d->ssd.worker->update_area(d->ssd.worker, d->ram->update_surface,
941 &update, NULL, 0, 0);
942 qemu_mutex_lock_iothread();
943 break;
944 }
945 case QXL_IO_NOTIFY_CMD:
946 d->ssd.worker->wakeup(d->ssd.worker);
947 break;
948 case QXL_IO_NOTIFY_CURSOR:
949 d->ssd.worker->wakeup(d->ssd.worker);
950 break;
951 case QXL_IO_UPDATE_IRQ:
952 qxl_set_irq(d);
953 break;
954 case QXL_IO_NOTIFY_OOM:
955 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
956 break;
957 }
958 pthread_yield();
959 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
960 break;
961 }
962 d->oom_running = 1;
963 d->ssd.worker->oom(d->ssd.worker);
964 d->oom_running = 0;
965 break;
966 case QXL_IO_SET_MODE:
967 dprint(d, 1, "QXL_SET_MODE %d\n", val);
968 qxl_set_mode(d, val, 0);
969 break;
970 case QXL_IO_LOG:
971 if (d->guestdebug) {
972 fprintf(stderr, "qxl/guest: %s", d->ram->log_buf);
973 }
974 break;
975 case QXL_IO_RESET:
976 dprint(d, 1, "QXL_IO_RESET\n");
977 qxl_hard_reset(d, 0);
978 break;
979 case QXL_IO_MEMSLOT_ADD:
980 PANIC_ON(val >= NUM_MEMSLOTS);
981 PANIC_ON(d->guest_slots[val].active);
982 d->guest_slots[val].slot = d->ram->mem_slot;
983 qxl_add_memslot(d, val, 0);
984 break;
985 case QXL_IO_MEMSLOT_DEL:
986 qxl_del_memslot(d, val);
987 break;
988 case QXL_IO_CREATE_PRIMARY:
989 PANIC_ON(val != 0);
990 dprint(d, 1, "QXL_IO_CREATE_PRIMARY\n");
991 d->guest_primary.surface = d->ram->create_surface;
992 qxl_create_guest_primary(d, 0);
993 break;
994 case QXL_IO_DESTROY_PRIMARY:
995 PANIC_ON(val != 0);
996 dprint(d, 1, "QXL_IO_DESTROY_PRIMARY\n");
997 qxl_destroy_primary(d);
998 break;
999 case QXL_IO_DESTROY_SURFACE_WAIT:
1000 d->ssd.worker->destroy_surface_wait(d->ssd.worker, val);
1001 break;
1002 case QXL_IO_DESTROY_ALL_SURFACES:
1003 d->ssd.worker->destroy_surfaces(d->ssd.worker);
1004 break;
1005 default:
1006 fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port);
1007 abort();
1008 }
1009 }
1010
1011 static uint32_t ioport_read(void *opaque, uint32_t addr)
1012 {
1013 PCIQXLDevice *d = opaque;
1014
1015 dprint(d, 1, "%s: unexpected\n", __FUNCTION__);
1016 return 0xff;
1017 }
1018
1019 static void qxl_map(PCIDevice *pci, int region_num,
1020 pcibus_t addr, pcibus_t size, int type)
1021 {
1022 static const char *names[] = {
1023 [ QXL_IO_RANGE_INDEX ] = "ioports",
1024 [ QXL_RAM_RANGE_INDEX ] = "devram",
1025 [ QXL_ROM_RANGE_INDEX ] = "rom",
1026 [ QXL_VRAM_RANGE_INDEX ] = "vram",
1027 };
1028 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, pci);
1029
1030 dprint(qxl, 1, "%s: bar %d [%s] addr 0x%lx size 0x%lx\n", __FUNCTION__,
1031 region_num, names[region_num], addr, size);
1032
1033 switch (region_num) {
1034 case QXL_IO_RANGE_INDEX:
1035 register_ioport_write(addr, size, 1, ioport_write, pci);
1036 register_ioport_read(addr, size, 1, ioport_read, pci);
1037 qxl->io_base = addr;
1038 break;
1039 case QXL_RAM_RANGE_INDEX:
1040 cpu_register_physical_memory(addr, size, qxl->vga.vram_offset | IO_MEM_RAM);
1041 qxl->vga.map_addr = addr;
1042 qxl->vga.map_end = addr + size;
1043 if (qxl->id == 0) {
1044 vga_dirty_log_start(&qxl->vga);
1045 }
1046 break;
1047 case QXL_ROM_RANGE_INDEX:
1048 cpu_register_physical_memory(addr, size, qxl->rom_offset | IO_MEM_ROM);
1049 break;
1050 case QXL_VRAM_RANGE_INDEX:
1051 cpu_register_physical_memory(addr, size, qxl->vram_offset | IO_MEM_RAM);
1052 break;
1053 }
1054 }
1055
1056 static void pipe_read(void *opaque)
1057 {
1058 PCIQXLDevice *d = opaque;
1059 char dummy;
1060 int len;
1061
1062 do {
1063 len = read(d->pipe[0], &dummy, sizeof(dummy));
1064 } while (len == sizeof(dummy));
1065 qxl_set_irq(d);
1066 }
1067
1068 /* called from spice server thread context only */
1069 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1070 {
1071 uint32_t old_pending;
1072 uint32_t le_events = cpu_to_le32(events);
1073
1074 assert(d->ssd.running);
1075 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1076 if ((old_pending & le_events) == le_events) {
1077 return;
1078 }
1079 if (pthread_self() == d->main) {
1080 qxl_set_irq(d);
1081 } else {
1082 if (write(d->pipe[1], d, 1) != 1) {
1083 dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__);
1084 }
1085 }
1086 }
1087
1088 static void init_pipe_signaling(PCIQXLDevice *d)
1089 {
1090 if (pipe(d->pipe) < 0) {
1091 dprint(d, 1, "%s: pipe creation failed\n", __FUNCTION__);
1092 return;
1093 }
1094 #ifdef CONFIG_IOTHREAD
1095 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1096 #else
1097 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK /* | O_ASYNC */);
1098 #endif
1099 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1100 fcntl(d->pipe[0], F_SETOWN, getpid());
1101
1102 d->main = pthread_self();
1103 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1104 }
1105
1106 /* graphics console */
1107
1108 static void qxl_hw_update(void *opaque)
1109 {
1110 PCIQXLDevice *qxl = opaque;
1111 VGACommonState *vga = &qxl->vga;
1112
1113 switch (qxl->mode) {
1114 case QXL_MODE_VGA:
1115 vga->update(vga);
1116 break;
1117 case QXL_MODE_COMPAT:
1118 case QXL_MODE_NATIVE:
1119 qxl_render_update(qxl);
1120 break;
1121 default:
1122 break;
1123 }
1124 }
1125
1126 static void qxl_hw_invalidate(void *opaque)
1127 {
1128 PCIQXLDevice *qxl = opaque;
1129 VGACommonState *vga = &qxl->vga;
1130
1131 vga->invalidate(vga);
1132 }
1133
1134 static void qxl_hw_screen_dump(void *opaque, const char *filename)
1135 {
1136 PCIQXLDevice *qxl = opaque;
1137 VGACommonState *vga = &qxl->vga;
1138
1139 switch (qxl->mode) {
1140 case QXL_MODE_COMPAT:
1141 case QXL_MODE_NATIVE:
1142 qxl_render_update(qxl);
1143 ppm_save(filename, qxl->ssd.ds->surface);
1144 break;
1145 case QXL_MODE_VGA:
1146 vga->screen_dump(vga, filename);
1147 break;
1148 default:
1149 break;
1150 }
1151 }
1152
1153 static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1154 {
1155 PCIQXLDevice *qxl = opaque;
1156 VGACommonState *vga = &qxl->vga;
1157
1158 if (qxl->mode == QXL_MODE_VGA) {
1159 vga->text_update(vga, chardata);
1160 return;
1161 }
1162 }
1163
1164 static void qxl_vm_change_state_handler(void *opaque, int running, int reason)
1165 {
1166 PCIQXLDevice *qxl = opaque;
1167 qemu_spice_vm_change_state_handler(&qxl->ssd, running, reason);
1168
1169 if (!running && qxl->mode == QXL_MODE_NATIVE) {
1170 /* dirty all vram (which holds surfaces) to make sure it is saved */
1171 /* FIXME #1: should go out during "live" stage */
1172 /* FIXME #2: we only need to save the areas which are actually used */
1173 ram_addr_t addr = qxl->vram_offset;
1174 qxl_set_dirty(addr, addr + qxl->vram_size);
1175 }
1176 }
1177
1178 /* display change listener */
1179
1180 static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
1181 {
1182 if (qxl0->mode == QXL_MODE_VGA) {
1183 qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
1184 }
1185 }
1186
1187 static void display_resize(struct DisplayState *ds)
1188 {
1189 if (qxl0->mode == QXL_MODE_VGA) {
1190 qemu_spice_display_resize(&qxl0->ssd);
1191 }
1192 }
1193
1194 static void display_refresh(struct DisplayState *ds)
1195 {
1196 if (qxl0->mode == QXL_MODE_VGA) {
1197 qemu_spice_display_refresh(&qxl0->ssd);
1198 }
1199 }
1200
1201 static DisplayChangeListener display_listener = {
1202 .dpy_update = display_update,
1203 .dpy_resize = display_resize,
1204 .dpy_refresh = display_refresh,
1205 };
1206
1207 static int qxl_init_common(PCIQXLDevice *qxl)
1208 {
1209 uint8_t* config = qxl->pci.config;
1210 uint32_t pci_device_id;
1211 uint32_t pci_device_rev;
1212 uint32_t io_size;
1213
1214 qxl->mode = QXL_MODE_UNDEFINED;
1215 qxl->generation = 1;
1216 qxl->num_memslots = NUM_MEMSLOTS;
1217 qxl->num_surfaces = NUM_SURFACES;
1218
1219 switch (qxl->revision) {
1220 case 1: /* spice 0.4 -- qxl-1 */
1221 pci_device_id = QXL_DEVICE_ID_STABLE;
1222 pci_device_rev = QXL_REVISION_STABLE_V04;
1223 break;
1224 case 2: /* spice 0.6 -- qxl-2 */
1225 pci_device_id = QXL_DEVICE_ID_STABLE;
1226 pci_device_rev = QXL_REVISION_STABLE_V06;
1227 break;
1228 default: /* experimental */
1229 pci_device_id = QXL_DEVICE_ID_DEVEL;
1230 pci_device_rev = 1;
1231 break;
1232 }
1233
1234 pci_config_set_vendor_id(config, REDHAT_PCI_VENDOR_ID);
1235 pci_config_set_device_id(config, pci_device_id);
1236 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1237 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1238
1239 qxl->rom_size = qxl_rom_size();
1240 qxl->rom_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vrom", qxl->rom_size);
1241 init_qxl_rom(qxl);
1242 init_qxl_ram(qxl);
1243
1244 if (qxl->vram_size < 16 * 1024 * 1024) {
1245 qxl->vram_size = 16 * 1024 * 1024;
1246 }
1247 if (qxl->revision == 1) {
1248 qxl->vram_size = 4096;
1249 }
1250 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1251 qxl->vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vram", qxl->vram_size);
1252
1253 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1254 if (qxl->revision == 1) {
1255 io_size = 8;
1256 }
1257
1258 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1259 io_size, PCI_BASE_ADDRESS_SPACE_IO, qxl_map);
1260
1261 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1262 qxl->rom_size, PCI_BASE_ADDRESS_SPACE_MEMORY,
1263 qxl_map);
1264
1265 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1266 qxl->vga.vram_size, PCI_BASE_ADDRESS_SPACE_MEMORY,
1267 qxl_map);
1268
1269 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, qxl->vram_size,
1270 PCI_BASE_ADDRESS_SPACE_MEMORY, qxl_map);
1271
1272 qxl->ssd.qxl.base.sif = &qxl_interface.base;
1273 qxl->ssd.qxl.id = qxl->id;
1274 qemu_spice_add_interface(&qxl->ssd.qxl.base);
1275 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
1276
1277 init_pipe_signaling(qxl);
1278 qxl_reset_state(qxl);
1279
1280 return 0;
1281 }
1282
1283 static int qxl_init_primary(PCIDevice *dev)
1284 {
1285 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1286 VGACommonState *vga = &qxl->vga;
1287 ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1288
1289 qxl->id = 0;
1290
1291 if (ram_size < 32 * 1024 * 1024) {
1292 ram_size = 32 * 1024 * 1024;
1293 }
1294 vga_common_init(vga, ram_size);
1295 vga_init(vga);
1296 register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write, vga);
1297 register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write, vga);
1298 register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write, vga);
1299 register_ioport_write(0x3ba, 1, 1, qxl_vga_ioport_write, vga);
1300 register_ioport_write(0x3da, 1, 1, qxl_vga_ioport_write, vga);
1301
1302 vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
1303 qxl_hw_screen_dump, qxl_hw_text_update, qxl);
1304 qxl->ssd.ds = vga->ds;
1305 qxl->ssd.bufsize = (16 * 1024 * 1024);
1306 qxl->ssd.buf = qemu_malloc(qxl->ssd.bufsize);
1307
1308 qxl0 = qxl;
1309 register_displaychangelistener(vga->ds, &display_listener);
1310
1311 pci_config_set_class(dev->config, PCI_CLASS_DISPLAY_VGA);
1312 return qxl_init_common(qxl);
1313 }
1314
1315 static int qxl_init_secondary(PCIDevice *dev)
1316 {
1317 static int device_id = 1;
1318 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1319 ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1320
1321 qxl->id = device_id++;
1322
1323 if (ram_size < 16 * 1024 * 1024) {
1324 ram_size = 16 * 1024 * 1024;
1325 }
1326 qxl->vga.vram_size = ram_size;
1327 qxl->vga.vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vgavram",
1328 qxl->vga.vram_size);
1329 qxl->vga.vram_ptr = qemu_get_ram_ptr(qxl->vga.vram_offset);
1330
1331 pci_config_set_class(dev->config, PCI_CLASS_DISPLAY_OTHER);
1332 return qxl_init_common(qxl);
1333 }
1334
1335 static void qxl_pre_save(void *opaque)
1336 {
1337 PCIQXLDevice* d = opaque;
1338 uint8_t *ram_start = d->vga.vram_ptr;
1339
1340 dprint(d, 1, "%s:\n", __FUNCTION__);
1341 if (d->last_release == NULL) {
1342 d->last_release_offset = 0;
1343 } else {
1344 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
1345 }
1346 assert(d->last_release_offset < d->vga.vram_size);
1347 }
1348
1349 static int qxl_pre_load(void *opaque)
1350 {
1351 PCIQXLDevice* d = opaque;
1352
1353 dprint(d, 1, "%s: start\n", __FUNCTION__);
1354 qxl_hard_reset(d, 1);
1355 qxl_exit_vga_mode(d);
1356 dprint(d, 1, "%s: done\n", __FUNCTION__);
1357 return 0;
1358 }
1359
1360 static int qxl_post_load(void *opaque, int version)
1361 {
1362 PCIQXLDevice* d = opaque;
1363 uint8_t *ram_start = d->vga.vram_ptr;
1364 QXLCommandExt *cmds;
1365 int in, out, i, newmode;
1366
1367 dprint(d, 1, "%s: start\n", __FUNCTION__);
1368
1369 assert(d->last_release_offset < d->vga.vram_size);
1370 if (d->last_release_offset == 0) {
1371 d->last_release = NULL;
1372 } else {
1373 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
1374 }
1375
1376 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
1377
1378 dprint(d, 1, "%s: restore mode\n", __FUNCTION__);
1379 newmode = d->mode;
1380 d->mode = QXL_MODE_UNDEFINED;
1381 switch (newmode) {
1382 case QXL_MODE_UNDEFINED:
1383 break;
1384 case QXL_MODE_VGA:
1385 qxl_enter_vga_mode(d);
1386 break;
1387 case QXL_MODE_NATIVE:
1388 for (i = 0; i < NUM_MEMSLOTS; i++) {
1389 if (!d->guest_slots[i].active) {
1390 continue;
1391 }
1392 qxl_add_memslot(d, i, 0);
1393 }
1394 qxl_create_guest_primary(d, 1);
1395
1396 /* replay surface-create and cursor-set commands */
1397 cmds = qemu_mallocz(sizeof(QXLCommandExt) * (NUM_SURFACES + 1));
1398 for (in = 0, out = 0; in < NUM_SURFACES; in++) {
1399 if (d->guest_surfaces.cmds[in] == 0) {
1400 continue;
1401 }
1402 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
1403 cmds[out].cmd.type = QXL_CMD_SURFACE;
1404 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1405 out++;
1406 }
1407 cmds[out].cmd.data = d->guest_cursor;
1408 cmds[out].cmd.type = QXL_CMD_CURSOR;
1409 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1410 out++;
1411 d->ssd.worker->loadvm_commands(d->ssd.worker, cmds, out);
1412 qemu_free(cmds);
1413
1414 break;
1415 case QXL_MODE_COMPAT:
1416 qxl_set_mode(d, d->shadow_rom.mode, 1);
1417 break;
1418 }
1419 dprint(d, 1, "%s: done\n", __FUNCTION__);
1420
1421 /* spice 0.4 compatibility -- accept but ignore */
1422 qemu_free(d->worker_data);
1423 d->worker_data = NULL;
1424 d->worker_data_size = 0;
1425
1426 return 0;
1427 }
1428
1429 #define QXL_SAVE_VERSION 20
1430
1431 static bool qxl_test_worker_data(void *opaque, int version_id)
1432 {
1433 PCIQXLDevice* d = opaque;
1434
1435 if (d->revision != 1) {
1436 return false;
1437 }
1438 if (!d->worker_data_size) {
1439 return false;
1440 }
1441 if (!d->worker_data) {
1442 d->worker_data = qemu_malloc(d->worker_data_size);
1443 }
1444 return true;
1445 }
1446
1447 static bool qxl_test_spice04(void *opaque, int version_id)
1448 {
1449 PCIQXLDevice* d = opaque;
1450 return d->revision == 1;
1451 }
1452
1453 static bool qxl_test_spice06(void *opaque)
1454 {
1455 PCIQXLDevice* d = opaque;
1456 return d->revision > 1;
1457 }
1458
1459 static VMStateDescription qxl_memslot = {
1460 .name = "qxl-memslot",
1461 .version_id = QXL_SAVE_VERSION,
1462 .minimum_version_id = QXL_SAVE_VERSION,
1463 .fields = (VMStateField[]) {
1464 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
1465 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
1466 VMSTATE_UINT32(active, struct guest_slots),
1467 VMSTATE_END_OF_LIST()
1468 }
1469 };
1470
1471 static VMStateDescription qxl_surface = {
1472 .name = "qxl-surface",
1473 .version_id = QXL_SAVE_VERSION,
1474 .minimum_version_id = QXL_SAVE_VERSION,
1475 .fields = (VMStateField[]) {
1476 VMSTATE_UINT32(width, QXLSurfaceCreate),
1477 VMSTATE_UINT32(height, QXLSurfaceCreate),
1478 VMSTATE_INT32(stride, QXLSurfaceCreate),
1479 VMSTATE_UINT32(format, QXLSurfaceCreate),
1480 VMSTATE_UINT32(position, QXLSurfaceCreate),
1481 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
1482 VMSTATE_UINT32(flags, QXLSurfaceCreate),
1483 VMSTATE_UINT32(type, QXLSurfaceCreate),
1484 VMSTATE_UINT64(mem, QXLSurfaceCreate),
1485 VMSTATE_END_OF_LIST()
1486 }
1487 };
1488
1489 static VMStateDescription qxl_vmstate_spice06 = {
1490 .name = "qxl/spice06",
1491 .version_id = QXL_SAVE_VERSION,
1492 .minimum_version_id = QXL_SAVE_VERSION,
1493 .fields = (VMStateField []) {
1494 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
1495 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
1496 qxl_memslot, struct guest_slots),
1497 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
1498 qxl_surface, QXLSurfaceCreate),
1499 VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice),
1500 VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
1501 vmstate_info_uint64, uint64_t),
1502 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
1503 VMSTATE_END_OF_LIST()
1504 },
1505 };
1506
1507 static VMStateDescription qxl_vmstate = {
1508 .name = "qxl",
1509 .version_id = QXL_SAVE_VERSION,
1510 .minimum_version_id = QXL_SAVE_VERSION,
1511 .pre_save = qxl_pre_save,
1512 .pre_load = qxl_pre_load,
1513 .post_load = qxl_post_load,
1514 .fields = (VMStateField []) {
1515 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
1516 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
1517 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
1518 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
1519 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
1520 VMSTATE_UINT32(mode, PCIQXLDevice),
1521 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
1522
1523 /* spice 0.4 sends/expects them */
1524 VMSTATE_VBUFFER_UINT32(vga.vram_ptr, PCIQXLDevice, 0, qxl_test_spice04, 0,
1525 vga.vram_size),
1526 VMSTATE_UINT32_TEST(worker_data_size, PCIQXLDevice, qxl_test_spice04),
1527 VMSTATE_VBUFFER_UINT32(worker_data, PCIQXLDevice, 0, qxl_test_worker_data, 0,
1528 worker_data_size),
1529
1530 VMSTATE_END_OF_LIST()
1531 },
1532 .subsections = (VMStateSubsection[]) {
1533 {
1534 /* additional spice 0.6 state */
1535 .vmsd = &qxl_vmstate_spice06,
1536 .needed = qxl_test_spice06,
1537 },{
1538 /* end of list */
1539 },
1540 },
1541 };
1542
1543 static PCIDeviceInfo qxl_info_primary = {
1544 .qdev.name = "qxl-vga",
1545 .qdev.desc = "Spice QXL GPU (primary, vga compatible)",
1546 .qdev.size = sizeof(PCIQXLDevice),
1547 .qdev.reset = qxl_reset_handler,
1548 .qdev.vmsd = &qxl_vmstate,
1549 .init = qxl_init_primary,
1550 .config_write = qxl_write_config,
1551 .romfile = "vgabios-qxl.bin",
1552 .qdev.props = (Property[]) {
1553 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024),
1554 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024),
1555 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2),
1556 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1557 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1558 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1559 DEFINE_PROP_END_OF_LIST(),
1560 }
1561 };
1562
1563 static PCIDeviceInfo qxl_info_secondary = {
1564 .qdev.name = "qxl",
1565 .qdev.desc = "Spice QXL GPU (secondary)",
1566 .qdev.size = sizeof(PCIQXLDevice),
1567 .qdev.reset = qxl_reset_handler,
1568 .qdev.vmsd = &qxl_vmstate,
1569 .init = qxl_init_secondary,
1570 .qdev.props = (Property[]) {
1571 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024),
1572 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024),
1573 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2),
1574 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1575 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1576 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1577 DEFINE_PROP_END_OF_LIST(),
1578 }
1579 };
1580
1581 static void qxl_register(void)
1582 {
1583 pci_qdev_register(&qxl_info_primary);
1584 pci_qdev_register(&qxl_info_secondary);
1585 }
1586
1587 device_init(qxl_register);
QEmu