target-sh4: implement flush-to-zero
[qemu.git] / hw / isa.h
blob19aa94c9fd53ed1993534132630ae18a8e211547
1 #ifndef HW_ISA_H
2 #define HW_ISA_H
4 /* ISA bus */
6 #include "ioport.h"
7 #include "qdev.h"
9 typedef struct ISABus ISABus;
10 typedef struct ISADevice ISADevice;
11 typedef struct ISADeviceInfo ISADeviceInfo;
13 struct ISADevice {
14 DeviceState qdev;
15 uint32_t isairq[2];
16 int nirqs;
17 uint16_t ioports[32];
18 int nioports;
21 typedef int (*isa_qdev_initfn)(ISADevice *dev);
22 struct ISADeviceInfo {
23 DeviceInfo qdev;
24 isa_qdev_initfn init;
27 ISABus *isa_bus_new(DeviceState *dev);
28 void isa_bus_irqs(qemu_irq *irqs);
29 qemu_irq isa_reserve_irq(int isairq);
30 void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq);
31 void isa_init_ioport(ISADevice *dev, uint16_t ioport);
32 void isa_init_ioport_range(ISADevice *dev, uint16_t start, uint16_t length);
33 void isa_qdev_register(ISADeviceInfo *info);
34 ISADevice *isa_create(const char *name);
35 ISADevice *isa_create_simple(const char *name);
37 extern target_phys_addr_t isa_mem_base;
39 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
41 /* dma.c */
42 int DMA_get_channel_mode (int nchan);
43 int DMA_read_memory (int nchan, void *buf, int pos, int size);
44 int DMA_write_memory (int nchan, void *buf, int pos, int size);
45 void DMA_hold_DREQ (int nchan);
46 void DMA_release_DREQ (int nchan);
47 void DMA_schedule(int nchan);
48 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit);
49 void DMA_register_channel (int nchan,
50 DMA_transfer_handler transfer_handler,
51 void *opaque);
52 #endif