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pci: implement pci bridge filtering.
[qemu.git] / hw / pci.c
blob336c1a3794a19a1c6fbd3e232495c4a0e752a346
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "pci_host.h"
27 #include "monitor.h"
28 #include "net.h"
29 #include "sysemu.h"
30
31 //#define DEBUG_PCI
32 #ifdef DEBUG_PCI
33 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
34 #else
35 # define PCI_DPRINTF(format, ...) do { } while (0)
36 #endif
37
38 struct PCIBus {
39 BusState qbus;
40 int devfn_min;
41 pci_set_irq_fn set_irq;
42 pci_map_irq_fn map_irq;
43 pci_hotplug_fn hotplug;
44 uint32_t config_reg; /* XXX: suppress */
45 void *irq_opaque;
46 PCIDevice *devices[256];
47 PCIDevice *parent_dev;
48
49 QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
50 QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
51
52 /* The bus IRQ state is the logical OR of the connected devices.
53 Keep a count of the number of devices with raised IRQs. */
54 int nirq;
55 int *irq_count;
56 };
57
58 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
59
60 static struct BusInfo pci_bus_info = {
61 .name = "PCI",
62 .size = sizeof(PCIBus),
63 .print_dev = pcibus_dev_print,
64 .props = (Property[]) {
65 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
66 DEFINE_PROP_END_OF_LIST()
67 }
68 };
69
70 static void pci_update_mappings(PCIDevice *d);
71 static void pci_set_irq(void *opaque, int irq_num, int level);
72
73 target_phys_addr_t pci_mem_base;
74 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
75 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
76
77 struct PCIHostBus {
78 int domain;
79 struct PCIBus *bus;
80 QLIST_ENTRY(PCIHostBus) next;
81 };
82 static QLIST_HEAD(, PCIHostBus) host_buses;
83
84 static const VMStateDescription vmstate_pcibus = {
85 .name = "PCIBUS",
86 .version_id = 1,
87 .minimum_version_id = 1,
88 .minimum_version_id_old = 1,
89 .fields = (VMStateField []) {
90 VMSTATE_INT32_EQUAL(nirq, PCIBus),
91 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
92 VMSTATE_END_OF_LIST()
93 }
94 };
95
96 static int pci_bar(PCIDevice *d, int reg)
97 {
98 uint8_t type;
99
100 if (reg != PCI_ROM_SLOT)
101 return PCI_BASE_ADDRESS_0 + reg * 4;
102
103 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
104 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
105 }
106
107 static void pci_device_reset(PCIDevice *dev)
108 {
109 int r;
110
111 memset(dev->irq_state, 0, sizeof dev->irq_state);
112 dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
113 PCI_COMMAND_MASTER);
114 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
115 dev->config[PCI_INTERRUPT_LINE] = 0x0;
116 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
117 if (!dev->io_regions[r].size) {
118 continue;
119 }
120 pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);
121 }
122 pci_update_mappings(dev);
123 }
124
125 static void pci_bus_reset(void *opaque)
126 {
127 PCIBus *bus = opaque;
128 int i;
129
130 for (i = 0; i < bus->nirq; i++) {
131 bus->irq_count[i] = 0;
132 }
133 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
134 if (bus->devices[i]) {
135 pci_device_reset(bus->devices[i]);
136 }
137 }
138 }
139
140 static void pci_host_bus_register(int domain, PCIBus *bus)
141 {
142 struct PCIHostBus *host;
143 host = qemu_mallocz(sizeof(*host));
144 host->domain = domain;
145 host->bus = bus;
146 QLIST_INSERT_HEAD(&host_buses, host, next);
147 }
148
149 PCIBus *pci_find_host_bus(int domain)
150 {
151 struct PCIHostBus *host;
152
153 QLIST_FOREACH(host, &host_buses, next) {
154 if (host->domain == domain) {
155 return host->bus;
156 }
157 }
158
159 return NULL;
160 }
161
162 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
163 const char *name, int devfn_min)
164 {
165 static int nbus = 0;
166
167 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
168 bus->devfn_min = devfn_min;
169
170 /* host bridge */
171 QLIST_INIT(&bus->child);
172 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
173
174 vmstate_register(nbus++, &vmstate_pcibus, bus);
175 qemu_register_reset(pci_bus_reset, bus);
176 }
177
178 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
179 {
180 PCIBus *bus;
181
182 bus = qemu_mallocz(sizeof(*bus));
183 bus->qbus.qdev_allocated = 1;
184 pci_bus_new_inplace(bus, parent, name, devfn_min);
185 return bus;
186 }
187
188 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
189 void *irq_opaque, int nirq)
190 {
191 bus->set_irq = set_irq;
192 bus->map_irq = map_irq;
193 bus->irq_opaque = irq_opaque;
194 bus->nirq = nirq;
195 bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
196 }
197
198 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
199 {
200 bus->qbus.allow_hotplug = 1;
201 bus->hotplug = hotplug;
202 }
203
204 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
205 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
206 void *irq_opaque, int devfn_min, int nirq)
207 {
208 PCIBus *bus;
209
210 bus = pci_bus_new(parent, name, devfn_min);
211 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
212 return bus;
213 }
214
215 static void pci_register_secondary_bus(PCIBus *parent,
216 PCIBus *bus,
217 PCIDevice *dev,
218 pci_map_irq_fn map_irq,
219 const char *name)
220 {
221 qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
222 bus->map_irq = map_irq;
223 bus->parent_dev = dev;
224
225 QLIST_INIT(&bus->child);
226 QLIST_INSERT_HEAD(&parent->child, bus, sibling);
227 }
228
229 static void pci_unregister_secondary_bus(PCIBus *bus)
230 {
231 assert(QLIST_EMPTY(&bus->child));
232 QLIST_REMOVE(bus, sibling);
233 }
234
235 int pci_bus_num(PCIBus *s)
236 {
237 if (!s->parent_dev)
238 return 0; /* pci host bridge */
239 return s->parent_dev->config[PCI_SECONDARY_BUS];
240 }
241
242 static uint8_t pci_sub_bus(PCIBus *s)
243 {
244 if (!s->parent_dev)
245 return 255; /* pci host bridge */
246 return s->parent_dev->config[PCI_SUBORDINATE_BUS];
247 }
248
249 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
250 {
251 PCIDevice *s = container_of(pv, PCIDevice, config);
252 uint8_t *config;
253 int i;
254
255 assert(size == pci_config_size(s));
256 config = qemu_malloc(size);
257
258 qemu_get_buffer(f, config, size);
259 for (i = 0; i < size; ++i) {
260 if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
261 qemu_free(config);
262 return -EINVAL;
263 }
264 }
265 memcpy(s->config, config, size);
266
267 pci_update_mappings(s);
268
269 qemu_free(config);
270 return 0;
271 }
272
273 /* just put buffer */
274 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
275 {
276 const uint8_t *v = pv;
277 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
278 qemu_put_buffer(f, v, size);
279 }
280
281 static VMStateInfo vmstate_info_pci_config = {
282 .name = "pci config",
283 .get = get_pci_config_device,
284 .put = put_pci_config_device,
285 };
286
287 const VMStateDescription vmstate_pci_device = {
288 .name = "PCIDevice",
289 .version_id = 2,
290 .minimum_version_id = 1,
291 .minimum_version_id_old = 1,
292 .fields = (VMStateField []) {
293 VMSTATE_INT32_LE(version_id, PCIDevice),
294 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
295 vmstate_info_pci_config,
296 PCI_CONFIG_SPACE_SIZE),
297 VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2),
298 VMSTATE_END_OF_LIST()
299 }
300 };
301
302 const VMStateDescription vmstate_pcie_device = {
303 .name = "PCIDevice",
304 .version_id = 2,
305 .minimum_version_id = 1,
306 .minimum_version_id_old = 1,
307 .fields = (VMStateField []) {
308 VMSTATE_INT32_LE(version_id, PCIDevice),
309 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
310 vmstate_info_pci_config,
311 PCIE_CONFIG_SPACE_SIZE),
312 VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2),
313 VMSTATE_END_OF_LIST()
314 }
315 };
316
317 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
318 {
319 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
320 }
321
322 void pci_device_save(PCIDevice *s, QEMUFile *f)
323 {
324 vmstate_save_state(f, pci_get_vmstate(s), s);
325 }
326
327 int pci_device_load(PCIDevice *s, QEMUFile *f)
328 {
329 return vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
330 }
331
332 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
333 {
334 uint16_t *id;
335
336 id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
337 id[0] = cpu_to_le16(pci_default_sub_vendor_id);
338 id[1] = cpu_to_le16(pci_default_sub_device_id);
339 return 0;
340 }
341
342 /*
343 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
344 */
345 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
346 {
347 const char *p;
348 char *e;
349 unsigned long val;
350 unsigned long dom = 0, bus = 0;
351 unsigned slot = 0;
352
353 p = addr;
354 val = strtoul(p, &e, 16);
355 if (e == p)
356 return -1;
357 if (*e == ':') {
358 bus = val;
359 p = e + 1;
360 val = strtoul(p, &e, 16);
361 if (e == p)
362 return -1;
363 if (*e == ':') {
364 dom = bus;
365 bus = val;
366 p = e + 1;
367 val = strtoul(p, &e, 16);
368 if (e == p)
369 return -1;
370 }
371 }
372
373 if (dom > 0xffff || bus > 0xff || val > 0x1f)
374 return -1;
375
376 slot = val;
377
378 if (*e)
379 return -1;
380
381 /* Note: QEMU doesn't implement domains other than 0 */
382 if (!pci_find_bus(pci_find_host_bus(dom), bus))
383 return -1;
384
385 *domp = dom;
386 *busp = bus;
387 *slotp = slot;
388 return 0;
389 }
390
391 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
392 unsigned *slotp)
393 {
394 /* strip legacy tag */
395 if (!strncmp(addr, "pci_addr=", 9)) {
396 addr += 9;
397 }
398 if (pci_parse_devaddr(addr, domp, busp, slotp)) {
399 monitor_printf(mon, "Invalid pci address\n");
400 return -1;
401 }
402 return 0;
403 }
404
405 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
406 {
407 int dom, bus;
408 unsigned slot;
409
410 if (!devaddr) {
411 *devfnp = -1;
412 return pci_find_bus(pci_find_host_bus(0), 0);
413 }
414
415 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
416 return NULL;
417 }
418
419 *devfnp = slot << 3;
420 return pci_find_bus(pci_find_host_bus(0), bus);
421 }
422
423 static void pci_init_cmask(PCIDevice *dev)
424 {
425 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
426 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
427 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
428 dev->cmask[PCI_REVISION_ID] = 0xff;
429 dev->cmask[PCI_CLASS_PROG] = 0xff;
430 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
431 dev->cmask[PCI_HEADER_TYPE] = 0xff;
432 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
433 }
434
435 static void pci_init_wmask(PCIDevice *dev)
436 {
437 int i;
438 int config_size = pci_config_size(dev);
439
440 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
441 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
442 pci_set_word(dev->wmask + PCI_COMMAND,
443 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
444 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
445 dev->wmask[i] = 0xff;
446 }
447
448 static void pci_init_wmask_bridge(PCIDevice *d)
449 {
450 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
451 PCI_SEC_LETENCY_TIMER */
452 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
453
454 /* base and limit */
455 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
456 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
457 pci_set_word(d->wmask + PCI_MEMORY_BASE,
458 PCI_MEMORY_RANGE_MASK & 0xffff);
459 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
460 PCI_MEMORY_RANGE_MASK & 0xffff);
461 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
462 PCI_PREF_RANGE_MASK & 0xffff);
463 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
464 PCI_PREF_RANGE_MASK & 0xffff);
465
466 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
467 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
468
469 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
470 }
471
472 static void pci_config_alloc(PCIDevice *pci_dev)
473 {
474 int config_size = pci_config_size(pci_dev);
475
476 pci_dev->config = qemu_mallocz(config_size);
477 pci_dev->cmask = qemu_mallocz(config_size);
478 pci_dev->wmask = qemu_mallocz(config_size);
479 pci_dev->used = qemu_mallocz(config_size);
480 }
481
482 static void pci_config_free(PCIDevice *pci_dev)
483 {
484 qemu_free(pci_dev->config);
485 qemu_free(pci_dev->cmask);
486 qemu_free(pci_dev->wmask);
487 qemu_free(pci_dev->used);
488 }
489
490 /* -1 for devfn means auto assign */
491 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
492 const char *name, int devfn,
493 PCIConfigReadFunc *config_read,
494 PCIConfigWriteFunc *config_write,
495 uint8_t header_type)
496 {
497 if (devfn < 0) {
498 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
499 if (!bus->devices[devfn])
500 goto found;
501 }
502 return NULL;
503 found: ;
504 } else if (bus->devices[devfn]) {
505 return NULL;
506 }
507 pci_dev->bus = bus;
508 pci_dev->devfn = devfn;
509 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
510 memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
511 pci_config_alloc(pci_dev);
512
513 header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
514 if (header_type == PCI_HEADER_TYPE_NORMAL) {
515 pci_set_default_subsystem_id(pci_dev);
516 }
517 pci_init_cmask(pci_dev);
518 pci_init_wmask(pci_dev);
519 if (header_type == PCI_HEADER_TYPE_BRIDGE) {
520 pci_init_wmask_bridge(pci_dev);
521 }
522
523 if (!config_read)
524 config_read = pci_default_read_config;
525 if (!config_write)
526 config_write = pci_default_write_config;
527 pci_dev->config_read = config_read;
528 pci_dev->config_write = config_write;
529 bus->devices[devfn] = pci_dev;
530 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
531 pci_dev->version_id = 2; /* Current pci device vmstate version */
532 return pci_dev;
533 }
534
535 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
536 int instance_size, int devfn,
537 PCIConfigReadFunc *config_read,
538 PCIConfigWriteFunc *config_write)
539 {
540 PCIDevice *pci_dev;
541
542 pci_dev = qemu_mallocz(instance_size);
543 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
544 config_read, config_write,
545 PCI_HEADER_TYPE_NORMAL);
546 return pci_dev;
547 }
548 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
549 {
550 return addr + pci_mem_base;
551 }
552
553 static void pci_unregister_io_regions(PCIDevice *pci_dev)
554 {
555 PCIIORegion *r;
556 int i;
557
558 for(i = 0; i < PCI_NUM_REGIONS; i++) {
559 r = &pci_dev->io_regions[i];
560 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
561 continue;
562 if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
563 isa_unassign_ioport(r->addr, r->filtered_size);
564 } else {
565 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
566 r->filtered_size,
567 IO_MEM_UNASSIGNED);
568 }
569 }
570 }
571
572 static int pci_unregister_device(DeviceState *dev)
573 {
574 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
575 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
576 int ret = 0;
577
578 if (info->exit)
579 ret = info->exit(pci_dev);
580 if (ret)
581 return ret;
582
583 pci_unregister_io_regions(pci_dev);
584
585 qemu_free_irqs(pci_dev->irq);
586 pci_dev->bus->devices[pci_dev->devfn] = NULL;
587 pci_config_free(pci_dev);
588 return 0;
589 }
590
591 void pci_register_bar(PCIDevice *pci_dev, int region_num,
592 pcibus_t size, int type,
593 PCIMapIORegionFunc *map_func)
594 {
595 PCIIORegion *r;
596 uint32_t addr;
597 pcibus_t wmask;
598
599 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
600 return;
601
602 if (size & (size-1)) {
603 fprintf(stderr, "ERROR: PCI region size must be pow2 "
604 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
605 exit(1);
606 }
607
608 r = &pci_dev->io_regions[region_num];
609 r->addr = PCI_BAR_UNMAPPED;
610 r->size = size;
611 r->filtered_size = size;
612 r->type = type;
613 r->map_func = map_func;
614
615 wmask = ~(size - 1);
616 addr = pci_bar(pci_dev, region_num);
617 if (region_num == PCI_ROM_SLOT) {
618 /* ROM enable bit is writeable */
619 wmask |= PCI_ROM_ADDRESS_ENABLE;
620 }
621 pci_set_long(pci_dev->config + addr, type);
622 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
623 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
624 pci_set_quad(pci_dev->wmask + addr, wmask);
625 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
626 } else {
627 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
628 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
629 }
630 }
631
632 static uint32_t pci_config_get_io_base(PCIDevice *d,
633 uint32_t base, uint32_t base_upper16)
634 {
635 uint32_t val;
636
637 val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
638 if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
639 val |= (uint32_t)pci_get_word(d->config + PCI_IO_BASE_UPPER16) << 16;
640 }
641 return val;
642 }
643
644 static uint64_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
645 {
646 return ((uint64_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
647 << 16;
648 }
649
650 static uint64_t pci_config_get_pref_base(PCIDevice *d,
651 uint32_t base, uint32_t upper)
652 {
653 uint64_t val;
654 val = ((uint64_t)pci_get_word(d->config + base) &
655 PCI_PREF_RANGE_MASK) << 16;
656 val |= (uint64_t)pci_get_long(d->config + upper) << 32;
657 return val;
658 }
659
660 static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
661 {
662 pcibus_t base;
663 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
664 base = pci_config_get_io_base(bridge,
665 PCI_IO_BASE, PCI_IO_BASE_UPPER16);
666 } else {
667 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
668 base = pci_config_get_pref_base(
669 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
670 } else {
671 base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
672 }
673 }
674
675 return base;
676 }
677
678 static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
679 {
680 pcibus_t limit;
681 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
682 limit = pci_config_get_io_base(bridge,
683 PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
684 limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */
685 } else {
686 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
687 limit = pci_config_get_pref_base(
688 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
689 } else {
690 limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
691 }
692 limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
693 }
694 return limit;
695 }
696
697 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
698 uint8_t type)
699 {
700 pcibus_t base = *addr;
701 pcibus_t limit = *addr + *size - 1;
702 PCIDevice *br;
703
704 for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
705 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
706
707 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
708 if (!(cmd & PCI_COMMAND_IO)) {
709 goto no_map;
710 }
711 } else {
712 if (!(cmd & PCI_COMMAND_MEMORY)) {
713 goto no_map;
714 }
715 }
716
717 base = MAX(base, pci_bridge_get_base(br, type));
718 limit = MIN(limit, pci_bridge_get_limit(br, type));
719 }
720
721 if (base > limit) {
722 no_map:
723 *addr = PCI_BAR_UNMAPPED;
724 *size = 0;
725 } else {
726 *addr = base;
727 *size = limit - base + 1;
728 }
729 }
730
731 static void pci_update_mappings(PCIDevice *d)
732 {
733 PCIIORegion *r;
734 int cmd, i;
735 pcibus_t last_addr, new_addr;
736 pcibus_t filtered_size;
737
738 cmd = pci_get_word(d->config + PCI_COMMAND);
739 for(i = 0; i < PCI_NUM_REGIONS; i++) {
740 r = &d->io_regions[i];
741
742 /* this region isn't registered */
743 if (r->size == 0)
744 continue;
745
746 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
747 if (cmd & PCI_COMMAND_IO) {
748 new_addr = pci_get_long(d->config + pci_bar(d, i));
749 new_addr = new_addr & ~(r->size - 1);
750 last_addr = new_addr + r->size - 1;
751 /* NOTE: we have only 64K ioports on PC */
752 if (last_addr <= new_addr || new_addr == 0 ||
753 last_addr >= 0x10000) {
754 new_addr = PCI_BAR_UNMAPPED;
755 }
756 } else {
757 new_addr = PCI_BAR_UNMAPPED;
758 }
759 } else {
760 if (cmd & PCI_COMMAND_MEMORY) {
761 if (r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
762 new_addr = pci_get_quad(d->config + pci_bar(d, i));
763 } else {
764 new_addr = pci_get_long(d->config + pci_bar(d, i));
765 }
766 /* the ROM slot has a specific enable bit */
767 if (i == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE))
768 goto no_mem_map;
769 new_addr = new_addr & ~(r->size - 1);
770 last_addr = new_addr + r->size - 1;
771 /* NOTE: we do not support wrapping */
772 /* XXX: as we cannot support really dynamic
773 mappings, we handle specific values as invalid
774 mappings. */
775 if (last_addr <= new_addr || new_addr == 0 ||
776 last_addr == PCI_BAR_UNMAPPED ||
777
778 /* Now pcibus_t is 64bit.
779 * Check if 32 bit BAR wrap around explicitly.
780 * Without this, PC ide doesn't work well.
781 * TODO: remove this work around.
782 */
783 (!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) &&
784 last_addr >= UINT32_MAX) ||
785
786 /*
787 * OS is allowed to set BAR beyond its addressable
788 * bits. For example, 32 bit OS can set 64bit bar
789 * to >4G. Check it.
790 */
791 last_addr >= TARGET_PHYS_ADDR_MAX) {
792 new_addr = PCI_BAR_UNMAPPED;
793 }
794 } else {
795 no_mem_map:
796 new_addr = PCI_BAR_UNMAPPED;
797 }
798 }
799
800 /* bridge filtering */
801 filtered_size = r->size;
802 if (new_addr != PCI_BAR_UNMAPPED) {
803 pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
804 }
805
806 /* This bar isn't changed */
807 if (new_addr == r->addr && filtered_size == r->filtered_size)
808 continue;
809
810 /* now do the real mapping */
811 if (r->addr != PCI_BAR_UNMAPPED) {
812 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
813 int class;
814 /* NOTE: specific hack for IDE in PC case:
815 only one byte must be mapped. */
816 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
817 if (class == 0x0101 && r->size == 4) {
818 isa_unassign_ioport(r->addr + 2, 1);
819 } else {
820 isa_unassign_ioport(r->addr, r->filtered_size);
821 }
822 } else {
823 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
824 r->filtered_size,
825 IO_MEM_UNASSIGNED);
826 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
827 }
828 }
829 r->addr = new_addr;
830 r->filtered_size = filtered_size;
831 if (r->addr != PCI_BAR_UNMAPPED) {
832 /*
833 * TODO: currently almost all the map funcions assumes
834 * filtered_size == size and addr & ~(size - 1) == addr.
835 * However with bridge filtering, they aren't always true.
836 * Teach them such cases, such that filtered_size < size and
837 * addr & (size - 1) != 0.
838 */
839 r->map_func(d, i, r->addr, r->filtered_size, r->type);
840 }
841 }
842 }
843
844 uint32_t pci_default_read_config(PCIDevice *d,
845 uint32_t address, int len)
846 {
847 uint32_t val = 0;
848 assert(len == 1 || len == 2 || len == 4);
849 len = MIN(len, pci_config_size(d) - address);
850 memcpy(&val, d->config + address, len);
851 return le32_to_cpu(val);
852 }
853
854 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
855 {
856 int i;
857 uint32_t config_size = pci_config_size(d);
858
859 for(i = 0; i < l && addr < config_size; val >>= 8, ++i, ++addr) {
860 uint8_t wmask = d->wmask[addr];
861 d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
862 }
863 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
864 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
865 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
866 range_covers_byte(addr, l, PCI_COMMAND))
867 pci_update_mappings(d);
868 }
869
870 /***********************************************************/
871 /* generic PCI irq support */
872
873 /* 0 <= irq_num <= 3. level must be 0 or 1 */
874 static void pci_set_irq(void *opaque, int irq_num, int level)
875 {
876 PCIDevice *pci_dev = opaque;
877 PCIBus *bus;
878 int change;
879
880 change = level - pci_dev->irq_state[irq_num];
881 if (!change)
882 return;
883
884 pci_dev->irq_state[irq_num] = level;
885 for (;;) {
886 bus = pci_dev->bus;
887 irq_num = bus->map_irq(pci_dev, irq_num);
888 if (bus->set_irq)
889 break;
890 pci_dev = bus->parent_dev;
891 }
892 bus->irq_count[irq_num] += change;
893 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
894 }
895
896 /***********************************************************/
897 /* monitor info on PCI */
898
899 typedef struct {
900 uint16_t class;
901 const char *desc;
902 } pci_class_desc;
903
904 static const pci_class_desc pci_class_descriptions[] =
905 {
906 { 0x0100, "SCSI controller"},
907 { 0x0101, "IDE controller"},
908 { 0x0102, "Floppy controller"},
909 { 0x0103, "IPI controller"},
910 { 0x0104, "RAID controller"},
911 { 0x0106, "SATA controller"},
912 { 0x0107, "SAS controller"},
913 { 0x0180, "Storage controller"},
914 { 0x0200, "Ethernet controller"},
915 { 0x0201, "Token Ring controller"},
916 { 0x0202, "FDDI controller"},
917 { 0x0203, "ATM controller"},
918 { 0x0280, "Network controller"},
919 { 0x0300, "VGA controller"},
920 { 0x0301, "XGA controller"},
921 { 0x0302, "3D controller"},
922 { 0x0380, "Display controller"},
923 { 0x0400, "Video controller"},
924 { 0x0401, "Audio controller"},
925 { 0x0402, "Phone"},
926 { 0x0480, "Multimedia controller"},
927 { 0x0500, "RAM controller"},
928 { 0x0501, "Flash controller"},
929 { 0x0580, "Memory controller"},
930 { 0x0600, "Host bridge"},
931 { 0x0601, "ISA bridge"},
932 { 0x0602, "EISA bridge"},
933 { 0x0603, "MC bridge"},
934 { 0x0604, "PCI bridge"},
935 { 0x0605, "PCMCIA bridge"},
936 { 0x0606, "NUBUS bridge"},
937 { 0x0607, "CARDBUS bridge"},
938 { 0x0608, "RACEWAY bridge"},
939 { 0x0680, "Bridge"},
940 { 0x0c03, "USB controller"},
941 { 0, NULL}
942 };
943
944 static void pci_info_device(PCIBus *bus, PCIDevice *d)
945 {
946 Monitor *mon = cur_mon;
947 int i, class;
948 PCIIORegion *r;
949 const pci_class_desc *desc;
950
951 monitor_printf(mon, " Bus %2d, device %3d, function %d:\n",
952 pci_bus_num(d->bus),
953 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
954 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
955 monitor_printf(mon, " ");
956 desc = pci_class_descriptions;
957 while (desc->desc && class != desc->class)
958 desc++;
959 if (desc->desc) {
960 monitor_printf(mon, "%s", desc->desc);
961 } else {
962 monitor_printf(mon, "Class %04x", class);
963 }
964 monitor_printf(mon, ": PCI device %04x:%04x\n",
965 pci_get_word(d->config + PCI_VENDOR_ID),
966 pci_get_word(d->config + PCI_DEVICE_ID));
967
968 if (d->config[PCI_INTERRUPT_PIN] != 0) {
969 monitor_printf(mon, " IRQ %d.\n",
970 d->config[PCI_INTERRUPT_LINE]);
971 }
972 if (class == 0x0604) {
973 monitor_printf(mon, " BUS %d.\n", d->config[0x19]);
974 }
975 for(i = 0;i < PCI_NUM_REGIONS; i++) {
976 r = &d->io_regions[i];
977 if (r->size != 0) {
978 monitor_printf(mon, " BAR%d: ", i);
979 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
980 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
981 " [0x%04"FMT_PCIBUS"].\n",
982 r->addr, r->addr + r->size - 1);
983 } else {
984 const char *type = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64 ?
985 "64 bit" : "32 bit";
986 const char *prefetch =
987 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH ?
988 " prefetchable" : "";
989
990 monitor_printf(mon, "%s%s memory at 0x%08"FMT_PCIBUS
991 " [0x%08"FMT_PCIBUS"].\n",
992 type, prefetch,
993 r->addr, r->addr + r->size - 1);
994 }
995 }
996 }
997 monitor_printf(mon, " id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
998 if (class == 0x0604 && d->config[0x19] != 0) {
999 pci_for_each_device(bus, d->config[0x19], pci_info_device);
1000 }
1001 }
1002
1003 static void pci_for_each_device_under_bus(PCIBus *bus,
1004 void (*fn)(PCIBus *b, PCIDevice *d))
1005 {
1006 PCIDevice *d;
1007 int devfn;
1008
1009 for(devfn = 0; devfn < 256; devfn++) {
1010 d = bus->devices[devfn];
1011 if (d)
1012 fn(bus, d);
1013 }
1014 }
1015
1016 void pci_for_each_device(PCIBus *bus, int bus_num,
1017 void (*fn)(PCIBus *b, PCIDevice *d))
1018 {
1019 bus = pci_find_bus(bus, bus_num);
1020
1021 if (bus) {
1022 pci_for_each_device_under_bus(bus, fn);
1023 }
1024 }
1025
1026 void pci_info(Monitor *mon)
1027 {
1028 struct PCIHostBus *host;
1029 QLIST_FOREACH(host, &host_buses, next) {
1030 pci_for_each_device(host->bus, 0, pci_info_device);
1031 }
1032 }
1033
1034 static const char * const pci_nic_models[] = {
1035 "ne2k_pci",
1036 "i82551",
1037 "i82557b",
1038 "i82559er",
1039 "rtl8139",
1040 "e1000",
1041 "pcnet",
1042 "virtio",
1043 NULL
1044 };
1045
1046 static const char * const pci_nic_names[] = {
1047 "ne2k_pci",
1048 "i82551",
1049 "i82557b",
1050 "i82559er",
1051 "rtl8139",
1052 "e1000",
1053 "pcnet",
1054 "virtio-net-pci",
1055 NULL
1056 };
1057
1058 /* Initialize a PCI NIC. */
1059 /* FIXME callers should check for failure, but don't */
1060 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1061 const char *default_devaddr)
1062 {
1063 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1064 PCIBus *bus;
1065 int devfn;
1066 PCIDevice *pci_dev;
1067 DeviceState *dev;
1068 int i;
1069
1070 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1071 if (i < 0)
1072 return NULL;
1073
1074 bus = pci_get_bus_devfn(&devfn, devaddr);
1075 if (!bus) {
1076 qemu_error("Invalid PCI device address %s for device %s\n",
1077 devaddr, pci_nic_names[i]);
1078 return NULL;
1079 }
1080
1081 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1082 dev = &pci_dev->qdev;
1083 if (nd->name)
1084 dev->id = qemu_strdup(nd->name);
1085 qdev_set_nic_properties(dev, nd);
1086 if (qdev_init(dev) < 0)
1087 return NULL;
1088 return pci_dev;
1089 }
1090
1091 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1092 const char *default_devaddr)
1093 {
1094 PCIDevice *res;
1095
1096 if (qemu_show_nic_models(nd->model, pci_nic_models))
1097 exit(0);
1098
1099 res = pci_nic_init(nd, default_model, default_devaddr);
1100 if (!res)
1101 exit(1);
1102 return res;
1103 }
1104
1105 typedef struct {
1106 PCIDevice dev;
1107 PCIBus bus;
1108 uint32_t vid;
1109 uint32_t did;
1110 } PCIBridge;
1111
1112
1113 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1114 {
1115 pci_update_mappings(d);
1116 }
1117
1118 static void pci_bridge_update_mappings(PCIBus *b)
1119 {
1120 PCIBus *child;
1121
1122 pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1123
1124 QLIST_FOREACH(child, &b->child, sibling) {
1125 pci_bridge_update_mappings(child);
1126 }
1127 }
1128
1129 static void pci_bridge_write_config(PCIDevice *d,
1130 uint32_t address, uint32_t val, int len)
1131 {
1132 pci_default_write_config(d, address, val, len);
1133
1134 if (/* io base/limit */
1135 ranges_overlap(address, len, PCI_IO_BASE, 2) ||
1136
1137 /* memory base/limit, prefetchable base/limit and
1138 io base/limit upper 16 */
1139 ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
1140 pci_bridge_update_mappings(d->bus);
1141 }
1142 }
1143
1144 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1145 {
1146 PCIBus *sec;
1147
1148 if (!bus)
1149 return NULL;
1150
1151 if (pci_bus_num(bus) == bus_num) {
1152 return bus;
1153 }
1154
1155 /* try child bus */
1156 QLIST_FOREACH(sec, &bus->child, sibling) {
1157 if (pci_bus_num(sec) <= bus_num && bus_num <= pci_sub_bus(sec)) {
1158 return pci_find_bus(sec, bus_num);
1159 }
1160 }
1161
1162 return NULL;
1163 }
1164
1165 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1166 {
1167 bus = pci_find_bus(bus, bus_num);
1168
1169 if (!bus)
1170 return NULL;
1171
1172 return bus->devices[PCI_DEVFN(slot, function)];
1173 }
1174
1175 static int pci_bridge_initfn(PCIDevice *dev)
1176 {
1177 PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
1178
1179 pci_config_set_vendor_id(s->dev.config, s->vid);
1180 pci_config_set_device_id(s->dev.config, s->did);
1181
1182 /* TODO: intial value
1183 * command register:
1184 * According to PCI bridge spec, after reset
1185 * bus master bit is off
1186 * memory space enable bit is off
1187 * According to manual (805-1251.pdf).(See abp_pbi.c for its links.)
1188 * the reset value should be zero unless the boot pin is tied high
1189 * (which is tru) and thus it should be PCI_COMMAND_MEMORY.
1190 *
1191 * For now, don't touch the value.
1192 * Later command register will be set to zero and apb_pci.c will
1193 * override the value.
1194 * Same for latency timer, and multi function bit of header type.
1195 */
1196 pci_set_word(dev->config + PCI_COMMAND,
1197 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1198
1199 pci_set_word(dev->config + PCI_STATUS,
1200 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1201 pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
1202 dev->config[PCI_LATENCY_TIMER] = 0x10;
1203 dev->config[PCI_HEADER_TYPE] =
1204 PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE;
1205 pci_set_word(dev->config + PCI_SEC_STATUS,
1206 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1207 return 0;
1208 }
1209
1210 static int pci_bridge_exitfn(PCIDevice *pci_dev)
1211 {
1212 PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
1213 PCIBus *bus = &s->bus;
1214 pci_unregister_secondary_bus(bus);
1215 return 0;
1216 }
1217
1218 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
1219 pci_map_irq_fn map_irq, const char *name)
1220 {
1221 PCIDevice *dev;
1222 PCIBridge *s;
1223
1224 dev = pci_create(bus, devfn, "pci-bridge");
1225 qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
1226 qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
1227 qdev_init_nofail(&dev->qdev);
1228
1229 s = DO_UPCAST(PCIBridge, dev, dev);
1230 pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name);
1231 return &s->bus;
1232 }
1233
1234 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1235 {
1236 PCIDevice *pci_dev = (PCIDevice *)qdev;
1237 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1238 PCIBus *bus;
1239 int devfn, rc;
1240
1241 /* initialize cap_present for pci_is_express() and pci_config_size() */
1242 if (info->is_express) {
1243 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1244 }
1245
1246 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1247 devfn = pci_dev->devfn;
1248 pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1249 info->config_read, info->config_write,
1250 info->header_type);
1251 assert(pci_dev);
1252 rc = info->init(pci_dev);
1253 if (rc != 0)
1254 return rc;
1255 if (qdev->hotplugged)
1256 bus->hotplug(pci_dev, 1);
1257 return 0;
1258 }
1259
1260 static int pci_unplug_device(DeviceState *qdev)
1261 {
1262 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1263
1264 dev->bus->hotplug(dev, 0);
1265 return 0;
1266 }
1267
1268 void pci_qdev_register(PCIDeviceInfo *info)
1269 {
1270 info->qdev.init = pci_qdev_init;
1271 info->qdev.unplug = pci_unplug_device;
1272 info->qdev.exit = pci_unregister_device;
1273 info->qdev.bus_info = &pci_bus_info;
1274 qdev_register(&info->qdev);
1275 }
1276
1277 void pci_qdev_register_many(PCIDeviceInfo *info)
1278 {
1279 while (info->qdev.name) {
1280 pci_qdev_register(info);
1281 info++;
1282 }
1283 }
1284
1285 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1286 {
1287 DeviceState *dev;
1288
1289 dev = qdev_create(&bus->qbus, name);
1290 qdev_prop_set_uint32(dev, "addr", devfn);
1291 return DO_UPCAST(PCIDevice, qdev, dev);
1292 }
1293
1294 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1295 {
1296 PCIDevice *dev = pci_create(bus, devfn, name);
1297 qdev_init_nofail(&dev->qdev);
1298 return dev;
1299 }
1300
1301 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1302 {
1303 int config_size = pci_config_size(pdev);
1304 int offset = PCI_CONFIG_HEADER_SIZE;
1305 int i;
1306 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1307 if (pdev->used[i])
1308 offset = i + 1;
1309 else if (i - offset + 1 == size)
1310 return offset;
1311 return 0;
1312 }
1313
1314 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1315 uint8_t *prev_p)
1316 {
1317 uint8_t next, prev;
1318
1319 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1320 return 0;
1321
1322 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1323 prev = next + PCI_CAP_LIST_NEXT)
1324 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1325 break;
1326
1327 if (prev_p)
1328 *prev_p = prev;
1329 return next;
1330 }
1331
1332 /* Reserve space and add capability to the linked list in pci config space */
1333 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1334 {
1335 uint8_t offset = pci_find_space(pdev, size);
1336 uint8_t *config = pdev->config + offset;
1337 if (!offset)
1338 return -ENOSPC;
1339 config[PCI_CAP_LIST_ID] = cap_id;
1340 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1341 pdev->config[PCI_CAPABILITY_LIST] = offset;
1342 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1343 memset(pdev->used + offset, 0xFF, size);
1344 /* Make capability read-only by default */
1345 memset(pdev->wmask + offset, 0, size);
1346 /* Check capability by default */
1347 memset(pdev->cmask + offset, 0xFF, size);
1348 return offset;
1349 }
1350
1351 /* Unlink capability from the pci config space. */
1352 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1353 {
1354 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1355 if (!offset)
1356 return;
1357 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1358 /* Make capability writeable again */
1359 memset(pdev->wmask + offset, 0xff, size);
1360 /* Clear cmask as device-specific registers can't be checked */
1361 memset(pdev->cmask + offset, 0, size);
1362 memset(pdev->used + offset, 0, size);
1363
1364 if (!pdev->config[PCI_CAPABILITY_LIST])
1365 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1366 }
1367
1368 /* Reserve space for capability at a known offset (to call after load). */
1369 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1370 {
1371 memset(pdev->used + offset, 0xff, size);
1372 }
1373
1374 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1375 {
1376 return pci_find_capability_list(pdev, cap_id, NULL);
1377 }
1378
1379 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1380 {
1381 PCIDevice *d = (PCIDevice *)dev;
1382 const pci_class_desc *desc;
1383 char ctxt[64];
1384 PCIIORegion *r;
1385 int i, class;
1386
1387 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1388 desc = pci_class_descriptions;
1389 while (desc->desc && class != desc->class)
1390 desc++;
1391 if (desc->desc) {
1392 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1393 } else {
1394 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1395 }
1396
1397 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1398 "pci id %04x:%04x (sub %04x:%04x)\n",
1399 indent, "", ctxt,
1400 d->config[PCI_SECONDARY_BUS],
1401 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1402 pci_get_word(d->config + PCI_VENDOR_ID),
1403 pci_get_word(d->config + PCI_DEVICE_ID),
1404 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1405 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1406 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1407 r = &d->io_regions[i];
1408 if (!r->size)
1409 continue;
1410 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1411 " [0x%"FMT_PCIBUS"]\n",
1412 indent, "",
1413 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1414 r->addr, r->addr + r->size - 1);
1415 }
1416 }
1417
1418 static PCIDeviceInfo bridge_info = {
1419 .qdev.name = "pci-bridge",
1420 .qdev.size = sizeof(PCIBridge),
1421 .init = pci_bridge_initfn,
1422 .exit = pci_bridge_exitfn,
1423 .config_write = pci_bridge_write_config,
1424 .qdev.props = (Property[]) {
1425 DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1426 DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1427 DEFINE_PROP_END_OF_LIST(),
1428 }
1429 };
1430
1431 static void pci_register_devices(void)
1432 {
1433 pci_qdev_register(&bridge_info);
1434 }
1435
1436 device_init(pci_register_devices)
QEmu