2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2009, 2011 Stefan Weil
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * - See TODO comments in code.
29 /* Marker for missing code. */
32 fprintf(stderr, "TODO %s:%u: %s()\n", \
33 __FILE__, __LINE__, __func__); \
37 /* Bitfield n...m (in 32 bit value). */
38 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
40 /* Macros used in tcg_target_op_defs. */
43 #if TCG_TARGET_REG_BITS == 32
48 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
56 /* TODO: documentation. */
57 static const TCGTargetOpDef tcg_target_op_defs
[] = {
58 { INDEX_op_exit_tb
, { NULL
} },
59 { INDEX_op_goto_tb
, { NULL
} },
60 { INDEX_op_br
, { NULL
} },
62 { INDEX_op_ld8u_i32
, { R
, R
} },
63 { INDEX_op_ld8s_i32
, { R
, R
} },
64 { INDEX_op_ld16u_i32
, { R
, R
} },
65 { INDEX_op_ld16s_i32
, { R
, R
} },
66 { INDEX_op_ld_i32
, { R
, R
} },
67 { INDEX_op_st8_i32
, { R
, R
} },
68 { INDEX_op_st16_i32
, { R
, R
} },
69 { INDEX_op_st_i32
, { R
, R
} },
71 { INDEX_op_add_i32
, { R
, RI
, RI
} },
72 { INDEX_op_sub_i32
, { R
, RI
, RI
} },
73 { INDEX_op_mul_i32
, { R
, RI
, RI
} },
74 #if TCG_TARGET_HAS_div_i32
75 { INDEX_op_div_i32
, { R
, R
, R
} },
76 { INDEX_op_divu_i32
, { R
, R
, R
} },
77 { INDEX_op_rem_i32
, { R
, R
, R
} },
78 { INDEX_op_remu_i32
, { R
, R
, R
} },
79 #elif TCG_TARGET_HAS_div2_i32
80 { INDEX_op_div2_i32
, { R
, R
, "0", "1", R
} },
81 { INDEX_op_divu2_i32
, { R
, R
, "0", "1", R
} },
83 /* TODO: Does R, RI, RI result in faster code than R, R, RI?
84 If both operands are constants, we can optimize. */
85 { INDEX_op_and_i32
, { R
, RI
, RI
} },
86 #if TCG_TARGET_HAS_andc_i32
87 { INDEX_op_andc_i32
, { R
, RI
, RI
} },
89 #if TCG_TARGET_HAS_eqv_i32
90 { INDEX_op_eqv_i32
, { R
, RI
, RI
} },
92 #if TCG_TARGET_HAS_nand_i32
93 { INDEX_op_nand_i32
, { R
, RI
, RI
} },
95 #if TCG_TARGET_HAS_nor_i32
96 { INDEX_op_nor_i32
, { R
, RI
, RI
} },
98 { INDEX_op_or_i32
, { R
, RI
, RI
} },
99 #if TCG_TARGET_HAS_orc_i32
100 { INDEX_op_orc_i32
, { R
, RI
, RI
} },
102 { INDEX_op_xor_i32
, { R
, RI
, RI
} },
103 { INDEX_op_shl_i32
, { R
, RI
, RI
} },
104 { INDEX_op_shr_i32
, { R
, RI
, RI
} },
105 { INDEX_op_sar_i32
, { R
, RI
, RI
} },
106 #if TCG_TARGET_HAS_rot_i32
107 { INDEX_op_rotl_i32
, { R
, RI
, RI
} },
108 { INDEX_op_rotr_i32
, { R
, RI
, RI
} },
110 #if TCG_TARGET_HAS_deposit_i32
111 { INDEX_op_deposit_i32
, { R
, "0", R
} },
114 { INDEX_op_brcond_i32
, { R
, RI
} },
116 { INDEX_op_setcond_i32
, { R
, R
, RI
} },
117 #if TCG_TARGET_REG_BITS == 64
118 { INDEX_op_setcond_i64
, { R
, R
, RI
} },
119 #endif /* TCG_TARGET_REG_BITS == 64 */
121 #if TCG_TARGET_REG_BITS == 32
122 /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
123 { INDEX_op_add2_i32
, { R
, R
, R
, R
, R
, R
} },
124 { INDEX_op_sub2_i32
, { R
, R
, R
, R
, R
, R
} },
125 { INDEX_op_brcond2_i32
, { R
, R
, RI
, RI
} },
126 { INDEX_op_mulu2_i32
, { R
, R
, R
, R
} },
127 { INDEX_op_setcond2_i32
, { R
, R
, R
, RI
, RI
} },
130 #if TCG_TARGET_HAS_not_i32
131 { INDEX_op_not_i32
, { R
, R
} },
133 #if TCG_TARGET_HAS_neg_i32
134 { INDEX_op_neg_i32
, { R
, R
} },
137 #if TCG_TARGET_REG_BITS == 64
138 { INDEX_op_ld8u_i64
, { R
, R
} },
139 { INDEX_op_ld8s_i64
, { R
, R
} },
140 { INDEX_op_ld16u_i64
, { R
, R
} },
141 { INDEX_op_ld16s_i64
, { R
, R
} },
142 { INDEX_op_ld32u_i64
, { R
, R
} },
143 { INDEX_op_ld32s_i64
, { R
, R
} },
144 { INDEX_op_ld_i64
, { R
, R
} },
146 { INDEX_op_st8_i64
, { R
, R
} },
147 { INDEX_op_st16_i64
, { R
, R
} },
148 { INDEX_op_st32_i64
, { R
, R
} },
149 { INDEX_op_st_i64
, { R
, R
} },
151 { INDEX_op_add_i64
, { R
, RI
, RI
} },
152 { INDEX_op_sub_i64
, { R
, RI
, RI
} },
153 { INDEX_op_mul_i64
, { R
, RI
, RI
} },
154 #if TCG_TARGET_HAS_div_i64
155 { INDEX_op_div_i64
, { R
, R
, R
} },
156 { INDEX_op_divu_i64
, { R
, R
, R
} },
157 { INDEX_op_rem_i64
, { R
, R
, R
} },
158 { INDEX_op_remu_i64
, { R
, R
, R
} },
159 #elif TCG_TARGET_HAS_div2_i64
160 { INDEX_op_div2_i64
, { R
, R
, "0", "1", R
} },
161 { INDEX_op_divu2_i64
, { R
, R
, "0", "1", R
} },
163 { INDEX_op_and_i64
, { R
, RI
, RI
} },
164 #if TCG_TARGET_HAS_andc_i64
165 { INDEX_op_andc_i64
, { R
, RI
, RI
} },
167 #if TCG_TARGET_HAS_eqv_i64
168 { INDEX_op_eqv_i64
, { R
, RI
, RI
} },
170 #if TCG_TARGET_HAS_nand_i64
171 { INDEX_op_nand_i64
, { R
, RI
, RI
} },
173 #if TCG_TARGET_HAS_nor_i64
174 { INDEX_op_nor_i64
, { R
, RI
, RI
} },
176 { INDEX_op_or_i64
, { R
, RI
, RI
} },
177 #if TCG_TARGET_HAS_orc_i64
178 { INDEX_op_orc_i64
, { R
, RI
, RI
} },
180 { INDEX_op_xor_i64
, { R
, RI
, RI
} },
181 { INDEX_op_shl_i64
, { R
, RI
, RI
} },
182 { INDEX_op_shr_i64
, { R
, RI
, RI
} },
183 { INDEX_op_sar_i64
, { R
, RI
, RI
} },
184 #if TCG_TARGET_HAS_rot_i64
185 { INDEX_op_rotl_i64
, { R
, RI
, RI
} },
186 { INDEX_op_rotr_i64
, { R
, RI
, RI
} },
188 #if TCG_TARGET_HAS_deposit_i64
189 { INDEX_op_deposit_i64
, { R
, "0", R
} },
191 { INDEX_op_brcond_i64
, { R
, RI
} },
193 #if TCG_TARGET_HAS_ext8s_i64
194 { INDEX_op_ext8s_i64
, { R
, R
} },
196 #if TCG_TARGET_HAS_ext16s_i64
197 { INDEX_op_ext16s_i64
, { R
, R
} },
199 #if TCG_TARGET_HAS_ext32s_i64
200 { INDEX_op_ext32s_i64
, { R
, R
} },
202 #if TCG_TARGET_HAS_ext8u_i64
203 { INDEX_op_ext8u_i64
, { R
, R
} },
205 #if TCG_TARGET_HAS_ext16u_i64
206 { INDEX_op_ext16u_i64
, { R
, R
} },
208 #if TCG_TARGET_HAS_ext32u_i64
209 { INDEX_op_ext32u_i64
, { R
, R
} },
211 { INDEX_op_ext_i32_i64
, { R
, R
} },
212 { INDEX_op_extu_i32_i64
, { R
, R
} },
213 #if TCG_TARGET_HAS_bswap16_i64
214 { INDEX_op_bswap16_i64
, { R
, R
} },
216 #if TCG_TARGET_HAS_bswap32_i64
217 { INDEX_op_bswap32_i64
, { R
, R
} },
219 #if TCG_TARGET_HAS_bswap64_i64
220 { INDEX_op_bswap64_i64
, { R
, R
} },
222 #if TCG_TARGET_HAS_not_i64
223 { INDEX_op_not_i64
, { R
, R
} },
225 #if TCG_TARGET_HAS_neg_i64
226 { INDEX_op_neg_i64
, { R
, R
} },
228 #endif /* TCG_TARGET_REG_BITS == 64 */
230 { INDEX_op_qemu_ld_i32
, { R
, L
} },
231 { INDEX_op_qemu_ld_i64
, { R64
, L
} },
233 { INDEX_op_qemu_st_i32
, { R
, S
} },
234 { INDEX_op_qemu_st_i64
, { R64
, S
} },
236 #if TCG_TARGET_HAS_ext8s_i32
237 { INDEX_op_ext8s_i32
, { R
, R
} },
239 #if TCG_TARGET_HAS_ext16s_i32
240 { INDEX_op_ext16s_i32
, { R
, R
} },
242 #if TCG_TARGET_HAS_ext8u_i32
243 { INDEX_op_ext8u_i32
, { R
, R
} },
245 #if TCG_TARGET_HAS_ext16u_i32
246 { INDEX_op_ext16u_i32
, { R
, R
} },
249 #if TCG_TARGET_HAS_bswap16_i32
250 { INDEX_op_bswap16_i32
, { R
, R
} },
252 #if TCG_TARGET_HAS_bswap32_i32
253 { INDEX_op_bswap32_i32
, { R
, R
} },
256 { INDEX_op_mb
, { } },
260 static const TCGTargetOpDef
*tcg_target_op_def(TCGOpcode op
)
262 int i
, n
= ARRAY_SIZE(tcg_target_op_defs
);
264 for (i
= 0; i
< n
; ++i
) {
265 if (tcg_target_op_defs
[i
].op
== op
) {
266 return &tcg_target_op_defs
[i
];
272 static const int tcg_target_reg_alloc_order
[] = {
277 #if 0 /* used for TCG_REG_CALL_STACK */
283 #if TCG_TARGET_NB_REGS >= 16
295 #if MAX_OPC_PARAM_IARGS != 5
296 # error Fix needed, number of supported input arguments changed!
299 static const int tcg_target_call_iarg_regs
[] = {
304 #if 0 /* used for TCG_REG_CALL_STACK */
308 #if TCG_TARGET_REG_BITS == 32
309 /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
312 #if TCG_TARGET_NB_REGS >= 16
317 # error Too few input registers available
322 static const int tcg_target_call_oarg_regs
[] = {
324 #if TCG_TARGET_REG_BITS == 32
329 #ifdef CONFIG_DEBUG_TCG
330 static const char *const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
339 #if TCG_TARGET_NB_REGS >= 16
348 #if TCG_TARGET_NB_REGS >= 32
370 static void patch_reloc(tcg_insn_unit
*code_ptr
, int type
,
371 intptr_t value
, intptr_t addend
)
373 /* tcg_out_reloc always uses the same type, addend. */
374 tcg_debug_assert(type
== sizeof(tcg_target_long
));
375 tcg_debug_assert(addend
== 0);
376 tcg_debug_assert(value
!= 0);
377 if (TCG_TARGET_REG_BITS
== 32) {
378 tcg_patch32(code_ptr
, value
);
380 tcg_patch64(code_ptr
, value
);
384 /* Parse target specific constraints. */
385 static const char *target_parse_constraint(TCGArgConstraint
*ct
,
386 const char *ct_str
, TCGType type
)
390 case 'L': /* qemu_ld constraint */
391 case 'S': /* qemu_st constraint */
392 ct
->ct
|= TCG_CT_REG
;
393 ct
->u
.regs
= BIT(TCG_TARGET_NB_REGS
) - 1;
401 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
402 /* Show current bytecode. Used by tcg interpreter. */
403 void tci_disas(uint8_t opc
)
405 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
406 fprintf(stderr
, "TCG %s %u, %u, %u\n",
407 def
->name
, def
->nb_oargs
, def
->nb_iargs
, def
->nb_cargs
);
411 /* Write value (native size). */
412 static void tcg_out_i(TCGContext
*s
, tcg_target_ulong v
)
414 if (TCG_TARGET_REG_BITS
== 32) {
422 static void tcg_out_op_t(TCGContext
*s
, TCGOpcode op
)
428 /* Write register. */
429 static void tcg_out_r(TCGContext
*s
, TCGArg t0
)
431 tcg_debug_assert(t0
< TCG_TARGET_NB_REGS
);
435 /* Write register or constant (native size). */
436 static void tcg_out_ri(TCGContext
*s
, int const_arg
, TCGArg arg
)
439 tcg_debug_assert(const_arg
== 1);
440 tcg_out8(s
, TCG_CONST
);
447 /* Write register or constant (32 bit). */
448 static void tcg_out_ri32(TCGContext
*s
, int const_arg
, TCGArg arg
)
451 tcg_debug_assert(const_arg
== 1);
452 tcg_out8(s
, TCG_CONST
);
459 #if TCG_TARGET_REG_BITS == 64
460 /* Write register or constant (64 bit). */
461 static void tcg_out_ri64(TCGContext
*s
, int const_arg
, TCGArg arg
)
464 tcg_debug_assert(const_arg
== 1);
465 tcg_out8(s
, TCG_CONST
);
474 static void tci_out_label(TCGContext
*s
, TCGLabel
*label
)
476 if (label
->has_value
) {
477 tcg_out_i(s
, label
->u
.value
);
478 tcg_debug_assert(label
->u
.value
);
480 tcg_out_reloc(s
, s
->code_ptr
, sizeof(tcg_target_ulong
), label
, 0);
481 s
->code_ptr
+= sizeof(tcg_target_ulong
);
485 static void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg1
,
488 uint8_t *old_code_ptr
= s
->code_ptr
;
489 if (type
== TCG_TYPE_I32
) {
490 tcg_out_op_t(s
, INDEX_op_ld_i32
);
495 tcg_debug_assert(type
== TCG_TYPE_I64
);
496 #if TCG_TARGET_REG_BITS == 64
497 tcg_out_op_t(s
, INDEX_op_ld_i64
);
500 tcg_debug_assert(arg2
== (int32_t)arg2
);
506 old_code_ptr
[1] = s
->code_ptr
- old_code_ptr
;
509 static void tcg_out_mov(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
)
511 uint8_t *old_code_ptr
= s
->code_ptr
;
512 tcg_debug_assert(ret
!= arg
);
513 #if TCG_TARGET_REG_BITS == 32
514 tcg_out_op_t(s
, INDEX_op_mov_i32
);
516 tcg_out_op_t(s
, INDEX_op_mov_i64
);
520 old_code_ptr
[1] = s
->code_ptr
- old_code_ptr
;
523 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
524 TCGReg t0
, tcg_target_long arg
)
526 uint8_t *old_code_ptr
= s
->code_ptr
;
527 uint32_t arg32
= arg
;
528 if (type
== TCG_TYPE_I32
|| arg
== arg32
) {
529 tcg_out_op_t(s
, INDEX_op_movi_i32
);
533 tcg_debug_assert(type
== TCG_TYPE_I64
);
534 #if TCG_TARGET_REG_BITS == 64
535 tcg_out_op_t(s
, INDEX_op_movi_i64
);
542 old_code_ptr
[1] = s
->code_ptr
- old_code_ptr
;
545 static inline void tcg_out_call(TCGContext
*s
, tcg_insn_unit
*arg
)
547 uint8_t *old_code_ptr
= s
->code_ptr
;
548 tcg_out_op_t(s
, INDEX_op_call
);
549 tcg_out_ri(s
, 1, (uintptr_t)arg
);
550 old_code_ptr
[1] = s
->code_ptr
- old_code_ptr
;
553 static void tcg_out_op(TCGContext
*s
, TCGOpcode opc
, const TCGArg
*args
,
554 const int *const_args
)
556 uint8_t *old_code_ptr
= s
->code_ptr
;
558 tcg_out_op_t(s
, opc
);
561 case INDEX_op_exit_tb
:
562 tcg_out64(s
, args
[0]);
564 case INDEX_op_goto_tb
:
565 if (s
->tb_jmp_insn_offset
) {
566 /* Direct jump method. */
567 /* Align for atomic patching and thread safety */
568 s
->code_ptr
= QEMU_ALIGN_PTR_UP(s
->code_ptr
, 4);
569 s
->tb_jmp_insn_offset
[args
[0]] = tcg_current_code_size(s
);
572 /* Indirect jump method. */
575 s
->tb_jmp_reset_offset
[args
[0]] = tcg_current_code_size(s
);
578 tci_out_label(s
, arg_label(args
[0]));
580 case INDEX_op_setcond_i32
:
581 tcg_out_r(s
, args
[0]);
582 tcg_out_r(s
, args
[1]);
583 tcg_out_ri32(s
, const_args
[2], args
[2]);
584 tcg_out8(s
, args
[3]); /* condition */
586 #if TCG_TARGET_REG_BITS == 32
587 case INDEX_op_setcond2_i32
:
588 /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
589 tcg_out_r(s
, args
[0]);
590 tcg_out_r(s
, args
[1]);
591 tcg_out_r(s
, args
[2]);
592 tcg_out_ri32(s
, const_args
[3], args
[3]);
593 tcg_out_ri32(s
, const_args
[4], args
[4]);
594 tcg_out8(s
, args
[5]); /* condition */
596 #elif TCG_TARGET_REG_BITS == 64
597 case INDEX_op_setcond_i64
:
598 tcg_out_r(s
, args
[0]);
599 tcg_out_r(s
, args
[1]);
600 tcg_out_ri64(s
, const_args
[2], args
[2]);
601 tcg_out8(s
, args
[3]); /* condition */
604 case INDEX_op_ld8u_i32
:
605 case INDEX_op_ld8s_i32
:
606 case INDEX_op_ld16u_i32
:
607 case INDEX_op_ld16s_i32
:
608 case INDEX_op_ld_i32
:
609 case INDEX_op_st8_i32
:
610 case INDEX_op_st16_i32
:
611 case INDEX_op_st_i32
:
612 case INDEX_op_ld8u_i64
:
613 case INDEX_op_ld8s_i64
:
614 case INDEX_op_ld16u_i64
:
615 case INDEX_op_ld16s_i64
:
616 case INDEX_op_ld32u_i64
:
617 case INDEX_op_ld32s_i64
:
618 case INDEX_op_ld_i64
:
619 case INDEX_op_st8_i64
:
620 case INDEX_op_st16_i64
:
621 case INDEX_op_st32_i64
:
622 case INDEX_op_st_i64
:
623 tcg_out_r(s
, args
[0]);
624 tcg_out_r(s
, args
[1]);
625 tcg_debug_assert(args
[2] == (int32_t)args
[2]);
626 tcg_out32(s
, args
[2]);
628 case INDEX_op_add_i32
:
629 case INDEX_op_sub_i32
:
630 case INDEX_op_mul_i32
:
631 case INDEX_op_and_i32
:
632 case INDEX_op_andc_i32
: /* Optional (TCG_TARGET_HAS_andc_i32). */
633 case INDEX_op_eqv_i32
: /* Optional (TCG_TARGET_HAS_eqv_i32). */
634 case INDEX_op_nand_i32
: /* Optional (TCG_TARGET_HAS_nand_i32). */
635 case INDEX_op_nor_i32
: /* Optional (TCG_TARGET_HAS_nor_i32). */
636 case INDEX_op_or_i32
:
637 case INDEX_op_orc_i32
: /* Optional (TCG_TARGET_HAS_orc_i32). */
638 case INDEX_op_xor_i32
:
639 case INDEX_op_shl_i32
:
640 case INDEX_op_shr_i32
:
641 case INDEX_op_sar_i32
:
642 case INDEX_op_rotl_i32
: /* Optional (TCG_TARGET_HAS_rot_i32). */
643 case INDEX_op_rotr_i32
: /* Optional (TCG_TARGET_HAS_rot_i32). */
644 tcg_out_r(s
, args
[0]);
645 tcg_out_ri32(s
, const_args
[1], args
[1]);
646 tcg_out_ri32(s
, const_args
[2], args
[2]);
648 case INDEX_op_deposit_i32
: /* Optional (TCG_TARGET_HAS_deposit_i32). */
649 tcg_out_r(s
, args
[0]);
650 tcg_out_r(s
, args
[1]);
651 tcg_out_r(s
, args
[2]);
652 tcg_debug_assert(args
[3] <= UINT8_MAX
);
653 tcg_out8(s
, args
[3]);
654 tcg_debug_assert(args
[4] <= UINT8_MAX
);
655 tcg_out8(s
, args
[4]);
658 #if TCG_TARGET_REG_BITS == 64
659 case INDEX_op_add_i64
:
660 case INDEX_op_sub_i64
:
661 case INDEX_op_mul_i64
:
662 case INDEX_op_and_i64
:
663 case INDEX_op_andc_i64
: /* Optional (TCG_TARGET_HAS_andc_i64). */
664 case INDEX_op_eqv_i64
: /* Optional (TCG_TARGET_HAS_eqv_i64). */
665 case INDEX_op_nand_i64
: /* Optional (TCG_TARGET_HAS_nand_i64). */
666 case INDEX_op_nor_i64
: /* Optional (TCG_TARGET_HAS_nor_i64). */
667 case INDEX_op_or_i64
:
668 case INDEX_op_orc_i64
: /* Optional (TCG_TARGET_HAS_orc_i64). */
669 case INDEX_op_xor_i64
:
670 case INDEX_op_shl_i64
:
671 case INDEX_op_shr_i64
:
672 case INDEX_op_sar_i64
:
673 case INDEX_op_rotl_i64
: /* Optional (TCG_TARGET_HAS_rot_i64). */
674 case INDEX_op_rotr_i64
: /* Optional (TCG_TARGET_HAS_rot_i64). */
675 tcg_out_r(s
, args
[0]);
676 tcg_out_ri64(s
, const_args
[1], args
[1]);
677 tcg_out_ri64(s
, const_args
[2], args
[2]);
679 case INDEX_op_deposit_i64
: /* Optional (TCG_TARGET_HAS_deposit_i64). */
680 tcg_out_r(s
, args
[0]);
681 tcg_out_r(s
, args
[1]);
682 tcg_out_r(s
, args
[2]);
683 tcg_debug_assert(args
[3] <= UINT8_MAX
);
684 tcg_out8(s
, args
[3]);
685 tcg_debug_assert(args
[4] <= UINT8_MAX
);
686 tcg_out8(s
, args
[4]);
688 case INDEX_op_div_i64
: /* Optional (TCG_TARGET_HAS_div_i64). */
689 case INDEX_op_divu_i64
: /* Optional (TCG_TARGET_HAS_div_i64). */
690 case INDEX_op_rem_i64
: /* Optional (TCG_TARGET_HAS_div_i64). */
691 case INDEX_op_remu_i64
: /* Optional (TCG_TARGET_HAS_div_i64). */
694 case INDEX_op_div2_i64
: /* Optional (TCG_TARGET_HAS_div2_i64). */
695 case INDEX_op_divu2_i64
: /* Optional (TCG_TARGET_HAS_div2_i64). */
698 case INDEX_op_brcond_i64
:
699 tcg_out_r(s
, args
[0]);
700 tcg_out_ri64(s
, const_args
[1], args
[1]);
701 tcg_out8(s
, args
[2]); /* condition */
702 tci_out_label(s
, arg_label(args
[3]));
704 case INDEX_op_bswap16_i64
: /* Optional (TCG_TARGET_HAS_bswap16_i64). */
705 case INDEX_op_bswap32_i64
: /* Optional (TCG_TARGET_HAS_bswap32_i64). */
706 case INDEX_op_bswap64_i64
: /* Optional (TCG_TARGET_HAS_bswap64_i64). */
707 case INDEX_op_not_i64
: /* Optional (TCG_TARGET_HAS_not_i64). */
708 case INDEX_op_neg_i64
: /* Optional (TCG_TARGET_HAS_neg_i64). */
709 case INDEX_op_ext8s_i64
: /* Optional (TCG_TARGET_HAS_ext8s_i64). */
710 case INDEX_op_ext8u_i64
: /* Optional (TCG_TARGET_HAS_ext8u_i64). */
711 case INDEX_op_ext16s_i64
: /* Optional (TCG_TARGET_HAS_ext16s_i64). */
712 case INDEX_op_ext16u_i64
: /* Optional (TCG_TARGET_HAS_ext16u_i64). */
713 case INDEX_op_ext32s_i64
: /* Optional (TCG_TARGET_HAS_ext32s_i64). */
714 case INDEX_op_ext32u_i64
: /* Optional (TCG_TARGET_HAS_ext32u_i64). */
715 case INDEX_op_ext_i32_i64
:
716 case INDEX_op_extu_i32_i64
:
717 #endif /* TCG_TARGET_REG_BITS == 64 */
718 case INDEX_op_neg_i32
: /* Optional (TCG_TARGET_HAS_neg_i32). */
719 case INDEX_op_not_i32
: /* Optional (TCG_TARGET_HAS_not_i32). */
720 case INDEX_op_ext8s_i32
: /* Optional (TCG_TARGET_HAS_ext8s_i32). */
721 case INDEX_op_ext16s_i32
: /* Optional (TCG_TARGET_HAS_ext16s_i32). */
722 case INDEX_op_ext8u_i32
: /* Optional (TCG_TARGET_HAS_ext8u_i32). */
723 case INDEX_op_ext16u_i32
: /* Optional (TCG_TARGET_HAS_ext16u_i32). */
724 case INDEX_op_bswap16_i32
: /* Optional (TCG_TARGET_HAS_bswap16_i32). */
725 case INDEX_op_bswap32_i32
: /* Optional (TCG_TARGET_HAS_bswap32_i32). */
726 tcg_out_r(s
, args
[0]);
727 tcg_out_r(s
, args
[1]);
729 case INDEX_op_div_i32
: /* Optional (TCG_TARGET_HAS_div_i32). */
730 case INDEX_op_divu_i32
: /* Optional (TCG_TARGET_HAS_div_i32). */
731 case INDEX_op_rem_i32
: /* Optional (TCG_TARGET_HAS_div_i32). */
732 case INDEX_op_remu_i32
: /* Optional (TCG_TARGET_HAS_div_i32). */
733 tcg_out_r(s
, args
[0]);
734 tcg_out_ri32(s
, const_args
[1], args
[1]);
735 tcg_out_ri32(s
, const_args
[2], args
[2]);
737 case INDEX_op_div2_i32
: /* Optional (TCG_TARGET_HAS_div2_i32). */
738 case INDEX_op_divu2_i32
: /* Optional (TCG_TARGET_HAS_div2_i32). */
741 #if TCG_TARGET_REG_BITS == 32
742 case INDEX_op_add2_i32
:
743 case INDEX_op_sub2_i32
:
744 tcg_out_r(s
, args
[0]);
745 tcg_out_r(s
, args
[1]);
746 tcg_out_r(s
, args
[2]);
747 tcg_out_r(s
, args
[3]);
748 tcg_out_r(s
, args
[4]);
749 tcg_out_r(s
, args
[5]);
751 case INDEX_op_brcond2_i32
:
752 tcg_out_r(s
, args
[0]);
753 tcg_out_r(s
, args
[1]);
754 tcg_out_ri32(s
, const_args
[2], args
[2]);
755 tcg_out_ri32(s
, const_args
[3], args
[3]);
756 tcg_out8(s
, args
[4]); /* condition */
757 tci_out_label(s
, arg_label(args
[5]));
759 case INDEX_op_mulu2_i32
:
760 tcg_out_r(s
, args
[0]);
761 tcg_out_r(s
, args
[1]);
762 tcg_out_r(s
, args
[2]);
763 tcg_out_r(s
, args
[3]);
766 case INDEX_op_brcond_i32
:
767 tcg_out_r(s
, args
[0]);
768 tcg_out_ri32(s
, const_args
[1], args
[1]);
769 tcg_out8(s
, args
[2]); /* condition */
770 tci_out_label(s
, arg_label(args
[3]));
772 case INDEX_op_qemu_ld_i32
:
773 tcg_out_r(s
, *args
++);
774 tcg_out_r(s
, *args
++);
775 if (TARGET_LONG_BITS
> TCG_TARGET_REG_BITS
) {
776 tcg_out_r(s
, *args
++);
778 tcg_out_i(s
, *args
++);
780 case INDEX_op_qemu_ld_i64
:
781 tcg_out_r(s
, *args
++);
782 if (TCG_TARGET_REG_BITS
== 32) {
783 tcg_out_r(s
, *args
++);
785 tcg_out_r(s
, *args
++);
786 if (TARGET_LONG_BITS
> TCG_TARGET_REG_BITS
) {
787 tcg_out_r(s
, *args
++);
789 tcg_out_i(s
, *args
++);
791 case INDEX_op_qemu_st_i32
:
792 tcg_out_r(s
, *args
++);
793 tcg_out_r(s
, *args
++);
794 if (TARGET_LONG_BITS
> TCG_TARGET_REG_BITS
) {
795 tcg_out_r(s
, *args
++);
797 tcg_out_i(s
, *args
++);
799 case INDEX_op_qemu_st_i64
:
800 tcg_out_r(s
, *args
++);
801 if (TCG_TARGET_REG_BITS
== 32) {
802 tcg_out_r(s
, *args
++);
804 tcg_out_r(s
, *args
++);
805 if (TARGET_LONG_BITS
> TCG_TARGET_REG_BITS
) {
806 tcg_out_r(s
, *args
++);
808 tcg_out_i(s
, *args
++);
812 case INDEX_op_mov_i32
: /* Always emitted via tcg_out_mov. */
813 case INDEX_op_mov_i64
:
814 case INDEX_op_movi_i32
: /* Always emitted via tcg_out_movi. */
815 case INDEX_op_movi_i64
:
816 case INDEX_op_call
: /* Always emitted via tcg_out_call. */
820 old_code_ptr
[1] = s
->code_ptr
- old_code_ptr
;
823 static void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
, TCGReg arg1
,
826 uint8_t *old_code_ptr
= s
->code_ptr
;
827 if (type
== TCG_TYPE_I32
) {
828 tcg_out_op_t(s
, INDEX_op_st_i32
);
833 tcg_debug_assert(type
== TCG_TYPE_I64
);
834 #if TCG_TARGET_REG_BITS == 64
835 tcg_out_op_t(s
, INDEX_op_st_i64
);
843 old_code_ptr
[1] = s
->code_ptr
- old_code_ptr
;
846 static inline bool tcg_out_sti(TCGContext
*s
, TCGType type
, TCGArg val
,
847 TCGReg base
, intptr_t ofs
)
852 /* Test if a constant matches the constraint. */
853 static int tcg_target_const_match(tcg_target_long val
, TCGType type
,
854 const TCGArgConstraint
*arg_ct
)
856 /* No need to return 0 or 1, 0 or != 0 is good enough. */
857 return arg_ct
->ct
& TCG_CT_CONST
;
860 static void tcg_target_init(TCGContext
*s
)
862 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
863 const char *envval
= getenv("DEBUG_TCG");
865 qemu_set_log(strtol(envval
, NULL
, 0));
869 /* The current code uses uint8_t for tcg operations. */
870 tcg_debug_assert(tcg_op_defs_max
<= UINT8_MAX
);
872 /* Registers available for 32 bit operations. */
873 tcg_target_available_regs
[TCG_TYPE_I32
] = BIT(TCG_TARGET_NB_REGS
) - 1;
874 /* Registers available for 64 bit operations. */
875 tcg_target_available_regs
[TCG_TYPE_I64
] = BIT(TCG_TARGET_NB_REGS
) - 1;
876 /* TODO: Which registers should be set here? */
877 tcg_target_call_clobber_regs
= BIT(TCG_TARGET_NB_REGS
) - 1;
879 s
->reserved_regs
= 0;
880 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_CALL_STACK
);
882 /* We use negative offsets from "sp" so that we can distinguish
883 stores that might pretend to be call arguments. */
884 tcg_set_frame(s
, TCG_REG_CALL_STACK
,
885 -CPU_TEMP_BUF_NLONGS
* sizeof(long),
886 CPU_TEMP_BUF_NLONGS
* sizeof(long));
889 /* Generate global QEMU prologue and epilogue code. */
890 static inline void tcg_target_qemu_prologue(TCGContext
*s
)