hw/ppce500_mpc8544ds.c

   1 /*
   2  * QEMU PowerPC MPC8544DS board emulation
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <yu.liu@freescale.com>
   7  *
   8  * This file is derived from hw/ppc440_bamboo.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "config.h"
  18 #include "qemu-common.h"
  19 #include "net.h"
  20 #include "hw.h"
  21 #include "pc.h"
  22 #include "pci.h"
  23 #include "boards.h"
  24 #include "sysemu.h"
  25 #include "kvm.h"
  26 #include "kvm_ppc.h"
  27 #include "device_tree.h"
  28 #include "openpic.h"
  29 #include "ppc.h"
  30 #include "loader.h"
  31 #include "elf.h"
  32 #include "sysbus.h"
  33 #include "exec-memory.h"
  34 #include "host-utils.h"
  35
  36 #define BINARY_DEVICE_TREE_FILE    "mpc8544ds.dtb"
  37 #define UIMAGE_LOAD_BASE           0
  38 #define DTC_LOAD_PAD               0x500000
  39 #define DTC_PAD_MASK               0xFFFFF
  40 #define INITRD_LOAD_PAD            0x2000000
  41 #define INITRD_PAD_MASK            0xFFFFFF
  42
  43 #define RAM_SIZES_ALIGN            (64UL << 20)
  44
  45 #define MPC8544_CCSRBAR_BASE       0xE0000000ULL
  46 #define MPC8544_CCSRBAR_SIZE       0x00100000ULL
  47 #define MPC8544_MPIC_REGS_BASE     (MPC8544_CCSRBAR_BASE + 0x40000ULL)
  48 #define MPC8544_SERIAL0_REGS_BASE  (MPC8544_CCSRBAR_BASE + 0x4500ULL)
  49 #define MPC8544_SERIAL1_REGS_BASE  (MPC8544_CCSRBAR_BASE + 0x4600ULL)
  50 #define MPC8544_PCI_REGS_BASE      (MPC8544_CCSRBAR_BASE + 0x8000ULL)
  51 #define MPC8544_PCI_REGS_SIZE      0x1000ULL
  52 #define MPC8544_PCI_IO             0xE1000000ULL
  53 #define MPC8544_PCI_IOLEN          0x10000ULL
  54 #define MPC8544_UTIL_BASE          (MPC8544_CCSRBAR_BASE + 0xe0000ULL)
  55 #define MPC8544_SPIN_BASE          0xEF000000ULL
  56
  57 struct boot_info
  58 {
  59     uint32_t dt_base;
  60     uint32_t dt_size;
  61     uint32_t entry;
  62 };
  63
  64 static void pci_map_create(void *fdt, uint32_t *pci_map, uint32_t mpic)
  65 {
  66     int i;
  67     const uint32_t tmp[] = {
  68                              /* IDSEL 0x11 J17 Slot 1 */
  69                              0x8800, 0x0, 0x0, 0x1, mpic, 0x2, 0x1, 0x0, 0x0,
  70                              0x8800, 0x0, 0x0, 0x2, mpic, 0x3, 0x1, 0x0, 0x0,
  71                              0x8800, 0x0, 0x0, 0x3, mpic, 0x4, 0x1, 0x0, 0x0,
  72                              0x8800, 0x0, 0x0, 0x4, mpic, 0x1, 0x1, 0x0, 0x0,
  73
  74                              /* IDSEL 0x12 J16 Slot 2 */
  75                              0x9000, 0x0, 0x0, 0x1, mpic, 0x3, 0x1, 0x0, 0x0,
  76                              0x9000, 0x0, 0x0, 0x2, mpic, 0x4, 0x1, 0x0, 0x0,
  77                              0x9000, 0x0, 0x0, 0x3, mpic, 0x2, 0x1, 0x0, 0x0,
  78                              0x9000, 0x0, 0x0, 0x4, mpic, 0x1, 0x1, 0x0, 0x0,
  79                            };
  80     for (i = 0; i < ARRAY_SIZE(tmp); i++) {
  81         pci_map[i] = cpu_to_be32(tmp[i]);
  82     }
  83 }
  84
  85 static void dt_serial_create(void *fdt, unsigned long long offset,
  86                              const char *soc, const char *mpic,
  87                              const char *alias, int idx, bool defcon)
  88 {
  89     char ser[128];
  90
  91     snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset);
  92     qemu_devtree_add_subnode(fdt, ser);
  93     qemu_devtree_setprop_string(fdt, ser, "device_type", "serial");
  94     qemu_devtree_setprop_string(fdt, ser, "compatible", "ns16550");
  95     qemu_devtree_setprop_cells(fdt, ser, "reg", offset, 0x100);
  96     qemu_devtree_setprop_cell(fdt, ser, "cell-index", idx);
  97     qemu_devtree_setprop_cell(fdt, ser, "clock-frequency", 0);
  98     qemu_devtree_setprop_cells(fdt, ser, "interrupts", 42, 2, 0, 0);
  99     qemu_devtree_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
 100     qemu_devtree_setprop_string(fdt, "/aliases", alias, ser);
 101
 102     if (defcon) {
 103         qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
 104     }
 105 }
 106
 107 static int mpc8544_load_device_tree(CPUPPCState *env,
 108                                     target_phys_addr_t addr,
 109                                     target_phys_addr_t ramsize,
 110                                     target_phys_addr_t initrd_base,
 111                                     target_phys_addr_t initrd_size,
 112                                     const char *kernel_cmdline)
 113 {
 114     int ret = -1;
 115     uint64_t mem_reg_property[] = { 0, cpu_to_be64(ramsize) };
 116     int fdt_size;
 117     void *fdt;
 118     uint8_t hypercall[16];
 119     uint32_t clock_freq = 400000000;
 120     uint32_t tb_freq = 400000000;
 121     int i;
 122     char compatible[] = "MPC8544DS\0MPC85xxDS";
 123     char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
 124     char model[] = "MPC8544DS";
 125     char soc[128];
 126     char mpic[128];
 127     uint32_t mpic_ph;
 128     char gutil[128];
 129     char pci[128];
 130     uint32_t pci_map[9 * 8];
 131     uint32_t pci_ranges[14] =
 132         {
 133             0x2000000, 0x0, 0xc0000000,
 134             0x0, 0xc0000000,
 135             0x0, 0x20000000,
 136
 137             0x1000000, 0x0, 0x0,
 138             0x0, 0xe1000000,
 139             0x0, 0x10000,
 140         };
 141     QemuOpts *machine_opts;
 142     const char *dumpdtb = NULL;
 143     const char *dtb_file = NULL;
 144
 145     machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
 146     if (machine_opts) {
 147         dumpdtb = qemu_opt_get(machine_opts, "dumpdtb");
 148         dtb_file = qemu_opt_get(machine_opts, "dtb");
 149     }
 150
 151     if (dtb_file) {
 152         char *filename;
 153         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
 154         if (!filename) {
 155             goto out;
 156         }
 157
 158         fdt = load_device_tree(filename, &fdt_size);
 159         if (!fdt) {
 160             goto out;
 161         }
 162         goto done;
 163     }
 164
 165     fdt = create_device_tree(&fdt_size);
 166     if (fdt == NULL) {
 167         goto out;
 168     }
 169
 170     /* Manipulate device tree in memory. */
 171     qemu_devtree_setprop_string(fdt, "/", "model", model);
 172     qemu_devtree_setprop(fdt, "/", "compatible", compatible,
 173                          sizeof(compatible));
 174     qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2);
 175     qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2);
 176
 177     qemu_devtree_add_subnode(fdt, "/memory");
 178     qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory");
 179     qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
 180                          sizeof(mem_reg_property));
 181
 182     qemu_devtree_add_subnode(fdt, "/chosen");
 183     if (initrd_size) {
 184         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
 185                                         initrd_base);
 186         if (ret < 0) {
 187             fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
 188         }
 189
 190         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 191                                         (initrd_base + initrd_size));
 192         if (ret < 0) {
 193             fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
 194         }
 195     }
 196
 197     ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
 198                                       kernel_cmdline);
 199     if (ret < 0)
 200         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 201
 202     if (kvm_enabled()) {
 203         /* Read out host's frequencies */
 204         clock_freq = kvmppc_get_clockfreq();
 205         tb_freq = kvmppc_get_tbfreq();
 206
 207         /* indicate KVM hypercall interface */
 208         qemu_devtree_add_subnode(fdt, "/hypervisor");
 209         qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible",
 210                                     "linux,kvm");
 211         kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
 212         qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions",
 213                              hypercall, sizeof(hypercall));
 214     }
 215
 216     /* Create CPU nodes */
 217     qemu_devtree_add_subnode(fdt, "/cpus");
 218     qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1);
 219     qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0);
 220
 221     /* We need to generate the cpu nodes in reverse order, so Linux can pick
 222        the first node as boot node and be happy */
 223     for (i = smp_cpus - 1; i >= 0; i--) {
 224         char cpu_name[128];
 225         uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);
 226
 227         for (env = first_cpu; env != NULL; env = env->next_cpu) {
 228             if (env->cpu_index == i) {
 229                 break;
 230             }
 231         }
 232
 233         if (!env) {
 234             continue;
 235         }
 236
 237         snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index);
 238         qemu_devtree_add_subnode(fdt, cpu_name);
 239         qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
 240         qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
 241         qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu");
 242         qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index);
 243         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",
 244                                   env->dcache_line_size);
 245         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",
 246                                   env->icache_line_size);
 247         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
 248         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
 249         qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
 250         if (env->cpu_index) {
 251             qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled");
 252             qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table");
 253             qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr",
 254                                      cpu_release_addr);
 255         } else {
 256             qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay");
 257         }
 258     }
 259
 260     qemu_devtree_add_subnode(fdt, "/aliases");
 261     /* XXX These should go into their respective devices' code */
 262     snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE);
 263     qemu_devtree_add_subnode(fdt, soc);
 264     qemu_devtree_setprop_string(fdt, soc, "device_type", "soc");
 265     qemu_devtree_setprop(fdt, soc, "compatible", compatible_sb,
 266                          sizeof(compatible_sb));
 267     qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1);
 268     qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1);
 269     qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0,
 270                                MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE,
 271                                MPC8544_CCSRBAR_SIZE);
 272     /* XXX should contain a reasonable value */
 273     qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0);
 274
 275     snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc,
 276              MPC8544_MPIC_REGS_BASE - MPC8544_CCSRBAR_BASE);
 277     qemu_devtree_add_subnode(fdt, mpic);
 278     qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic");
 279     qemu_devtree_setprop_string(fdt, mpic, "compatible", "fsl,mpic");
 280     qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_BASE -
 281                                MPC8544_CCSRBAR_BASE, 0x40000);
 282     qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0);
 283     qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 4);
 284     mpic_ph = qemu_devtree_alloc_phandle(fdt);
 285     qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph);
 286     qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
 287     qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
 288     qemu_devtree_setprop(fdt, mpic, "big-endian", NULL, 0);
 289     qemu_devtree_setprop(fdt, mpic, "single-cpu-affinity", NULL, 0);
 290     qemu_devtree_setprop_cell(fdt, mpic, "last-interrupt-source", 255);
 291
 292     /*
 293      * We have to generate ser1 first, because Linux takes the first
 294      * device it finds in the dt as serial output device. And we generate
 295      * devices in reverse order to the dt.
 296      */
 297     dt_serial_create(fdt, MPC8544_SERIAL1_REGS_BASE - MPC8544_CCSRBAR_BASE,
 298                      soc, mpic, "serial1", 1, false);
 299     dt_serial_create(fdt, MPC8544_SERIAL0_REGS_BASE - MPC8544_CCSRBAR_BASE,
 300                      soc, mpic, "serial0", 0, true);
 301
 302     snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
 303              MPC8544_UTIL_BASE - MPC8544_CCSRBAR_BASE);
 304     qemu_devtree_add_subnode(fdt, gutil);
 305     qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
 306     qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_BASE -
 307                                MPC8544_CCSRBAR_BASE, 0x1000);
 308     qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
 309
 310     snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
 311     qemu_devtree_add_subnode(fdt, pci);
 312     qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0);
 313     qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
 314     qemu_devtree_setprop_string(fdt, pci, "device_type", "pci");
 315     qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
 316                                0x0, 0x7);
 317     pci_map_create(fdt, pci_map, qemu_devtree_get_phandle(fdt, mpic));
 318     qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, sizeof(pci_map));
 319     qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
 320     qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2, 0, 0);
 321     qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255);
 322     for (i = 0; i < 14; i++) {
 323         pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
 324     }
 325     qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
 326     qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
 327                                MPC8544_PCI_REGS_BASE, 0, 0x1000);
 328     qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666);
 329     qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1);
 330     qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2);
 331     qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3);
 332     qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci);
 333
 334 done:
 335     if (dumpdtb) {
 336         /* Dump the dtb to a file and quit */
 337         FILE *f = fopen(dumpdtb, "wb");
 338         size_t len;
 339         len = fwrite(fdt, fdt_size, 1, f);
 340         fclose(f);
 341         if (len != fdt_size) {
 342             exit(1);
 343         }
 344         exit(0);
 345     }
 346
 347     ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
 348     if (ret < 0) {
 349         goto out;
 350     }
 351     g_free(fdt);
 352     ret = fdt_size;
 353
 354 out:
 355
 356     return ret;
 357 }
 358
 359 /* Create -kernel TLB entries for BookE.  */
 360 static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
 361 {
 362     return 63 - clz64(size >> 10);
 363 }
 364
 365 static void mmubooke_create_initial_mapping(CPUPPCState *env)
 366 {
 367     struct boot_info *bi = env->load_info;
 368     ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
 369     target_phys_addr_t size, dt_end;
 370     int ps;
 371
 372     /* Our initial TLB entry needs to cover everything from 0 to
 373        the device tree top */
 374     dt_end = bi->dt_base + bi->dt_size;
 375     ps = booke206_page_size_to_tlb(dt_end) + 1;
 376     size = (ps << MAS1_TSIZE_SHIFT);
 377     tlb->mas1 = MAS1_VALID | size;
 378     tlb->mas2 = 0;
 379     tlb->mas7_3 = 0;
 380     tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
 381
 382     env->tlb_dirty = true;
 383 }
 384
 385 static void mpc8544ds_cpu_reset_sec(void *opaque)
 386 {
 387     PowerPCCPU *cpu = opaque;
 388     CPUPPCState *env = &cpu->env;
 389
 390     cpu_reset(CPU(cpu));
 391
 392     /* Secondary CPU starts in halted state for now. Needs to change when
 393        implementing non-kernel boot. */
 394     env->halted = 1;
 395     env->exception_index = EXCP_HLT;
 396 }
 397
 398 static void mpc8544ds_cpu_reset(void *opaque)
 399 {
 400     PowerPCCPU *cpu = opaque;
 401     CPUPPCState *env = &cpu->env;
 402     struct boot_info *bi = env->load_info;
 403
 404     cpu_reset(CPU(cpu));
 405
 406     /* Set initial guest state. */
 407     env->halted = 0;
 408     env->gpr[1] = (16<<20) - 8;
 409     env->gpr[3] = bi->dt_base;
 410     env->nip = bi->entry;
 411     mmubooke_create_initial_mapping(env);
 412 }
 413
 414 static void mpc8544ds_init(ram_addr_t ram_size,
 415                          const char *boot_device,
 416                          const char *kernel_filename,
 417                          const char *kernel_cmdline,
 418                          const char *initrd_filename,
 419                          const char *cpu_model)
 420 {
 421     MemoryRegion *address_space_mem = get_system_memory();
 422     MemoryRegion *ram = g_new(MemoryRegion, 1);
 423     PCIBus *pci_bus;
 424     CPUPPCState *env = NULL;
 425     uint64_t elf_entry;
 426     uint64_t elf_lowaddr;
 427     target_phys_addr_t entry=0;
 428     target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE;
 429     target_long kernel_size=0;
 430     target_ulong dt_base = 0;
 431     target_ulong initrd_base = 0;
 432     target_long initrd_size=0;
 433     int i=0;
 434     unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
 435     qemu_irq **irqs, *mpic;
 436     DeviceState *dev;
 437     CPUPPCState *firstenv = NULL;
 438
 439     /* Setup CPUs */
 440     if (cpu_model == NULL) {
 441         cpu_model = "e500v2_v30";
 442     }
 443
 444     irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
 445     irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
 446     for (i = 0; i < smp_cpus; i++) {
 447         PowerPCCPU *cpu;
 448         qemu_irq *input;
 449
 450         cpu = cpu_ppc_init(cpu_model);
 451         if (cpu == NULL) {
 452             fprintf(stderr, "Unable to initialize CPU!\n");
 453             exit(1);
 454         }
 455         env = &cpu->env;
 456
 457         if (!firstenv) {
 458             firstenv = env;
 459         }
 460
 461         irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
 462         input = (qemu_irq *)env->irq_inputs;
 463         irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
 464         irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
 465         env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
 466
 467         ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500);
 468
 469         /* Register reset handler */
 470         if (!i) {
 471             /* Primary CPU */
 472             struct boot_info *boot_info;
 473             boot_info = g_malloc0(sizeof(struct boot_info));
 474             qemu_register_reset(mpc8544ds_cpu_reset, cpu);
 475             env->load_info = boot_info;
 476         } else {
 477             /* Secondary CPUs */
 478             qemu_register_reset(mpc8544ds_cpu_reset_sec, cpu);
 479         }
 480     }
 481
 482     env = firstenv;
 483
 484     /* Fixup Memory size on a alignment boundary */
 485     ram_size &= ~(RAM_SIZES_ALIGN - 1);
 486
 487     /* Register Memory */
 488     memory_region_init_ram(ram, "mpc8544ds.ram", ram_size);
 489     vmstate_register_ram_global(ram);
 490     memory_region_add_subregion(address_space_mem, 0, ram);
 491
 492     /* MPIC */
 493     mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE,
 494                      smp_cpus, irqs, NULL);
 495
 496     if (!mpic) {
 497         cpu_abort(env, "MPIC failed to initialize\n");
 498     }
 499
 500     /* Serial */
 501     if (serial_hds[0]) {
 502         serial_mm_init(address_space_mem, MPC8544_SERIAL0_REGS_BASE,
 503                        0, mpic[12+26], 399193,
 504                        serial_hds[0], DEVICE_BIG_ENDIAN);
 505     }
 506
 507     if (serial_hds[1]) {
 508         serial_mm_init(address_space_mem, MPC8544_SERIAL1_REGS_BASE,
 509                        0, mpic[12+26], 399193,
 510                        serial_hds[0], DEVICE_BIG_ENDIAN);
 511     }
 512
 513     /* General Utility device */
 514     sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL);
 515
 516     /* PCI */
 517     dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE,
 518                                 mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]],
 519                                 mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]],
 520                                 NULL);
 521     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 522     if (!pci_bus)
 523         printf("couldn't create PCI controller!\n");
 524
 525     isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN);
 526
 527     if (pci_bus) {
 528         /* Register network interfaces. */
 529         for (i = 0; i < nb_nics; i++) {
 530             pci_nic_init_nofail(&nd_table[i], "virtio", NULL);
 531         }
 532     }
 533
 534     /* Register spinning region */
 535     sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
 536
 537     /* Load kernel. */
 538     if (kernel_filename) {
 539         kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL);
 540         if (kernel_size < 0) {
 541             kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry,
 542                                    &elf_lowaddr, NULL, 1, ELF_MACHINE, 0);
 543             entry = elf_entry;
 544             loadaddr = elf_lowaddr;
 545         }
 546         /* XXX try again as binary */
 547         if (kernel_size < 0) {
 548             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 549                     kernel_filename);
 550             exit(1);
 551         }
 552     }
 553
 554     /* Load initrd. */
 555     if (initrd_filename) {
 556         initrd_base = (kernel_size + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
 557         initrd_size = load_image_targphys(initrd_filename, initrd_base,
 558                                           ram_size - initrd_base);
 559
 560         if (initrd_size < 0) {
 561             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 562                     initrd_filename);
 563             exit(1);
 564         }
 565     }
 566
 567     /* If we're loading a kernel directly, we must load the device tree too. */
 568     if (kernel_filename) {
 569         struct boot_info *boot_info;
 570         int dt_size;
 571
 572         dt_base = (loadaddr + kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
 573         dt_size = mpc8544_load_device_tree(env, dt_base, ram_size, initrd_base,
 574                                            initrd_size, kernel_cmdline);
 575         if (dt_size < 0) {
 576             fprintf(stderr, "couldn't load device tree\n");
 577             exit(1);
 578         }
 579
 580         boot_info = env->load_info;
 581         boot_info->entry = entry;
 582         boot_info->dt_base = dt_base;
 583         boot_info->dt_size = dt_size;
 584     }
 585
 586     if (kvm_enabled()) {
 587         kvmppc_init();
 588     }
 589 }
 590
 591 static QEMUMachine mpc8544ds_machine = {
 592     .name = "mpc8544ds",
 593     .desc = "mpc8544ds",
 594     .init = mpc8544ds_init,
 595     .max_cpus = 15,
 596 };
 597
 598 static void mpc8544ds_machine_init(void)
 599 {
 600     qemu_register_machine(&mpc8544ds_machine);
 601 }
 602
 603 machine_init(mpc8544ds_machine_init);