target/hexagon/cpu.c

   1 /*
   2  *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qemu/qemu-print.h"
  20 #include "cpu.h"
  21 #include "internal.h"
  22 #include "exec/exec-all.h"
  23 #include "qapi/error.h"
  24 #include "hw/qdev-properties.h"
  25 #include "fpu/softfloat-helpers.h"
  26
  27 static void hexagon_v67_cpu_init(Object *obj)
  28 {
  29 }
  30
  31 static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)
  32 {
  33     ObjectClass *oc;
  34     char *typename;
  35     char **cpuname;
  36
  37     cpuname = g_strsplit(cpu_model, ",", 1);
  38     typename = g_strdup_printf(HEXAGON_CPU_TYPE_NAME("%s"), cpuname[0]);
  39     oc = object_class_by_name(typename);
  40     g_strfreev(cpuname);
  41     g_free(typename);
  42     if (!oc || !object_class_dynamic_cast(oc, TYPE_HEXAGON_CPU) ||
  43         object_class_is_abstract(oc)) {
  44         return NULL;
  45     }
  46     return oc;
  47 }
  48
  49 static Property hexagon_lldb_compat_property =
  50     DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false);
  51 static Property hexagon_lldb_stack_adjust_property =
  52     DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust,
  53                          0, qdev_prop_uint32, target_ulong);
  54
  55 const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {
  56    "r0", "r1",  "r2",  "r3",  "r4",   "r5",  "r6",  "r7",
  57    "r8", "r9",  "r10", "r11", "r12",  "r13", "r14", "r15",
  58   "r16", "r17", "r18", "r19", "r20",  "r21", "r22", "r23",
  59   "r24", "r25", "r26", "r27", "r28",  "r29", "r30", "r31",
  60   "sa0", "lc0", "sa1", "lc1", "p3_0", "c5",  "m0",  "m1",
  61   "usr", "pc",  "ugp", "gp",  "cs0",  "cs1", "c14", "c15",
  62   "c16", "c17", "c18", "c19", "pkt_cnt",  "insn_cnt", "hvx_cnt", "c23",
  63   "c24", "c25", "c26", "c27", "c28",  "c29", "c30", "c31",
  64 };
  65
  66 /*
  67  * One of the main debugging techniques is to use "-d cpu" and compare against
  68  * LLDB output when single stepping.  However, the target and qemu put the
  69  * stacks at different locations.  This is used to compensate so the diff is
  70  * cleaner.
  71  */
  72 static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr)
  73 {
  74     HexagonCPU *cpu = env_archcpu(env);
  75     target_ulong stack_adjust = cpu->lldb_stack_adjust;
  76     target_ulong stack_start = env->stack_start;
  77     target_ulong stack_size = 0x10000;
  78
  79     if (stack_adjust == 0) {
  80         return addr;
  81     }
  82
  83     if (stack_start + 0x1000 >= addr && addr >= (stack_start - stack_size)) {
  84         return addr - stack_adjust;
  85     }
  86     return addr;
  87 }
  88
  89 /* HEX_REG_P3_0_ALIASED (aka C4) is an alias for the predicate registers */
  90 static target_ulong read_p3_0(CPUHexagonState *env)
  91 {
  92     int32_t control_reg = 0;
  93     int i;
  94     for (i = NUM_PREGS - 1; i >= 0; i--) {
  95         control_reg <<= 8;
  96         control_reg |= env->pred[i] & 0xff;
  97     }
  98     return control_reg;
  99 }
 100
 101 static void print_reg(FILE *f, CPUHexagonState *env, int regnum)
 102 {
 103     target_ulong value;
 104
 105     if (regnum == HEX_REG_P3_0_ALIASED) {
 106         value = read_p3_0(env);
 107     } else {
 108         value = regnum < 32 ? adjust_stack_ptrs(env, env->gpr[regnum])
 109                             : env->gpr[regnum];
 110     }
 111
 112     qemu_fprintf(f, "  %s = 0x" TARGET_FMT_lx "\n",
 113                  hexagon_regnames[regnum], value);
 114 }
 115
 116 static void print_vreg(FILE *f, CPUHexagonState *env, int regnum,
 117                        bool skip_if_zero)
 118 {
 119     if (skip_if_zero) {
 120         bool nonzero_found = false;
 121         for (int i = 0; i < MAX_VEC_SIZE_BYTES; i++) {
 122             if (env->VRegs[regnum].ub[i] != 0) {
 123                 nonzero_found = true;
 124                 break;
 125             }
 126         }
 127         if (!nonzero_found) {
 128             return;
 129         }
 130     }
 131
 132     qemu_fprintf(f, "  v%d = ( ", regnum);
 133     qemu_fprintf(f, "0x%02x", env->VRegs[regnum].ub[MAX_VEC_SIZE_BYTES - 1]);
 134     for (int i = MAX_VEC_SIZE_BYTES - 2; i >= 0; i--) {
 135         qemu_fprintf(f, ", 0x%02x", env->VRegs[regnum].ub[i]);
 136     }
 137     qemu_fprintf(f, " )\n");
 138 }
 139
 140 void hexagon_debug_vreg(CPUHexagonState *env, int regnum)
 141 {
 142     print_vreg(stdout, env, regnum, false);
 143 }
 144
 145 static void print_qreg(FILE *f, CPUHexagonState *env, int regnum,
 146                        bool skip_if_zero)
 147 {
 148     if (skip_if_zero) {
 149         bool nonzero_found = false;
 150         for (int i = 0; i < MAX_VEC_SIZE_BYTES / 8; i++) {
 151             if (env->QRegs[regnum].ub[i] != 0) {
 152                 nonzero_found = true;
 153                 break;
 154             }
 155         }
 156         if (!nonzero_found) {
 157             return;
 158         }
 159     }
 160
 161     qemu_fprintf(f, "  q%d = ( ", regnum);
 162     qemu_fprintf(f, "0x%02x",
 163                  env->QRegs[regnum].ub[MAX_VEC_SIZE_BYTES / 8 - 1]);
 164     for (int i = MAX_VEC_SIZE_BYTES / 8 - 2; i >= 0; i--) {
 165         qemu_fprintf(f, ", 0x%02x", env->QRegs[regnum].ub[i]);
 166     }
 167     qemu_fprintf(f, " )\n");
 168 }
 169
 170 void hexagon_debug_qreg(CPUHexagonState *env, int regnum)
 171 {
 172     print_qreg(stdout, env, regnum, false);
 173 }
 174
 175 static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags)
 176 {
 177     HexagonCPU *cpu = env_archcpu(env);
 178
 179     if (cpu->lldb_compat) {
 180         /*
 181          * When comparing with LLDB, it doesn't step through single-cycle
 182          * hardware loops the same way.  So, we just skip them here
 183          */
 184         if (env->gpr[HEX_REG_PC] == env->last_pc_dumped) {
 185             return;
 186         }
 187         env->last_pc_dumped = env->gpr[HEX_REG_PC];
 188     }
 189
 190     qemu_fprintf(f, "General Purpose Registers = {\n");
 191     for (int i = 0; i < 32; i++) {
 192         print_reg(f, env, i);
 193     }
 194     print_reg(f, env, HEX_REG_SA0);
 195     print_reg(f, env, HEX_REG_LC0);
 196     print_reg(f, env, HEX_REG_SA1);
 197     print_reg(f, env, HEX_REG_LC1);
 198     print_reg(f, env, HEX_REG_M0);
 199     print_reg(f, env, HEX_REG_M1);
 200     print_reg(f, env, HEX_REG_USR);
 201     print_reg(f, env, HEX_REG_P3_0_ALIASED);
 202     print_reg(f, env, HEX_REG_GP);
 203     print_reg(f, env, HEX_REG_UGP);
 204     print_reg(f, env, HEX_REG_PC);
 205 #ifdef CONFIG_USER_ONLY
 206     /*
 207      * Not modelled in user mode, print junk to minimize the diff's
 208      * with LLDB output
 209      */
 210     qemu_fprintf(f, "  cause = 0x000000db\n");
 211     qemu_fprintf(f, "  badva = 0x00000000\n");
 212     qemu_fprintf(f, "  cs0 = 0x00000000\n");
 213     qemu_fprintf(f, "  cs1 = 0x00000000\n");
 214 #else
 215     print_reg(f, env, HEX_REG_CAUSE);
 216     print_reg(f, env, HEX_REG_BADVA);
 217     print_reg(f, env, HEX_REG_CS0);
 218     print_reg(f, env, HEX_REG_CS1);
 219 #endif
 220     qemu_fprintf(f, "}\n");
 221
 222     if (flags & CPU_DUMP_FPU) {
 223         qemu_fprintf(f, "Vector Registers = {\n");
 224         for (int i = 0; i < NUM_VREGS; i++) {
 225             print_vreg(f, env, i, true);
 226         }
 227         for (int i = 0; i < NUM_QREGS; i++) {
 228             print_qreg(f, env, i, true);
 229         }
 230         qemu_fprintf(f, "}\n");
 231     }
 232 }
 233
 234 static void hexagon_dump_state(CPUState *cs, FILE *f, int flags)
 235 {
 236     HexagonCPU *cpu = HEXAGON_CPU(cs);
 237     CPUHexagonState *env = &cpu->env;
 238
 239     hexagon_dump(env, f, flags);
 240 }
 241
 242 void hexagon_debug(CPUHexagonState *env)
 243 {
 244     hexagon_dump(env, stdout, CPU_DUMP_FPU);
 245 }
 246
 247 static void hexagon_cpu_set_pc(CPUState *cs, vaddr value)
 248 {
 249     HexagonCPU *cpu = HEXAGON_CPU(cs);
 250     CPUHexagonState *env = &cpu->env;
 251     env->gpr[HEX_REG_PC] = value;
 252 }
 253
 254 static vaddr hexagon_cpu_get_pc(CPUState *cs)
 255 {
 256     HexagonCPU *cpu = HEXAGON_CPU(cs);
 257     CPUHexagonState *env = &cpu->env;
 258     return env->gpr[HEX_REG_PC];
 259 }
 260
 261 static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
 262                                             const TranslationBlock *tb)
 263 {
 264     HexagonCPU *cpu = HEXAGON_CPU(cs);
 265     CPUHexagonState *env = &cpu->env;
 266     env->gpr[HEX_REG_PC] = tb_pc(tb);
 267 }
 268
 269 static bool hexagon_cpu_has_work(CPUState *cs)
 270 {
 271     return true;
 272 }
 273
 274 static void hexagon_restore_state_to_opc(CPUState *cs,
 275                                          const TranslationBlock *tb,
 276                                          const uint64_t *data)
 277 {
 278     HexagonCPU *cpu = HEXAGON_CPU(cs);
 279     CPUHexagonState *env = &cpu->env;
 280
 281     env->gpr[HEX_REG_PC] = data[0];
 282 }
 283
 284 static void hexagon_cpu_reset_hold(Object *obj)
 285 {
 286     CPUState *cs = CPU(obj);
 287     HexagonCPU *cpu = HEXAGON_CPU(cs);
 288     HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(cpu);
 289     CPUHexagonState *env = &cpu->env;
 290
 291     if (mcc->parent_phases.hold) {
 292         mcc->parent_phases.hold(obj);
 293     }
 294
 295     set_default_nan_mode(1, &env->fp_status);
 296     set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
 297 }
 298
 299 static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 300 {
 301     info->print_insn = print_insn_hexagon;
 302 }
 303
 304 static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
 305 {
 306     CPUState *cs = CPU(dev);
 307     HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(dev);
 308     Error *local_err = NULL;
 309
 310     cpu_exec_realizefn(cs, &local_err);
 311     if (local_err != NULL) {
 312         error_propagate(errp, local_err);
 313         return;
 314     }
 315
 316     qemu_init_vcpu(cs);
 317     cpu_reset(cs);
 318
 319     mcc->parent_realize(dev, errp);
 320 }
 321
 322 static void hexagon_cpu_init(Object *obj)
 323 {
 324     HexagonCPU *cpu = HEXAGON_CPU(obj);
 325
 326     cpu_set_cpustate_pointers(cpu);
 327     qdev_property_add_static(DEVICE(obj), &hexagon_lldb_compat_property);
 328     qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property);
 329 }
 330
 331 #include "hw/core/tcg-cpu-ops.h"
 332
 333 static const struct TCGCPUOps hexagon_tcg_ops = {
 334     .initialize = hexagon_translate_init,
 335     .synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
 336     .restore_state_to_opc = hexagon_restore_state_to_opc,
 337 };
 338
 339 static void hexagon_cpu_class_init(ObjectClass *c, void *data)
 340 {
 341     HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c);
 342     CPUClass *cc = CPU_CLASS(c);
 343     DeviceClass *dc = DEVICE_CLASS(c);
 344     ResettableClass *rc = RESETTABLE_CLASS(c);
 345
 346     device_class_set_parent_realize(dc, hexagon_cpu_realize,
 347                                     &mcc->parent_realize);
 348
 349     resettable_class_set_parent_phases(rc, NULL, hexagon_cpu_reset_hold, NULL,
 350                                        &mcc->parent_phases);
 351
 352     cc->class_by_name = hexagon_cpu_class_by_name;
 353     cc->has_work = hexagon_cpu_has_work;
 354     cc->dump_state = hexagon_dump_state;
 355     cc->set_pc = hexagon_cpu_set_pc;
 356     cc->get_pc = hexagon_cpu_get_pc;
 357     cc->gdb_read_register = hexagon_gdb_read_register;
 358     cc->gdb_write_register = hexagon_gdb_write_register;
 359     cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS + NUM_VREGS + NUM_QREGS;
 360     cc->gdb_stop_before_watchpoint = true;
 361     cc->disas_set_info = hexagon_cpu_disas_set_info;
 362     cc->tcg_ops = &hexagon_tcg_ops;
 363 }
 364
 365 #define DEFINE_CPU(type_name, initfn)      \
 366     {                                      \
 367         .name = type_name,                 \
 368         .parent = TYPE_HEXAGON_CPU,        \
 369         .instance_init = initfn            \
 370     }
 371
 372 static const TypeInfo hexagon_cpu_type_infos[] = {
 373     {
 374         .name = TYPE_HEXAGON_CPU,
 375         .parent = TYPE_CPU,
 376         .instance_size = sizeof(HexagonCPU),
 377         .instance_init = hexagon_cpu_init,
 378         .abstract = true,
 379         .class_size = sizeof(HexagonCPUClass),
 380         .class_init = hexagon_cpu_class_init,
 381     },
 382     DEFINE_CPU(TYPE_HEXAGON_CPU_V67,              hexagon_v67_cpu_init),
 383 };
 384
 385 DEFINE_TYPES(hexagon_cpu_type_infos)