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Merge tag 'qemu-macppc-20230206' of https://github.com/mcayland/qemu into staging
[qemu.git] / hw / intc / pnv_xive2.c
blob7176d7023406f58520deb674438d5c725ed469f1
1 /*
2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10)
3 *
4 * Copyright (c) 2019-2022, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu/log.h"
12 #include "qapi/error.h"
13 #include "target/ppc/cpu.h"
14 #include "sysemu/cpus.h"
15 #include "sysemu/dma.h"
16 #include "monitor/monitor.h"
17 #include "hw/ppc/fdt.h"
18 #include "hw/ppc/pnv.h"
19 #include "hw/ppc/pnv_chip.h"
20 #include "hw/ppc/pnv_core.h"
21 #include "hw/ppc/pnv_xscom.h"
22 #include "hw/ppc/xive2.h"
23 #include "hw/ppc/pnv_xive.h"
24 #include "hw/ppc/xive_regs.h"
25 #include "hw/ppc/xive2_regs.h"
26 #include "hw/ppc/ppc.h"
27 #include "hw/qdev-properties.h"
28 #include "sysemu/reset.h"
29
30 #include <libfdt.h>
31
32 #include "pnv_xive2_regs.h"
33
34 #undef XIVE2_DEBUG
35
36 /*
37 * Virtual structures table (VST)
38 */
39 #define SBE_PER_BYTE 4
40
41 typedef struct XiveVstInfo {
42 const char *name;
43 uint32_t size;
44 uint32_t max_blocks;
45 } XiveVstInfo;
46
47 static const XiveVstInfo vst_infos[] = {
48
49 [VST_EAS] = { "EAT", sizeof(Xive2Eas), 16 },
50 [VST_ESB] = { "ESB", 1, 16 },
51 [VST_END] = { "ENDT", sizeof(Xive2End), 16 },
52
53 [VST_NVP] = { "NVPT", sizeof(Xive2Nvp), 16 },
54 [VST_NVG] = { "NVGT", sizeof(Xive2Nvgc), 16 },
55 [VST_NVC] = { "NVCT", sizeof(Xive2Nvgc), 16 },
56
57 [VST_IC] = { "IC", 1 /* ? */ , 16 }, /* Topology # */
58 [VST_SYNC] = { "SYNC", 1 /* ? */ , 16 }, /* Topology # */
59
60 /*
61 * This table contains the backing store pages for the interrupt
62 * fifos of the VC sub-engine in case of overflow.
63 *
64 * 0 - IPI,
65 * 1 - HWD,
66 * 2 - NxC,
67 * 3 - INT,
68 * 4 - OS-Queue,
69 * 5 - Pool-Queue,
70 * 6 - Hard-Queue
71 */
72 [VST_ERQ] = { "ERQ", 1, VC_QUEUE_COUNT },
73 };
74
75 #define xive2_error(xive, fmt, ...) \
76 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \
77 (xive)->chip->chip_id, ## __VA_ARGS__);
78
79 /*
80 * TODO: Document block id override
81 */
82 static uint32_t pnv_xive2_block_id(PnvXive2 *xive)
83 {
84 uint8_t blk = xive->chip->chip_id;
85 uint64_t cfg_val = xive->cq_regs[CQ_XIVE_CFG >> 3];
86
87 if (cfg_val & CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE) {
88 blk = GETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, cfg_val);
89 }
90
91 return blk;
92 }
93
94 /*
95 * Remote access to controllers. HW uses MMIOs. For now, a simple scan
96 * of the chips is good enough.
97 *
98 * TODO: Block scope support
99 */
100 static PnvXive2 *pnv_xive2_get_remote(uint8_t blk)
101 {
102 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
103 int i;
104
105 for (i = 0; i < pnv->num_chips; i++) {
106 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
107 PnvXive2 *xive = &chip10->xive;
108
109 if (pnv_xive2_block_id(xive) == blk) {
110 return xive;
111 }
112 }
113 return NULL;
114 }
115
116 /*
117 * VST accessors for ESB, EAT, ENDT, NVP
118 *
119 * Indirect VST tables are arrays of VSDs pointing to a page (of same
120 * size). Each page is a direct VST table.
121 */
122
123 #define XIVE_VSD_SIZE 8
124
125 /* Indirect page size can be 4K, 64K, 2M, 16M. */
126 static uint64_t pnv_xive2_vst_page_size_allowed(uint32_t page_shift)
127 {
128 return page_shift == 12 || page_shift == 16 ||
129 page_shift == 21 || page_shift == 24;
130 }
131
132 static uint64_t pnv_xive2_vst_addr_direct(PnvXive2 *xive, uint32_t type,
133 uint64_t vsd, uint32_t idx)
134 {
135 const XiveVstInfo *info = &vst_infos[type];
136 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK;
137 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12);
138 uint32_t idx_max;
139
140 idx_max = vst_tsize / info->size - 1;
141 if (idx > idx_max) {
142 #ifdef XIVE2_DEBUG
143 xive2_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?",
144 info->name, idx, idx_max);
145 #endif
146 return 0;
147 }
148
149 return vst_addr + idx * info->size;
150 }
151
152 static uint64_t pnv_xive2_vst_addr_indirect(PnvXive2 *xive, uint32_t type,
153 uint64_t vsd, uint32_t idx)
154 {
155 const XiveVstInfo *info = &vst_infos[type];
156 uint64_t vsd_addr;
157 uint32_t vsd_idx;
158 uint32_t page_shift;
159 uint32_t vst_per_page;
160
161 /* Get the page size of the indirect table. */
162 vsd_addr = vsd & VSD_ADDRESS_MASK;
163 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED);
164
165 if (!(vsd & VSD_ADDRESS_MASK)) {
166 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx);
167 return 0;
168 }
169
170 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12;
171
172 if (!pnv_xive2_vst_page_size_allowed(page_shift)) {
173 xive2_error(xive, "VST: invalid %s page shift %d", info->name,
174 page_shift);
175 return 0;
176 }
177
178 vst_per_page = (1ull << page_shift) / info->size;
179 vsd_idx = idx / vst_per_page;
180
181 /* Load the VSD we are looking for, if not already done */
182 if (vsd_idx) {
183 vsd_addr = vsd_addr + vsd_idx * XIVE_VSD_SIZE;
184 ldq_be_dma(&address_space_memory, vsd_addr, &vsd,
185 MEMTXATTRS_UNSPECIFIED);
186
187 if (!(vsd & VSD_ADDRESS_MASK)) {
188 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx);
189 return 0;
190 }
191
192 /*
193 * Check that the pages have a consistent size across the
194 * indirect table
195 */
196 if (page_shift != GETFIELD(VSD_TSIZE, vsd) + 12) {
197 xive2_error(xive, "VST: %s entry %x indirect page size differ !?",
198 info->name, idx);
199 return 0;
200 }
201 }
202
203 return pnv_xive2_vst_addr_direct(xive, type, vsd, (idx % vst_per_page));
204 }
205
206 static uint64_t pnv_xive2_vst_addr(PnvXive2 *xive, uint32_t type, uint8_t blk,
207 uint32_t idx)
208 {
209 const XiveVstInfo *info = &vst_infos[type];
210 uint64_t vsd;
211
212 if (blk >= info->max_blocks) {
213 xive2_error(xive, "VST: invalid block id %d for VST %s %d !?",
214 blk, info->name, idx);
215 return 0;
216 }
217
218 vsd = xive->vsds[type][blk];
219
220 /* Remote VST access */
221 if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) {
222 xive = pnv_xive2_get_remote(blk);
223
224 return xive ? pnv_xive2_vst_addr(xive, type, blk, idx) : 0;
225 }
226
227 if (VSD_INDIRECT & vsd) {
228 return pnv_xive2_vst_addr_indirect(xive, type, vsd, idx);
229 }
230
231 return pnv_xive2_vst_addr_direct(xive, type, vsd, idx);
232 }
233
234 static int pnv_xive2_vst_read(PnvXive2 *xive, uint32_t type, uint8_t blk,
235 uint32_t idx, void *data)
236 {
237 const XiveVstInfo *info = &vst_infos[type];
238 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx);
239
240 if (!addr) {
241 return -1;
242 }
243
244 cpu_physical_memory_read(addr, data, info->size);
245 return 0;
246 }
247
248 #define XIVE_VST_WORD_ALL -1
249
250 static int pnv_xive2_vst_write(PnvXive2 *xive, uint32_t type, uint8_t blk,
251 uint32_t idx, void *data, uint32_t word_number)
252 {
253 const XiveVstInfo *info = &vst_infos[type];
254 uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx);
255
256 if (!addr) {
257 return -1;
258 }
259
260 if (word_number == XIVE_VST_WORD_ALL) {
261 cpu_physical_memory_write(addr, data, info->size);
262 } else {
263 cpu_physical_memory_write(addr + word_number * 4,
264 data + word_number * 4, 4);
265 }
266 return 0;
267 }
268
269 static int pnv_xive2_get_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx,
270 uint8_t *pq)
271 {
272 PnvXive2 *xive = PNV_XIVE2(xrtr);
273
274 if (pnv_xive2_block_id(xive) != blk) {
275 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx));
276 return -1;
277 }
278
279 *pq = xive_source_esb_get(&xive->ipi_source, idx);
280 return 0;
281 }
282
283 static int pnv_xive2_set_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx,
284 uint8_t *pq)
285 {
286 PnvXive2 *xive = PNV_XIVE2(xrtr);
287
288 if (pnv_xive2_block_id(xive) != blk) {
289 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx));
290 return -1;
291 }
292
293 *pq = xive_source_esb_set(&xive->ipi_source, idx, *pq);
294 return 0;
295 }
296
297 static int pnv_xive2_get_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx,
298 Xive2End *end)
299 {
300 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_END, blk, idx, end);
301 }
302
303 static int pnv_xive2_write_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx,
304 Xive2End *end, uint8_t word_number)
305 {
306 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_END, blk, idx, end,
307 word_number);
308 }
309
310 static int pnv_xive2_end_update(PnvXive2 *xive)
311 {
312 uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID,
313 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]);
314 uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX,
315 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]);
316 int i;
317 uint64_t endc_watch[4];
318
319 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) {
320 endc_watch[i] =
321 cpu_to_be64(xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i]);
322 }
323
324 return pnv_xive2_vst_write(xive, VST_END, blk, idx, endc_watch,
325 XIVE_VST_WORD_ALL);
326 }
327
328 static void pnv_xive2_end_cache_load(PnvXive2 *xive)
329 {
330 uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID,
331 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]);
332 uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX,
333 xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]);
334 uint64_t endc_watch[4] = { 0 };
335 int i;
336
337 if (pnv_xive2_vst_read(xive, VST_END, blk, idx, endc_watch)) {
338 xive2_error(xive, "VST: no END entry %x/%x !?", blk, idx);
339 }
340
341 for (i = 0; i < ARRAY_SIZE(endc_watch); i++) {
342 xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i] =
343 be64_to_cpu(endc_watch[i]);
344 }
345 }
346
347 static int pnv_xive2_get_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx,
348 Xive2Nvp *nvp)
349 {
350 return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp);
351 }
352
353 static int pnv_xive2_write_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx,
354 Xive2Nvp *nvp, uint8_t word_number)
355 {
356 return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp,
357 word_number);
358 }
359
360 static int pnv_xive2_nvp_update(PnvXive2 *xive)
361 {
362 uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID,
363 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]);
364 uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX,
365 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]);
366 int i;
367 uint64_t nxc_watch[4];
368
369 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) {
370 nxc_watch[i] =
371 cpu_to_be64(xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i]);
372 }
373
374 return pnv_xive2_vst_write(xive, VST_NVP, blk, idx, nxc_watch,
375 XIVE_VST_WORD_ALL);
376 }
377
378 static void pnv_xive2_nvp_cache_load(PnvXive2 *xive)
379 {
380 uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID,
381 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]);
382 uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX,
383 xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]);
384 uint64_t nxc_watch[4] = { 0 };
385 int i;
386
387 if (pnv_xive2_vst_read(xive, VST_NVP, blk, idx, nxc_watch)) {
388 xive2_error(xive, "VST: no NVP entry %x/%x !?", blk, idx);
389 }
390
391 for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) {
392 xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i] =
393 be64_to_cpu(nxc_watch[i]);
394 }
395 }
396
397 static int pnv_xive2_get_eas(Xive2Router *xrtr, uint8_t blk, uint32_t idx,
398 Xive2Eas *eas)
399 {
400 PnvXive2 *xive = PNV_XIVE2(xrtr);
401
402 if (pnv_xive2_block_id(xive) != blk) {
403 xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx));
404 return -1;
405 }
406
407 return pnv_xive2_vst_read(xive, VST_EAS, blk, idx, eas);
408 }
409
410 static uint32_t pnv_xive2_get_config(Xive2Router *xrtr)
411 {
412 PnvXive2 *xive = PNV_XIVE2(xrtr);
413 uint32_t cfg = 0;
414
415 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS) {
416 cfg |= XIVE2_GEN1_TIMA_OS;
417 }
418
419 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE) {
420 cfg |= XIVE2_VP_SAVE_RESTORE;
421 }
422
423 if (GETFIELD(CQ_XIVE_CFG_HYP_HARD_RANGE,
424 xive->cq_regs[CQ_XIVE_CFG >> 3]) == CQ_XIVE_CFG_THREADID_8BITS) {
425 cfg |= XIVE2_THREADID_8BITS;
426 }
427
428 return cfg;
429 }
430
431 static bool pnv_xive2_is_cpu_enabled(PnvXive2 *xive, PowerPCCPU *cpu)
432 {
433 int pir = ppc_cpu_pir(cpu);
434 uint32_t fc = PNV10_PIR2FUSEDCORE(pir);
435 uint64_t reg = fc < 8 ? TCTXT_EN0 : TCTXT_EN1;
436 uint32_t bit = pir & 0x3f;
437
438 return xive->tctxt_regs[reg >> 3] & PPC_BIT(bit);
439 }
440
441 static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format,
442 uint8_t nvt_blk, uint32_t nvt_idx,
443 bool cam_ignore, uint8_t priority,
444 uint32_t logic_serv, XiveTCTXMatch *match)
445 {
446 PnvXive2 *xive = PNV_XIVE2(xptr);
447 PnvChip *chip = xive->chip;
448 int count = 0;
449 int i, j;
450 bool gen1_tima_os =
451 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS;
452
453 for (i = 0; i < chip->nr_cores; i++) {
454 PnvCore *pc = chip->cores[i];
455 CPUCore *cc = CPU_CORE(pc);
456
457 for (j = 0; j < cc->nr_threads; j++) {
458 PowerPCCPU *cpu = pc->threads[j];
459 XiveTCTX *tctx;
460 int ring;
461
462 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) {
463 continue;
464 }
465
466 tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
467
468 if (gen1_tima_os) {
469 ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk,
470 nvt_idx, cam_ignore,
471 logic_serv);
472 } else {
473 ring = xive2_presenter_tctx_match(xptr, tctx, format, nvt_blk,
474 nvt_idx, cam_ignore,
475 logic_serv);
476 }
477
478 /*
479 * Save the context and follow on to catch duplicates,
480 * that we don't support yet.
481 */
482 if (ring != -1) {
483 if (match->tctx) {
484 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a "
485 "thread context NVT %x/%x\n",
486 nvt_blk, nvt_idx);
487 return false;
488 }
489
490 match->ring = ring;
491 match->tctx = tctx;
492 count++;
493 }
494 }
495 }
496
497 return count;
498 }
499
500 static uint8_t pnv_xive2_get_block_id(Xive2Router *xrtr)
501 {
502 return pnv_xive2_block_id(PNV_XIVE2(xrtr));
503 }
504
505 /*
506 * The TIMA MMIO space is shared among the chips and to identify the
507 * chip from which the access is being done, we extract the chip id
508 * from the PIR.
509 */
510 static PnvXive2 *pnv_xive2_tm_get_xive(PowerPCCPU *cpu)
511 {
512 int pir = ppc_cpu_pir(cpu);
513 XivePresenter *xptr = XIVE_TCTX(pnv_cpu_state(cpu)->intc)->xptr;
514 PnvXive2 *xive = PNV_XIVE2(xptr);
515
516 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) {
517 xive2_error(xive, "IC: CPU %x is not enabled", pir);
518 }
519 return xive;
520 }
521
522 /*
523 * The internal sources of the interrupt controller have no knowledge
524 * of the XIVE2 chip on which they reside. Encode the block id in the
525 * source interrupt number before forwarding the source event
526 * notification to the Router. This is required on a multichip system.
527 */
528 static void pnv_xive2_notify(XiveNotifier *xn, uint32_t srcno, bool pq_checked)
529 {
530 PnvXive2 *xive = PNV_XIVE2(xn);
531 uint8_t blk = pnv_xive2_block_id(xive);
532
533 xive2_router_notify(xn, XIVE_EAS(blk, srcno), pq_checked);
534 }
535
536 /*
537 * Set Translation Tables
538 *
539 * TODO add support for multiple sets
540 */
541 static int pnv_xive2_stt_set_data(PnvXive2 *xive, uint64_t val)
542 {
543 uint8_t tsel = GETFIELD(CQ_TAR_SELECT, xive->cq_regs[CQ_TAR >> 3]);
544 uint8_t entry = GETFIELD(CQ_TAR_ENTRY_SELECT,
545 xive->cq_regs[CQ_TAR >> 3]);
546
547 switch (tsel) {
548 case CQ_TAR_NVPG:
549 case CQ_TAR_ESB:
550 case CQ_TAR_END:
551 xive->tables[tsel][entry] = val;
552 break;
553 default:
554 xive2_error(xive, "IC: unsupported table %d", tsel);
555 return -1;
556 }
557
558 if (xive->cq_regs[CQ_TAR >> 3] & CQ_TAR_AUTOINC) {
559 xive->cq_regs[CQ_TAR >> 3] = SETFIELD(CQ_TAR_ENTRY_SELECT,
560 xive->cq_regs[CQ_TAR >> 3], ++entry);
561 }
562
563 return 0;
564 }
565 /*
566 * Virtual Structure Tables (VST) configuration
567 */
568 static void pnv_xive2_vst_set_exclusive(PnvXive2 *xive, uint8_t type,
569 uint8_t blk, uint64_t vsd)
570 {
571 Xive2EndSource *end_xsrc = &xive->end_source;
572 XiveSource *xsrc = &xive->ipi_source;
573 const XiveVstInfo *info = &vst_infos[type];
574 uint32_t page_shift = GETFIELD(VSD_TSIZE, vsd) + 12;
575 uint64_t vst_tsize = 1ull << page_shift;
576 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK;
577
578 /* Basic checks */
579
580 if (VSD_INDIRECT & vsd) {
581 if (!pnv_xive2_vst_page_size_allowed(page_shift)) {
582 xive2_error(xive, "VST: invalid %s page shift %d", info->name,
583 page_shift);
584 return;
585 }
586 }
587
588 if (!QEMU_IS_ALIGNED(vst_addr, 1ull << page_shift)) {
589 xive2_error(xive, "VST: %s table address 0x%"PRIx64
590 " is not aligned with page shift %d",
591 info->name, vst_addr, page_shift);
592 return;
593 }
594
595 /* Record the table configuration (in SRAM on HW) */
596 xive->vsds[type][blk] = vsd;
597
598 /* Now tune the models with the configuration provided by the FW */
599
600 switch (type) {
601 case VST_ESB:
602 /*
603 * Backing store pages for the source PQ bits. The model does
604 * not use these PQ bits backed in RAM because the XiveSource
605 * model has its own.
606 *
607 * If the table is direct, we can compute the number of PQ
608 * entries provisioned by FW (such as skiboot) and resize the
609 * ESB window accordingly.
610 */
611 if (!(VSD_INDIRECT & vsd)) {
612 memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE
613 * (1ull << xsrc->esb_shift));
614 }
615
616 memory_region_add_subregion(&xive->esb_mmio, 0, &xsrc->esb_mmio);
617 break;
618
619 case VST_EAS: /* Nothing to be done */
620 break;
621
622 case VST_END:
623 /*
624 * Backing store pages for the END.
625 */
626 if (!(VSD_INDIRECT & vsd)) {
627 memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size)
628 * (1ull << end_xsrc->esb_shift));
629 }
630 memory_region_add_subregion(&xive->end_mmio, 0, &end_xsrc->esb_mmio);
631 break;
632
633 case VST_NVP: /* Not modeled */
634 case VST_NVG: /* Not modeled */
635 case VST_NVC: /* Not modeled */
636 case VST_IC: /* Not modeled */
637 case VST_SYNC: /* Not modeled */
638 case VST_ERQ: /* Not modeled */
639 break;
640
641 default:
642 g_assert_not_reached();
643 }
644 }
645
646 /*
647 * Both PC and VC sub-engines are configured as each use the Virtual
648 * Structure Tables
649 */
650 static void pnv_xive2_vst_set_data(PnvXive2 *xive, uint64_t vsd)
651 {
652 uint8_t mode = GETFIELD(VSD_MODE, vsd);
653 uint8_t type = GETFIELD(VC_VSD_TABLE_SELECT,
654 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]);
655 uint8_t blk = GETFIELD(VC_VSD_TABLE_ADDRESS,
656 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]);
657 uint64_t vst_addr = vsd & VSD_ADDRESS_MASK;
658
659 if (type > VST_ERQ) {
660 xive2_error(xive, "VST: invalid table type %d", type);
661 return;
662 }
663
664 if (blk >= vst_infos[type].max_blocks) {
665 xive2_error(xive, "VST: invalid block id %d for"
666 " %s table", blk, vst_infos[type].name);
667 return;
668 }
669
670 if (!vst_addr) {
671 xive2_error(xive, "VST: invalid %s table address",
672 vst_infos[type].name);
673 return;
674 }
675
676 switch (mode) {
677 case VSD_MODE_FORWARD:
678 xive->vsds[type][blk] = vsd;
679 break;
680
681 case VSD_MODE_EXCLUSIVE:
682 pnv_xive2_vst_set_exclusive(xive, type, blk, vsd);
683 break;
684
685 default:
686 xive2_error(xive, "VST: unsupported table mode %d", mode);
687 return;
688 }
689 }
690
691 /*
692 * MMIO handlers
693 */
694
695
696 /*
697 * IC BAR layout
698 *
699 * Page 0: Internal CQ register accesses (reads & writes)
700 * Page 1: Internal PC register accesses (reads & writes)
701 * Page 2: Internal VC register accesses (reads & writes)
702 * Page 3: Internal TCTXT (TIMA) reg accesses (read & writes)
703 * Page 4: Notify Port page (writes only, w/data),
704 * Page 5: Reserved
705 * Page 6: Sync Poll page (writes only, dataless)
706 * Page 7: Sync Inject page (writes only, dataless)
707 * Page 8: LSI Trigger page (writes only, dataless)
708 * Page 9: LSI SB Management page (reads & writes dataless)
709 * Pages 10-255: Reserved
710 * Pages 256-383: Direct mapped Thread Context Area (reads & writes)
711 * covering the 128 threads in P10.
712 * Pages 384-511: Reserved
713 */
714 typedef struct PnvXive2Region {
715 const char *name;
716 uint32_t pgoff;
717 uint32_t pgsize;
718 const MemoryRegionOps *ops;
719 } PnvXive2Region;
720
721 static const MemoryRegionOps pnv_xive2_ic_cq_ops;
722 static const MemoryRegionOps pnv_xive2_ic_pc_ops;
723 static const MemoryRegionOps pnv_xive2_ic_vc_ops;
724 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops;
725 static const MemoryRegionOps pnv_xive2_ic_notify_ops;
726 static const MemoryRegionOps pnv_xive2_ic_sync_ops;
727 static const MemoryRegionOps pnv_xive2_ic_lsi_ops;
728 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops;
729
730 /* 512 pages. 4K: 2M range, 64K: 32M range */
731 static const PnvXive2Region pnv_xive2_ic_regions[] = {
732 { "xive-ic-cq", 0, 1, &pnv_xive2_ic_cq_ops },
733 { "xive-ic-vc", 1, 1, &pnv_xive2_ic_vc_ops },
734 { "xive-ic-pc", 2, 1, &pnv_xive2_ic_pc_ops },
735 { "xive-ic-tctxt", 3, 1, &pnv_xive2_ic_tctxt_ops },
736 { "xive-ic-notify", 4, 1, &pnv_xive2_ic_notify_ops },
737 /* page 5 reserved */
738 { "xive-ic-sync", 6, 2, &pnv_xive2_ic_sync_ops },
739 { "xive-ic-lsi", 8, 2, &pnv_xive2_ic_lsi_ops },
740 /* pages 10-255 reserved */
741 { "xive-ic-tm-indirect", 256, 128, &pnv_xive2_ic_tm_indirect_ops },
742 /* pages 384-511 reserved */
743 };
744
745 /*
746 * CQ operations
747 */
748
749 static uint64_t pnv_xive2_ic_cq_read(void *opaque, hwaddr offset,
750 unsigned size)
751 {
752 PnvXive2 *xive = PNV_XIVE2(opaque);
753 uint32_t reg = offset >> 3;
754 uint64_t val = 0;
755
756 switch (offset) {
757 case CQ_XIVE_CAP: /* Set at reset */
758 case CQ_XIVE_CFG:
759 val = xive->cq_regs[reg];
760 break;
761 case CQ_MSGSND: /* TODO check the #cores of the machine */
762 val = 0xffffffff00000000;
763 break;
764 case CQ_CFG_PB_GEN:
765 val = CQ_CFG_PB_GEN_PB_INIT; /* TODO: fix CQ_CFG_PB_GEN default value */
766 break;
767 default:
768 xive2_error(xive, "CQ: invalid read @%"HWADDR_PRIx, offset);
769 }
770
771 return val;
772 }
773
774 static uint64_t pnv_xive2_bar_size(uint64_t val)
775 {
776 return 1ull << (GETFIELD(CQ_BAR_RANGE, val) + 24);
777 }
778
779 static void pnv_xive2_ic_cq_write(void *opaque, hwaddr offset,
780 uint64_t val, unsigned size)
781 {
782 PnvXive2 *xive = PNV_XIVE2(opaque);
783 MemoryRegion *sysmem = get_system_memory();
784 uint32_t reg = offset >> 3;
785 int i;
786
787 switch (offset) {
788 case CQ_XIVE_CFG:
789 case CQ_RST_CTL: /* TODO: reset all BARs */
790 break;
791
792 case CQ_IC_BAR:
793 xive->ic_shift = val & CQ_IC_BAR_64K ? 16 : 12;
794 if (!(val & CQ_IC_BAR_VALID)) {
795 xive->ic_base = 0;
796 if (xive->cq_regs[reg] & CQ_IC_BAR_VALID) {
797 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) {
798 memory_region_del_subregion(&xive->ic_mmio,
799 &xive->ic_mmios[i]);
800 }
801 memory_region_del_subregion(sysmem, &xive->ic_mmio);
802 }
803 } else {
804 xive->ic_base = val & ~(CQ_IC_BAR_VALID | CQ_IC_BAR_64K);
805 if (!(xive->cq_regs[reg] & CQ_IC_BAR_VALID)) {
806 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) {
807 memory_region_add_subregion(&xive->ic_mmio,
808 pnv_xive2_ic_regions[i].pgoff << xive->ic_shift,
809 &xive->ic_mmios[i]);
810 }
811 memory_region_add_subregion(sysmem, xive->ic_base,
812 &xive->ic_mmio);
813 }
814 }
815 break;
816
817 case CQ_TM_BAR:
818 xive->tm_shift = val & CQ_TM_BAR_64K ? 16 : 12;
819 if (!(val & CQ_TM_BAR_VALID)) {
820 xive->tm_base = 0;
821 if (xive->cq_regs[reg] & CQ_TM_BAR_VALID) {
822 memory_region_del_subregion(sysmem, &xive->tm_mmio);
823 }
824 } else {
825 xive->tm_base = val & ~(CQ_TM_BAR_VALID | CQ_TM_BAR_64K);
826 if (!(xive->cq_regs[reg] & CQ_TM_BAR_VALID)) {
827 memory_region_add_subregion(sysmem, xive->tm_base,
828 &xive->tm_mmio);
829 }
830 }
831 break;
832
833 case CQ_ESB_BAR:
834 xive->esb_shift = val & CQ_BAR_64K ? 16 : 12;
835 if (!(val & CQ_BAR_VALID)) {
836 xive->esb_base = 0;
837 if (xive->cq_regs[reg] & CQ_BAR_VALID) {
838 memory_region_del_subregion(sysmem, &xive->esb_mmio);
839 }
840 } else {
841 xive->esb_base = val & CQ_BAR_ADDR;
842 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) {
843 memory_region_set_size(&xive->esb_mmio,
844 pnv_xive2_bar_size(val));
845 memory_region_add_subregion(sysmem, xive->esb_base,
846 &xive->esb_mmio);
847 }
848 }
849 break;
850
851 case CQ_END_BAR:
852 xive->end_shift = val & CQ_BAR_64K ? 16 : 12;
853 if (!(val & CQ_BAR_VALID)) {
854 xive->end_base = 0;
855 if (xive->cq_regs[reg] & CQ_BAR_VALID) {
856 memory_region_del_subregion(sysmem, &xive->end_mmio);
857 }
858 } else {
859 xive->end_base = val & CQ_BAR_ADDR;
860 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) {
861 memory_region_set_size(&xive->end_mmio,
862 pnv_xive2_bar_size(val));
863 memory_region_add_subregion(sysmem, xive->end_base,
864 &xive->end_mmio);
865 }
866 }
867 break;
868
869 case CQ_NVC_BAR:
870 xive->nvc_shift = val & CQ_BAR_64K ? 16 : 12;
871 if (!(val & CQ_BAR_VALID)) {
872 xive->nvc_base = 0;
873 if (xive->cq_regs[reg] & CQ_BAR_VALID) {
874 memory_region_del_subregion(sysmem, &xive->nvc_mmio);
875 }
876 } else {
877 xive->nvc_base = val & CQ_BAR_ADDR;
878 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) {
879 memory_region_set_size(&xive->nvc_mmio,
880 pnv_xive2_bar_size(val));
881 memory_region_add_subregion(sysmem, xive->nvc_base,
882 &xive->nvc_mmio);
883 }
884 }
885 break;
886
887 case CQ_NVPG_BAR:
888 xive->nvpg_shift = val & CQ_BAR_64K ? 16 : 12;
889 if (!(val & CQ_BAR_VALID)) {
890 xive->nvpg_base = 0;
891 if (xive->cq_regs[reg] & CQ_BAR_VALID) {
892 memory_region_del_subregion(sysmem, &xive->nvpg_mmio);
893 }
894 } else {
895 xive->nvpg_base = val & CQ_BAR_ADDR;
896 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) {
897 memory_region_set_size(&xive->nvpg_mmio,
898 pnv_xive2_bar_size(val));
899 memory_region_add_subregion(sysmem, xive->nvpg_base,
900 &xive->nvpg_mmio);
901 }
902 }
903 break;
904
905 case CQ_TAR: /* Set Translation Table Address */
906 break;
907 case CQ_TDR: /* Set Translation Table Data */
908 pnv_xive2_stt_set_data(xive, val);
909 break;
910 case CQ_FIRMASK_OR: /* FIR error reporting */
911 break;
912 default:
913 xive2_error(xive, "CQ: invalid write 0x%"HWADDR_PRIx, offset);
914 return;
915 }
916
917 xive->cq_regs[reg] = val;
918 }
919
920 static const MemoryRegionOps pnv_xive2_ic_cq_ops = {
921 .read = pnv_xive2_ic_cq_read,
922 .write = pnv_xive2_ic_cq_write,
923 .endianness = DEVICE_BIG_ENDIAN,
924 .valid = {
925 .min_access_size = 8,
926 .max_access_size = 8,
927 },
928 .impl = {
929 .min_access_size = 8,
930 .max_access_size = 8,
931 },
932 };
933
934 static uint64_t pnv_xive2_ic_vc_read(void *opaque, hwaddr offset,
935 unsigned size)
936 {
937 PnvXive2 *xive = PNV_XIVE2(opaque);
938 uint64_t val = 0;
939 uint32_t reg = offset >> 3;
940
941 switch (offset) {
942 /*
943 * VSD table settings.
944 */
945 case VC_VSD_TABLE_ADDR:
946 case VC_VSD_TABLE_DATA:
947 val = xive->vc_regs[reg];
948 break;
949
950 /*
951 * ESB cache updates (not modeled)
952 */
953 case VC_ESBC_FLUSH_CTRL:
954 xive->vc_regs[reg] &= ~VC_ESBC_FLUSH_CTRL_POLL_VALID;
955 val = xive->vc_regs[reg];
956 break;
957
958 /*
959 * EAS cache updates (not modeled)
960 */
961 case VC_EASC_FLUSH_CTRL:
962 xive->vc_regs[reg] &= ~VC_EASC_FLUSH_CTRL_POLL_VALID;
963 val = xive->vc_regs[reg];
964 break;
965
966 /*
967 * END cache updates
968 */
969 case VC_ENDC_WATCH0_SPEC:
970 xive->vc_regs[reg] &= ~(VC_ENDC_WATCH_FULL | VC_ENDC_WATCH_CONFLICT);
971 val = xive->vc_regs[reg];
972 break;
973
974 case VC_ENDC_WATCH0_DATA0:
975 /*
976 * Load DATA registers from cache with data requested by the
977 * SPEC register
978 */
979 pnv_xive2_end_cache_load(xive);
980 val = xive->vc_regs[reg];
981 break;
982
983 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3:
984 val = xive->vc_regs[reg];
985 break;
986
987 case VC_ENDC_FLUSH_CTRL:
988 xive->vc_regs[reg] &= ~VC_ENDC_FLUSH_CTRL_POLL_VALID;
989 val = xive->vc_regs[reg];
990 break;
991
992 /*
993 * Indirect invalidation
994 */
995 case VC_AT_MACRO_KILL_MASK:
996 val = xive->vc_regs[reg];
997 break;
998
999 case VC_AT_MACRO_KILL:
1000 xive->vc_regs[reg] &= ~VC_AT_MACRO_KILL_VALID;
1001 val = xive->vc_regs[reg];
1002 break;
1003
1004 /*
1005 * Interrupt fifo overflow in memory backing store (Not modeled)
1006 */
1007 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6:
1008 val = xive->vc_regs[reg];
1009 break;
1010
1011 /*
1012 * Synchronisation
1013 */
1014 case VC_ENDC_SYNC_DONE:
1015 val = VC_ENDC_SYNC_POLL_DONE;
1016 break;
1017 default:
1018 xive2_error(xive, "VC: invalid read @%"HWADDR_PRIx, offset);
1019 }
1020
1021 return val;
1022 }
1023
1024 static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset,
1025 uint64_t val, unsigned size)
1026 {
1027 PnvXive2 *xive = PNV_XIVE2(opaque);
1028 uint32_t reg = offset >> 3;
1029
1030 switch (offset) {
1031 /*
1032 * VSD table settings.
1033 */
1034 case VC_VSD_TABLE_ADDR:
1035 break;
1036 case VC_VSD_TABLE_DATA:
1037 pnv_xive2_vst_set_data(xive, val);
1038 break;
1039
1040 /*
1041 * ESB cache updates (not modeled)
1042 */
1043 /* case VC_ESBC_FLUSH_CTRL: */
1044 case VC_ESBC_FLUSH_POLL:
1045 xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |= VC_ESBC_FLUSH_CTRL_POLL_VALID;
1046 /* ESB update */
1047 break;
1048
1049 /*
1050 * EAS cache updates (not modeled)
1051 */
1052 /* case VC_EASC_FLUSH_CTRL: */
1053 case VC_EASC_FLUSH_POLL:
1054 xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |= VC_EASC_FLUSH_CTRL_POLL_VALID;
1055 /* EAS update */
1056 break;
1057
1058 /*
1059 * END cache updates
1060 */
1061 case VC_ENDC_WATCH0_SPEC:
1062 val &= ~VC_ENDC_WATCH_CONFLICT; /* HW will set this bit */
1063 break;
1064
1065 case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3:
1066 break;
1067 case VC_ENDC_WATCH0_DATA0:
1068 /* writing to DATA0 triggers the cache write */
1069 xive->vc_regs[reg] = val;
1070 pnv_xive2_end_update(xive);
1071 break;
1072
1073
1074 /* case VC_ENDC_FLUSH_CTRL: */
1075 case VC_ENDC_FLUSH_POLL:
1076 xive->vc_regs[VC_ENDC_FLUSH_CTRL >> 3] |= VC_ENDC_FLUSH_CTRL_POLL_VALID;
1077 break;
1078
1079 /*
1080 * Indirect invalidation
1081 */
1082 case VC_AT_MACRO_KILL:
1083 case VC_AT_MACRO_KILL_MASK:
1084 break;
1085
1086 /*
1087 * Interrupt fifo overflow in memory backing store (Not modeled)
1088 */
1089 case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6:
1090 break;
1091
1092 /*
1093 * Synchronisation
1094 */
1095 case VC_ENDC_SYNC_DONE:
1096 break;
1097
1098 default:
1099 xive2_error(xive, "VC: invalid write @%"HWADDR_PRIx, offset);
1100 return;
1101 }
1102
1103 xive->vc_regs[reg] = val;
1104 }
1105
1106 static const MemoryRegionOps pnv_xive2_ic_vc_ops = {
1107 .read = pnv_xive2_ic_vc_read,
1108 .write = pnv_xive2_ic_vc_write,
1109 .endianness = DEVICE_BIG_ENDIAN,
1110 .valid = {
1111 .min_access_size = 8,
1112 .max_access_size = 8,
1113 },
1114 .impl = {
1115 .min_access_size = 8,
1116 .max_access_size = 8,
1117 },
1118 };
1119
1120 static uint64_t pnv_xive2_ic_pc_read(void *opaque, hwaddr offset,
1121 unsigned size)
1122 {
1123 PnvXive2 *xive = PNV_XIVE2(opaque);
1124 uint64_t val = -1;
1125 uint32_t reg = offset >> 3;
1126
1127 switch (offset) {
1128 /*
1129 * VSD table settings.
1130 */
1131 case PC_VSD_TABLE_ADDR:
1132 case PC_VSD_TABLE_DATA:
1133 val = xive->pc_regs[reg];
1134 break;
1135
1136 /*
1137 * cache updates
1138 */
1139 case PC_NXC_WATCH0_SPEC:
1140 xive->pc_regs[reg] &= ~(PC_NXC_WATCH_FULL | PC_NXC_WATCH_CONFLICT);
1141 val = xive->pc_regs[reg];
1142 break;
1143
1144 case PC_NXC_WATCH0_DATA0:
1145 /*
1146 * Load DATA registers from cache with data requested by the
1147 * SPEC register
1148 */
1149 pnv_xive2_nvp_cache_load(xive);
1150 val = xive->pc_regs[reg];
1151 break;
1152
1153 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3:
1154 val = xive->pc_regs[reg];
1155 break;
1156
1157 case PC_NXC_FLUSH_CTRL:
1158 xive->pc_regs[reg] &= ~PC_NXC_FLUSH_CTRL_POLL_VALID;
1159 val = xive->pc_regs[reg];
1160 break;
1161
1162 /*
1163 * Indirect invalidation
1164 */
1165 case PC_AT_KILL:
1166 xive->pc_regs[reg] &= ~PC_AT_KILL_VALID;
1167 val = xive->pc_regs[reg];
1168 break;
1169
1170 default:
1171 xive2_error(xive, "PC: invalid read @%"HWADDR_PRIx, offset);
1172 }
1173
1174 return val;
1175 }
1176
1177 static void pnv_xive2_ic_pc_write(void *opaque, hwaddr offset,
1178 uint64_t val, unsigned size)
1179 {
1180 PnvXive2 *xive = PNV_XIVE2(opaque);
1181 uint32_t reg = offset >> 3;
1182
1183 switch (offset) {
1184
1185 /*
1186 * VSD table settings. Only taken into account in the VC
1187 * sub-engine because the Xive2Router model combines both VC and PC
1188 * sub-engines
1189 */
1190 case PC_VSD_TABLE_ADDR:
1191 case PC_VSD_TABLE_DATA:
1192 break;
1193
1194 /*
1195 * cache updates
1196 */
1197 case PC_NXC_WATCH0_SPEC:
1198 val &= ~PC_NXC_WATCH_CONFLICT; /* HW will set this bit */
1199 break;
1200
1201 case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3:
1202 break;
1203 case PC_NXC_WATCH0_DATA0:
1204 /* writing to DATA0 triggers the cache write */
1205 xive->pc_regs[reg] = val;
1206 pnv_xive2_nvp_update(xive);
1207 break;
1208
1209 /* case PC_NXC_FLUSH_CTRL: */
1210 case PC_NXC_FLUSH_POLL:
1211 xive->pc_regs[PC_NXC_FLUSH_CTRL >> 3] |= PC_NXC_FLUSH_CTRL_POLL_VALID;
1212 break;
1213
1214 /*
1215 * Indirect invalidation
1216 */
1217 case PC_AT_KILL:
1218 case PC_AT_KILL_MASK:
1219 break;
1220
1221 default:
1222 xive2_error(xive, "PC: invalid write @%"HWADDR_PRIx, offset);
1223 return;
1224 }
1225
1226 xive->pc_regs[reg] = val;
1227 }
1228
1229 static const MemoryRegionOps pnv_xive2_ic_pc_ops = {
1230 .read = pnv_xive2_ic_pc_read,
1231 .write = pnv_xive2_ic_pc_write,
1232 .endianness = DEVICE_BIG_ENDIAN,
1233 .valid = {
1234 .min_access_size = 8,
1235 .max_access_size = 8,
1236 },
1237 .impl = {
1238 .min_access_size = 8,
1239 .max_access_size = 8,
1240 },
1241 };
1242
1243
1244 static uint64_t pnv_xive2_ic_tctxt_read(void *opaque, hwaddr offset,
1245 unsigned size)
1246 {
1247 PnvXive2 *xive = PNV_XIVE2(opaque);
1248 uint64_t val = -1;
1249 uint32_t reg = offset >> 3;
1250
1251 switch (offset) {
1252 /*
1253 * XIVE2 hardware thread enablement
1254 */
1255 case TCTXT_EN0:
1256 case TCTXT_EN1:
1257 val = xive->tctxt_regs[reg];
1258 break;
1259
1260 case TCTXT_EN0_SET:
1261 case TCTXT_EN0_RESET:
1262 val = xive->tctxt_regs[TCTXT_EN0 >> 3];
1263 break;
1264 case TCTXT_EN1_SET:
1265 case TCTXT_EN1_RESET:
1266 val = xive->tctxt_regs[TCTXT_EN1 >> 3];
1267 break;
1268 default:
1269 xive2_error(xive, "TCTXT: invalid read @%"HWADDR_PRIx, offset);
1270 }
1271
1272 return val;
1273 }
1274
1275 static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset,
1276 uint64_t val, unsigned size)
1277 {
1278 PnvXive2 *xive = PNV_XIVE2(opaque);
1279
1280 switch (offset) {
1281 /*
1282 * XIVE2 hardware thread enablement
1283 */
1284 case TCTXT_EN0: /* Physical Thread Enable */
1285 case TCTXT_EN1: /* Physical Thread Enable (fused core) */
1286 break;
1287
1288 case TCTXT_EN0_SET:
1289 xive->tctxt_regs[TCTXT_EN0 >> 3] |= val;
1290 break;
1291 case TCTXT_EN1_SET:
1292 xive->tctxt_regs[TCTXT_EN1 >> 3] |= val;
1293 break;
1294 case TCTXT_EN0_RESET:
1295 xive->tctxt_regs[TCTXT_EN0 >> 3] &= ~val;
1296 break;
1297 case TCTXT_EN1_RESET:
1298 xive->tctxt_regs[TCTXT_EN1 >> 3] &= ~val;
1299 break;
1300
1301 default:
1302 xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset);
1303 return;
1304 }
1305 }
1306
1307 static const MemoryRegionOps pnv_xive2_ic_tctxt_ops = {
1308 .read = pnv_xive2_ic_tctxt_read,
1309 .write = pnv_xive2_ic_tctxt_write,
1310 .endianness = DEVICE_BIG_ENDIAN,
1311 .valid = {
1312 .min_access_size = 8,
1313 .max_access_size = 8,
1314 },
1315 .impl = {
1316 .min_access_size = 8,
1317 .max_access_size = 8,
1318 },
1319 };
1320
1321 /*
1322 * Redirect XSCOM to MMIO handlers
1323 */
1324 static uint64_t pnv_xive2_xscom_read(void *opaque, hwaddr offset,
1325 unsigned size)
1326 {
1327 PnvXive2 *xive = PNV_XIVE2(opaque);
1328 uint64_t val = -1;
1329 uint32_t xscom_reg = offset >> 3;
1330 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3;
1331
1332 switch (xscom_reg) {
1333 case 0x000 ... 0x0FF:
1334 val = pnv_xive2_ic_cq_read(opaque, mmio_offset, size);
1335 break;
1336 case 0x100 ... 0x1FF:
1337 val = pnv_xive2_ic_vc_read(opaque, mmio_offset, size);
1338 break;
1339 case 0x200 ... 0x2FF:
1340 val = pnv_xive2_ic_pc_read(opaque, mmio_offset, size);
1341 break;
1342 case 0x300 ... 0x3FF:
1343 val = pnv_xive2_ic_tctxt_read(opaque, mmio_offset, size);
1344 break;
1345 default:
1346 xive2_error(xive, "XSCOM: invalid read @%"HWADDR_PRIx, offset);
1347 }
1348
1349 return val;
1350 }
1351
1352 static void pnv_xive2_xscom_write(void *opaque, hwaddr offset,
1353 uint64_t val, unsigned size)
1354 {
1355 PnvXive2 *xive = PNV_XIVE2(opaque);
1356 uint32_t xscom_reg = offset >> 3;
1357 uint32_t mmio_offset = (xscom_reg & 0xFF) << 3;
1358
1359 switch (xscom_reg) {
1360 case 0x000 ... 0x0FF:
1361 pnv_xive2_ic_cq_write(opaque, mmio_offset, val, size);
1362 break;
1363 case 0x100 ... 0x1FF:
1364 pnv_xive2_ic_vc_write(opaque, mmio_offset, val, size);
1365 break;
1366 case 0x200 ... 0x2FF:
1367 pnv_xive2_ic_pc_write(opaque, mmio_offset, val, size);
1368 break;
1369 case 0x300 ... 0x3FF:
1370 pnv_xive2_ic_tctxt_write(opaque, mmio_offset, val, size);
1371 break;
1372 default:
1373 xive2_error(xive, "XSCOM: invalid write @%"HWADDR_PRIx, offset);
1374 }
1375 }
1376
1377 static const MemoryRegionOps pnv_xive2_xscom_ops = {
1378 .read = pnv_xive2_xscom_read,
1379 .write = pnv_xive2_xscom_write,
1380 .endianness = DEVICE_BIG_ENDIAN,
1381 .valid = {
1382 .min_access_size = 8,
1383 .max_access_size = 8,
1384 },
1385 .impl = {
1386 .min_access_size = 8,
1387 .max_access_size = 8,
1388 },
1389 };
1390
1391 /*
1392 * Notify port page. The layout is compatible between 4K and 64K pages :
1393 *
1394 * Page 1 Notify page (writes only)
1395 * 0x000 - 0x7FF IPI interrupt (NPU)
1396 * 0x800 - 0xFFF HW interrupt triggers (PSI, PHB)
1397 */
1398
1399 static void pnv_xive2_ic_hw_trigger(PnvXive2 *xive, hwaddr addr,
1400 uint64_t val)
1401 {
1402 uint8_t blk;
1403 uint32_t idx;
1404
1405 if (val & XIVE_TRIGGER_END) {
1406 xive2_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64,
1407 addr, val);
1408 return;
1409 }
1410
1411 /*
1412 * Forward the source event notification directly to the Router.
1413 * The source interrupt number should already be correctly encoded
1414 * with the chip block id by the sending device (PHB, PSI).
1415 */
1416 blk = XIVE_EAS_BLOCK(val);
1417 idx = XIVE_EAS_INDEX(val);
1418
1419 xive2_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx),
1420 !!(val & XIVE_TRIGGER_PQ));
1421 }
1422
1423 static void pnv_xive2_ic_notify_write(void *opaque, hwaddr offset,
1424 uint64_t val, unsigned size)
1425 {
1426 PnvXive2 *xive = PNV_XIVE2(opaque);
1427
1428 /* VC: IPI triggers */
1429 switch (offset) {
1430 case 0x000 ... 0x7FF:
1431 /* TODO: check IPI notify sub-page routing */
1432 pnv_xive2_ic_hw_trigger(opaque, offset, val);
1433 break;
1434
1435 /* VC: HW triggers */
1436 case 0x800 ... 0xFFF:
1437 pnv_xive2_ic_hw_trigger(opaque, offset, val);
1438 break;
1439
1440 default:
1441 xive2_error(xive, "NOTIFY: invalid write @%"HWADDR_PRIx, offset);
1442 }
1443 }
1444
1445 static uint64_t pnv_xive2_ic_notify_read(void *opaque, hwaddr offset,
1446 unsigned size)
1447 {
1448 PnvXive2 *xive = PNV_XIVE2(opaque);
1449
1450 /* loads are invalid */
1451 xive2_error(xive, "NOTIFY: invalid read @%"HWADDR_PRIx, offset);
1452 return -1;
1453 }
1454
1455 static const MemoryRegionOps pnv_xive2_ic_notify_ops = {
1456 .read = pnv_xive2_ic_notify_read,
1457 .write = pnv_xive2_ic_notify_write,
1458 .endianness = DEVICE_BIG_ENDIAN,
1459 .valid = {
1460 .min_access_size = 8,
1461 .max_access_size = 8,
1462 },
1463 .impl = {
1464 .min_access_size = 8,
1465 .max_access_size = 8,
1466 },
1467 };
1468
1469 static uint64_t pnv_xive2_ic_lsi_read(void *opaque, hwaddr offset,
1470 unsigned size)
1471 {
1472 PnvXive2 *xive = PNV_XIVE2(opaque);
1473
1474 xive2_error(xive, "LSI: invalid read @%"HWADDR_PRIx, offset);
1475 return -1;
1476 }
1477
1478 static void pnv_xive2_ic_lsi_write(void *opaque, hwaddr offset,
1479 uint64_t val, unsigned size)
1480 {
1481 PnvXive2 *xive = PNV_XIVE2(opaque);
1482
1483 xive2_error(xive, "LSI: invalid write @%"HWADDR_PRIx, offset);
1484 }
1485
1486 static const MemoryRegionOps pnv_xive2_ic_lsi_ops = {
1487 .read = pnv_xive2_ic_lsi_read,
1488 .write = pnv_xive2_ic_lsi_write,
1489 .endianness = DEVICE_BIG_ENDIAN,
1490 .valid = {
1491 .min_access_size = 8,
1492 .max_access_size = 8,
1493 },
1494 .impl = {
1495 .min_access_size = 8,
1496 .max_access_size = 8,
1497 },
1498 };
1499
1500 /*
1501 * Sync MMIO page (write only)
1502 */
1503 #define PNV_XIVE2_SYNC_IPI 0x000
1504 #define PNV_XIVE2_SYNC_HW 0x080
1505 #define PNV_XIVE2_SYNC_NxC 0x100
1506 #define PNV_XIVE2_SYNC_INT 0x180
1507 #define PNV_XIVE2_SYNC_OS_ESC 0x200
1508 #define PNV_XIVE2_SYNC_POOL_ESC 0x280
1509 #define PNV_XIVE2_SYNC_HARD_ESC 0x300
1510
1511 static uint64_t pnv_xive2_ic_sync_read(void *opaque, hwaddr offset,
1512 unsigned size)
1513 {
1514 PnvXive2 *xive = PNV_XIVE2(opaque);
1515
1516 /* loads are invalid */
1517 xive2_error(xive, "SYNC: invalid read @%"HWADDR_PRIx, offset);
1518 return -1;
1519 }
1520
1521 static void pnv_xive2_ic_sync_write(void *opaque, hwaddr offset,
1522 uint64_t val, unsigned size)
1523 {
1524 PnvXive2 *xive = PNV_XIVE2(opaque);
1525
1526 switch (offset) {
1527 case PNV_XIVE2_SYNC_IPI:
1528 case PNV_XIVE2_SYNC_HW:
1529 case PNV_XIVE2_SYNC_NxC:
1530 case PNV_XIVE2_SYNC_INT:
1531 case PNV_XIVE2_SYNC_OS_ESC:
1532 case PNV_XIVE2_SYNC_POOL_ESC:
1533 case PNV_XIVE2_SYNC_HARD_ESC:
1534 break;
1535 default:
1536 xive2_error(xive, "SYNC: invalid write @%"HWADDR_PRIx, offset);
1537 }
1538 }
1539
1540 static const MemoryRegionOps pnv_xive2_ic_sync_ops = {
1541 .read = pnv_xive2_ic_sync_read,
1542 .write = pnv_xive2_ic_sync_write,
1543 .endianness = DEVICE_BIG_ENDIAN,
1544 .valid = {
1545 .min_access_size = 8,
1546 .max_access_size = 8,
1547 },
1548 .impl = {
1549 .min_access_size = 8,
1550 .max_access_size = 8,
1551 },
1552 };
1553
1554 /*
1555 * When the TM direct pages of the IC controller are accessed, the
1556 * target HW thread is deduced from the page offset.
1557 */
1558 static uint32_t pnv_xive2_ic_tm_get_pir(PnvXive2 *xive, hwaddr offset)
1559 {
1560 /* On P10, the node ID shift in the PIR register is 8 bits */
1561 return xive->chip->chip_id << 8 | offset >> xive->ic_shift;
1562 }
1563
1564 static XiveTCTX *pnv_xive2_get_indirect_tctx(PnvXive2 *xive, uint32_t pir)
1565 {
1566 PnvChip *chip = xive->chip;
1567 PowerPCCPU *cpu = NULL;
1568
1569 cpu = pnv_chip_find_cpu(chip, pir);
1570 if (!cpu) {
1571 xive2_error(xive, "IC: invalid PIR %x for indirect access", pir);
1572 return NULL;
1573 }
1574
1575 if (!pnv_xive2_is_cpu_enabled(xive, cpu)) {
1576 xive2_error(xive, "IC: CPU %x is not enabled", pir);
1577 }
1578
1579 return XIVE_TCTX(pnv_cpu_state(cpu)->intc);
1580 }
1581
1582 static uint64_t pnv_xive2_ic_tm_indirect_read(void *opaque, hwaddr offset,
1583 unsigned size)
1584 {
1585 PnvXive2 *xive = PNV_XIVE2(opaque);
1586 uint32_t pir;
1587 XiveTCTX *tctx;
1588 uint64_t val = -1;
1589
1590 pir = pnv_xive2_ic_tm_get_pir(xive, offset);
1591 tctx = pnv_xive2_get_indirect_tctx(xive, pir);
1592 if (tctx) {
1593 val = xive_tctx_tm_read(NULL, tctx, offset, size);
1594 }
1595
1596 return val;
1597 }
1598
1599 static void pnv_xive2_ic_tm_indirect_write(void *opaque, hwaddr offset,
1600 uint64_t val, unsigned size)
1601 {
1602 PnvXive2 *xive = PNV_XIVE2(opaque);
1603 uint32_t pir;
1604 XiveTCTX *tctx;
1605
1606 pir = pnv_xive2_ic_tm_get_pir(xive, offset);
1607 tctx = pnv_xive2_get_indirect_tctx(xive, pir);
1608 if (tctx) {
1609 xive_tctx_tm_write(NULL, tctx, offset, val, size);
1610 }
1611 }
1612
1613 static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops = {
1614 .read = pnv_xive2_ic_tm_indirect_read,
1615 .write = pnv_xive2_ic_tm_indirect_write,
1616 .endianness = DEVICE_BIG_ENDIAN,
1617 .valid = {
1618 .min_access_size = 8,
1619 .max_access_size = 8,
1620 },
1621 .impl = {
1622 .min_access_size = 8,
1623 .max_access_size = 8,
1624 },
1625 };
1626
1627 /*
1628 * TIMA ops
1629 */
1630
1631 /*
1632 * Special TIMA offsets to handle accesses in a POWER10 way.
1633 *
1634 * Only the CAM line updates done by the hypervisor should be handled
1635 * specifically.
1636 */
1637 #define HV_PAGE_OFFSET (XIVE_TM_HV_PAGE << TM_SHIFT)
1638 #define HV_PUSH_OS_CTX_OFFSET (HV_PAGE_OFFSET | (TM_QW1_OS + TM_WORD2))
1639 #define HV_PULL_OS_CTX_OFFSET (HV_PAGE_OFFSET | TM_SPC_PULL_OS_CTX)
1640
1641 static void pnv_xive2_tm_write(void *opaque, hwaddr offset,
1642 uint64_t value, unsigned size)
1643 {
1644 PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
1645 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu);
1646 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
1647 XivePresenter *xptr = XIVE_PRESENTER(xive);
1648 bool gen1_tima_os =
1649 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS;
1650
1651 /* TODO: should we switch the TM ops table instead ? */
1652 if (!gen1_tima_os && offset == HV_PUSH_OS_CTX_OFFSET) {
1653 xive2_tm_push_os_ctx(xptr, tctx, offset, value, size);
1654 return;
1655 }
1656
1657 /* Other TM ops are the same as XIVE1 */
1658 xive_tctx_tm_write(xptr, tctx, offset, value, size);
1659 }
1660
1661 static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size)
1662 {
1663 PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
1664 PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu);
1665 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
1666 XivePresenter *xptr = XIVE_PRESENTER(xive);
1667 bool gen1_tima_os =
1668 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS;
1669
1670 /* TODO: should we switch the TM ops table instead ? */
1671 if (!gen1_tima_os && offset == HV_PULL_OS_CTX_OFFSET) {
1672 return xive2_tm_pull_os_ctx(xptr, tctx, offset, size);
1673 }
1674
1675 /* Other TM ops are the same as XIVE1 */
1676 return xive_tctx_tm_read(xptr, tctx, offset, size);
1677 }
1678
1679 static const MemoryRegionOps pnv_xive2_tm_ops = {
1680 .read = pnv_xive2_tm_read,
1681 .write = pnv_xive2_tm_write,
1682 .endianness = DEVICE_BIG_ENDIAN,
1683 .valid = {
1684 .min_access_size = 1,
1685 .max_access_size = 8,
1686 },
1687 .impl = {
1688 .min_access_size = 1,
1689 .max_access_size = 8,
1690 },
1691 };
1692
1693 static uint64_t pnv_xive2_nvc_read(void *opaque, hwaddr offset,
1694 unsigned size)
1695 {
1696 PnvXive2 *xive = PNV_XIVE2(opaque);
1697
1698 xive2_error(xive, "NVC: invalid read @%"HWADDR_PRIx, offset);
1699 return -1;
1700 }
1701
1702 static void pnv_xive2_nvc_write(void *opaque, hwaddr offset,
1703 uint64_t val, unsigned size)
1704 {
1705 PnvXive2 *xive = PNV_XIVE2(opaque);
1706
1707 xive2_error(xive, "NVC: invalid write @%"HWADDR_PRIx, offset);
1708 }
1709
1710 static const MemoryRegionOps pnv_xive2_nvc_ops = {
1711 .read = pnv_xive2_nvc_read,
1712 .write = pnv_xive2_nvc_write,
1713 .endianness = DEVICE_BIG_ENDIAN,
1714 .valid = {
1715 .min_access_size = 8,
1716 .max_access_size = 8,
1717 },
1718 .impl = {
1719 .min_access_size = 8,
1720 .max_access_size = 8,
1721 },
1722 };
1723
1724 static uint64_t pnv_xive2_nvpg_read(void *opaque, hwaddr offset,
1725 unsigned size)
1726 {
1727 PnvXive2 *xive = PNV_XIVE2(opaque);
1728
1729 xive2_error(xive, "NVPG: invalid read @%"HWADDR_PRIx, offset);
1730 return -1;
1731 }
1732
1733 static void pnv_xive2_nvpg_write(void *opaque, hwaddr offset,
1734 uint64_t val, unsigned size)
1735 {
1736 PnvXive2 *xive = PNV_XIVE2(opaque);
1737
1738 xive2_error(xive, "NVPG: invalid write @%"HWADDR_PRIx, offset);
1739 }
1740
1741 static const MemoryRegionOps pnv_xive2_nvpg_ops = {
1742 .read = pnv_xive2_nvpg_read,
1743 .write = pnv_xive2_nvpg_write,
1744 .endianness = DEVICE_BIG_ENDIAN,
1745 .valid = {
1746 .min_access_size = 8,
1747 .max_access_size = 8,
1748 },
1749 .impl = {
1750 .min_access_size = 8,
1751 .max_access_size = 8,
1752 },
1753 };
1754
1755 /*
1756 * POWER10 default capabilities: 0x2000120076f000FC
1757 */
1758 #define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC
1759
1760 /*
1761 * POWER10 default configuration: 0x0030000033000000
1762 *
1763 * 8bits thread id was dropped for P10
1764 */
1765 #define PNV_XIVE2_CONFIGURATION 0x0030000033000000
1766
1767 static void pnv_xive2_reset(void *dev)
1768 {
1769 PnvXive2 *xive = PNV_XIVE2(dev);
1770 XiveSource *xsrc = &xive->ipi_source;
1771 Xive2EndSource *end_xsrc = &xive->end_source;
1772
1773 xive->cq_regs[CQ_XIVE_CAP >> 3] = xive->capabilities;
1774 xive->cq_regs[CQ_XIVE_CFG >> 3] = xive->config;
1775
1776 /* HW hardwires the #Topology of the chip in the block field */
1777 xive->cq_regs[CQ_XIVE_CFG >> 3] |=
1778 SETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, 0ull, xive->chip->chip_id);
1779
1780 /* Set default page size to 64k */
1781 xive->ic_shift = xive->esb_shift = xive->end_shift = 16;
1782 xive->nvc_shift = xive->nvpg_shift = xive->tm_shift = 16;
1783
1784 /* Clear source MMIOs */
1785 if (memory_region_is_mapped(&xsrc->esb_mmio)) {
1786 memory_region_del_subregion(&xive->esb_mmio, &xsrc->esb_mmio);
1787 }
1788
1789 if (memory_region_is_mapped(&end_xsrc->esb_mmio)) {
1790 memory_region_del_subregion(&xive->end_mmio, &end_xsrc->esb_mmio);
1791 }
1792 }
1793
1794 /*
1795 * Maximum number of IRQs and ENDs supported by HW. Will be tuned by
1796 * software.
1797 */
1798 #define PNV_XIVE2_NR_IRQS (PNV10_XIVE2_ESB_SIZE / (1ull << XIVE_ESB_64K_2PAGE))
1799 #define PNV_XIVE2_NR_ENDS (PNV10_XIVE2_END_SIZE / (1ull << XIVE_ESB_64K_2PAGE))
1800
1801 static void pnv_xive2_realize(DeviceState *dev, Error **errp)
1802 {
1803 PnvXive2 *xive = PNV_XIVE2(dev);
1804 PnvXive2Class *pxc = PNV_XIVE2_GET_CLASS(dev);
1805 XiveSource *xsrc = &xive->ipi_source;
1806 Xive2EndSource *end_xsrc = &xive->end_source;
1807 Error *local_err = NULL;
1808 int i;
1809
1810 pxc->parent_realize(dev, &local_err);
1811 if (local_err) {
1812 error_propagate(errp, local_err);
1813 return;
1814 }
1815
1816 assert(xive->chip);
1817
1818 /*
1819 * The XiveSource and Xive2EndSource objects are realized with the
1820 * maximum allowed HW configuration. The ESB MMIO regions will be
1821 * resized dynamically when the controller is configured by the FW
1822 * to limit accesses to resources not provisioned.
1823 */
1824 object_property_set_int(OBJECT(xsrc), "flags", XIVE_SRC_STORE_EOI,
1825 &error_fatal);
1826 object_property_set_int(OBJECT(xsrc), "nr-irqs", PNV_XIVE2_NR_IRQS,
1827 &error_fatal);
1828 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive),
1829 &error_fatal);
1830 qdev_realize(DEVICE(xsrc), NULL, &local_err);
1831 if (local_err) {
1832 error_propagate(errp, local_err);
1833 return;
1834 }
1835
1836 object_property_set_int(OBJECT(end_xsrc), "nr-ends", PNV_XIVE2_NR_ENDS,
1837 &error_fatal);
1838 object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive),
1839 &error_abort);
1840 qdev_realize(DEVICE(end_xsrc), NULL, &local_err);
1841 if (local_err) {
1842 error_propagate(errp, local_err);
1843 return;
1844 }
1845
1846 /* XSCOM region, used for initial configuration of the BARs */
1847 memory_region_init_io(&xive->xscom_regs, OBJECT(dev),
1848 &pnv_xive2_xscom_ops, xive, "xscom-xive",
1849 PNV10_XSCOM_XIVE2_SIZE << 3);
1850
1851 /* Interrupt controller MMIO regions */
1852 xive->ic_shift = 16;
1853 memory_region_init(&xive->ic_mmio, OBJECT(dev), "xive-ic",
1854 PNV10_XIVE2_IC_SIZE);
1855
1856 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) {
1857 memory_region_init_io(&xive->ic_mmios[i], OBJECT(dev),
1858 pnv_xive2_ic_regions[i].ops, xive,
1859 pnv_xive2_ic_regions[i].name,
1860 pnv_xive2_ic_regions[i].pgsize << xive->ic_shift);
1861 }
1862
1863 /*
1864 * VC MMIO regions.
1865 */
1866 xive->esb_shift = 16;
1867 xive->end_shift = 16;
1868 memory_region_init(&xive->esb_mmio, OBJECT(xive), "xive-esb",
1869 PNV10_XIVE2_ESB_SIZE);
1870 memory_region_init(&xive->end_mmio, OBJECT(xive), "xive-end",
1871 PNV10_XIVE2_END_SIZE);
1872
1873 /* Presenter Controller MMIO region (not modeled) */
1874 xive->nvc_shift = 16;
1875 xive->nvpg_shift = 16;
1876 memory_region_init_io(&xive->nvc_mmio, OBJECT(dev),
1877 &pnv_xive2_nvc_ops, xive,
1878 "xive-nvc", PNV10_XIVE2_NVC_SIZE);
1879
1880 memory_region_init_io(&xive->nvpg_mmio, OBJECT(dev),
1881 &pnv_xive2_nvpg_ops, xive,
1882 "xive-nvpg", PNV10_XIVE2_NVPG_SIZE);
1883
1884 /* Thread Interrupt Management Area (Direct) */
1885 xive->tm_shift = 16;
1886 memory_region_init_io(&xive->tm_mmio, OBJECT(dev), &pnv_xive2_tm_ops,
1887 xive, "xive-tima", PNV10_XIVE2_TM_SIZE);
1888
1889 qemu_register_reset(pnv_xive2_reset, dev);
1890 }
1891
1892 static Property pnv_xive2_properties[] = {
1893 DEFINE_PROP_UINT64("ic-bar", PnvXive2, ic_base, 0),
1894 DEFINE_PROP_UINT64("esb-bar", PnvXive2, esb_base, 0),
1895 DEFINE_PROP_UINT64("end-bar", PnvXive2, end_base, 0),
1896 DEFINE_PROP_UINT64("nvc-bar", PnvXive2, nvc_base, 0),
1897 DEFINE_PROP_UINT64("nvpg-bar", PnvXive2, nvpg_base, 0),
1898 DEFINE_PROP_UINT64("tm-bar", PnvXive2, tm_base, 0),
1899 DEFINE_PROP_UINT64("capabilities", PnvXive2, capabilities,
1900 PNV_XIVE2_CAPABILITIES),
1901 DEFINE_PROP_UINT64("config", PnvXive2, config,
1902 PNV_XIVE2_CONFIGURATION),
1903 DEFINE_PROP_LINK("chip", PnvXive2, chip, TYPE_PNV_CHIP, PnvChip *),
1904 DEFINE_PROP_END_OF_LIST(),
1905 };
1906
1907 static void pnv_xive2_instance_init(Object *obj)
1908 {
1909 PnvXive2 *xive = PNV_XIVE2(obj);
1910
1911 object_initialize_child(obj, "ipi_source", &xive->ipi_source,
1912 TYPE_XIVE_SOURCE);
1913 object_initialize_child(obj, "end_source", &xive->end_source,
1914 TYPE_XIVE2_END_SOURCE);
1915 }
1916
1917 static int pnv_xive2_dt_xscom(PnvXScomInterface *dev, void *fdt,
1918 int xscom_offset)
1919 {
1920 const char compat_p10[] = "ibm,power10-xive-x";
1921 char *name;
1922 int offset;
1923 uint32_t reg[] = {
1924 cpu_to_be32(PNV10_XSCOM_XIVE2_BASE),
1925 cpu_to_be32(PNV10_XSCOM_XIVE2_SIZE)
1926 };
1927
1928 name = g_strdup_printf("xive@%x", PNV10_XSCOM_XIVE2_BASE);
1929 offset = fdt_add_subnode(fdt, xscom_offset, name);
1930 _FDT(offset);
1931 g_free(name);
1932
1933 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
1934 _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10,
1935 sizeof(compat_p10)));
1936 return 0;
1937 }
1938
1939 static void pnv_xive2_class_init(ObjectClass *klass, void *data)
1940 {
1941 DeviceClass *dc = DEVICE_CLASS(klass);
1942 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
1943 Xive2RouterClass *xrc = XIVE2_ROUTER_CLASS(klass);
1944 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass);
1945 XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass);
1946 PnvXive2Class *pxc = PNV_XIVE2_CLASS(klass);
1947
1948 xdc->dt_xscom = pnv_xive2_dt_xscom;
1949
1950 dc->desc = "PowerNV XIVE2 Interrupt Controller (POWER10)";
1951 device_class_set_parent_realize(dc, pnv_xive2_realize,
1952 &pxc->parent_realize);
1953 device_class_set_props(dc, pnv_xive2_properties);
1954
1955 xrc->get_eas = pnv_xive2_get_eas;
1956 xrc->get_pq = pnv_xive2_get_pq;
1957 xrc->set_pq = pnv_xive2_set_pq;
1958 xrc->get_end = pnv_xive2_get_end;
1959 xrc->write_end = pnv_xive2_write_end;
1960 xrc->get_nvp = pnv_xive2_get_nvp;
1961 xrc->write_nvp = pnv_xive2_write_nvp;
1962 xrc->get_config = pnv_xive2_get_config;
1963 xrc->get_block_id = pnv_xive2_get_block_id;
1964
1965 xnc->notify = pnv_xive2_notify;
1966
1967 xpc->match_nvt = pnv_xive2_match_nvt;
1968 };
1969
1970 static const TypeInfo pnv_xive2_info = {
1971 .name = TYPE_PNV_XIVE2,
1972 .parent = TYPE_XIVE2_ROUTER,
1973 .instance_init = pnv_xive2_instance_init,
1974 .instance_size = sizeof(PnvXive2),
1975 .class_init = pnv_xive2_class_init,
1976 .class_size = sizeof(PnvXive2Class),
1977 .interfaces = (InterfaceInfo[]) {
1978 { TYPE_PNV_XSCOM_INTERFACE },
1979 { }
1980 }
1981 };
1982
1983 static void pnv_xive2_register_types(void)
1984 {
1985 type_register_static(&pnv_xive2_info);
1986 }
1987
1988 type_init(pnv_xive2_register_types)
1989
1990 static void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx,
1991 Monitor *mon)
1992 {
1993 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5);
1994 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5);
1995
1996 if (!xive2_nvp_is_valid(nvp)) {
1997 return;
1998 }
1999
2000 monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x",
2001 nvp_idx, eq_blk, eq_idx,
2002 xive_get_field32(NVP2_W2_IPB, nvp->w2));
2003 /*
2004 * When the NVP is HW controlled, more fields are updated
2005 */
2006 if (xive2_nvp_is_hw(nvp)) {
2007 monitor_printf(mon, " CPPR:%02x",
2008 xive_get_field32(NVP2_W2_CPPR, nvp->w2));
2009 if (xive2_nvp_is_co(nvp)) {
2010 monitor_printf(mon, " CO:%04x",
2011 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1));
2012 }
2013 }
2014 monitor_printf(mon, "\n");
2015 }
2016
2017 /*
2018 * If the table is direct, we can compute the number of PQ entries
2019 * provisioned by FW.
2020 */
2021 static uint32_t pnv_xive2_nr_esbs(PnvXive2 *xive)
2022 {
2023 uint8_t blk = pnv_xive2_block_id(xive);
2024 uint64_t vsd = xive->vsds[VST_ESB][blk];
2025 uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12);
2026
2027 return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE;
2028 }
2029
2030 /*
2031 * Compute the number of entries per indirect subpage.
2032 */
2033 static uint64_t pnv_xive2_vst_per_subpage(PnvXive2 *xive, uint32_t type)
2034 {
2035 uint8_t blk = pnv_xive2_block_id(xive);
2036 uint64_t vsd = xive->vsds[type][blk];
2037 const XiveVstInfo *info = &vst_infos[type];
2038 uint64_t vsd_addr;
2039 uint32_t page_shift;
2040
2041 /* For direct tables, fake a valid value */
2042 if (!(VSD_INDIRECT & vsd)) {
2043 return 1;
2044 }
2045
2046 /* Get the page size of the indirect table. */
2047 vsd_addr = vsd & VSD_ADDRESS_MASK;
2048 ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED);
2049
2050 if (!(vsd & VSD_ADDRESS_MASK)) {
2051 #ifdef XIVE2_DEBUG
2052 xive2_error(xive, "VST: invalid %s entry!?", info->name);
2053 #endif
2054 return 0;
2055 }
2056
2057 page_shift = GETFIELD(VSD_TSIZE, vsd) + 12;
2058
2059 if (!pnv_xive2_vst_page_size_allowed(page_shift)) {
2060 xive2_error(xive, "VST: invalid %s page shift %d", info->name,
2061 page_shift);
2062 return 0;
2063 }
2064
2065 return (1ull << page_shift) / info->size;
2066 }
2067
2068 void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon)
2069 {
2070 Xive2Router *xrtr = XIVE2_ROUTER(xive);
2071 uint8_t blk = pnv_xive2_block_id(xive);
2072 uint8_t chip_id = xive->chip->chip_id;
2073 uint32_t srcno0 = XIVE_EAS(blk, 0);
2074 uint32_t nr_esbs = pnv_xive2_nr_esbs(xive);
2075 Xive2Eas eas;
2076 Xive2End end;
2077 Xive2Nvp nvp;
2078 int i;
2079 uint64_t xive_nvp_per_subpage;
2080
2081 monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0,
2082 srcno0 + nr_esbs - 1);
2083 xive_source_pic_print_info(&xive->ipi_source, srcno0, mon);
2084
2085 monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0,
2086 srcno0 + nr_esbs - 1);
2087 for (i = 0; i < nr_esbs; i++) {
2088 if (xive2_router_get_eas(xrtr, blk, i, &eas)) {
2089 break;
2090 }
2091 if (!xive2_eas_is_masked(&eas)) {
2092 xive2_eas_pic_print_info(&eas, i, mon);
2093 }
2094 }
2095
2096 monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk);
2097 i = 0;
2098 while (!xive2_router_get_end(xrtr, blk, i, &end)) {
2099 xive2_end_eas_pic_print_info(&end, i++, mon);
2100 }
2101
2102 monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk);
2103 i = 0;
2104 while (!xive2_router_get_end(xrtr, blk, i, &end)) {
2105 xive2_end_pic_print_info(&end, i++, mon);
2106 }
2107
2108 monitor_printf(mon, "XIVE[%x] #%d NVPT %08x .. %08x\n", chip_id, blk,
2109 0, XIVE2_NVP_COUNT - 1);
2110 xive_nvp_per_subpage = pnv_xive2_vst_per_subpage(xive, VST_NVP);
2111 for (i = 0; i < XIVE2_NVP_COUNT; i += xive_nvp_per_subpage) {
2112 while (!xive2_router_get_nvp(xrtr, blk, i, &nvp)) {
2113 xive2_nvp_pic_print_info(&nvp, i++, mon);
2114 }
2115 }
2116 }
QEmu