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ppc64: Allocate IRQ lines with qdev_init_gpio_in()
[qemu.git] / hw / ppc / ppc.c
blob15f2b5f0f07a15cc4933162facfd98dd0e455701
1 /*
2 * QEMU generic PowerPC hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/irq.h"
27 #include "hw/ppc/ppc.h"
28 #include "hw/ppc/ppc_e500.h"
29 #include "qemu/timer.h"
30 #include "sysemu/cpus.h"
31 #include "qemu/log.h"
32 #include "qemu/main-loop.h"
33 #include "qemu/error-report.h"
34 #include "sysemu/kvm.h"
35 #include "sysemu/runstate.h"
36 #include "kvm_ppc.h"
37 #include "migration/vmstate.h"
38 #include "trace.h"
39
40 static void cpu_ppc_tb_stop (CPUPPCState *env);
41 static void cpu_ppc_tb_start (CPUPPCState *env);
42
43 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level)
44 {
45 CPUState *cs = CPU(cpu);
46 CPUPPCState *env = &cpu->env;
47 unsigned int old_pending;
48 bool locked = false;
49
50 /* We may already have the BQL if coming from the reset path */
51 if (!qemu_mutex_iothread_locked()) {
52 locked = true;
53 qemu_mutex_lock_iothread();
54 }
55
56 old_pending = env->pending_interrupts;
57
58 if (level) {
59 env->pending_interrupts |= 1 << n_IRQ;
60 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
61 } else {
62 env->pending_interrupts &= ~(1 << n_IRQ);
63 if (env->pending_interrupts == 0) {
64 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
65 }
66 }
67
68 if (old_pending != env->pending_interrupts) {
69 kvmppc_set_interrupt(cpu, n_IRQ, level);
70 }
71
72
73 trace_ppc_irq_set_exit(env, n_IRQ, level, env->pending_interrupts,
74 CPU(cpu)->interrupt_request);
75
76 if (locked) {
77 qemu_mutex_unlock_iothread();
78 }
79 }
80
81 /* PowerPC 6xx / 7xx internal IRQ controller */
82 static void ppc6xx_set_irq(void *opaque, int pin, int level)
83 {
84 PowerPCCPU *cpu = opaque;
85 CPUPPCState *env = &cpu->env;
86 int cur_level;
87
88 trace_ppc_irq_set(env, pin, level);
89
90 cur_level = (env->irq_input_state >> pin) & 1;
91 /* Don't generate spurious events */
92 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
93 CPUState *cs = CPU(cpu);
94
95 switch (pin) {
96 case PPC6xx_INPUT_TBEN:
97 /* Level sensitive - active high */
98 trace_ppc_irq_set_state("time base", level);
99 if (level) {
100 cpu_ppc_tb_start(env);
101 } else {
102 cpu_ppc_tb_stop(env);
103 }
104 break;
105 case PPC6xx_INPUT_INT:
106 /* Level sensitive - active high */
107 trace_ppc_irq_set_state("external IRQ", level);
108 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
109 break;
110 case PPC6xx_INPUT_SMI:
111 /* Level sensitive - active high */
112 trace_ppc_irq_set_state("SMI IRQ", level);
113 ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level);
114 break;
115 case PPC6xx_INPUT_MCP:
116 /* Negative edge sensitive */
117 /* XXX: TODO: actual reaction may depends on HID0 status
118 * 603/604/740/750: check HID0[EMCP]
119 */
120 if (cur_level == 1 && level == 0) {
121 trace_ppc_irq_set_state("machine check", 1);
122 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
123 }
124 break;
125 case PPC6xx_INPUT_CKSTP_IN:
126 /* Level sensitive - active low */
127 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
128 /* XXX: Note that the only way to restart the CPU is to reset it */
129 if (level) {
130 trace_ppc_irq_cpu("stop");
131 cs->halted = 1;
132 }
133 break;
134 case PPC6xx_INPUT_HRESET:
135 /* Level sensitive - active low */
136 if (level) {
137 trace_ppc_irq_reset("CPU");
138 cpu_interrupt(cs, CPU_INTERRUPT_RESET);
139 }
140 break;
141 case PPC6xx_INPUT_SRESET:
142 trace_ppc_irq_set_state("RESET IRQ", level);
143 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
144 break;
145 default:
146 g_assert_not_reached();
147 }
148 if (level)
149 env->irq_input_state |= 1 << pin;
150 else
151 env->irq_input_state &= ~(1 << pin);
152 }
153 }
154
155 void ppc6xx_irq_init(PowerPCCPU *cpu)
156 {
157 CPUPPCState *env = &cpu->env;
158
159 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu,
160 PPC6xx_INPUT_NB);
161 }
162
163 #if defined(TARGET_PPC64)
164 /* PowerPC 970 internal IRQ controller */
165 static void ppc970_set_irq(void *opaque, int pin, int level)
166 {
167 PowerPCCPU *cpu = opaque;
168 CPUPPCState *env = &cpu->env;
169 int cur_level;
170
171 trace_ppc_irq_set(env, pin, level);
172
173 cur_level = (env->irq_input_state >> pin) & 1;
174 /* Don't generate spurious events */
175 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
176 CPUState *cs = CPU(cpu);
177
178 switch (pin) {
179 case PPC970_INPUT_INT:
180 /* Level sensitive - active high */
181 trace_ppc_irq_set_state("external IRQ", level);
182 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
183 break;
184 case PPC970_INPUT_THINT:
185 /* Level sensitive - active high */
186 trace_ppc_irq_set_state("SMI IRQ", level);
187 ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level);
188 break;
189 case PPC970_INPUT_MCP:
190 /* Negative edge sensitive */
191 /* XXX: TODO: actual reaction may depends on HID0 status
192 * 603/604/740/750: check HID0[EMCP]
193 */
194 if (cur_level == 1 && level == 0) {
195 trace_ppc_irq_set_state("machine check", 1);
196 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
197 }
198 break;
199 case PPC970_INPUT_CKSTP:
200 /* Level sensitive - active low */
201 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
202 if (level) {
203 trace_ppc_irq_cpu("stop");
204 cs->halted = 1;
205 } else {
206 trace_ppc_irq_cpu("restart");
207 cs->halted = 0;
208 qemu_cpu_kick(cs);
209 }
210 break;
211 case PPC970_INPUT_HRESET:
212 /* Level sensitive - active low */
213 if (level) {
214 cpu_interrupt(cs, CPU_INTERRUPT_RESET);
215 }
216 break;
217 case PPC970_INPUT_SRESET:
218 trace_ppc_irq_set_state("RESET IRQ", level);
219 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
220 break;
221 case PPC970_INPUT_TBEN:
222 trace_ppc_irq_set_state("TBEN IRQ", level);
223 /* XXX: TODO */
224 break;
225 default:
226 g_assert_not_reached();
227 }
228 if (level)
229 env->irq_input_state |= 1 << pin;
230 else
231 env->irq_input_state &= ~(1 << pin);
232 }
233 }
234
235 void ppc970_irq_init(PowerPCCPU *cpu)
236 {
237 qdev_init_gpio_in(DEVICE(cpu), ppc970_set_irq, PPC970_INPUT_NB);
238 }
239
240 /* POWER7 internal IRQ controller */
241 static void power7_set_irq(void *opaque, int pin, int level)
242 {
243 PowerPCCPU *cpu = opaque;
244
245 trace_ppc_irq_set(&cpu->env, pin, level);
246
247 switch (pin) {
248 case POWER7_INPUT_INT:
249 /* Level sensitive - active high */
250 trace_ppc_irq_set_state("external IRQ", level);
251 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
252 break;
253 default:
254 g_assert_not_reached();
255 }
256 }
257
258 void ppcPOWER7_irq_init(PowerPCCPU *cpu)
259 {
260 qdev_init_gpio_in(DEVICE(cpu), power7_set_irq, POWER7_INPUT_NB);
261 }
262
263 /* POWER9 internal IRQ controller */
264 static void power9_set_irq(void *opaque, int pin, int level)
265 {
266 PowerPCCPU *cpu = opaque;
267
268 trace_ppc_irq_set(&cpu->env, pin, level);
269
270 switch (pin) {
271 case POWER9_INPUT_INT:
272 /* Level sensitive - active high */
273 trace_ppc_irq_set_state("external IRQ", level);
274 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
275 break;
276 case POWER9_INPUT_HINT:
277 /* Level sensitive - active high */
278 trace_ppc_irq_set_state("HV external IRQ", level);
279 ppc_set_irq(cpu, PPC_INTERRUPT_HVIRT, level);
280 break;
281 default:
282 g_assert_not_reached();
283 return;
284 }
285 }
286
287 void ppcPOWER9_irq_init(PowerPCCPU *cpu)
288 {
289 qdev_init_gpio_in(DEVICE(cpu), power9_set_irq, POWER9_INPUT_NB);
290 }
291 #endif /* defined(TARGET_PPC64) */
292
293 void ppc40x_core_reset(PowerPCCPU *cpu)
294 {
295 CPUPPCState *env = &cpu->env;
296 target_ulong dbsr;
297
298 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC core\n");
299 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
300 dbsr = env->spr[SPR_40x_DBSR];
301 dbsr &= ~0x00000300;
302 dbsr |= 0x00000100;
303 env->spr[SPR_40x_DBSR] = dbsr;
304 }
305
306 void ppc40x_chip_reset(PowerPCCPU *cpu)
307 {
308 CPUPPCState *env = &cpu->env;
309 target_ulong dbsr;
310
311 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC chip\n");
312 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
313 /* XXX: TODO reset all internal peripherals */
314 dbsr = env->spr[SPR_40x_DBSR];
315 dbsr &= ~0x00000300;
316 dbsr |= 0x00000200;
317 env->spr[SPR_40x_DBSR] = dbsr;
318 }
319
320 void ppc40x_system_reset(PowerPCCPU *cpu)
321 {
322 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC system\n");
323 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
324 }
325
326 void store_40x_dbcr0(CPUPPCState *env, uint32_t val)
327 {
328 PowerPCCPU *cpu = env_archcpu(env);
329
330 qemu_mutex_lock_iothread();
331
332 switch ((val >> 28) & 0x3) {
333 case 0x0:
334 /* No action */
335 break;
336 case 0x1:
337 /* Core reset */
338 ppc40x_core_reset(cpu);
339 break;
340 case 0x2:
341 /* Chip reset */
342 ppc40x_chip_reset(cpu);
343 break;
344 case 0x3:
345 /* System reset */
346 ppc40x_system_reset(cpu);
347 break;
348 }
349
350 qemu_mutex_unlock_iothread();
351 }
352
353 /* PowerPC 40x internal IRQ controller */
354 static void ppc40x_set_irq(void *opaque, int pin, int level)
355 {
356 PowerPCCPU *cpu = opaque;
357 CPUPPCState *env = &cpu->env;
358 int cur_level;
359
360 trace_ppc_irq_set(env, pin, level);
361
362 cur_level = (env->irq_input_state >> pin) & 1;
363 /* Don't generate spurious events */
364 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
365 CPUState *cs = CPU(cpu);
366
367 switch (pin) {
368 case PPC40x_INPUT_RESET_SYS:
369 if (level) {
370 trace_ppc_irq_reset("system");
371 ppc40x_system_reset(cpu);
372 }
373 break;
374 case PPC40x_INPUT_RESET_CHIP:
375 if (level) {
376 trace_ppc_irq_reset("chip");
377 ppc40x_chip_reset(cpu);
378 }
379 break;
380 case PPC40x_INPUT_RESET_CORE:
381 /* XXX: TODO: update DBSR[MRR] */
382 if (level) {
383 trace_ppc_irq_reset("core");
384 ppc40x_core_reset(cpu);
385 }
386 break;
387 case PPC40x_INPUT_CINT:
388 /* Level sensitive - active high */
389 trace_ppc_irq_set_state("critical IRQ", level);
390 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
391 break;
392 case PPC40x_INPUT_INT:
393 /* Level sensitive - active high */
394 trace_ppc_irq_set_state("external IRQ", level);
395 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
396 break;
397 case PPC40x_INPUT_HALT:
398 /* Level sensitive - active low */
399 if (level) {
400 trace_ppc_irq_cpu("stop");
401 cs->halted = 1;
402 } else {
403 trace_ppc_irq_cpu("restart");
404 cs->halted = 0;
405 qemu_cpu_kick(cs);
406 }
407 break;
408 case PPC40x_INPUT_DEBUG:
409 /* Level sensitive - active high */
410 trace_ppc_irq_set_state("debug pin", level);
411 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
412 break;
413 default:
414 g_assert_not_reached();
415 }
416 if (level)
417 env->irq_input_state |= 1 << pin;
418 else
419 env->irq_input_state &= ~(1 << pin);
420 }
421 }
422
423 void ppc40x_irq_init(PowerPCCPU *cpu)
424 {
425 CPUPPCState *env = &cpu->env;
426
427 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
428 cpu, PPC40x_INPUT_NB);
429 }
430
431 /* PowerPC E500 internal IRQ controller */
432 static void ppce500_set_irq(void *opaque, int pin, int level)
433 {
434 PowerPCCPU *cpu = opaque;
435 CPUPPCState *env = &cpu->env;
436 int cur_level;
437
438 trace_ppc_irq_set(env, pin, level);
439
440 cur_level = (env->irq_input_state >> pin) & 1;
441 /* Don't generate spurious events */
442 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
443 switch (pin) {
444 case PPCE500_INPUT_MCK:
445 if (level) {
446 trace_ppc_irq_reset("system");
447 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
448 }
449 break;
450 case PPCE500_INPUT_RESET_CORE:
451 if (level) {
452 trace_ppc_irq_reset("core");
453 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level);
454 }
455 break;
456 case PPCE500_INPUT_CINT:
457 /* Level sensitive - active high */
458 trace_ppc_irq_set_state("critical IRQ", level);
459 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
460 break;
461 case PPCE500_INPUT_INT:
462 /* Level sensitive - active high */
463 trace_ppc_irq_set_state("core IRQ", level);
464 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
465 break;
466 case PPCE500_INPUT_DEBUG:
467 /* Level sensitive - active high */
468 trace_ppc_irq_set_state("debug pin", level);
469 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
470 break;
471 default:
472 g_assert_not_reached();
473 }
474 if (level)
475 env->irq_input_state |= 1 << pin;
476 else
477 env->irq_input_state &= ~(1 << pin);
478 }
479 }
480
481 void ppce500_irq_init(PowerPCCPU *cpu)
482 {
483 CPUPPCState *env = &cpu->env;
484
485 env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
486 cpu, PPCE500_INPUT_NB);
487 }
488
489 /* Enable or Disable the E500 EPR capability */
490 void ppce500_set_mpic_proxy(bool enabled)
491 {
492 CPUState *cs;
493
494 CPU_FOREACH(cs) {
495 PowerPCCPU *cpu = POWERPC_CPU(cs);
496
497 cpu->env.mpic_proxy = enabled;
498 if (kvm_enabled()) {
499 kvmppc_set_mpic_proxy(cpu, enabled);
500 }
501 }
502 }
503
504 /*****************************************************************************/
505 /* PowerPC time base and decrementer emulation */
506
507 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset)
508 {
509 /* TB time in tb periods */
510 return muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND) + tb_offset;
511 }
512
513 uint64_t cpu_ppc_load_tbl (CPUPPCState *env)
514 {
515 ppc_tb_t *tb_env = env->tb_env;
516 uint64_t tb;
517
518 if (kvm_enabled()) {
519 return env->spr[SPR_TBL];
520 }
521
522 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
523 trace_ppc_tb_load(tb);
524
525 return tb;
526 }
527
528 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env)
529 {
530 ppc_tb_t *tb_env = env->tb_env;
531 uint64_t tb;
532
533 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
534 trace_ppc_tb_load(tb);
535
536 return tb >> 32;
537 }
538
539 uint32_t cpu_ppc_load_tbu (CPUPPCState *env)
540 {
541 if (kvm_enabled()) {
542 return env->spr[SPR_TBU];
543 }
544
545 return _cpu_ppc_load_tbu(env);
546 }
547
548 static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
549 int64_t *tb_offsetp, uint64_t value)
550 {
551 *tb_offsetp = value -
552 muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND);
553
554 trace_ppc_tb_store(value, *tb_offsetp);
555 }
556
557 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value)
558 {
559 ppc_tb_t *tb_env = env->tb_env;
560 uint64_t tb;
561
562 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
563 tb &= 0xFFFFFFFF00000000ULL;
564 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
565 &tb_env->tb_offset, tb | (uint64_t)value);
566 }
567
568 static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value)
569 {
570 ppc_tb_t *tb_env = env->tb_env;
571 uint64_t tb;
572
573 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
574 tb &= 0x00000000FFFFFFFFULL;
575 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
576 &tb_env->tb_offset, ((uint64_t)value << 32) | tb);
577 }
578
579 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value)
580 {
581 _cpu_ppc_store_tbu(env, value);
582 }
583
584 uint64_t cpu_ppc_load_atbl (CPUPPCState *env)
585 {
586 ppc_tb_t *tb_env = env->tb_env;
587 uint64_t tb;
588
589 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
590 trace_ppc_tb_load(tb);
591
592 return tb;
593 }
594
595 uint32_t cpu_ppc_load_atbu (CPUPPCState *env)
596 {
597 ppc_tb_t *tb_env = env->tb_env;
598 uint64_t tb;
599
600 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
601 trace_ppc_tb_load(tb);
602
603 return tb >> 32;
604 }
605
606 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value)
607 {
608 ppc_tb_t *tb_env = env->tb_env;
609 uint64_t tb;
610
611 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
612 tb &= 0xFFFFFFFF00000000ULL;
613 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
614 &tb_env->atb_offset, tb | (uint64_t)value);
615 }
616
617 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value)
618 {
619 ppc_tb_t *tb_env = env->tb_env;
620 uint64_t tb;
621
622 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
623 tb &= 0x00000000FFFFFFFFULL;
624 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
625 &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
626 }
627
628 uint64_t cpu_ppc_load_vtb(CPUPPCState *env)
629 {
630 ppc_tb_t *tb_env = env->tb_env;
631
632 return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
633 tb_env->vtb_offset);
634 }
635
636 void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value)
637 {
638 ppc_tb_t *tb_env = env->tb_env;
639
640 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
641 &tb_env->vtb_offset, value);
642 }
643
644 void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value)
645 {
646 ppc_tb_t *tb_env = env->tb_env;
647 uint64_t tb;
648
649 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
650 tb_env->tb_offset);
651 tb &= 0xFFFFFFUL;
652 tb |= (value & ~0xFFFFFFUL);
653 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
654 &tb_env->tb_offset, tb);
655 }
656
657 static void cpu_ppc_tb_stop (CPUPPCState *env)
658 {
659 ppc_tb_t *tb_env = env->tb_env;
660 uint64_t tb, atb, vmclk;
661
662 /* If the time base is already frozen, do nothing */
663 if (tb_env->tb_freq != 0) {
664 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
665 /* Get the time base */
666 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset);
667 /* Get the alternate time base */
668 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset);
669 /* Store the time base value (ie compute the current offset) */
670 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
671 /* Store the alternate time base value (compute the current offset) */
672 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
673 /* Set the time base frequency to zero */
674 tb_env->tb_freq = 0;
675 /* Now, the time bases are frozen to tb_offset / atb_offset value */
676 }
677 }
678
679 static void cpu_ppc_tb_start (CPUPPCState *env)
680 {
681 ppc_tb_t *tb_env = env->tb_env;
682 uint64_t tb, atb, vmclk;
683
684 /* If the time base is not frozen, do nothing */
685 if (tb_env->tb_freq == 0) {
686 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
687 /* Get the time base from tb_offset */
688 tb = tb_env->tb_offset;
689 /* Get the alternate time base from atb_offset */
690 atb = tb_env->atb_offset;
691 /* Restore the tb frequency from the decrementer frequency */
692 tb_env->tb_freq = tb_env->decr_freq;
693 /* Store the time base value */
694 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
695 /* Store the alternate time base value */
696 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
697 }
698 }
699
700 bool ppc_decr_clear_on_delivery(CPUPPCState *env)
701 {
702 ppc_tb_t *tb_env = env->tb_env;
703 int flags = PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL;
704 return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED);
705 }
706
707 static inline int64_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next)
708 {
709 ppc_tb_t *tb_env = env->tb_env;
710 int64_t decr, diff;
711
712 diff = next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
713 if (diff >= 0) {
714 decr = muldiv64(diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND);
715 } else if (tb_env->flags & PPC_TIMER_BOOKE) {
716 decr = 0;
717 } else {
718 decr = -muldiv64(-diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND);
719 }
720 trace_ppc_decr_load(decr);
721
722 return decr;
723 }
724
725 target_ulong cpu_ppc_load_decr(CPUPPCState *env)
726 {
727 ppc_tb_t *tb_env = env->tb_env;
728 uint64_t decr;
729
730 if (kvm_enabled()) {
731 return env->spr[SPR_DECR];
732 }
733
734 decr = _cpu_ppc_load_decr(env, tb_env->decr_next);
735
736 /*
737 * If large decrementer is enabled then the decrementer is signed extened
738 * to 64 bits, otherwise it is a 32 bit value.
739 */
740 if (env->spr[SPR_LPCR] & LPCR_LD) {
741 return decr;
742 }
743 return (uint32_t) decr;
744 }
745
746 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env)
747 {
748 PowerPCCPU *cpu = env_archcpu(env);
749 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
750 ppc_tb_t *tb_env = env->tb_env;
751 uint64_t hdecr;
752
753 hdecr = _cpu_ppc_load_decr(env, tb_env->hdecr_next);
754
755 /*
756 * If we have a large decrementer (POWER9 or later) then hdecr is sign
757 * extended to 64 bits, otherwise it is 32 bits.
758 */
759 if (pcc->lrg_decr_bits > 32) {
760 return hdecr;
761 }
762 return (uint32_t) hdecr;
763 }
764
765 uint64_t cpu_ppc_load_purr (CPUPPCState *env)
766 {
767 ppc_tb_t *tb_env = env->tb_env;
768
769 return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
770 tb_env->purr_offset);
771 }
772
773 /* When decrementer expires,
774 * all we need to do is generate or queue a CPU exception
775 */
776 static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu)
777 {
778 /* Raise it */
779 trace_ppc_decr_excp("raise");
780 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1);
781 }
782
783 static inline void cpu_ppc_decr_lower(PowerPCCPU *cpu)
784 {
785 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0);
786 }
787
788 static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu)
789 {
790 CPUPPCState *env = &cpu->env;
791
792 /* Raise it */
793 trace_ppc_decr_excp("raise HV");
794
795 /* The architecture specifies that we don't deliver HDEC
796 * interrupts in a PM state. Not only they don't cause a
797 * wakeup but they also get effectively discarded.
798 */
799 if (!env->resume_as_sreset) {
800 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1);
801 }
802 }
803
804 static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu)
805 {
806 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0);
807 }
808
809 static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp,
810 QEMUTimer *timer,
811 void (*raise_excp)(void *),
812 void (*lower_excp)(PowerPCCPU *),
813 target_ulong decr, target_ulong value,
814 int nr_bits)
815 {
816 CPUPPCState *env = &cpu->env;
817 ppc_tb_t *tb_env = env->tb_env;
818 uint64_t now, next;
819 int64_t signed_value;
820 int64_t signed_decr;
821
822 /* Truncate value to decr_width and sign extend for simplicity */
823 signed_value = sextract64(value, 0, nr_bits);
824 signed_decr = sextract64(decr, 0, nr_bits);
825
826 trace_ppc_decr_store(nr_bits, decr, value);
827
828 if (kvm_enabled()) {
829 /* KVM handles decrementer exceptions, we don't need our own timer */
830 return;
831 }
832
833 /*
834 * Going from 2 -> 1, 1 -> 0 or 0 -> -1 is the event to generate a DEC
835 * interrupt.
836 *
837 * If we get a really small DEC value, we can assume that by the time we
838 * handled it we should inject an interrupt already.
839 *
840 * On MSB level based DEC implementations the MSB always means the interrupt
841 * is pending, so raise it on those.
842 *
843 * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers
844 * an edge interrupt, so raise it here too.
845 */
846 if ((value < 3) ||
847 ((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && signed_value < 0) ||
848 ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && signed_value < 0
849 && signed_decr >= 0)) {
850 (*raise_excp)(cpu);
851 return;
852 }
853
854 /* On MSB level based systems a 0 for the MSB stops interrupt delivery */
855 if (signed_value >= 0 && (tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL)) {
856 (*lower_excp)(cpu);
857 }
858
859 /* Calculate the next timer event */
860 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
861 next = now + muldiv64(value, NANOSECONDS_PER_SECOND, tb_env->decr_freq);
862 *nextp = next;
863
864 /* Adjust timer */
865 timer_mod(timer, next);
866 }
867
868 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, target_ulong decr,
869 target_ulong value, int nr_bits)
870 {
871 ppc_tb_t *tb_env = cpu->env.tb_env;
872
873 __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer,
874 tb_env->decr_timer->cb, &cpu_ppc_decr_lower, decr,
875 value, nr_bits);
876 }
877
878 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value)
879 {
880 PowerPCCPU *cpu = env_archcpu(env);
881 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
882 int nr_bits = 32;
883
884 if (env->spr[SPR_LPCR] & LPCR_LD) {
885 nr_bits = pcc->lrg_decr_bits;
886 }
887
888 _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, nr_bits);
889 }
890
891 static void cpu_ppc_decr_cb(void *opaque)
892 {
893 PowerPCCPU *cpu = opaque;
894
895 cpu_ppc_decr_excp(cpu);
896 }
897
898 static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, target_ulong hdecr,
899 target_ulong value, int nr_bits)
900 {
901 ppc_tb_t *tb_env = cpu->env.tb_env;
902
903 if (tb_env->hdecr_timer != NULL) {
904 __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer,
905 tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower,
906 hdecr, value, nr_bits);
907 }
908 }
909
910 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value)
911 {
912 PowerPCCPU *cpu = env_archcpu(env);
913 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
914
915 _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value,
916 pcc->lrg_decr_bits);
917 }
918
919 static void cpu_ppc_hdecr_cb(void *opaque)
920 {
921 PowerPCCPU *cpu = opaque;
922
923 cpu_ppc_hdecr_excp(cpu);
924 }
925
926 void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value)
927 {
928 ppc_tb_t *tb_env = env->tb_env;
929
930 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
931 &tb_env->purr_offset, value);
932 }
933
934 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
935 {
936 CPUPPCState *env = opaque;
937 PowerPCCPU *cpu = env_archcpu(env);
938 ppc_tb_t *tb_env = env->tb_env;
939
940 tb_env->tb_freq = freq;
941 tb_env->decr_freq = freq;
942 /* There is a bug in Linux 2.4 kernels:
943 * if a decrementer exception is pending when it enables msr_ee at startup,
944 * it's not ready to handle it...
945 */
946 _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32);
947 _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32);
948 cpu_ppc_store_purr(env, 0x0000000000000000ULL);
949 }
950
951 static void timebase_save(PPCTimebase *tb)
952 {
953 uint64_t ticks = cpu_get_host_ticks();
954 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
955
956 if (!first_ppc_cpu->env.tb_env) {
957 error_report("No timebase object");
958 return;
959 }
960
961 /* not used anymore, we keep it for compatibility */
962 tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST);
963 /*
964 * tb_offset is only expected to be changed by QEMU so
965 * there is no need to update it from KVM here
966 */
967 tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset;
968
969 tb->runstate_paused =
970 runstate_check(RUN_STATE_PAUSED) || runstate_check(RUN_STATE_SAVE_VM);
971 }
972
973 static void timebase_load(PPCTimebase *tb)
974 {
975 CPUState *cpu;
976 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
977 int64_t tb_off_adj, tb_off;
978 unsigned long freq;
979
980 if (!first_ppc_cpu->env.tb_env) {
981 error_report("No timebase object");
982 return;
983 }
984
985 freq = first_ppc_cpu->env.tb_env->tb_freq;
986
987 tb_off_adj = tb->guest_timebase - cpu_get_host_ticks();
988
989 tb_off = first_ppc_cpu->env.tb_env->tb_offset;
990 trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off,
991 (tb_off_adj - tb_off) / freq);
992
993 /* Set new offset to all CPUs */
994 CPU_FOREACH(cpu) {
995 PowerPCCPU *pcpu = POWERPC_CPU(cpu);
996 pcpu->env.tb_env->tb_offset = tb_off_adj;
997 kvmppc_set_reg_tb_offset(pcpu, pcpu->env.tb_env->tb_offset);
998 }
999 }
1000
1001 void cpu_ppc_clock_vm_state_change(void *opaque, bool running,
1002 RunState state)
1003 {
1004 PPCTimebase *tb = opaque;
1005
1006 if (running) {
1007 timebase_load(tb);
1008 } else {
1009 timebase_save(tb);
1010 }
1011 }
1012
1013 /*
1014 * When migrating a running guest, read the clock just
1015 * before migration, so that the guest clock counts
1016 * during the events between:
1017 *
1018 * * vm_stop()
1019 * *
1020 * * pre_save()
1021 *
1022 * This reduces clock difference on migration from 5s
1023 * to 0.1s (when max_downtime == 5s), because sending the
1024 * final pages of memory (which happens between vm_stop()
1025 * and pre_save()) takes max_downtime.
1026 */
1027 static int timebase_pre_save(void *opaque)
1028 {
1029 PPCTimebase *tb = opaque;
1030
1031 /* guest_timebase won't be overridden in case of paused guest or savevm */
1032 if (!tb->runstate_paused) {
1033 timebase_save(tb);
1034 }
1035
1036 return 0;
1037 }
1038
1039 const VMStateDescription vmstate_ppc_timebase = {
1040 .name = "timebase",
1041 .version_id = 1,
1042 .minimum_version_id = 1,
1043 .pre_save = timebase_pre_save,
1044 .fields = (VMStateField []) {
1045 VMSTATE_UINT64(guest_timebase, PPCTimebase),
1046 VMSTATE_INT64(time_of_the_day_ns, PPCTimebase),
1047 VMSTATE_END_OF_LIST()
1048 },
1049 };
1050
1051 /* Set up (once) timebase frequency (in Hz) */
1052 clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
1053 {
1054 PowerPCCPU *cpu = env_archcpu(env);
1055 ppc_tb_t *tb_env;
1056
1057 tb_env = g_new0(ppc_tb_t, 1);
1058 env->tb_env = tb_env;
1059 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
1060 if (is_book3s_arch2x(env)) {
1061 /* All Book3S 64bit CPUs implement level based DEC logic */
1062 tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL;
1063 }
1064 /* Create new timer */
1065 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu);
1066 if (env->has_hv_mode && !cpu->vhyp) {
1067 tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_hdecr_cb,
1068 cpu);
1069 } else {
1070 tb_env->hdecr_timer = NULL;
1071 }
1072 cpu_ppc_set_tb_clk(env, freq);
1073
1074 return &cpu_ppc_set_tb_clk;
1075 }
1076
1077 void cpu_ppc_tb_free(CPUPPCState *env)
1078 {
1079 timer_free(env->tb_env->decr_timer);
1080 timer_free(env->tb_env->hdecr_timer);
1081 g_free(env->tb_env);
1082 }
1083
1084 /* cpu_ppc_hdecr_init may be used if the timer is not used by HDEC emulation */
1085 void cpu_ppc_hdecr_init(CPUPPCState *env)
1086 {
1087 PowerPCCPU *cpu = env_archcpu(env);
1088
1089 assert(env->tb_env->hdecr_timer == NULL);
1090
1091 env->tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1092 &cpu_ppc_hdecr_cb, cpu);
1093 }
1094
1095 void cpu_ppc_hdecr_exit(CPUPPCState *env)
1096 {
1097 PowerPCCPU *cpu = env_archcpu(env);
1098
1099 timer_free(env->tb_env->hdecr_timer);
1100 env->tb_env->hdecr_timer = NULL;
1101
1102 cpu_ppc_hdecr_lower(cpu);
1103 }
1104
1105 /*****************************************************************************/
1106 /* PowerPC 40x timers */
1107
1108 /* PIT, FIT & WDT */
1109 typedef struct ppc40x_timer_t ppc40x_timer_t;
1110 struct ppc40x_timer_t {
1111 uint64_t pit_reload; /* PIT auto-reload value */
1112 uint64_t fit_next; /* Tick for next FIT interrupt */
1113 QEMUTimer *fit_timer;
1114 uint64_t wdt_next; /* Tick for next WDT interrupt */
1115 QEMUTimer *wdt_timer;
1116
1117 /* 405 have the PIT, 440 have a DECR. */
1118 unsigned int decr_excp;
1119 };
1120
1121 /* Fixed interval timer */
1122 static void cpu_4xx_fit_cb (void *opaque)
1123 {
1124 PowerPCCPU *cpu = opaque;
1125 CPUPPCState *env = &cpu->env;
1126 ppc_tb_t *tb_env;
1127 ppc40x_timer_t *ppc40x_timer;
1128 uint64_t now, next;
1129
1130 tb_env = env->tb_env;
1131 ppc40x_timer = tb_env->opaque;
1132 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1133 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
1134 case 0:
1135 next = 1 << 9;
1136 break;
1137 case 1:
1138 next = 1 << 13;
1139 break;
1140 case 2:
1141 next = 1 << 17;
1142 break;
1143 case 3:
1144 next = 1 << 21;
1145 break;
1146 default:
1147 /* Cannot occur, but makes gcc happy */
1148 return;
1149 }
1150 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->tb_freq);
1151 if (next == now)
1152 next++;
1153 timer_mod(ppc40x_timer->fit_timer, next);
1154 env->spr[SPR_40x_TSR] |= 1 << 26;
1155 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) {
1156 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1);
1157 }
1158 trace_ppc4xx_fit((int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
1159 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
1160 }
1161
1162 /* Programmable interval timer */
1163 static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
1164 {
1165 ppc40x_timer_t *ppc40x_timer;
1166 uint64_t now, next;
1167
1168 ppc40x_timer = tb_env->opaque;
1169 if (ppc40x_timer->pit_reload <= 1 ||
1170 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
1171 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
1172 /* Stop PIT */
1173 trace_ppc4xx_pit_stop();
1174 timer_del(tb_env->decr_timer);
1175 } else {
1176 trace_ppc4xx_pit_start(ppc40x_timer->pit_reload);
1177 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1178 next = now + muldiv64(ppc40x_timer->pit_reload,
1179 NANOSECONDS_PER_SECOND, tb_env->decr_freq);
1180 if (is_excp)
1181 next += tb_env->decr_next - now;
1182 if (next == now)
1183 next++;
1184 timer_mod(tb_env->decr_timer, next);
1185 tb_env->decr_next = next;
1186 }
1187 }
1188
1189 static void cpu_4xx_pit_cb (void *opaque)
1190 {
1191 PowerPCCPU *cpu = opaque;
1192 CPUPPCState *env = &cpu->env;
1193 ppc_tb_t *tb_env;
1194 ppc40x_timer_t *ppc40x_timer;
1195
1196 tb_env = env->tb_env;
1197 ppc40x_timer = tb_env->opaque;
1198 env->spr[SPR_40x_TSR] |= 1 << 27;
1199 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) {
1200 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1);
1201 }
1202 start_stop_pit(env, tb_env, 1);
1203 trace_ppc4xx_pit((int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
1204 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
1205 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
1206 ppc40x_timer->pit_reload);
1207 }
1208
1209 /* Watchdog timer */
1210 static void cpu_4xx_wdt_cb (void *opaque)
1211 {
1212 PowerPCCPU *cpu = opaque;
1213 CPUPPCState *env = &cpu->env;
1214 ppc_tb_t *tb_env;
1215 ppc40x_timer_t *ppc40x_timer;
1216 uint64_t now, next;
1217
1218 tb_env = env->tb_env;
1219 ppc40x_timer = tb_env->opaque;
1220 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1221 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
1222 case 0:
1223 next = 1 << 17;
1224 break;
1225 case 1:
1226 next = 1 << 21;
1227 break;
1228 case 2:
1229 next = 1 << 25;
1230 break;
1231 case 3:
1232 next = 1 << 29;
1233 break;
1234 default:
1235 /* Cannot occur, but makes gcc happy */
1236 return;
1237 }
1238 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->decr_freq);
1239 if (next == now)
1240 next++;
1241 trace_ppc4xx_wdt(env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
1242 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
1243 case 0x0:
1244 case 0x1:
1245 timer_mod(ppc40x_timer->wdt_timer, next);
1246 ppc40x_timer->wdt_next = next;
1247 env->spr[SPR_40x_TSR] |= 1U << 31;
1248 break;
1249 case 0x2:
1250 timer_mod(ppc40x_timer->wdt_timer, next);
1251 ppc40x_timer->wdt_next = next;
1252 env->spr[SPR_40x_TSR] |= 1 << 30;
1253 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) {
1254 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1);
1255 }
1256 break;
1257 case 0x3:
1258 env->spr[SPR_40x_TSR] &= ~0x30000000;
1259 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
1260 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
1261 case 0x0:
1262 /* No reset */
1263 break;
1264 case 0x1: /* Core reset */
1265 ppc40x_core_reset(cpu);
1266 break;
1267 case 0x2: /* Chip reset */
1268 ppc40x_chip_reset(cpu);
1269 break;
1270 case 0x3: /* System reset */
1271 ppc40x_system_reset(cpu);
1272 break;
1273 }
1274 }
1275 }
1276
1277 void store_40x_pit (CPUPPCState *env, target_ulong val)
1278 {
1279 ppc_tb_t *tb_env;
1280 ppc40x_timer_t *ppc40x_timer;
1281
1282 tb_env = env->tb_env;
1283 ppc40x_timer = tb_env->opaque;
1284 trace_ppc40x_store_pit(val);
1285 ppc40x_timer->pit_reload = val;
1286 start_stop_pit(env, tb_env, 0);
1287 }
1288
1289 target_ulong load_40x_pit (CPUPPCState *env)
1290 {
1291 return cpu_ppc_load_decr(env);
1292 }
1293
1294 void store_40x_tsr(CPUPPCState *env, target_ulong val)
1295 {
1296 PowerPCCPU *cpu = env_archcpu(env);
1297
1298 trace_ppc40x_store_tcr(val);
1299
1300 env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
1301 if (val & 0x80000000) {
1302 ppc_set_irq(cpu, PPC_INTERRUPT_PIT, 0);
1303 }
1304 }
1305
1306 void store_40x_tcr(CPUPPCState *env, target_ulong val)
1307 {
1308 PowerPCCPU *cpu = env_archcpu(env);
1309 ppc_tb_t *tb_env;
1310
1311 trace_ppc40x_store_tsr(val);
1312
1313 tb_env = env->tb_env;
1314 env->spr[SPR_40x_TCR] = val & 0xFFC00000;
1315 start_stop_pit(env, tb_env, 1);
1316 cpu_4xx_wdt_cb(cpu);
1317 }
1318
1319 static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
1320 {
1321 CPUPPCState *env = opaque;
1322 ppc_tb_t *tb_env = env->tb_env;
1323
1324 trace_ppc40x_set_tb_clk(freq);
1325 tb_env->tb_freq = freq;
1326 tb_env->decr_freq = freq;
1327 /* XXX: we should also update all timers */
1328 }
1329
1330 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
1331 unsigned int decr_excp)
1332 {
1333 ppc_tb_t *tb_env;
1334 ppc40x_timer_t *ppc40x_timer;
1335 PowerPCCPU *cpu = env_archcpu(env);
1336
1337 trace_ppc40x_timers_init(freq);
1338
1339 tb_env = g_new0(ppc_tb_t, 1);
1340 ppc40x_timer = g_new0(ppc40x_timer_t, 1);
1341
1342 env->tb_env = tb_env;
1343 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
1344 tb_env->tb_freq = freq;
1345 tb_env->decr_freq = freq;
1346 tb_env->opaque = ppc40x_timer;
1347
1348 /* We use decr timer for PIT */
1349 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, cpu);
1350 ppc40x_timer->fit_timer =
1351 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, cpu);
1352 ppc40x_timer->wdt_timer =
1353 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, cpu);
1354 ppc40x_timer->decr_excp = decr_excp;
1355
1356 return &ppc_40x_set_tb_clk;
1357 }
1358
1359 /*****************************************************************************/
1360 /* Embedded PowerPC Device Control Registers */
1361 typedef struct ppc_dcrn_t ppc_dcrn_t;
1362 struct ppc_dcrn_t {
1363 dcr_read_cb dcr_read;
1364 dcr_write_cb dcr_write;
1365 void *opaque;
1366 };
1367
1368 /* XXX: on 460, DCR addresses are 32 bits wide,
1369 * using DCRIPR to get the 22 upper bits of the DCR address
1370 */
1371 #define DCRN_NB 1024
1372 struct ppc_dcr_t {
1373 ppc_dcrn_t dcrn[DCRN_NB];
1374 int (*read_error)(int dcrn);
1375 int (*write_error)(int dcrn);
1376 };
1377
1378 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1379 {
1380 ppc_dcrn_t *dcr;
1381
1382 if (dcrn < 0 || dcrn >= DCRN_NB)
1383 goto error;
1384 dcr = &dcr_env->dcrn[dcrn];
1385 if (dcr->dcr_read == NULL)
1386 goto error;
1387 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
1388 trace_ppc_dcr_read(dcrn, *valp);
1389
1390 return 0;
1391
1392 error:
1393 if (dcr_env->read_error != NULL)
1394 return (*dcr_env->read_error)(dcrn);
1395
1396 return -1;
1397 }
1398
1399 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1400 {
1401 ppc_dcrn_t *dcr;
1402
1403 if (dcrn < 0 || dcrn >= DCRN_NB)
1404 goto error;
1405 dcr = &dcr_env->dcrn[dcrn];
1406 if (dcr->dcr_write == NULL)
1407 goto error;
1408 trace_ppc_dcr_write(dcrn, val);
1409 (*dcr->dcr_write)(dcr->opaque, dcrn, val);
1410
1411 return 0;
1412
1413 error:
1414 if (dcr_env->write_error != NULL)
1415 return (*dcr_env->write_error)(dcrn);
1416
1417 return -1;
1418 }
1419
1420 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
1421 dcr_read_cb dcr_read, dcr_write_cb dcr_write)
1422 {
1423 ppc_dcr_t *dcr_env;
1424 ppc_dcrn_t *dcr;
1425
1426 dcr_env = env->dcr_env;
1427 if (dcr_env == NULL)
1428 return -1;
1429 if (dcrn < 0 || dcrn >= DCRN_NB)
1430 return -1;
1431 dcr = &dcr_env->dcrn[dcrn];
1432 if (dcr->opaque != NULL ||
1433 dcr->dcr_read != NULL ||
1434 dcr->dcr_write != NULL)
1435 return -1;
1436 dcr->opaque = opaque;
1437 dcr->dcr_read = dcr_read;
1438 dcr->dcr_write = dcr_write;
1439
1440 return 0;
1441 }
1442
1443 int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn),
1444 int (*write_error)(int dcrn))
1445 {
1446 ppc_dcr_t *dcr_env;
1447
1448 dcr_env = g_new0(ppc_dcr_t, 1);
1449 dcr_env->read_error = read_error;
1450 dcr_env->write_error = write_error;
1451 env->dcr_env = dcr_env;
1452
1453 return 0;
1454 }
1455
1456 /*****************************************************************************/
1457
1458 int ppc_cpu_pir(PowerPCCPU *cpu)
1459 {
1460 CPUPPCState *env = &cpu->env;
1461 return env->spr_cb[SPR_PIR].default_value;
1462 }
1463
1464 PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
1465 {
1466 CPUState *cs;
1467
1468 CPU_FOREACH(cs) {
1469 PowerPCCPU *cpu = POWERPC_CPU(cs);
1470
1471 if (ppc_cpu_pir(cpu) == pir) {
1472 return cpu;
1473 }
1474 }
1475
1476 return NULL;
1477 }
1478
1479 void ppc_irq_reset(PowerPCCPU *cpu)
1480 {
1481 CPUPPCState *env = &cpu->env;
1482
1483 env->irq_input_state = 0;
1484 kvmppc_set_interrupt(cpu, PPC_INTERRUPT_EXT, 0);
1485 }
QEmu