hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29
  30 //#define DEBUG_PCI
  31 #ifdef DEBUG_PCI
  32 # define PCI_DPRINTF(format, ...)       printf(format, __VA_ARGS__)
  33 #else
  34 # define PCI_DPRINTF(format, ...)       do { } while (0)
  35 #endif
  36
  37 struct PCIBus {
  38     BusState qbus;
  39     int bus_num;
  40     int devfn_min;
  41     pci_set_irq_fn set_irq;
  42     pci_map_irq_fn map_irq;
  43     uint32_t config_reg; /* XXX: suppress */
  44     /* low level pic */
  45     SetIRQFunc *low_set_irq;
  46     qemu_irq *irq_opaque;
  47     PCIDevice *devices[256];
  48     PCIDevice *parent_dev;
  49     PCIBus *next;
  50     /* The bus IRQ state is the logical OR of the connected devices.
  51        Keep a count of the number of devices with raised IRQs.  */
  52     int nirq;
  53     int *irq_count;
  54 };
  55
  56 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  57
  58 static struct BusInfo pci_bus_info = {
  59     .name       = "PCI",
  60     .size       = sizeof(PCIBus),
  61     .print_dev  = pcibus_dev_print,
  62 };
  63
  64 static void pci_update_mappings(PCIDevice *d);
  65 static void pci_set_irq(void *opaque, int irq_num, int level);
  66
  67 target_phys_addr_t pci_mem_base;
  68 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  69 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  70 static PCIBus *first_bus;
  71
  72 static void pcibus_save(QEMUFile *f, void *opaque)
  73 {
  74     PCIBus *bus = (PCIBus *)opaque;
  75     int i;
  76
  77     qemu_put_be32(f, bus->nirq);
  78     for (i = 0; i < bus->nirq; i++)
  79         qemu_put_be32(f, bus->irq_count[i]);
  80 }
  81
  82 static int  pcibus_load(QEMUFile *f, void *opaque, int version_id)
  83 {
  84     PCIBus *bus = (PCIBus *)opaque;
  85     int i, nirq;
  86
  87     if (version_id != 1)
  88         return -EINVAL;
  89
  90     nirq = qemu_get_be32(f);
  91     if (bus->nirq != nirq) {
  92         fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
  93                 nirq, bus->nirq);
  94         return -EINVAL;
  95     }
  96
  97     for (i = 0; i < nirq; i++)
  98         bus->irq_count[i] = qemu_get_be32(f);
  99
 100     return 0;
 101 }
 102
 103 static void pci_bus_reset(void *opaque)
 104 {
 105     PCIBus *bus = (PCIBus *)opaque;
 106     int i;
 107
 108     for (i = 0; i < bus->nirq; i++) {
 109         bus->irq_count[i] = 0;
 110     }
 111     for (i = 0; i < 256; i++) {
 112         if (bus->devices[i])
 113             memset(bus->devices[i]->irq_state, 0,
 114                    sizeof(bus->devices[i]->irq_state));
 115     }
 116 }
 117
 118 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 119                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 120                          qemu_irq *pic, int devfn_min, int nirq)
 121 {
 122     PCIBus *bus;
 123     static int nbus = 0;
 124
 125     bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, parent, name));
 126     bus->set_irq = set_irq;
 127     bus->map_irq = map_irq;
 128     bus->irq_opaque = pic;
 129     bus->devfn_min = devfn_min;
 130     bus->nirq = nirq;
 131     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 132     bus->next = first_bus;
 133     first_bus = bus;
 134     register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
 135     qemu_register_reset(pci_bus_reset, bus);
 136     return bus;
 137 }
 138
 139 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
 140 {
 141     PCIBus *bus;
 142
 143     bus = qemu_mallocz(sizeof(PCIBus));
 144     bus->map_irq = map_irq;
 145     bus->parent_dev = dev;
 146     bus->next = dev->bus->next;
 147     dev->bus->next = bus;
 148     return bus;
 149 }
 150
 151 int pci_bus_num(PCIBus *s)
 152 {
 153     return s->bus_num;
 154 }
 155
 156 void pci_device_save(PCIDevice *s, QEMUFile *f)
 157 {
 158     int i;
 159
 160     qemu_put_be32(f, 2); /* PCI device version */
 161     qemu_put_buffer(f, s->config, 256);
 162     for (i = 0; i < 4; i++)
 163         qemu_put_be32(f, s->irq_state[i]);
 164 }
 165
 166 int pci_device_load(PCIDevice *s, QEMUFile *f)
 167 {
 168     uint8_t config[PCI_CONFIG_SPACE_SIZE];
 169     uint32_t version_id;
 170     int i;
 171
 172     version_id = qemu_get_be32(f);
 173     if (version_id > 2)
 174         return -EINVAL;
 175     qemu_get_buffer(f, config, sizeof config);
 176     for (i = 0; i < sizeof config; ++i)
 177         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
 178             return -EINVAL;
 179     memcpy(s->config, config, sizeof config);
 180
 181     pci_update_mappings(s);
 182
 183     if (version_id >= 2)
 184         for (i = 0; i < 4; i ++)
 185             s->irq_state[i] = qemu_get_be32(f);
 186     return 0;
 187 }
 188
 189 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 190 {
 191     uint16_t *id;
 192
 193     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 194     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 195     id[1] = cpu_to_le16(pci_default_sub_device_id);
 196     return 0;
 197 }
 198
 199 /*
 200  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 201  */
 202 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 203 {
 204     const char *p;
 205     char *e;
 206     unsigned long val;
 207     unsigned long dom = 0, bus = 0;
 208     unsigned slot = 0;
 209
 210     p = addr;
 211     val = strtoul(p, &e, 16);
 212     if (e == p)
 213         return -1;
 214     if (*e == ':') {
 215         bus = val;
 216         p = e + 1;
 217         val = strtoul(p, &e, 16);
 218         if (e == p)
 219             return -1;
 220         if (*e == ':') {
 221             dom = bus;
 222             bus = val;
 223             p = e + 1;
 224             val = strtoul(p, &e, 16);
 225             if (e == p)
 226                 return -1;
 227         }
 228     }
 229
 230     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 231         return -1;
 232
 233     slot = val;
 234
 235     if (*e)
 236         return -1;
 237
 238     /* Note: QEMU doesn't implement domains other than 0 */
 239     if (dom != 0 || pci_find_bus(bus) == NULL)
 240         return -1;
 241
 242     *domp = dom;
 243     *busp = bus;
 244     *slotp = slot;
 245     return 0;
 246 }
 247
 248 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 249                      unsigned *slotp)
 250 {
 251     /* strip legacy tag */
 252     if (!strncmp(addr, "pci_addr=", 9)) {
 253         addr += 9;
 254     }
 255     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 256         monitor_printf(mon, "Invalid pci address\n");
 257         return -1;
 258     }
 259     return 0;
 260 }
 261
 262 static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 263 {
 264     int dom, bus;
 265     unsigned slot;
 266
 267     if (!devaddr) {
 268         *devfnp = -1;
 269         return pci_find_bus(0);
 270     }
 271
 272     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 273         return NULL;
 274     }
 275
 276     *devfnp = slot << 3;
 277     return pci_find_bus(bus);
 278 }
 279
 280 static void pci_init_cmask(PCIDevice *dev)
 281 {
 282     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 283     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 284     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 285     dev->cmask[PCI_REVISION_ID] = 0xff;
 286     dev->cmask[PCI_CLASS_PROG] = 0xff;
 287     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 288     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 289     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 290 }
 291
 292 static void pci_init_wmask(PCIDevice *dev)
 293 {
 294     int i;
 295     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 296     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 297     dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 298                               | PCI_COMMAND_MASTER;
 299     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 300         dev->wmask[i] = 0xff;
 301 }
 302
 303 /* -1 for devfn means auto assign */
 304 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 305                                          const char *name, int devfn,
 306                                          PCIConfigReadFunc *config_read,
 307                                          PCIConfigWriteFunc *config_write)
 308 {
 309     if (devfn < 0) {
 310         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 311             if (!bus->devices[devfn])
 312                 goto found;
 313         }
 314         return NULL;
 315     found: ;
 316     } else if (bus->devices[devfn]) {
 317         return NULL;
 318     }
 319     pci_dev->bus = bus;
 320     pci_dev->devfn = devfn;
 321     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 322     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 323     pci_set_default_subsystem_id(pci_dev);
 324     pci_init_cmask(pci_dev);
 325     pci_init_wmask(pci_dev);
 326
 327     if (!config_read)
 328         config_read = pci_default_read_config;
 329     if (!config_write)
 330         config_write = pci_default_write_config;
 331     pci_dev->config_read = config_read;
 332     pci_dev->config_write = config_write;
 333     bus->devices[devfn] = pci_dev;
 334     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 335     return pci_dev;
 336 }
 337
 338 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 339                                int instance_size, int devfn,
 340                                PCIConfigReadFunc *config_read,
 341                                PCIConfigWriteFunc *config_write)
 342 {
 343     PCIDevice *pci_dev;
 344
 345     pci_dev = qemu_mallocz(instance_size);
 346     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 347                                      config_read, config_write);
 348     return pci_dev;
 349 }
 350 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 351 {
 352     return addr + pci_mem_base;
 353 }
 354
 355 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 356 {
 357     PCIIORegion *r;
 358     int i;
 359
 360     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 361         r = &pci_dev->io_regions[i];
 362         if (!r->size || r->addr == -1)
 363             continue;
 364         if (r->type == PCI_ADDRESS_SPACE_IO) {
 365             isa_unassign_ioport(r->addr, r->size);
 366         } else {
 367             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 368                                                      r->size,
 369                                                      IO_MEM_UNASSIGNED);
 370         }
 371     }
 372 }
 373
 374 int pci_unregister_device(PCIDevice *pci_dev)
 375 {
 376     int ret = 0;
 377
 378     if (pci_dev->unregister)
 379         ret = pci_dev->unregister(pci_dev);
 380     if (ret)
 381         return ret;
 382
 383     pci_unregister_io_regions(pci_dev);
 384
 385     qemu_free_irqs(pci_dev->irq);
 386     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 387     qdev_free(&pci_dev->qdev);
 388     return 0;
 389 }
 390
 391 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 392                             uint32_t size, int type,
 393                             PCIMapIORegionFunc *map_func)
 394 {
 395     PCIIORegion *r;
 396     uint32_t addr;
 397     uint32_t wmask;
 398
 399     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 400         return;
 401
 402     if (size & (size-1)) {
 403         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 404                     "type=0x%x, size=0x%x\n", type, size);
 405         exit(1);
 406     }
 407
 408     r = &pci_dev->io_regions[region_num];
 409     r->addr = -1;
 410     r->size = size;
 411     r->type = type;
 412     r->map_func = map_func;
 413
 414     wmask = ~(size - 1);
 415     if (region_num == PCI_ROM_SLOT) {
 416         addr = 0x30;
 417         /* ROM enable bit is writeable */
 418         wmask |= 1;
 419     } else {
 420         addr = 0x10 + region_num * 4;
 421     }
 422     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 423     *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask);
 424     *(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
 425 }
 426
 427 static void pci_update_mappings(PCIDevice *d)
 428 {
 429     PCIIORegion *r;
 430     int cmd, i;
 431     uint32_t last_addr, new_addr, config_ofs;
 432
 433     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 434     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 435         r = &d->io_regions[i];
 436         if (i == PCI_ROM_SLOT) {
 437             config_ofs = 0x30;
 438         } else {
 439             config_ofs = 0x10 + i * 4;
 440         }
 441         if (r->size != 0) {
 442             if (r->type & PCI_ADDRESS_SPACE_IO) {
 443                 if (cmd & PCI_COMMAND_IO) {
 444                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 445                                                          config_ofs));
 446                     new_addr = new_addr & ~(r->size - 1);
 447                     last_addr = new_addr + r->size - 1;
 448                     /* NOTE: we have only 64K ioports on PC */
 449                     if (last_addr <= new_addr || new_addr == 0 ||
 450                         last_addr >= 0x10000) {
 451                         new_addr = -1;
 452                     }
 453                 } else {
 454                     new_addr = -1;
 455                 }
 456             } else {
 457                 if (cmd & PCI_COMMAND_MEMORY) {
 458                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 459                                                          config_ofs));
 460                     /* the ROM slot has a specific enable bit */
 461                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 462                         goto no_mem_map;
 463                     new_addr = new_addr & ~(r->size - 1);
 464                     last_addr = new_addr + r->size - 1;
 465                     /* NOTE: we do not support wrapping */
 466                     /* XXX: as we cannot support really dynamic
 467                        mappings, we handle specific values as invalid
 468                        mappings. */
 469                     if (last_addr <= new_addr || new_addr == 0 ||
 470                         last_addr == -1) {
 471                         new_addr = -1;
 472                     }
 473                 } else {
 474                 no_mem_map:
 475                     new_addr = -1;
 476                 }
 477             }
 478             /* now do the real mapping */
 479             if (new_addr != r->addr) {
 480                 if (r->addr != -1) {
 481                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 482                         int class;
 483                         /* NOTE: specific hack for IDE in PC case:
 484                            only one byte must be mapped. */
 485                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 486                         if (class == 0x0101 && r->size == 4) {
 487                             isa_unassign_ioport(r->addr + 2, 1);
 488                         } else {
 489                             isa_unassign_ioport(r->addr, r->size);
 490                         }
 491                     } else {
 492                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 493                                                      r->size,
 494                                                      IO_MEM_UNASSIGNED);
 495                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 496                     }
 497                 }
 498                 r->addr = new_addr;
 499                 if (r->addr != -1) {
 500                     r->map_func(d, i, r->addr, r->size, r->type);
 501                 }
 502             }
 503         }
 504     }
 505 }
 506
 507 uint32_t pci_default_read_config(PCIDevice *d,
 508                                  uint32_t address, int len)
 509 {
 510     uint32_t val;
 511
 512     switch(len) {
 513     default:
 514     case 4:
 515         if (address <= 0xfc) {
 516             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 517             break;
 518         }
 519         /* fall through */
 520     case 2:
 521         if (address <= 0xfe) {
 522             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 523             break;
 524         }
 525         /* fall through */
 526     case 1:
 527         val = d->config[address];
 528         break;
 529     }
 530     return val;
 531 }
 532
 533 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 534 {
 535     uint8_t orig[PCI_CONFIG_SPACE_SIZE];
 536     int i;
 537
 538     /* not efficient, but simple */
 539     memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
 540     for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) {
 541         uint8_t wmask = d->wmask[addr];
 542         d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
 543     }
 544     if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24)
 545         || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
 546             & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
 547         pci_update_mappings(d);
 548 }
 549
 550 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 551 {
 552     PCIBus *s = opaque;
 553     PCIDevice *pci_dev;
 554     int config_addr, bus_num;
 555
 556 #if 0
 557     PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n",
 558                 addr, val, len);
 559 #endif
 560     bus_num = (addr >> 16) & 0xff;
 561     while (s && s->bus_num != bus_num)
 562         s = s->next;
 563     if (!s)
 564         return;
 565     pci_dev = s->devices[(addr >> 8) & 0xff];
 566     if (!pci_dev)
 567         return;
 568     config_addr = addr & 0xff;
 569     PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 570                 pci_dev->name, config_addr, val, len);
 571     pci_dev->config_write(pci_dev, config_addr, val, len);
 572 }
 573
 574 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 575 {
 576     PCIBus *s = opaque;
 577     PCIDevice *pci_dev;
 578     int config_addr, bus_num;
 579     uint32_t val;
 580
 581     bus_num = (addr >> 16) & 0xff;
 582     while (s && s->bus_num != bus_num)
 583         s= s->next;
 584     if (!s)
 585         goto fail;
 586     pci_dev = s->devices[(addr >> 8) & 0xff];
 587     if (!pci_dev) {
 588     fail:
 589         switch(len) {
 590         case 1:
 591             val = 0xff;
 592             break;
 593         case 2:
 594             val = 0xffff;
 595             break;
 596         default:
 597         case 4:
 598             val = 0xffffffff;
 599             break;
 600         }
 601         goto the_end;
 602     }
 603     config_addr = addr & 0xff;
 604     val = pci_dev->config_read(pci_dev, config_addr, len);
 605     PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 606                 pci_dev->name, config_addr, val, len);
 607  the_end:
 608 #if 0
 609     PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n",
 610                 addr, val, len);
 611 #endif
 612     return val;
 613 }
 614
 615 /***********************************************************/
 616 /* generic PCI irq support */
 617
 618 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 619 static void pci_set_irq(void *opaque, int irq_num, int level)
 620 {
 621     PCIDevice *pci_dev = (PCIDevice *)opaque;
 622     PCIBus *bus;
 623     int change;
 624
 625     change = level - pci_dev->irq_state[irq_num];
 626     if (!change)
 627         return;
 628
 629     pci_dev->irq_state[irq_num] = level;
 630     for (;;) {
 631         bus = pci_dev->bus;
 632         irq_num = bus->map_irq(pci_dev, irq_num);
 633         if (bus->set_irq)
 634             break;
 635         pci_dev = bus->parent_dev;
 636     }
 637     bus->irq_count[irq_num] += change;
 638     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 639 }
 640
 641 /***********************************************************/
 642 /* monitor info on PCI */
 643
 644 typedef struct {
 645     uint16_t class;
 646     const char *desc;
 647 } pci_class_desc;
 648
 649 static const pci_class_desc pci_class_descriptions[] =
 650 {
 651     { 0x0100, "SCSI controller"},
 652     { 0x0101, "IDE controller"},
 653     { 0x0102, "Floppy controller"},
 654     { 0x0103, "IPI controller"},
 655     { 0x0104, "RAID controller"},
 656     { 0x0106, "SATA controller"},
 657     { 0x0107, "SAS controller"},
 658     { 0x0180, "Storage controller"},
 659     { 0x0200, "Ethernet controller"},
 660     { 0x0201, "Token Ring controller"},
 661     { 0x0202, "FDDI controller"},
 662     { 0x0203, "ATM controller"},
 663     { 0x0280, "Network controller"},
 664     { 0x0300, "VGA controller"},
 665     { 0x0301, "XGA controller"},
 666     { 0x0302, "3D controller"},
 667     { 0x0380, "Display controller"},
 668     { 0x0400, "Video controller"},
 669     { 0x0401, "Audio controller"},
 670     { 0x0402, "Phone"},
 671     { 0x0480, "Multimedia controller"},
 672     { 0x0500, "RAM controller"},
 673     { 0x0501, "Flash controller"},
 674     { 0x0580, "Memory controller"},
 675     { 0x0600, "Host bridge"},
 676     { 0x0601, "ISA bridge"},
 677     { 0x0602, "EISA bridge"},
 678     { 0x0603, "MC bridge"},
 679     { 0x0604, "PCI bridge"},
 680     { 0x0605, "PCMCIA bridge"},
 681     { 0x0606, "NUBUS bridge"},
 682     { 0x0607, "CARDBUS bridge"},
 683     { 0x0608, "RACEWAY bridge"},
 684     { 0x0680, "Bridge"},
 685     { 0x0c03, "USB controller"},
 686     { 0, NULL}
 687 };
 688
 689 static void pci_info_device(PCIDevice *d)
 690 {
 691     Monitor *mon = cur_mon;
 692     int i, class;
 693     PCIIORegion *r;
 694     const pci_class_desc *desc;
 695
 696     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 697                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 698     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 699     monitor_printf(mon, "    ");
 700     desc = pci_class_descriptions;
 701     while (desc->desc && class != desc->class)
 702         desc++;
 703     if (desc->desc) {
 704         monitor_printf(mon, "%s", desc->desc);
 705     } else {
 706         monitor_printf(mon, "Class %04x", class);
 707     }
 708     monitor_printf(mon, ": PCI device %04x:%04x\n",
 709            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 710            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 711
 712     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 713         monitor_printf(mon, "      IRQ %d.\n",
 714                        d->config[PCI_INTERRUPT_LINE]);
 715     }
 716     if (class == 0x0604) {
 717         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 718     }
 719     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 720         r = &d->io_regions[i];
 721         if (r->size != 0) {
 722             monitor_printf(mon, "      BAR%d: ", i);
 723             if (r->type & PCI_ADDRESS_SPACE_IO) {
 724                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 725                                r->addr, r->addr + r->size - 1);
 726             } else {
 727                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 728                                r->addr, r->addr + r->size - 1);
 729             }
 730         }
 731     }
 732     if (class == 0x0604 && d->config[0x19] != 0) {
 733         pci_for_each_device(d->config[0x19], pci_info_device);
 734     }
 735 }
 736
 737 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 738 {
 739     PCIBus *bus = first_bus;
 740     PCIDevice *d;
 741     int devfn;
 742
 743     while (bus && bus->bus_num != bus_num)
 744         bus = bus->next;
 745     if (bus) {
 746         for(devfn = 0; devfn < 256; devfn++) {
 747             d = bus->devices[devfn];
 748             if (d)
 749                 fn(d);
 750         }
 751     }
 752 }
 753
 754 void pci_info(Monitor *mon)
 755 {
 756     pci_for_each_device(0, pci_info_device);
 757 }
 758
 759 PCIDevice *pci_create(const char *name, const char *devaddr)
 760 {
 761     PCIBus *bus;
 762     int devfn;
 763     DeviceState *dev;
 764
 765     bus = pci_get_bus_devfn(&devfn, devaddr);
 766     if (!bus) {
 767         fprintf(stderr, "Invalid PCI device address %s for device %s\n",
 768                 devaddr, name);
 769         exit(1);
 770     }
 771
 772     dev = qdev_create(&bus->qbus, name);
 773     qdev_set_prop_int(dev, "devfn", devfn);
 774     return (PCIDevice *)dev;
 775 }
 776
 777 static const char * const pci_nic_models[] = {
 778     "ne2k_pci",
 779     "i82551",
 780     "i82557b",
 781     "i82559er",
 782     "rtl8139",
 783     "e1000",
 784     "pcnet",
 785     "virtio",
 786     NULL
 787 };
 788
 789 static const char * const pci_nic_names[] = {
 790     "ne2k_pci",
 791     "i82551",
 792     "i82557b",
 793     "i82559er",
 794     "rtl8139",
 795     "e1000",
 796     "pcnet",
 797     "virtio-net-pci",
 798     NULL
 799 };
 800
 801 /* Initialize a PCI NIC.  */
 802 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 803                         const char *default_devaddr)
 804 {
 805     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
 806     PCIDevice *pci_dev;
 807     DeviceState *dev;
 808     int i;
 809
 810     qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 811
 812     for (i = 0; pci_nic_models[i]; i++) {
 813         if (strcmp(nd->model, pci_nic_models[i]) == 0) {
 814             pci_dev = pci_create(pci_nic_names[i], devaddr);
 815             dev = &pci_dev->qdev;
 816             qdev_set_netdev(dev, nd);
 817             qdev_init(dev);
 818             nd->private = dev;
 819             return pci_dev;
 820         }
 821     }
 822
 823     return NULL;
 824 }
 825
 826 typedef struct {
 827     PCIDevice dev;
 828     PCIBus *bus;
 829 } PCIBridge;
 830
 831 static void pci_bridge_write_config(PCIDevice *d,
 832                              uint32_t address, uint32_t val, int len)
 833 {
 834     PCIBridge *s = (PCIBridge *)d;
 835
 836     pci_default_write_config(d, address, val, len);
 837     s->bus->bus_num = d->config[PCI_SECONDARY_BUS];
 838 }
 839
 840 PCIBus *pci_find_bus(int bus_num)
 841 {
 842     PCIBus *bus = first_bus;
 843
 844     while (bus && bus->bus_num != bus_num)
 845         bus = bus->next;
 846
 847     return bus;
 848 }
 849
 850 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 851 {
 852     PCIBus *bus = pci_find_bus(bus_num);
 853
 854     if (!bus)
 855         return NULL;
 856
 857     return bus->devices[PCI_DEVFN(slot, function)];
 858 }
 859
 860 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 861                         pci_map_irq_fn map_irq, const char *name)
 862 {
 863     PCIBridge *s;
 864     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 865                                          devfn, NULL, pci_bridge_write_config);
 866
 867     pci_config_set_vendor_id(s->dev.config, vid);
 868     pci_config_set_device_id(s->dev.config, did);
 869
 870     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 871     s->dev.config[0x05] = 0x00;
 872     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 873     s->dev.config[0x07] = 0x00; // status = fast devsel
 874     s->dev.config[0x08] = 0x00; // revision
 875     s->dev.config[0x09] = 0x00; // programming i/f
 876     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
 877     s->dev.config[0x0D] = 0x10; // latency_timer
 878     s->dev.config[PCI_HEADER_TYPE] =
 879         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
 880     s->dev.config[0x1E] = 0xa0; // secondary status
 881
 882     s->bus = pci_register_secondary_bus(&s->dev, map_irq);
 883     return s->bus;
 884 }
 885
 886 static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
 887 {
 888     PCIDevice *pci_dev = (PCIDevice *)qdev;
 889     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
 890     PCIBus *bus;
 891     int devfn;
 892
 893     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
 894     devfn = qdev_get_prop_int(qdev, "devfn", -1);
 895     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
 896                                      info->config_read, info->config_write);
 897     assert(pci_dev);
 898     info->init(pci_dev);
 899 }
 900
 901 void pci_qdev_register(PCIDeviceInfo *info)
 902 {
 903     info->qdev.init = pci_qdev_init;
 904     info->qdev.bus_info = &pci_bus_info;
 905     qdev_register(&info->qdev);
 906 }
 907
 908 void pci_qdev_register_many(PCIDeviceInfo *info)
 909 {
 910     while (info->qdev.name) {
 911         pci_qdev_register(info);
 912         info++;
 913     }
 914 }
 915
 916 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
 917 {
 918     DeviceState *dev;
 919
 920     dev = qdev_create(&bus->qbus, name);
 921     qdev_set_prop_int(dev, "devfn", devfn);
 922     qdev_init(dev);
 923
 924     return (PCIDevice *)dev;
 925 }
 926
 927 static int pci_find_space(PCIDevice *pdev, uint8_t size)
 928 {
 929     int offset = PCI_CONFIG_HEADER_SIZE;
 930     int i;
 931     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 932         if (pdev->used[i])
 933             offset = i + 1;
 934         else if (i - offset + 1 == size)
 935             return offset;
 936     return 0;
 937 }
 938
 939 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
 940                                         uint8_t *prev_p)
 941 {
 942     uint8_t next, prev;
 943
 944     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
 945         return 0;
 946
 947     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
 948          prev = next + PCI_CAP_LIST_NEXT)
 949         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
 950             break;
 951
 952     if (prev_p)
 953         *prev_p = prev;
 954     return next;
 955 }
 956
 957 /* Reserve space and add capability to the linked list in pci config space */
 958 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
 959 {
 960     uint8_t offset = pci_find_space(pdev, size);
 961     uint8_t *config = pdev->config + offset;
 962     if (!offset)
 963         return -ENOSPC;
 964     config[PCI_CAP_LIST_ID] = cap_id;
 965     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
 966     pdev->config[PCI_CAPABILITY_LIST] = offset;
 967     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
 968     memset(pdev->used + offset, 0xFF, size);
 969     /* Make capability read-only by default */
 970     memset(pdev->wmask + offset, 0, size);
 971     /* Check capability by default */
 972     memset(pdev->cmask + offset, 0xFF, size);
 973     return offset;
 974 }
 975
 976 /* Unlink capability from the pci config space. */
 977 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
 978 {
 979     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
 980     if (!offset)
 981         return;
 982     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
 983     /* Make capability writeable again */
 984     memset(pdev->wmask + offset, 0xff, size);
 985     /* Clear cmask as device-specific registers can't be checked */
 986     memset(pdev->cmask + offset, 0, size);
 987     memset(pdev->used + offset, 0, size);
 988
 989     if (!pdev->config[PCI_CAPABILITY_LIST])
 990         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
 991 }
 992
 993 /* Reserve space for capability at a known offset (to call after load). */
 994 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
 995 {
 996     memset(pdev->used + offset, 0xff, size);
 997 }
 998
 999 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1000 {
1001     return pci_find_capability_list(pdev, cap_id, NULL);
1002 }
1003
1004 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1005 {
1006     PCIDevice *d = (PCIDevice *)dev;
1007     const pci_class_desc *desc;
1008     char ctxt[64];
1009     PCIIORegion *r;
1010     int i, class;
1011
1012     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
1013     desc = pci_class_descriptions;
1014     while (desc->desc && class != desc->class)
1015         desc++;
1016     if (desc->desc) {
1017         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1018     } else {
1019         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1020     }
1021
1022     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1023                    "pci id %04x:%04x (sub %04x:%04x)\n",
1024                    indent, "", ctxt,
1025                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7,
1026                    le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1027                    le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))),
1028                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))),
1029                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID))));
1030     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1031         r = &d->io_regions[i];
1032         if (!r->size)
1033             continue;
1034         monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "",
1035                        i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem",
1036                        r->addr, r->addr + r->size - 1);
1037     }
1038 }