2 * Vectored Interrupt Controller for nios2 processor
4 * Copyright (c) 2022 Neuroblade
7 * QOM property "cpu": link to the Nios2 CPU (must be set)
8 * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines
9 * IRQ should be connected to nios2 IRQ0.
11 * Reference: "Embedded Peripherals IP User Guide
12 * for Intel® Quartus® Prime Design Suite: 21.4"
13 * Chapter 38 "Vectored Interrupt Controller Core"
14 * See: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/vectored-interrupt-controller-core.html
16 * Permission is hereby granted, free of charge, to any person obtaining a copy
17 * of this software and associated documentation files (the "Software"), to deal
18 * in the Software without restriction, including without limitation the rights
19 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
20 * copies of the Software, and to permit persons to whom the Software is
21 * furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice shall be included in
24 * all copies or substantial portions of the Software.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
27 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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35 #ifndef HW_INTC_NIOS2_VIC_H
36 #define HW_INTC_NIOS2_VIC_H
38 #define TYPE_NIOS2_VIC "nios2-vic"
39 OBJECT_DECLARE_SIMPLE_TYPE(Nios2VIC
, NIOS2_VIC
)
41 #define NIOS2_VIC_MAX_IRQ 32
45 SysBusDevice parent_obj
;
54 uint32_t int_config
[NIOS2_VIC_MAX_IRQ
];
56 uint32_t int_raw_status
;
60 uint32_t vec_tbl_base
;
61 uint32_t vec_tbl_addr
;
64 #endif /* HW_INTC_NIOS2_VIC_H */