include/hw/intc/loongarch_pch_msi.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * LoongArch 7A1000 I/O interrupt controller definitions
   4  *
   5  * Copyright (C) 2021 Loongson Technology Corporation Limited
   6  */
   7
   8 #define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi"
   9 OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI)
  10
  11 /* Msi irq start start from 64 to 255 */
  12 #define PCH_MSI_IRQ_START   64
  13 #define PCH_MSI_IRQ_END     255
  14 #define PCH_MSI_IRQ_NUM     192
  15
  16 struct LoongArchPCHMSI {
  17     SysBusDevice parent_obj;
  18     qemu_irq pch_msi_irq[PCH_MSI_IRQ_NUM];
  19     MemoryRegion msi_mmio;
  20     /* irq base passed to upper extioi intc */
  21     unsigned int irq_base;
  22 };