2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/host-utils.h"
22 #include "exec/helper-proto.h"
23 #include "exec/cpu_ldst.h"
24 #include "sysemu/kvm.h"
26 #ifndef CONFIG_USER_ONLY
27 static inline void cpu_mips_tlb_flush (CPUMIPSState
*env
, int flush_global
);
30 /*****************************************************************************/
31 /* Exceptions processing helpers */
33 void helper_raise_exception_err(CPUMIPSState
*env
, uint32_t exception
,
36 do_raise_exception_err(env
, exception
, error_code
, 0);
39 void helper_raise_exception(CPUMIPSState
*env
, uint32_t exception
)
41 do_raise_exception(env
, exception
, GETPC());
44 void helper_raise_exception_debug(CPUMIPSState
*env
)
46 do_raise_exception(env
, EXCP_DEBUG
, 0);
49 static void raise_exception(CPUMIPSState
*env
, uint32_t exception
)
51 do_raise_exception(env
, exception
, 0);
54 #if defined(CONFIG_USER_ONLY)
55 #define HELPER_LD(name, insn, type) \
56 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
57 int mem_idx, uintptr_t retaddr) \
59 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
62 #define HELPER_LD(name, insn, type) \
63 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
64 int mem_idx, uintptr_t retaddr) \
68 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
69 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
71 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
75 HELPER_LD(lw
, ldl
, int32_t)
76 #if defined(TARGET_MIPS64)
77 HELPER_LD(ld
, ldq
, int64_t)
81 #if defined(CONFIG_USER_ONLY)
82 #define HELPER_ST(name, insn, type) \
83 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
84 type val, int mem_idx, uintptr_t retaddr) \
86 cpu_##insn##_data_ra(env, addr, val, retaddr); \
89 #define HELPER_ST(name, insn, type) \
90 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
91 type val, int mem_idx, uintptr_t retaddr) \
95 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
96 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
98 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
102 HELPER_ST(sb
, stb
, uint8_t)
103 HELPER_ST(sw
, stl
, uint32_t)
104 #if defined(TARGET_MIPS64)
105 HELPER_ST(sd
, stq
, uint64_t)
109 target_ulong
helper_clo (target_ulong arg1
)
114 target_ulong
helper_clz (target_ulong arg1
)
119 #if defined(TARGET_MIPS64)
120 target_ulong
helper_dclo (target_ulong arg1
)
125 target_ulong
helper_dclz (target_ulong arg1
)
129 #endif /* TARGET_MIPS64 */
131 /* 64 bits arithmetic for 32 bits hosts */
132 static inline uint64_t get_HILO(CPUMIPSState
*env
)
134 return ((uint64_t)(env
->active_tc
.HI
[0]) << 32) | (uint32_t)env
->active_tc
.LO
[0];
137 static inline target_ulong
set_HIT0_LO(CPUMIPSState
*env
, uint64_t HILO
)
140 env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
141 tmp
= env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
145 static inline target_ulong
set_HI_LOT0(CPUMIPSState
*env
, uint64_t HILO
)
147 target_ulong tmp
= env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
148 env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
152 /* Multiplication variants of the vr54xx. */
153 target_ulong
helper_muls(CPUMIPSState
*env
, target_ulong arg1
,
156 return set_HI_LOT0(env
, 0 - ((int64_t)(int32_t)arg1
*
157 (int64_t)(int32_t)arg2
));
160 target_ulong
helper_mulsu(CPUMIPSState
*env
, target_ulong arg1
,
163 return set_HI_LOT0(env
, 0 - (uint64_t)(uint32_t)arg1
*
164 (uint64_t)(uint32_t)arg2
);
167 target_ulong
helper_macc(CPUMIPSState
*env
, target_ulong arg1
,
170 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
171 (int64_t)(int32_t)arg2
);
174 target_ulong
helper_macchi(CPUMIPSState
*env
, target_ulong arg1
,
177 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
178 (int64_t)(int32_t)arg2
);
181 target_ulong
helper_maccu(CPUMIPSState
*env
, target_ulong arg1
,
184 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) +
185 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
188 target_ulong
helper_macchiu(CPUMIPSState
*env
, target_ulong arg1
,
191 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) +
192 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
195 target_ulong
helper_msac(CPUMIPSState
*env
, target_ulong arg1
,
198 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
199 (int64_t)(int32_t)arg2
);
202 target_ulong
helper_msachi(CPUMIPSState
*env
, target_ulong arg1
,
205 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
206 (int64_t)(int32_t)arg2
);
209 target_ulong
helper_msacu(CPUMIPSState
*env
, target_ulong arg1
,
212 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) -
213 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
216 target_ulong
helper_msachiu(CPUMIPSState
*env
, target_ulong arg1
,
219 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) -
220 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
223 target_ulong
helper_mulhi(CPUMIPSState
*env
, target_ulong arg1
,
226 return set_HIT0_LO(env
, (int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
);
229 target_ulong
helper_mulhiu(CPUMIPSState
*env
, target_ulong arg1
,
232 return set_HIT0_LO(env
, (uint64_t)(uint32_t)arg1
*
233 (uint64_t)(uint32_t)arg2
);
236 target_ulong
helper_mulshi(CPUMIPSState
*env
, target_ulong arg1
,
239 return set_HIT0_LO(env
, 0 - (int64_t)(int32_t)arg1
*
240 (int64_t)(int32_t)arg2
);
243 target_ulong
helper_mulshiu(CPUMIPSState
*env
, target_ulong arg1
,
246 return set_HIT0_LO(env
, 0 - (uint64_t)(uint32_t)arg1
*
247 (uint64_t)(uint32_t)arg2
);
250 static inline target_ulong
bitswap(target_ulong v
)
252 v
= ((v
>> 1) & (target_ulong
)0x5555555555555555ULL
) |
253 ((v
& (target_ulong
)0x5555555555555555ULL
) << 1);
254 v
= ((v
>> 2) & (target_ulong
)0x3333333333333333ULL
) |
255 ((v
& (target_ulong
)0x3333333333333333ULL
) << 2);
256 v
= ((v
>> 4) & (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) |
257 ((v
& (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) << 4);
262 target_ulong
helper_dbitswap(target_ulong rt
)
268 target_ulong
helper_bitswap(target_ulong rt
)
270 return (int32_t)bitswap(rt
);
273 #ifndef CONFIG_USER_ONLY
275 static inline hwaddr
do_translate_address(CPUMIPSState
*env
,
276 target_ulong address
,
277 int rw
, uintptr_t retaddr
)
280 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
282 lladdr
= cpu_mips_translate_address(env
, address
, rw
);
284 if (lladdr
== -1LL) {
285 cpu_loop_exit_restore(cs
, retaddr
);
291 #define HELPER_LD_ATOMIC(name, insn, almask) \
292 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
294 if (arg & almask) { \
295 env->CP0_BadVAddr = arg; \
296 do_raise_exception(env, EXCP_AdEL, GETPC()); \
298 env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
299 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
302 HELPER_LD_ATOMIC(ll
, lw
, 0x3)
304 HELPER_LD_ATOMIC(lld
, ld
, 0x7)
306 #undef HELPER_LD_ATOMIC
308 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
309 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
310 target_ulong arg2, int mem_idx) \
314 if (arg2 & almask) { \
315 env->CP0_BadVAddr = arg2; \
316 do_raise_exception(env, EXCP_AdES, GETPC()); \
318 if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
319 tmp = do_##ld_insn(env, arg2, mem_idx, GETPC()); \
320 if (tmp == env->llval) { \
321 do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); \
327 HELPER_ST_ATOMIC(sc
, lw
, sw
, 0x3)
329 HELPER_ST_ATOMIC(scd
, ld
, sd
, 0x7)
331 #undef HELPER_ST_ATOMIC
334 #ifdef TARGET_WORDS_BIGENDIAN
335 #define GET_LMASK(v) ((v) & 3)
336 #define GET_OFFSET(addr, offset) (addr + (offset))
338 #define GET_LMASK(v) (((v) & 3) ^ 3)
339 #define GET_OFFSET(addr, offset) (addr - (offset))
342 void helper_swl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
345 do_sb(env
, arg2
, (uint8_t)(arg1
>> 24), mem_idx
, GETPC());
347 if (GET_LMASK(arg2
) <= 2) {
348 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 16), mem_idx
,
352 if (GET_LMASK(arg2
) <= 1) {
353 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 8), mem_idx
,
357 if (GET_LMASK(arg2
) == 0) {
358 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)arg1
, mem_idx
,
363 void helper_swr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
366 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
368 if (GET_LMASK(arg2
) >= 1) {
369 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
,
373 if (GET_LMASK(arg2
) >= 2) {
374 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
,
378 if (GET_LMASK(arg2
) == 3) {
379 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
,
384 #if defined(TARGET_MIPS64)
385 /* "half" load and stores. We must do the memory access inline,
386 or fault handling won't work. */
388 #ifdef TARGET_WORDS_BIGENDIAN
389 #define GET_LMASK64(v) ((v) & 7)
391 #define GET_LMASK64(v) (((v) & 7) ^ 7)
394 void helper_sdl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
397 do_sb(env
, arg2
, (uint8_t)(arg1
>> 56), mem_idx
, GETPC());
399 if (GET_LMASK64(arg2
) <= 6) {
400 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 48), mem_idx
,
404 if (GET_LMASK64(arg2
) <= 5) {
405 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 40), mem_idx
,
409 if (GET_LMASK64(arg2
) <= 4) {
410 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)(arg1
>> 32), mem_idx
,
414 if (GET_LMASK64(arg2
) <= 3) {
415 do_sb(env
, GET_OFFSET(arg2
, 4), (uint8_t)(arg1
>> 24), mem_idx
,
419 if (GET_LMASK64(arg2
) <= 2) {
420 do_sb(env
, GET_OFFSET(arg2
, 5), (uint8_t)(arg1
>> 16), mem_idx
,
424 if (GET_LMASK64(arg2
) <= 1) {
425 do_sb(env
, GET_OFFSET(arg2
, 6), (uint8_t)(arg1
>> 8), mem_idx
,
429 if (GET_LMASK64(arg2
) <= 0) {
430 do_sb(env
, GET_OFFSET(arg2
, 7), (uint8_t)arg1
, mem_idx
,
435 void helper_sdr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
438 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
, GETPC());
440 if (GET_LMASK64(arg2
) >= 1) {
441 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
,
445 if (GET_LMASK64(arg2
) >= 2) {
446 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
,
450 if (GET_LMASK64(arg2
) >= 3) {
451 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
,
455 if (GET_LMASK64(arg2
) >= 4) {
456 do_sb(env
, GET_OFFSET(arg2
, -4), (uint8_t)(arg1
>> 32), mem_idx
,
460 if (GET_LMASK64(arg2
) >= 5) {
461 do_sb(env
, GET_OFFSET(arg2
, -5), (uint8_t)(arg1
>> 40), mem_idx
,
465 if (GET_LMASK64(arg2
) >= 6) {
466 do_sb(env
, GET_OFFSET(arg2
, -6), (uint8_t)(arg1
>> 48), mem_idx
,
470 if (GET_LMASK64(arg2
) == 7) {
471 do_sb(env
, GET_OFFSET(arg2
, -7), (uint8_t)(arg1
>> 56), mem_idx
,
475 #endif /* TARGET_MIPS64 */
477 static const int multiple_regs
[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
479 void helper_lwm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
482 target_ulong base_reglist
= reglist
& 0xf;
483 target_ulong do_r31
= reglist
& 0x10;
485 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
488 for (i
= 0; i
< base_reglist
; i
++) {
489 env
->active_tc
.gpr
[multiple_regs
[i
]] =
490 (target_long
)do_lw(env
, addr
, mem_idx
, GETPC());
496 env
->active_tc
.gpr
[31] = (target_long
)do_lw(env
, addr
, mem_idx
,
501 void helper_swm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
504 target_ulong base_reglist
= reglist
& 0xf;
505 target_ulong do_r31
= reglist
& 0x10;
507 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
510 for (i
= 0; i
< base_reglist
; i
++) {
511 do_sw(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
,
518 do_sw(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
522 #if defined(TARGET_MIPS64)
523 void helper_ldm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
526 target_ulong base_reglist
= reglist
& 0xf;
527 target_ulong do_r31
= reglist
& 0x10;
529 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
532 for (i
= 0; i
< base_reglist
; i
++) {
533 env
->active_tc
.gpr
[multiple_regs
[i
]] = do_ld(env
, addr
, mem_idx
,
540 env
->active_tc
.gpr
[31] = do_ld(env
, addr
, mem_idx
, GETPC());
544 void helper_sdm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
547 target_ulong base_reglist
= reglist
& 0xf;
548 target_ulong do_r31
= reglist
& 0x10;
550 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
553 for (i
= 0; i
< base_reglist
; i
++) {
554 do_sd(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
,
561 do_sd(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
, GETPC());
566 #ifndef CONFIG_USER_ONLY
568 static bool mips_vpe_is_wfi(MIPSCPU
*c
)
570 CPUState
*cpu
= CPU(c
);
571 CPUMIPSState
*env
= &c
->env
;
573 /* If the VPE is halted but otherwise active, it means it's waiting for
575 return cpu
->halted
&& mips_vpe_active(env
);
578 static inline void mips_vpe_wake(MIPSCPU
*c
)
580 /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
581 because there might be other conditions that state that c should
583 cpu_interrupt(CPU(c
), CPU_INTERRUPT_WAKE
);
586 static inline void mips_vpe_sleep(MIPSCPU
*cpu
)
588 CPUState
*cs
= CPU(cpu
);
590 /* The VPE was shut off, really go to bed.
591 Reset any old _WAKE requests. */
593 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
596 static inline void mips_tc_wake(MIPSCPU
*cpu
, int tc
)
598 CPUMIPSState
*c
= &cpu
->env
;
600 /* FIXME: TC reschedule. */
601 if (mips_vpe_active(c
) && !mips_vpe_is_wfi(cpu
)) {
606 static inline void mips_tc_sleep(MIPSCPU
*cpu
, int tc
)
608 CPUMIPSState
*c
= &cpu
->env
;
610 /* FIXME: TC reschedule. */
611 if (!mips_vpe_active(c
)) {
618 * @env: CPU from which mapping is performed.
619 * @tc: Should point to an int with the value of the global TC index.
621 * This function will transform @tc into a local index within the
622 * returned #CPUMIPSState.
624 /* FIXME: This code assumes that all VPEs have the same number of TCs,
625 which depends on runtime setup. Can probably be fixed by
626 walking the list of CPUMIPSStates. */
627 static CPUMIPSState
*mips_cpu_map_tc(CPUMIPSState
*env
, int *tc
)
635 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))) {
636 /* Not allowed to address other CPUs. */
637 *tc
= env
->current_tc
;
641 cs
= CPU(mips_env_get_cpu(env
));
642 vpe_idx
= tc_idx
/ cs
->nr_threads
;
643 *tc
= tc_idx
% cs
->nr_threads
;
644 other_cs
= qemu_get_cpu(vpe_idx
);
645 if (other_cs
== NULL
) {
648 cpu
= MIPS_CPU(other_cs
);
652 /* The per VPE CP0_Status register shares some fields with the per TC
653 CP0_TCStatus registers. These fields are wired to the same registers,
654 so changes to either of them should be reflected on both registers.
656 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
658 These helper call synchronizes the regs for a given cpu. */
660 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
661 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
664 /* Called for updates to CP0_TCStatus. */
665 static void sync_c0_tcstatus(CPUMIPSState
*cpu
, int tc
,
669 uint32_t tcu
, tmx
, tasid
, tksu
;
670 uint32_t mask
= ((1U << CP0St_CU3
)
677 tcu
= (v
>> CP0TCSt_TCU0
) & 0xf;
678 tmx
= (v
>> CP0TCSt_TMX
) & 0x1;
680 tksu
= (v
>> CP0TCSt_TKSU
) & 0x3;
682 status
= tcu
<< CP0St_CU0
;
683 status
|= tmx
<< CP0St_MX
;
684 status
|= tksu
<< CP0St_KSU
;
686 cpu
->CP0_Status
&= ~mask
;
687 cpu
->CP0_Status
|= status
;
689 /* Sync the TASID with EntryHi. */
690 cpu
->CP0_EntryHi
&= ~0xff;
691 cpu
->CP0_EntryHi
|= tasid
;
696 /* Called for updates to CP0_EntryHi. */
697 static void sync_c0_entryhi(CPUMIPSState
*cpu
, int tc
)
700 uint32_t asid
, v
= cpu
->CP0_EntryHi
;
704 if (tc
== cpu
->current_tc
) {
705 tcst
= &cpu
->active_tc
.CP0_TCStatus
;
707 tcst
= &cpu
->tcs
[tc
].CP0_TCStatus
;
715 target_ulong
helper_mfc0_mvpcontrol(CPUMIPSState
*env
)
717 return env
->mvp
->CP0_MVPControl
;
720 target_ulong
helper_mfc0_mvpconf0(CPUMIPSState
*env
)
722 return env
->mvp
->CP0_MVPConf0
;
725 target_ulong
helper_mfc0_mvpconf1(CPUMIPSState
*env
)
727 return env
->mvp
->CP0_MVPConf1
;
730 target_ulong
helper_mfc0_random(CPUMIPSState
*env
)
732 return (int32_t)cpu_mips_get_random(env
);
735 target_ulong
helper_mfc0_tcstatus(CPUMIPSState
*env
)
737 return env
->active_tc
.CP0_TCStatus
;
740 target_ulong
helper_mftc0_tcstatus(CPUMIPSState
*env
)
742 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
743 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
745 if (other_tc
== other
->current_tc
)
746 return other
->active_tc
.CP0_TCStatus
;
748 return other
->tcs
[other_tc
].CP0_TCStatus
;
751 target_ulong
helper_mfc0_tcbind(CPUMIPSState
*env
)
753 return env
->active_tc
.CP0_TCBind
;
756 target_ulong
helper_mftc0_tcbind(CPUMIPSState
*env
)
758 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
759 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
761 if (other_tc
== other
->current_tc
)
762 return other
->active_tc
.CP0_TCBind
;
764 return other
->tcs
[other_tc
].CP0_TCBind
;
767 target_ulong
helper_mfc0_tcrestart(CPUMIPSState
*env
)
769 return env
->active_tc
.PC
;
772 target_ulong
helper_mftc0_tcrestart(CPUMIPSState
*env
)
774 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
775 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
777 if (other_tc
== other
->current_tc
)
778 return other
->active_tc
.PC
;
780 return other
->tcs
[other_tc
].PC
;
783 target_ulong
helper_mfc0_tchalt(CPUMIPSState
*env
)
785 return env
->active_tc
.CP0_TCHalt
;
788 target_ulong
helper_mftc0_tchalt(CPUMIPSState
*env
)
790 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
791 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
793 if (other_tc
== other
->current_tc
)
794 return other
->active_tc
.CP0_TCHalt
;
796 return other
->tcs
[other_tc
].CP0_TCHalt
;
799 target_ulong
helper_mfc0_tccontext(CPUMIPSState
*env
)
801 return env
->active_tc
.CP0_TCContext
;
804 target_ulong
helper_mftc0_tccontext(CPUMIPSState
*env
)
806 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
807 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
809 if (other_tc
== other
->current_tc
)
810 return other
->active_tc
.CP0_TCContext
;
812 return other
->tcs
[other_tc
].CP0_TCContext
;
815 target_ulong
helper_mfc0_tcschedule(CPUMIPSState
*env
)
817 return env
->active_tc
.CP0_TCSchedule
;
820 target_ulong
helper_mftc0_tcschedule(CPUMIPSState
*env
)
822 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
823 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
825 if (other_tc
== other
->current_tc
)
826 return other
->active_tc
.CP0_TCSchedule
;
828 return other
->tcs
[other_tc
].CP0_TCSchedule
;
831 target_ulong
helper_mfc0_tcschefback(CPUMIPSState
*env
)
833 return env
->active_tc
.CP0_TCScheFBack
;
836 target_ulong
helper_mftc0_tcschefback(CPUMIPSState
*env
)
838 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
839 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
841 if (other_tc
== other
->current_tc
)
842 return other
->active_tc
.CP0_TCScheFBack
;
844 return other
->tcs
[other_tc
].CP0_TCScheFBack
;
847 target_ulong
helper_mfc0_count(CPUMIPSState
*env
)
849 return (int32_t)cpu_mips_get_count(env
);
852 target_ulong
helper_mftc0_entryhi(CPUMIPSState
*env
)
854 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
855 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
857 return other
->CP0_EntryHi
;
860 target_ulong
helper_mftc0_cause(CPUMIPSState
*env
)
862 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
864 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
866 if (other_tc
== other
->current_tc
) {
867 tccause
= other
->CP0_Cause
;
869 tccause
= other
->CP0_Cause
;
875 target_ulong
helper_mftc0_status(CPUMIPSState
*env
)
877 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
878 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
880 return other
->CP0_Status
;
883 target_ulong
helper_mfc0_lladdr(CPUMIPSState
*env
)
885 return (int32_t)(env
->lladdr
>> env
->CP0_LLAddr_shift
);
888 target_ulong
helper_mfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
890 return (int32_t)env
->CP0_WatchLo
[sel
];
893 target_ulong
helper_mfc0_watchhi(CPUMIPSState
*env
, uint32_t sel
)
895 return env
->CP0_WatchHi
[sel
];
898 target_ulong
helper_mfc0_debug(CPUMIPSState
*env
)
900 target_ulong t0
= env
->CP0_Debug
;
901 if (env
->hflags
& MIPS_HFLAG_DM
)
907 target_ulong
helper_mftc0_debug(CPUMIPSState
*env
)
909 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
911 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
913 if (other_tc
== other
->current_tc
)
914 tcstatus
= other
->active_tc
.CP0_Debug_tcstatus
;
916 tcstatus
= other
->tcs
[other_tc
].CP0_Debug_tcstatus
;
918 /* XXX: Might be wrong, check with EJTAG spec. */
919 return (other
->CP0_Debug
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
920 (tcstatus
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
923 #if defined(TARGET_MIPS64)
924 target_ulong
helper_dmfc0_tcrestart(CPUMIPSState
*env
)
926 return env
->active_tc
.PC
;
929 target_ulong
helper_dmfc0_tchalt(CPUMIPSState
*env
)
931 return env
->active_tc
.CP0_TCHalt
;
934 target_ulong
helper_dmfc0_tccontext(CPUMIPSState
*env
)
936 return env
->active_tc
.CP0_TCContext
;
939 target_ulong
helper_dmfc0_tcschedule(CPUMIPSState
*env
)
941 return env
->active_tc
.CP0_TCSchedule
;
944 target_ulong
helper_dmfc0_tcschefback(CPUMIPSState
*env
)
946 return env
->active_tc
.CP0_TCScheFBack
;
949 target_ulong
helper_dmfc0_lladdr(CPUMIPSState
*env
)
951 return env
->lladdr
>> env
->CP0_LLAddr_shift
;
954 target_ulong
helper_dmfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
956 return env
->CP0_WatchLo
[sel
];
958 #endif /* TARGET_MIPS64 */
960 void helper_mtc0_index(CPUMIPSState
*env
, target_ulong arg1
)
962 uint32_t index_p
= env
->CP0_Index
& 0x80000000;
963 uint32_t tlb_index
= arg1
& 0x7fffffff;
964 if (tlb_index
< env
->tlb
->nb_tlb
) {
965 if (env
->insn_flags
& ISA_MIPS32R6
) {
966 index_p
|= arg1
& 0x80000000;
968 env
->CP0_Index
= index_p
| tlb_index
;
972 void helper_mtc0_mvpcontrol(CPUMIPSState
*env
, target_ulong arg1
)
977 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))
978 mask
|= (1 << CP0MVPCo_CPA
) | (1 << CP0MVPCo_VPC
) |
980 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
981 mask
|= (1 << CP0MVPCo_STLB
);
982 newval
= (env
->mvp
->CP0_MVPControl
& ~mask
) | (arg1
& mask
);
984 // TODO: Enable/disable shared TLB, enable/disable VPEs.
986 env
->mvp
->CP0_MVPControl
= newval
;
989 void helper_mtc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
994 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
995 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
996 newval
= (env
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
998 /* Yield scheduler intercept not implemented. */
999 /* Gating storage scheduler intercept not implemented. */
1001 // TODO: Enable/disable TCs.
1003 env
->CP0_VPEControl
= newval
;
1006 void helper_mttc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
1008 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1009 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1013 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
1014 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
1015 newval
= (other
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
1017 /* TODO: Enable/disable TCs. */
1019 other
->CP0_VPEControl
= newval
;
1022 target_ulong
helper_mftc0_vpecontrol(CPUMIPSState
*env
)
1024 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1025 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1026 /* FIXME: Mask away return zero on read bits. */
1027 return other
->CP0_VPEControl
;
1030 target_ulong
helper_mftc0_vpeconf0(CPUMIPSState
*env
)
1032 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1033 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1035 return other
->CP0_VPEConf0
;
1038 void helper_mtc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1043 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) {
1044 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))
1045 mask
|= (0xff << CP0VPEC0_XTC
);
1046 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1048 newval
= (env
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1050 // TODO: TC exclusive handling due to ERL/EXL.
1052 env
->CP0_VPEConf0
= newval
;
1055 void helper_mttc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1057 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1058 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1062 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1063 newval
= (other
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1065 /* TODO: TC exclusive handling due to ERL/EXL. */
1066 other
->CP0_VPEConf0
= newval
;
1069 void helper_mtc0_vpeconf1(CPUMIPSState
*env
, target_ulong arg1
)
1074 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1075 mask
|= (0xff << CP0VPEC1_NCX
) | (0xff << CP0VPEC1_NCP2
) |
1076 (0xff << CP0VPEC1_NCP1
);
1077 newval
= (env
->CP0_VPEConf1
& ~mask
) | (arg1
& mask
);
1079 /* UDI not implemented. */
1080 /* CP2 not implemented. */
1082 // TODO: Handle FPU (CP1) binding.
1084 env
->CP0_VPEConf1
= newval
;
1087 void helper_mtc0_yqmask(CPUMIPSState
*env
, target_ulong arg1
)
1089 /* Yield qualifier inputs not implemented. */
1090 env
->CP0_YQMask
= 0x00000000;
1093 void helper_mtc0_vpeopt(CPUMIPSState
*env
, target_ulong arg1
)
1095 env
->CP0_VPEOpt
= arg1
& 0x0000ffff;
1098 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1100 void helper_mtc0_entrylo0(CPUMIPSState
*env
, target_ulong arg1
)
1102 /* 1k pages not implemented */
1103 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1104 env
->CP0_EntryLo0
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1105 | (rxi
<< (CP0EnLo_XI
- 30));
1108 #if defined(TARGET_MIPS64)
1109 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1111 void helper_dmtc0_entrylo0(CPUMIPSState
*env
, uint64_t arg1
)
1113 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1114 env
->CP0_EntryLo0
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1118 void helper_mtc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1120 uint32_t mask
= env
->CP0_TCStatus_rw_bitmask
;
1123 newval
= (env
->active_tc
.CP0_TCStatus
& ~mask
) | (arg1
& mask
);
1125 env
->active_tc
.CP0_TCStatus
= newval
;
1126 sync_c0_tcstatus(env
, env
->current_tc
, newval
);
1129 void helper_mttc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1131 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1132 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1134 if (other_tc
== other
->current_tc
)
1135 other
->active_tc
.CP0_TCStatus
= arg1
;
1137 other
->tcs
[other_tc
].CP0_TCStatus
= arg1
;
1138 sync_c0_tcstatus(other
, other_tc
, arg1
);
1141 void helper_mtc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1143 uint32_t mask
= (1 << CP0TCBd_TBE
);
1146 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1147 mask
|= (1 << CP0TCBd_CurVPE
);
1148 newval
= (env
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1149 env
->active_tc
.CP0_TCBind
= newval
;
1152 void helper_mttc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1154 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1155 uint32_t mask
= (1 << CP0TCBd_TBE
);
1157 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1159 if (other
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1160 mask
|= (1 << CP0TCBd_CurVPE
);
1161 if (other_tc
== other
->current_tc
) {
1162 newval
= (other
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1163 other
->active_tc
.CP0_TCBind
= newval
;
1165 newval
= (other
->tcs
[other_tc
].CP0_TCBind
& ~mask
) | (arg1
& mask
);
1166 other
->tcs
[other_tc
].CP0_TCBind
= newval
;
1170 void helper_mtc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1172 env
->active_tc
.PC
= arg1
;
1173 env
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1175 /* MIPS16 not implemented. */
1178 void helper_mttc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1180 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1181 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1183 if (other_tc
== other
->current_tc
) {
1184 other
->active_tc
.PC
= arg1
;
1185 other
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1186 other
->lladdr
= 0ULL;
1187 /* MIPS16 not implemented. */
1189 other
->tcs
[other_tc
].PC
= arg1
;
1190 other
->tcs
[other_tc
].CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1191 other
->lladdr
= 0ULL;
1192 /* MIPS16 not implemented. */
1196 void helper_mtc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1198 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1200 env
->active_tc
.CP0_TCHalt
= arg1
& 0x1;
1202 // TODO: Halt TC / Restart (if allocated+active) TC.
1203 if (env
->active_tc
.CP0_TCHalt
& 1) {
1204 mips_tc_sleep(cpu
, env
->current_tc
);
1206 mips_tc_wake(cpu
, env
->current_tc
);
1210 void helper_mttc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1212 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1213 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1214 MIPSCPU
*other_cpu
= mips_env_get_cpu(other
);
1216 // TODO: Halt TC / Restart (if allocated+active) TC.
1218 if (other_tc
== other
->current_tc
)
1219 other
->active_tc
.CP0_TCHalt
= arg1
;
1221 other
->tcs
[other_tc
].CP0_TCHalt
= arg1
;
1224 mips_tc_sleep(other_cpu
, other_tc
);
1226 mips_tc_wake(other_cpu
, other_tc
);
1230 void helper_mtc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1232 env
->active_tc
.CP0_TCContext
= arg1
;
1235 void helper_mttc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1237 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1238 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1240 if (other_tc
== other
->current_tc
)
1241 other
->active_tc
.CP0_TCContext
= arg1
;
1243 other
->tcs
[other_tc
].CP0_TCContext
= arg1
;
1246 void helper_mtc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1248 env
->active_tc
.CP0_TCSchedule
= arg1
;
1251 void helper_mttc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1253 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1254 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1256 if (other_tc
== other
->current_tc
)
1257 other
->active_tc
.CP0_TCSchedule
= arg1
;
1259 other
->tcs
[other_tc
].CP0_TCSchedule
= arg1
;
1262 void helper_mtc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1264 env
->active_tc
.CP0_TCScheFBack
= arg1
;
1267 void helper_mttc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1269 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1270 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1272 if (other_tc
== other
->current_tc
)
1273 other
->active_tc
.CP0_TCScheFBack
= arg1
;
1275 other
->tcs
[other_tc
].CP0_TCScheFBack
= arg1
;
1278 void helper_mtc0_entrylo1(CPUMIPSState
*env
, target_ulong arg1
)
1280 /* 1k pages not implemented */
1281 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1282 env
->CP0_EntryLo1
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1283 | (rxi
<< (CP0EnLo_XI
- 30));
1286 #if defined(TARGET_MIPS64)
1287 void helper_dmtc0_entrylo1(CPUMIPSState
*env
, uint64_t arg1
)
1289 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1290 env
->CP0_EntryLo1
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1294 void helper_mtc0_context(CPUMIPSState
*env
, target_ulong arg1
)
1296 env
->CP0_Context
= (env
->CP0_Context
& 0x007FFFFF) | (arg1
& ~0x007FFFFF);
1299 void helper_mtc0_pagemask(CPUMIPSState
*env
, target_ulong arg1
)
1301 uint64_t mask
= arg1
>> (TARGET_PAGE_BITS
+ 1);
1302 if (!(env
->insn_flags
& ISA_MIPS32R6
) || (arg1
== ~0) ||
1303 (mask
== 0x0000 || mask
== 0x0003 || mask
== 0x000F ||
1304 mask
== 0x003F || mask
== 0x00FF || mask
== 0x03FF ||
1305 mask
== 0x0FFF || mask
== 0x3FFF || mask
== 0xFFFF)) {
1306 env
->CP0_PageMask
= arg1
& (0x1FFFFFFF & (TARGET_PAGE_MASK
<< 1));
1310 void helper_mtc0_pagegrain(CPUMIPSState
*env
, target_ulong arg1
)
1312 /* SmartMIPS not implemented */
1313 /* 1k pages not implemented */
1314 env
->CP0_PageGrain
= (arg1
& env
->CP0_PageGrain_rw_bitmask
) |
1315 (env
->CP0_PageGrain
& ~env
->CP0_PageGrain_rw_bitmask
);
1316 compute_hflags(env
);
1317 restore_pamask(env
);
1320 void helper_mtc0_wired(CPUMIPSState
*env
, target_ulong arg1
)
1322 if (env
->insn_flags
& ISA_MIPS32R6
) {
1323 if (arg1
< env
->tlb
->nb_tlb
) {
1324 env
->CP0_Wired
= arg1
;
1327 env
->CP0_Wired
= arg1
% env
->tlb
->nb_tlb
;
1331 void helper_mtc0_srsconf0(CPUMIPSState
*env
, target_ulong arg1
)
1333 env
->CP0_SRSConf0
|= arg1
& env
->CP0_SRSConf0_rw_bitmask
;
1336 void helper_mtc0_srsconf1(CPUMIPSState
*env
, target_ulong arg1
)
1338 env
->CP0_SRSConf1
|= arg1
& env
->CP0_SRSConf1_rw_bitmask
;
1341 void helper_mtc0_srsconf2(CPUMIPSState
*env
, target_ulong arg1
)
1343 env
->CP0_SRSConf2
|= arg1
& env
->CP0_SRSConf2_rw_bitmask
;
1346 void helper_mtc0_srsconf3(CPUMIPSState
*env
, target_ulong arg1
)
1348 env
->CP0_SRSConf3
|= arg1
& env
->CP0_SRSConf3_rw_bitmask
;
1351 void helper_mtc0_srsconf4(CPUMIPSState
*env
, target_ulong arg1
)
1353 env
->CP0_SRSConf4
|= arg1
& env
->CP0_SRSConf4_rw_bitmask
;
1356 void helper_mtc0_hwrena(CPUMIPSState
*env
, target_ulong arg1
)
1358 uint32_t mask
= 0x0000000F;
1360 if ((env
->CP0_Config1
& (1 << CP0C1_PC
)) &&
1361 (env
->insn_flags
& ISA_MIPS32R6
)) {
1364 if (env
->insn_flags
& ISA_MIPS32R6
) {
1367 if (env
->CP0_Config3
& (1 << CP0C3_ULRI
)) {
1370 if (arg1
& (1 << 29)) {
1371 env
->hflags
|= MIPS_HFLAG_HWRENA_ULR
;
1373 env
->hflags
&= ~MIPS_HFLAG_HWRENA_ULR
;
1377 env
->CP0_HWREna
= arg1
& mask
;
1380 void helper_mtc0_count(CPUMIPSState
*env
, target_ulong arg1
)
1382 cpu_mips_store_count(env
, arg1
);
1385 void helper_mtc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1387 target_ulong old
, val
, mask
;
1388 mask
= (TARGET_PAGE_MASK
<< 1) | 0xFF;
1389 if (((env
->CP0_Config4
>> CP0C4_IE
) & 0x3) >= 2) {
1390 mask
|= 1 << CP0EnHi_EHINV
;
1393 /* 1k pages not implemented */
1394 #if defined(TARGET_MIPS64)
1395 if (env
->insn_flags
& ISA_MIPS32R6
) {
1396 int entryhi_r
= extract64(arg1
, 62, 2);
1397 int config0_at
= extract32(env
->CP0_Config0
, 13, 2);
1398 bool no_supervisor
= (env
->CP0_Status_rw_bitmask
& 0x8) == 0;
1399 if ((entryhi_r
== 2) ||
1400 (entryhi_r
== 1 && (no_supervisor
|| config0_at
== 1))) {
1401 /* skip EntryHi.R field if new value is reserved */
1402 mask
&= ~(0x3ull
<< 62);
1405 mask
&= env
->SEGMask
;
1407 old
= env
->CP0_EntryHi
;
1408 val
= (arg1
& mask
) | (old
& ~mask
);
1409 env
->CP0_EntryHi
= val
;
1410 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
1411 sync_c0_entryhi(env
, env
->current_tc
);
1413 /* If the ASID changes, flush qemu's TLB. */
1414 if ((old
& 0xFF) != (val
& 0xFF))
1415 cpu_mips_tlb_flush(env
, 1);
1418 void helper_mttc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1420 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1421 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1423 other
->CP0_EntryHi
= arg1
;
1424 sync_c0_entryhi(other
, other_tc
);
1427 void helper_mtc0_compare(CPUMIPSState
*env
, target_ulong arg1
)
1429 cpu_mips_store_compare(env
, arg1
);
1432 void helper_mtc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1434 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1437 old
= env
->CP0_Status
;
1438 cpu_mips_store_status(env
, arg1
);
1439 val
= env
->CP0_Status
;
1441 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
1442 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1443 old
, old
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1444 val
, val
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1446 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
1447 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
1448 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
1449 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
1451 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
1457 void helper_mttc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1459 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1460 uint32_t mask
= env
->CP0_Status_rw_bitmask
& ~0xf1000018;
1461 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1463 other
->CP0_Status
= (other
->CP0_Status
& ~mask
) | (arg1
& mask
);
1464 sync_c0_status(env
, other
, other_tc
);
1467 void helper_mtc0_intctl(CPUMIPSState
*env
, target_ulong arg1
)
1469 env
->CP0_IntCtl
= (env
->CP0_IntCtl
& ~0x000003e0) | (arg1
& 0x000003e0);
1472 void helper_mtc0_srsctl(CPUMIPSState
*env
, target_ulong arg1
)
1474 uint32_t mask
= (0xf << CP0SRSCtl_ESS
) | (0xf << CP0SRSCtl_PSS
);
1475 env
->CP0_SRSCtl
= (env
->CP0_SRSCtl
& ~mask
) | (arg1
& mask
);
1478 void helper_mtc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1480 cpu_mips_store_cause(env
, arg1
);
1483 void helper_mttc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1485 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1486 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1488 cpu_mips_store_cause(other
, arg1
);
1491 target_ulong
helper_mftc0_epc(CPUMIPSState
*env
)
1493 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1494 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1496 return other
->CP0_EPC
;
1499 target_ulong
helper_mftc0_ebase(CPUMIPSState
*env
)
1501 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1502 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1504 return other
->CP0_EBase
;
1507 void helper_mtc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1509 env
->CP0_EBase
= (env
->CP0_EBase
& ~0x3FFFF000) | (arg1
& 0x3FFFF000);
1512 void helper_mttc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1514 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1515 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1516 other
->CP0_EBase
= (other
->CP0_EBase
& ~0x3FFFF000) | (arg1
& 0x3FFFF000);
1519 target_ulong
helper_mftc0_configx(CPUMIPSState
*env
, target_ulong idx
)
1521 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1522 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1525 case 0: return other
->CP0_Config0
;
1526 case 1: return other
->CP0_Config1
;
1527 case 2: return other
->CP0_Config2
;
1528 case 3: return other
->CP0_Config3
;
1529 /* 4 and 5 are reserved. */
1530 case 6: return other
->CP0_Config6
;
1531 case 7: return other
->CP0_Config7
;
1538 void helper_mtc0_config0(CPUMIPSState
*env
, target_ulong arg1
)
1540 env
->CP0_Config0
= (env
->CP0_Config0
& 0x81FFFFF8) | (arg1
& 0x00000007);
1543 void helper_mtc0_config2(CPUMIPSState
*env
, target_ulong arg1
)
1545 /* tertiary/secondary caches not implemented */
1546 env
->CP0_Config2
= (env
->CP0_Config2
& 0x8FFF0FFF);
1549 void helper_mtc0_config3(CPUMIPSState
*env
, target_ulong arg1
)
1551 if (env
->insn_flags
& ASE_MICROMIPS
) {
1552 env
->CP0_Config3
= (env
->CP0_Config3
& ~(1 << CP0C3_ISA_ON_EXC
)) |
1553 (arg1
& (1 << CP0C3_ISA_ON_EXC
));
1557 void helper_mtc0_config4(CPUMIPSState
*env
, target_ulong arg1
)
1559 env
->CP0_Config4
= (env
->CP0_Config4
& (~env
->CP0_Config4_rw_bitmask
)) |
1560 (arg1
& env
->CP0_Config4_rw_bitmask
);
1563 void helper_mtc0_config5(CPUMIPSState
*env
, target_ulong arg1
)
1565 env
->CP0_Config5
= (env
->CP0_Config5
& (~env
->CP0_Config5_rw_bitmask
)) |
1566 (arg1
& env
->CP0_Config5_rw_bitmask
);
1567 compute_hflags(env
);
1570 void helper_mtc0_lladdr(CPUMIPSState
*env
, target_ulong arg1
)
1572 target_long mask
= env
->CP0_LLAddr_rw_bitmask
;
1573 arg1
= arg1
<< env
->CP0_LLAddr_shift
;
1574 env
->lladdr
= (env
->lladdr
& ~mask
) | (arg1
& mask
);
1577 void helper_mtc0_watchlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1579 /* Watch exceptions for instructions, data loads, data stores
1581 env
->CP0_WatchLo
[sel
] = (arg1
& ~0x7);
1584 void helper_mtc0_watchhi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1586 env
->CP0_WatchHi
[sel
] = (arg1
& 0x40FF0FF8);
1587 env
->CP0_WatchHi
[sel
] &= ~(env
->CP0_WatchHi
[sel
] & arg1
& 0x7);
1590 void helper_mtc0_xcontext(CPUMIPSState
*env
, target_ulong arg1
)
1592 target_ulong mask
= (1ULL << (env
->SEGBITS
- 7)) - 1;
1593 env
->CP0_XContext
= (env
->CP0_XContext
& mask
) | (arg1
& ~mask
);
1596 void helper_mtc0_framemask(CPUMIPSState
*env
, target_ulong arg1
)
1598 env
->CP0_Framemask
= arg1
; /* XXX */
1601 void helper_mtc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1603 env
->CP0_Debug
= (env
->CP0_Debug
& 0x8C03FC1F) | (arg1
& 0x13300120);
1604 if (arg1
& (1 << CP0DB_DM
))
1605 env
->hflags
|= MIPS_HFLAG_DM
;
1607 env
->hflags
&= ~MIPS_HFLAG_DM
;
1610 void helper_mttc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1612 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1613 uint32_t val
= arg1
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
));
1614 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1616 /* XXX: Might be wrong, check with EJTAG spec. */
1617 if (other_tc
== other
->current_tc
)
1618 other
->active_tc
.CP0_Debug_tcstatus
= val
;
1620 other
->tcs
[other_tc
].CP0_Debug_tcstatus
= val
;
1621 other
->CP0_Debug
= (other
->CP0_Debug
&
1622 ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1623 (arg1
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1626 void helper_mtc0_performance0(CPUMIPSState
*env
, target_ulong arg1
)
1628 env
->CP0_Performance0
= arg1
& 0x000007ff;
1631 void helper_mtc0_taglo(CPUMIPSState
*env
, target_ulong arg1
)
1633 env
->CP0_TagLo
= arg1
& 0xFFFFFCF6;
1636 void helper_mtc0_datalo(CPUMIPSState
*env
, target_ulong arg1
)
1638 env
->CP0_DataLo
= arg1
; /* XXX */
1641 void helper_mtc0_taghi(CPUMIPSState
*env
, target_ulong arg1
)
1643 env
->CP0_TagHi
= arg1
; /* XXX */
1646 void helper_mtc0_datahi(CPUMIPSState
*env
, target_ulong arg1
)
1648 env
->CP0_DataHi
= arg1
; /* XXX */
1651 /* MIPS MT functions */
1652 target_ulong
helper_mftgpr(CPUMIPSState
*env
, uint32_t sel
)
1654 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1655 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1657 if (other_tc
== other
->current_tc
)
1658 return other
->active_tc
.gpr
[sel
];
1660 return other
->tcs
[other_tc
].gpr
[sel
];
1663 target_ulong
helper_mftlo(CPUMIPSState
*env
, uint32_t sel
)
1665 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1666 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1668 if (other_tc
== other
->current_tc
)
1669 return other
->active_tc
.LO
[sel
];
1671 return other
->tcs
[other_tc
].LO
[sel
];
1674 target_ulong
helper_mfthi(CPUMIPSState
*env
, uint32_t sel
)
1676 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1677 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1679 if (other_tc
== other
->current_tc
)
1680 return other
->active_tc
.HI
[sel
];
1682 return other
->tcs
[other_tc
].HI
[sel
];
1685 target_ulong
helper_mftacx(CPUMIPSState
*env
, uint32_t sel
)
1687 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1688 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1690 if (other_tc
== other
->current_tc
)
1691 return other
->active_tc
.ACX
[sel
];
1693 return other
->tcs
[other_tc
].ACX
[sel
];
1696 target_ulong
helper_mftdsp(CPUMIPSState
*env
)
1698 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1699 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1701 if (other_tc
== other
->current_tc
)
1702 return other
->active_tc
.DSPControl
;
1704 return other
->tcs
[other_tc
].DSPControl
;
1707 void helper_mttgpr(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1709 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1710 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1712 if (other_tc
== other
->current_tc
)
1713 other
->active_tc
.gpr
[sel
] = arg1
;
1715 other
->tcs
[other_tc
].gpr
[sel
] = arg1
;
1718 void helper_mttlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1720 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1721 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1723 if (other_tc
== other
->current_tc
)
1724 other
->active_tc
.LO
[sel
] = arg1
;
1726 other
->tcs
[other_tc
].LO
[sel
] = arg1
;
1729 void helper_mtthi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1731 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1732 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1734 if (other_tc
== other
->current_tc
)
1735 other
->active_tc
.HI
[sel
] = arg1
;
1737 other
->tcs
[other_tc
].HI
[sel
] = arg1
;
1740 void helper_mttacx(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1742 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1743 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1745 if (other_tc
== other
->current_tc
)
1746 other
->active_tc
.ACX
[sel
] = arg1
;
1748 other
->tcs
[other_tc
].ACX
[sel
] = arg1
;
1751 void helper_mttdsp(CPUMIPSState
*env
, target_ulong arg1
)
1753 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1754 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1756 if (other_tc
== other
->current_tc
)
1757 other
->active_tc
.DSPControl
= arg1
;
1759 other
->tcs
[other_tc
].DSPControl
= arg1
;
1762 /* MIPS MT functions */
1763 target_ulong
helper_dmt(void)
1769 target_ulong
helper_emt(void)
1775 target_ulong
helper_dvpe(CPUMIPSState
*env
)
1777 CPUState
*other_cs
= first_cpu
;
1778 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1780 CPU_FOREACH(other_cs
) {
1781 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1782 /* Turn off all VPEs except the one executing the dvpe. */
1783 if (&other_cpu
->env
!= env
) {
1784 other_cpu
->env
.mvp
->CP0_MVPControl
&= ~(1 << CP0MVPCo_EVP
);
1785 mips_vpe_sleep(other_cpu
);
1791 target_ulong
helper_evpe(CPUMIPSState
*env
)
1793 CPUState
*other_cs
= first_cpu
;
1794 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1796 CPU_FOREACH(other_cs
) {
1797 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1799 if (&other_cpu
->env
!= env
1800 /* If the VPE is WFI, don't disturb its sleep. */
1801 && !mips_vpe_is_wfi(other_cpu
)) {
1802 /* Enable the VPE. */
1803 other_cpu
->env
.mvp
->CP0_MVPControl
|= (1 << CP0MVPCo_EVP
);
1804 mips_vpe_wake(other_cpu
); /* And wake it up. */
1809 #endif /* !CONFIG_USER_ONLY */
1811 void helper_fork(target_ulong arg1
, target_ulong arg2
)
1813 // arg1 = rt, arg2 = rs
1814 // TODO: store to TC register
1817 target_ulong
helper_yield(CPUMIPSState
*env
, target_ulong arg
)
1819 target_long arg1
= arg
;
1822 /* No scheduling policy implemented. */
1824 if (env
->CP0_VPEControl
& (1 << CP0VPECo_YSI
) &&
1825 env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_DT
)) {
1826 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1827 env
->CP0_VPEControl
|= 4 << CP0VPECo_EXCPT
;
1828 do_raise_exception(env
, EXCP_THREAD
, GETPC());
1831 } else if (arg1
== 0) {
1832 if (0 /* TODO: TC underflow */) {
1833 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1834 do_raise_exception(env
, EXCP_THREAD
, GETPC());
1836 // TODO: Deallocate TC
1838 } else if (arg1
> 0) {
1839 /* Yield qualifier inputs not implemented. */
1840 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1841 env
->CP0_VPEControl
|= 2 << CP0VPECo_EXCPT
;
1842 do_raise_exception(env
, EXCP_THREAD
, GETPC());
1844 return env
->CP0_YQMask
;
1847 #ifndef CONFIG_USER_ONLY
1848 /* TLB management */
1849 static void cpu_mips_tlb_flush (CPUMIPSState
*env
, int flush_global
)
1851 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1853 /* Flush qemu's TLB and discard all shadowed entries. */
1854 tlb_flush(CPU(cpu
), flush_global
);
1855 env
->tlb
->tlb_in_use
= env
->tlb
->nb_tlb
;
1858 static void r4k_mips_tlb_flush_extra (CPUMIPSState
*env
, int first
)
1860 /* Discard entries from env->tlb[first] onwards. */
1861 while (env
->tlb
->tlb_in_use
> first
) {
1862 r4k_invalidate_tlb(env
, --env
->tlb
->tlb_in_use
, 0);
1866 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo
)
1868 #if defined(TARGET_MIPS64)
1869 return extract64(entrylo
, 6, 54);
1871 return extract64(entrylo
, 6, 24) | /* PFN */
1872 (extract64(entrylo
, 32, 32) << 24); /* PFNX */
1876 static void r4k_fill_tlb(CPUMIPSState
*env
, int idx
)
1880 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1881 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1882 if (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) {
1887 tlb
->VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
1888 #if defined(TARGET_MIPS64)
1889 tlb
->VPN
&= env
->SEGMask
;
1891 tlb
->ASID
= env
->CP0_EntryHi
& 0xFF;
1892 tlb
->PageMask
= env
->CP0_PageMask
;
1893 tlb
->G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
1894 tlb
->V0
= (env
->CP0_EntryLo0
& 2) != 0;
1895 tlb
->D0
= (env
->CP0_EntryLo0
& 4) != 0;
1896 tlb
->C0
= (env
->CP0_EntryLo0
>> 3) & 0x7;
1897 tlb
->XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) & 1;
1898 tlb
->RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) & 1;
1899 tlb
->PFN
[0] = get_tlb_pfn_from_entrylo(env
->CP0_EntryLo0
) << 12;
1900 tlb
->V1
= (env
->CP0_EntryLo1
& 2) != 0;
1901 tlb
->D1
= (env
->CP0_EntryLo1
& 4) != 0;
1902 tlb
->C1
= (env
->CP0_EntryLo1
>> 3) & 0x7;
1903 tlb
->XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) & 1;
1904 tlb
->RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) & 1;
1905 tlb
->PFN
[1] = get_tlb_pfn_from_entrylo(env
->CP0_EntryLo1
) << 12;
1908 void r4k_helper_tlbinv(CPUMIPSState
*env
)
1912 uint8_t ASID
= env
->CP0_EntryHi
& 0xFF;
1914 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
1915 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1916 if (!tlb
->G
&& tlb
->ASID
== ASID
) {
1920 cpu_mips_tlb_flush(env
, 1);
1923 void r4k_helper_tlbinvf(CPUMIPSState
*env
)
1927 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
1928 env
->tlb
->mmu
.r4k
.tlb
[idx
].EHINV
= 1;
1930 cpu_mips_tlb_flush(env
, 1);
1933 void r4k_helper_tlbwi(CPUMIPSState
*env
)
1939 bool G
, V0
, D0
, V1
, D1
;
1941 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
1942 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1943 VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
1944 #if defined(TARGET_MIPS64)
1945 VPN
&= env
->SEGMask
;
1947 ASID
= env
->CP0_EntryHi
& 0xff;
1948 G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
1949 V0
= (env
->CP0_EntryLo0
& 2) != 0;
1950 D0
= (env
->CP0_EntryLo0
& 4) != 0;
1951 V1
= (env
->CP0_EntryLo1
& 2) != 0;
1952 D1
= (env
->CP0_EntryLo1
& 4) != 0;
1954 /* Discard cached TLB entries, unless tlbwi is just upgrading access
1955 permissions on the current entry. */
1956 if (tlb
->VPN
!= VPN
|| tlb
->ASID
!= ASID
|| tlb
->G
!= G
||
1957 (tlb
->V0
&& !V0
) || (tlb
->D0
&& !D0
) ||
1958 (tlb
->V1
&& !V1
) || (tlb
->D1
&& !D1
)) {
1959 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
1962 r4k_invalidate_tlb(env
, idx
, 0);
1963 r4k_fill_tlb(env
, idx
);
1966 void r4k_helper_tlbwr(CPUMIPSState
*env
)
1968 int r
= cpu_mips_get_random(env
);
1970 r4k_invalidate_tlb(env
, r
, 1);
1971 r4k_fill_tlb(env
, r
);
1974 void r4k_helper_tlbp(CPUMIPSState
*env
)
1983 ASID
= env
->CP0_EntryHi
& 0xFF;
1984 for (i
= 0; i
< env
->tlb
->nb_tlb
; i
++) {
1985 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
1986 /* 1k pages are not supported. */
1987 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
1988 tag
= env
->CP0_EntryHi
& ~mask
;
1989 VPN
= tlb
->VPN
& ~mask
;
1990 #if defined(TARGET_MIPS64)
1991 tag
&= env
->SEGMask
;
1993 /* Check ASID, virtual page number & size */
1994 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
&& !tlb
->EHINV
) {
2000 if (i
== env
->tlb
->nb_tlb
) {
2001 /* No match. Discard any shadow entries, if any of them match. */
2002 for (i
= env
->tlb
->nb_tlb
; i
< env
->tlb
->tlb_in_use
; i
++) {
2003 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
2004 /* 1k pages are not supported. */
2005 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
2006 tag
= env
->CP0_EntryHi
& ~mask
;
2007 VPN
= tlb
->VPN
& ~mask
;
2008 #if defined(TARGET_MIPS64)
2009 tag
&= env
->SEGMask
;
2011 /* Check ASID, virtual page number & size */
2012 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
2013 r4k_mips_tlb_flush_extra (env
, i
);
2018 env
->CP0_Index
|= 0x80000000;
2022 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn
)
2024 #if defined(TARGET_MIPS64)
2025 return tlb_pfn
<< 6;
2027 return (extract64(tlb_pfn
, 0, 24) << 6) | /* PFN */
2028 (extract64(tlb_pfn
, 24, 32) << 32); /* PFNX */
2032 void r4k_helper_tlbr(CPUMIPSState
*env
)
2038 ASID
= env
->CP0_EntryHi
& 0xFF;
2039 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
2040 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2042 /* If this will change the current ASID, flush qemu's TLB. */
2043 if (ASID
!= tlb
->ASID
)
2044 cpu_mips_tlb_flush (env
, 1);
2046 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
2049 env
->CP0_EntryHi
= 1 << CP0EnHi_EHINV
;
2050 env
->CP0_PageMask
= 0;
2051 env
->CP0_EntryLo0
= 0;
2052 env
->CP0_EntryLo1
= 0;
2054 env
->CP0_EntryHi
= tlb
->VPN
| tlb
->ASID
;
2055 env
->CP0_PageMask
= tlb
->PageMask
;
2056 env
->CP0_EntryLo0
= tlb
->G
| (tlb
->V0
<< 1) | (tlb
->D0
<< 2) |
2057 ((uint64_t)tlb
->RI0
<< CP0EnLo_RI
) |
2058 ((uint64_t)tlb
->XI0
<< CP0EnLo_XI
) | (tlb
->C0
<< 3) |
2059 get_entrylo_pfn_from_tlb(tlb
->PFN
[0] >> 12);
2060 env
->CP0_EntryLo1
= tlb
->G
| (tlb
->V1
<< 1) | (tlb
->D1
<< 2) |
2061 ((uint64_t)tlb
->RI1
<< CP0EnLo_RI
) |
2062 ((uint64_t)tlb
->XI1
<< CP0EnLo_XI
) | (tlb
->C1
<< 3) |
2063 get_entrylo_pfn_from_tlb(tlb
->PFN
[1] >> 12);
2067 void helper_tlbwi(CPUMIPSState
*env
)
2069 env
->tlb
->helper_tlbwi(env
);
2072 void helper_tlbwr(CPUMIPSState
*env
)
2074 env
->tlb
->helper_tlbwr(env
);
2077 void helper_tlbp(CPUMIPSState
*env
)
2079 env
->tlb
->helper_tlbp(env
);
2082 void helper_tlbr(CPUMIPSState
*env
)
2084 env
->tlb
->helper_tlbr(env
);
2087 void helper_tlbinv(CPUMIPSState
*env
)
2089 env
->tlb
->helper_tlbinv(env
);
2092 void helper_tlbinvf(CPUMIPSState
*env
)
2094 env
->tlb
->helper_tlbinvf(env
);
2098 target_ulong
helper_di(CPUMIPSState
*env
)
2100 target_ulong t0
= env
->CP0_Status
;
2102 env
->CP0_Status
= t0
& ~(1 << CP0St_IE
);
2106 target_ulong
helper_ei(CPUMIPSState
*env
)
2108 target_ulong t0
= env
->CP0_Status
;
2110 env
->CP0_Status
= t0
| (1 << CP0St_IE
);
2114 static void debug_pre_eret(CPUMIPSState
*env
)
2116 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2117 qemu_log("ERET: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2118 env
->active_tc
.PC
, env
->CP0_EPC
);
2119 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2120 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2121 if (env
->hflags
& MIPS_HFLAG_DM
)
2122 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2127 static void debug_post_eret(CPUMIPSState
*env
)
2129 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
2131 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2132 qemu_log(" => PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2133 env
->active_tc
.PC
, env
->CP0_EPC
);
2134 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2135 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2136 if (env
->hflags
& MIPS_HFLAG_DM
)
2137 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2138 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
2139 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
2140 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
2141 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
2143 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
2149 static void set_pc(CPUMIPSState
*env
, target_ulong error_pc
)
2151 env
->active_tc
.PC
= error_pc
& ~(target_ulong
)1;
2153 env
->hflags
|= MIPS_HFLAG_M16
;
2155 env
->hflags
&= ~(MIPS_HFLAG_M16
);
2159 static inline void exception_return(CPUMIPSState
*env
)
2161 debug_pre_eret(env
);
2162 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
2163 set_pc(env
, env
->CP0_ErrorEPC
);
2164 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
2166 set_pc(env
, env
->CP0_EPC
);
2167 env
->CP0_Status
&= ~(1 << CP0St_EXL
);
2169 compute_hflags(env
);
2170 debug_post_eret(env
);
2173 void helper_eret(CPUMIPSState
*env
)
2175 exception_return(env
);
2179 void helper_eretnc(CPUMIPSState
*env
)
2181 exception_return(env
);
2184 void helper_deret(CPUMIPSState
*env
)
2186 debug_pre_eret(env
);
2187 set_pc(env
, env
->CP0_DEPC
);
2189 env
->hflags
&= ~MIPS_HFLAG_DM
;
2190 compute_hflags(env
);
2191 debug_post_eret(env
);
2193 #endif /* !CONFIG_USER_ONLY */
2195 static inline void check_hwrena(CPUMIPSState
*env
, int reg
)
2197 if ((env
->hflags
& MIPS_HFLAG_CP0
) || (env
->CP0_HWREna
& (1 << reg
))) {
2200 do_raise_exception(env
, EXCP_RI
, GETPC());
2203 target_ulong
helper_rdhwr_cpunum(CPUMIPSState
*env
)
2205 check_hwrena(env
, 0);
2206 return env
->CP0_EBase
& 0x3ff;
2209 target_ulong
helper_rdhwr_synci_step(CPUMIPSState
*env
)
2211 check_hwrena(env
, 1);
2212 return env
->SYNCI_Step
;
2215 target_ulong
helper_rdhwr_cc(CPUMIPSState
*env
)
2217 check_hwrena(env
, 2);
2218 #ifdef CONFIG_USER_ONLY
2219 return env
->CP0_Count
;
2221 return (int32_t)cpu_mips_get_count(env
);
2225 target_ulong
helper_rdhwr_ccres(CPUMIPSState
*env
)
2227 check_hwrena(env
, 3);
2231 target_ulong
helper_rdhwr_performance(CPUMIPSState
*env
)
2233 check_hwrena(env
, 4);
2234 return env
->CP0_Performance0
;
2237 target_ulong
helper_rdhwr_xnp(CPUMIPSState
*env
)
2239 check_hwrena(env
, 5);
2240 return (env
->CP0_Config5
>> CP0C5_XNP
) & 1;
2243 void helper_pmon(CPUMIPSState
*env
, int function
)
2247 case 2: /* TODO: char inbyte(int waitflag); */
2248 if (env
->active_tc
.gpr
[4] == 0)
2249 env
->active_tc
.gpr
[2] = -1;
2251 case 11: /* TODO: char inbyte (void); */
2252 env
->active_tc
.gpr
[2] = -1;
2256 printf("%c", (char)(env
->active_tc
.gpr
[4] & 0xFF));
2262 unsigned char *fmt
= (void *)(uintptr_t)env
->active_tc
.gpr
[4];
2269 void helper_wait(CPUMIPSState
*env
)
2271 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
2274 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
2275 /* Last instruction in the block, PC was updated before
2276 - no need to recover PC and icount */
2277 raise_exception(env
, EXCP_HLT
);
2280 #if !defined(CONFIG_USER_ONLY)
2282 void mips_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
2283 int access_type
, int is_user
,
2286 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2287 CPUMIPSState
*env
= &cpu
->env
;
2291 env
->CP0_BadVAddr
= addr
;
2293 if (access_type
== MMU_DATA_STORE
) {
2297 if (access_type
== MMU_INST_FETCH
) {
2298 error_code
|= EXCP_INST_NOTAVAIL
;
2302 do_raise_exception_err(env
, excp
, error_code
, retaddr
);
2305 void tlb_fill(CPUState
*cs
, target_ulong addr
, int is_write
, int mmu_idx
,
2310 ret
= mips_cpu_handle_mmu_fault(cs
, addr
, is_write
, mmu_idx
);
2312 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2313 CPUMIPSState
*env
= &cpu
->env
;
2315 do_raise_exception_err(env
, cs
->exception_index
,
2316 env
->error_code
, retaddr
);
2320 void mips_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2321 bool is_write
, bool is_exec
, int unused
,
2324 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2325 CPUMIPSState
*env
= &cpu
->env
;
2328 * Raising an exception with KVM enabled will crash because it won't be from
2329 * the main execution loop so the longjmp won't have a matching setjmp.
2330 * Until we can trigger a bus error exception through KVM lets just ignore
2333 if (kvm_enabled()) {
2338 raise_exception(env
, EXCP_IBE
);
2340 raise_exception(env
, EXCP_DBE
);
2343 #endif /* !CONFIG_USER_ONLY */
2345 /* Complex FPU operations which may need stack space. */
2347 #define FLOAT_TWO32 make_float32(1 << 30)
2348 #define FLOAT_TWO64 make_float64(1ULL << 62)
2349 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2350 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2352 /* convert MIPS rounding mode in FCR31 to IEEE library */
2353 unsigned int ieee_rm
[] = {
2354 float_round_nearest_even
,
2355 float_round_to_zero
,
2360 target_ulong
helper_cfc1(CPUMIPSState
*env
, uint32_t reg
)
2362 target_ulong arg1
= 0;
2366 arg1
= (int32_t)env
->active_fpu
.fcr0
;
2369 /* UFR Support - Read Status FR */
2370 if (env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) {
2371 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2373 ((env
->CP0_Status
& (1 << CP0St_FR
)) >> CP0St_FR
);
2375 do_raise_exception(env
, EXCP_RI
, GETPC());
2380 /* FRE Support - read Config5.FRE bit */
2381 if (env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) {
2382 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2383 arg1
= (env
->CP0_Config5
>> CP0C5_FRE
) & 1;
2385 helper_raise_exception(env
, EXCP_RI
);
2390 arg1
= ((env
->active_fpu
.fcr31
>> 24) & 0xfe) | ((env
->active_fpu
.fcr31
>> 23) & 0x1);
2393 arg1
= env
->active_fpu
.fcr31
& 0x0003f07c;
2396 arg1
= (env
->active_fpu
.fcr31
& 0x00000f83) | ((env
->active_fpu
.fcr31
>> 22) & 0x4);
2399 arg1
= (int32_t)env
->active_fpu
.fcr31
;
2406 void helper_ctc1(CPUMIPSState
*env
, target_ulong arg1
, uint32_t fs
, uint32_t rt
)
2410 /* UFR Alias - Reset Status FR */
2411 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2414 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2415 env
->CP0_Status
&= ~(1 << CP0St_FR
);
2416 compute_hflags(env
);
2418 do_raise_exception(env
, EXCP_RI
, GETPC());
2422 /* UNFR Alias - Set Status FR */
2423 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2426 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2427 env
->CP0_Status
|= (1 << CP0St_FR
);
2428 compute_hflags(env
);
2430 do_raise_exception(env
, EXCP_RI
, GETPC());
2434 /* FRE Support - clear Config5.FRE bit */
2435 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2438 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2439 env
->CP0_Config5
&= ~(1 << CP0C5_FRE
);
2440 compute_hflags(env
);
2442 helper_raise_exception(env
, EXCP_RI
);
2446 /* FRE Support - set Config5.FRE bit */
2447 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2450 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2451 env
->CP0_Config5
|= (1 << CP0C5_FRE
);
2452 compute_hflags(env
);
2454 helper_raise_exception(env
, EXCP_RI
);
2458 if ((env
->insn_flags
& ISA_MIPS32R6
) || (arg1
& 0xffffff00)) {
2461 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0x017fffff) | ((arg1
& 0xfe) << 24) |
2462 ((arg1
& 0x1) << 23);
2465 if (arg1
& 0x007c0000)
2467 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfffc0f83) | (arg1
& 0x0003f07c);
2470 if (arg1
& 0x007c0000)
2472 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfefff07c) | (arg1
& 0x00000f83) |
2473 ((arg1
& 0x4) << 22);
2476 if (env
->insn_flags
& ISA_MIPS32R6
) {
2477 uint32_t mask
= 0xfefc0000;
2478 env
->active_fpu
.fcr31
= (arg1
& ~mask
) |
2479 (env
->active_fpu
.fcr31
& mask
);
2480 } else if (!(arg1
& 0x007c0000)) {
2481 env
->active_fpu
.fcr31
= arg1
;
2487 /* set rounding mode */
2488 restore_rounding_mode(env
);
2489 /* set flush-to-zero mode */
2490 restore_flush_mode(env
);
2491 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2492 if ((GET_FP_ENABLE(env
->active_fpu
.fcr31
) | 0x20) & GET_FP_CAUSE(env
->active_fpu
.fcr31
))
2493 do_raise_exception(env
, EXCP_FPE
, GETPC());
2496 int ieee_ex_to_mips(int xcpt
)
2500 if (xcpt
& float_flag_invalid
) {
2503 if (xcpt
& float_flag_overflow
) {
2506 if (xcpt
& float_flag_underflow
) {
2507 ret
|= FP_UNDERFLOW
;
2509 if (xcpt
& float_flag_divbyzero
) {
2512 if (xcpt
& float_flag_inexact
) {
2519 static inline void update_fcr31(CPUMIPSState
*env
, uintptr_t pc
)
2521 int tmp
= ieee_ex_to_mips(get_float_exception_flags(&env
->active_fpu
.fp_status
));
2523 SET_FP_CAUSE(env
->active_fpu
.fcr31
, tmp
);
2526 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2528 if (GET_FP_ENABLE(env
->active_fpu
.fcr31
) & tmp
) {
2529 do_raise_exception(env
, EXCP_FPE
, pc
);
2531 UPDATE_FP_FLAGS(env
->active_fpu
.fcr31
, tmp
);
2537 Single precition routines have a "s" suffix, double precision a
2538 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2539 paired single lower "pl", paired single upper "pu". */
2541 /* unary operations, modifying fp status */
2542 uint64_t helper_float_sqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
2544 fdt0
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2545 update_fcr31(env
, GETPC());
2549 uint32_t helper_float_sqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
2551 fst0
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2552 update_fcr31(env
, GETPC());
2556 uint64_t helper_float_cvtd_s(CPUMIPSState
*env
, uint32_t fst0
)
2560 fdt2
= float32_to_float64(fst0
, &env
->active_fpu
.fp_status
);
2561 update_fcr31(env
, GETPC());
2565 uint64_t helper_float_cvtd_w(CPUMIPSState
*env
, uint32_t wt0
)
2569 fdt2
= int32_to_float64(wt0
, &env
->active_fpu
.fp_status
);
2570 update_fcr31(env
, GETPC());
2574 uint64_t helper_float_cvtd_l(CPUMIPSState
*env
, uint64_t dt0
)
2578 fdt2
= int64_to_float64(dt0
, &env
->active_fpu
.fp_status
);
2579 update_fcr31(env
, GETPC());
2583 uint64_t helper_float_cvtl_d(CPUMIPSState
*env
, uint64_t fdt0
)
2587 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2588 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2589 & (float_flag_invalid
| float_flag_overflow
)) {
2590 dt2
= FP_TO_INT64_OVERFLOW
;
2592 update_fcr31(env
, GETPC());
2596 uint64_t helper_float_cvtl_s(CPUMIPSState
*env
, uint32_t fst0
)
2600 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2601 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2602 & (float_flag_invalid
| float_flag_overflow
)) {
2603 dt2
= FP_TO_INT64_OVERFLOW
;
2605 update_fcr31(env
, GETPC());
2609 uint64_t helper_float_cvtps_pw(CPUMIPSState
*env
, uint64_t dt0
)
2614 fst2
= int32_to_float32(dt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2615 fsth2
= int32_to_float32(dt0
>> 32, &env
->active_fpu
.fp_status
);
2616 update_fcr31(env
, GETPC());
2617 return ((uint64_t)fsth2
<< 32) | fst2
;
2620 uint64_t helper_float_cvtpw_ps(CPUMIPSState
*env
, uint64_t fdt0
)
2626 wt2
= float32_to_int32(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2627 excp
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2628 if (excp
& (float_flag_overflow
| float_flag_invalid
)) {
2629 wt2
= FP_TO_INT32_OVERFLOW
;
2632 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2633 wth2
= float32_to_int32(fdt0
>> 32, &env
->active_fpu
.fp_status
);
2634 excph
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2635 if (excph
& (float_flag_overflow
| float_flag_invalid
)) {
2636 wth2
= FP_TO_INT32_OVERFLOW
;
2639 set_float_exception_flags(excp
| excph
, &env
->active_fpu
.fp_status
);
2640 update_fcr31(env
, GETPC());
2642 return ((uint64_t)wth2
<< 32) | wt2
;
2645 uint32_t helper_float_cvts_d(CPUMIPSState
*env
, uint64_t fdt0
)
2649 fst2
= float64_to_float32(fdt0
, &env
->active_fpu
.fp_status
);
2650 update_fcr31(env
, GETPC());
2654 uint32_t helper_float_cvts_w(CPUMIPSState
*env
, uint32_t wt0
)
2658 fst2
= int32_to_float32(wt0
, &env
->active_fpu
.fp_status
);
2659 update_fcr31(env
, GETPC());
2663 uint32_t helper_float_cvts_l(CPUMIPSState
*env
, uint64_t dt0
)
2667 fst2
= int64_to_float32(dt0
, &env
->active_fpu
.fp_status
);
2668 update_fcr31(env
, GETPC());
2672 uint32_t helper_float_cvts_pl(CPUMIPSState
*env
, uint32_t wt0
)
2677 update_fcr31(env
, GETPC());
2681 uint32_t helper_float_cvts_pu(CPUMIPSState
*env
, uint32_t wth0
)
2686 update_fcr31(env
, GETPC());
2690 uint32_t helper_float_cvtw_s(CPUMIPSState
*env
, uint32_t fst0
)
2694 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2695 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2696 & (float_flag_invalid
| float_flag_overflow
)) {
2697 wt2
= FP_TO_INT32_OVERFLOW
;
2699 update_fcr31(env
, GETPC());
2703 uint32_t helper_float_cvtw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2707 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2708 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2709 & (float_flag_invalid
| float_flag_overflow
)) {
2710 wt2
= FP_TO_INT32_OVERFLOW
;
2712 update_fcr31(env
, GETPC());
2716 uint64_t helper_float_roundl_d(CPUMIPSState
*env
, uint64_t fdt0
)
2720 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2721 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2722 restore_rounding_mode(env
);
2723 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2724 & (float_flag_invalid
| float_flag_overflow
)) {
2725 dt2
= FP_TO_INT64_OVERFLOW
;
2727 update_fcr31(env
, GETPC());
2731 uint64_t helper_float_roundl_s(CPUMIPSState
*env
, uint32_t fst0
)
2735 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2736 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2737 restore_rounding_mode(env
);
2738 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2739 & (float_flag_invalid
| float_flag_overflow
)) {
2740 dt2
= FP_TO_INT64_OVERFLOW
;
2742 update_fcr31(env
, GETPC());
2746 uint32_t helper_float_roundw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2750 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2751 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2752 restore_rounding_mode(env
);
2753 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2754 & (float_flag_invalid
| float_flag_overflow
)) {
2755 wt2
= FP_TO_INT32_OVERFLOW
;
2757 update_fcr31(env
, GETPC());
2761 uint32_t helper_float_roundw_s(CPUMIPSState
*env
, uint32_t fst0
)
2765 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2766 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2767 restore_rounding_mode(env
);
2768 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2769 & (float_flag_invalid
| float_flag_overflow
)) {
2770 wt2
= FP_TO_INT32_OVERFLOW
;
2772 update_fcr31(env
, GETPC());
2776 uint64_t helper_float_truncl_d(CPUMIPSState
*env
, uint64_t fdt0
)
2780 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2781 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2782 & (float_flag_invalid
| float_flag_overflow
)) {
2783 dt2
= FP_TO_INT64_OVERFLOW
;
2785 update_fcr31(env
, GETPC());
2789 uint64_t helper_float_truncl_s(CPUMIPSState
*env
, uint32_t fst0
)
2793 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2794 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2795 & (float_flag_invalid
| float_flag_overflow
)) {
2796 dt2
= FP_TO_INT64_OVERFLOW
;
2798 update_fcr31(env
, GETPC());
2802 uint32_t helper_float_truncw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2806 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2807 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2808 & (float_flag_invalid
| float_flag_overflow
)) {
2809 wt2
= FP_TO_INT32_OVERFLOW
;
2811 update_fcr31(env
, GETPC());
2815 uint32_t helper_float_truncw_s(CPUMIPSState
*env
, uint32_t fst0
)
2819 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2820 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2821 & (float_flag_invalid
| float_flag_overflow
)) {
2822 wt2
= FP_TO_INT32_OVERFLOW
;
2824 update_fcr31(env
, GETPC());
2828 uint64_t helper_float_ceill_d(CPUMIPSState
*env
, uint64_t fdt0
)
2832 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2833 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2834 restore_rounding_mode(env
);
2835 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2836 & (float_flag_invalid
| float_flag_overflow
)) {
2837 dt2
= FP_TO_INT64_OVERFLOW
;
2839 update_fcr31(env
, GETPC());
2843 uint64_t helper_float_ceill_s(CPUMIPSState
*env
, uint32_t fst0
)
2847 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2848 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2849 restore_rounding_mode(env
);
2850 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2851 & (float_flag_invalid
| float_flag_overflow
)) {
2852 dt2
= FP_TO_INT64_OVERFLOW
;
2854 update_fcr31(env
, GETPC());
2858 uint32_t helper_float_ceilw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2862 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2863 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2864 restore_rounding_mode(env
);
2865 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2866 & (float_flag_invalid
| float_flag_overflow
)) {
2867 wt2
= FP_TO_INT32_OVERFLOW
;
2869 update_fcr31(env
, GETPC());
2873 uint32_t helper_float_ceilw_s(CPUMIPSState
*env
, uint32_t fst0
)
2877 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2878 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2879 restore_rounding_mode(env
);
2880 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2881 & (float_flag_invalid
| float_flag_overflow
)) {
2882 wt2
= FP_TO_INT32_OVERFLOW
;
2884 update_fcr31(env
, GETPC());
2888 uint64_t helper_float_floorl_d(CPUMIPSState
*env
, uint64_t fdt0
)
2892 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2893 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2894 restore_rounding_mode(env
);
2895 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2896 & (float_flag_invalid
| float_flag_overflow
)) {
2897 dt2
= FP_TO_INT64_OVERFLOW
;
2899 update_fcr31(env
, GETPC());
2903 uint64_t helper_float_floorl_s(CPUMIPSState
*env
, uint32_t fst0
)
2907 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2908 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2909 restore_rounding_mode(env
);
2910 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2911 & (float_flag_invalid
| float_flag_overflow
)) {
2912 dt2
= FP_TO_INT64_OVERFLOW
;
2914 update_fcr31(env
, GETPC());
2918 uint32_t helper_float_floorw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2922 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2923 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2924 restore_rounding_mode(env
);
2925 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2926 & (float_flag_invalid
| float_flag_overflow
)) {
2927 wt2
= FP_TO_INT32_OVERFLOW
;
2929 update_fcr31(env
, GETPC());
2933 uint32_t helper_float_floorw_s(CPUMIPSState
*env
, uint32_t fst0
)
2937 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2938 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2939 restore_rounding_mode(env
);
2940 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2941 & (float_flag_invalid
| float_flag_overflow
)) {
2942 wt2
= FP_TO_INT32_OVERFLOW
;
2944 update_fcr31(env
, GETPC());
2948 /* unary operations, not modifying fp status */
2949 #define FLOAT_UNOP(name) \
2950 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
2952 return float64_ ## name(fdt0); \
2954 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
2956 return float32_ ## name(fst0); \
2958 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
2963 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2964 wth0 = float32_ ## name(fdt0 >> 32); \
2965 return ((uint64_t)wth0 << 32) | wt0; \
2971 /* MIPS specific unary operations */
2972 uint64_t helper_float_recip_d(CPUMIPSState
*env
, uint64_t fdt0
)
2976 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
2977 update_fcr31(env
, GETPC());
2981 uint32_t helper_float_recip_s(CPUMIPSState
*env
, uint32_t fst0
)
2985 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
2986 update_fcr31(env
, GETPC());
2990 uint64_t helper_float_rsqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
2994 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2995 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
2996 update_fcr31(env
, GETPC());
3000 uint32_t helper_float_rsqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
3004 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
3005 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3006 update_fcr31(env
, GETPC());
3010 uint64_t helper_float_recip1_d(CPUMIPSState
*env
, uint64_t fdt0
)
3014 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
3015 update_fcr31(env
, GETPC());
3019 uint32_t helper_float_recip1_s(CPUMIPSState
*env
, uint32_t fst0
)
3023 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
3024 update_fcr31(env
, GETPC());
3028 uint64_t helper_float_recip1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3033 fst2
= float32_div(float32_one
, fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3034 fsth2
= float32_div(float32_one
, fdt0
>> 32, &env
->active_fpu
.fp_status
);
3035 update_fcr31(env
, GETPC());
3036 return ((uint64_t)fsth2
<< 32) | fst2
;
3039 uint64_t helper_float_rsqrt1_d(CPUMIPSState
*env
, uint64_t fdt0
)
3043 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
3044 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
3045 update_fcr31(env
, GETPC());
3049 uint32_t helper_float_rsqrt1_s(CPUMIPSState
*env
, uint32_t fst0
)
3053 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
3054 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3055 update_fcr31(env
, GETPC());
3059 uint64_t helper_float_rsqrt1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3064 fst2
= float32_sqrt(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3065 fsth2
= float32_sqrt(fdt0
>> 32, &env
->active_fpu
.fp_status
);
3066 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3067 fsth2
= float32_div(float32_one
, fsth2
, &env
->active_fpu
.fp_status
);
3068 update_fcr31(env
, GETPC());
3069 return ((uint64_t)fsth2
<< 32) | fst2
;
3072 #define FLOAT_RINT(name, bits) \
3073 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3074 uint ## bits ## _t fs) \
3076 uint ## bits ## _t fdret; \
3078 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3079 update_fcr31(env, GETPC()); \
3083 FLOAT_RINT(rint_s
, 32)
3084 FLOAT_RINT(rint_d
, 64)
3087 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3088 #define FLOAT_CLASS_QUIET_NAN 0x002
3089 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3090 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3091 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3092 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3093 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3094 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3095 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3096 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3098 #define FLOAT_CLASS(name, bits) \
3099 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg) \
3101 if (float ## bits ## _is_signaling_nan(arg)) { \
3102 return FLOAT_CLASS_SIGNALING_NAN; \
3103 } else if (float ## bits ## _is_quiet_nan(arg)) { \
3104 return FLOAT_CLASS_QUIET_NAN; \
3105 } else if (float ## bits ## _is_neg(arg)) { \
3106 if (float ## bits ## _is_infinity(arg)) { \
3107 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3108 } else if (float ## bits ## _is_zero(arg)) { \
3109 return FLOAT_CLASS_NEGATIVE_ZERO; \
3110 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3111 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3113 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3116 if (float ## bits ## _is_infinity(arg)) { \
3117 return FLOAT_CLASS_POSITIVE_INFINITY; \
3118 } else if (float ## bits ## _is_zero(arg)) { \
3119 return FLOAT_CLASS_POSITIVE_ZERO; \
3120 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3121 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3123 return FLOAT_CLASS_POSITIVE_NORMAL; \
3128 FLOAT_CLASS(class_s
, 32)
3129 FLOAT_CLASS(class_d
, 64)
3132 /* binary operations */
3133 #define FLOAT_BINOP(name) \
3134 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3135 uint64_t fdt0, uint64_t fdt1) \
3139 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3140 update_fcr31(env, GETPC()); \
3144 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3145 uint32_t fst0, uint32_t fst1) \
3149 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3150 update_fcr31(env, GETPC()); \
3154 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3158 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3159 uint32_t fsth0 = fdt0 >> 32; \
3160 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3161 uint32_t fsth1 = fdt1 >> 32; \
3165 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3166 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3167 update_fcr31(env, GETPC()); \
3168 return ((uint64_t)wth2 << 32) | wt2; \
3177 /* MIPS specific binary operations */
3178 uint64_t helper_float_recip2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3180 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3181 fdt2
= float64_chs(float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
));
3182 update_fcr31(env
, GETPC());
3186 uint32_t helper_float_recip2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3188 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3189 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3190 update_fcr31(env
, GETPC());
3194 uint64_t helper_float_recip2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3196 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3197 uint32_t fsth0
= fdt0
>> 32;
3198 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3199 uint32_t fsth2
= fdt2
>> 32;
3201 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3202 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3203 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3204 fsth2
= float32_chs(float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
));
3205 update_fcr31(env
, GETPC());
3206 return ((uint64_t)fsth2
<< 32) | fst2
;
3209 uint64_t helper_float_rsqrt2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3211 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3212 fdt2
= float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
);
3213 fdt2
= float64_chs(float64_div(fdt2
, FLOAT_TWO64
, &env
->active_fpu
.fp_status
));
3214 update_fcr31(env
, GETPC());
3218 uint32_t helper_float_rsqrt2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3220 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3221 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3222 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3223 update_fcr31(env
, GETPC());
3227 uint64_t helper_float_rsqrt2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3229 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3230 uint32_t fsth0
= fdt0
>> 32;
3231 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3232 uint32_t fsth2
= fdt2
>> 32;
3234 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3235 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3236 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3237 fsth2
= float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
);
3238 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3239 fsth2
= float32_chs(float32_div(fsth2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3240 update_fcr31(env
, GETPC());
3241 return ((uint64_t)fsth2
<< 32) | fst2
;
3244 uint64_t helper_float_addr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3246 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3247 uint32_t fsth0
= fdt0
>> 32;
3248 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3249 uint32_t fsth1
= fdt1
>> 32;
3253 fst2
= float32_add (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3254 fsth2
= float32_add (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3255 update_fcr31(env
, GETPC());
3256 return ((uint64_t)fsth2
<< 32) | fst2
;
3259 uint64_t helper_float_mulr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3261 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3262 uint32_t fsth0
= fdt0
>> 32;
3263 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3264 uint32_t fsth1
= fdt1
>> 32;
3268 fst2
= float32_mul (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3269 fsth2
= float32_mul (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3270 update_fcr31(env
, GETPC());
3271 return ((uint64_t)fsth2
<< 32) | fst2
;
3274 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3275 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3276 uint ## bits ## _t fs, \
3277 uint ## bits ## _t ft) \
3279 uint ## bits ## _t fdret; \
3281 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3282 &env->active_fpu.fp_status); \
3283 update_fcr31(env, GETPC()); \
3287 FLOAT_MINMAX(max_s
, 32, maxnum
)
3288 FLOAT_MINMAX(max_d
, 64, maxnum
)
3289 FLOAT_MINMAX(maxa_s
, 32, maxnummag
)
3290 FLOAT_MINMAX(maxa_d
, 64, maxnummag
)
3292 FLOAT_MINMAX(min_s
, 32, minnum
)
3293 FLOAT_MINMAX(min_d
, 64, minnum
)
3294 FLOAT_MINMAX(mina_s
, 32, minnummag
)
3295 FLOAT_MINMAX(mina_d
, 64, minnummag
)
3298 /* ternary operations */
3299 #define UNFUSED_FMA(prefix, a, b, c, flags) \
3301 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
3302 if ((flags) & float_muladd_negate_c) { \
3303 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
3305 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
3307 if ((flags) & float_muladd_negate_result) { \
3308 a = prefix##_chs(a); \
3312 /* FMA based operations */
3313 #define FLOAT_FMA(name, type) \
3314 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3315 uint64_t fdt0, uint64_t fdt1, \
3318 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
3319 update_fcr31(env, GETPC()); \
3323 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3324 uint32_t fst0, uint32_t fst1, \
3327 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3328 update_fcr31(env, GETPC()); \
3332 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3333 uint64_t fdt0, uint64_t fdt1, \
3336 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3337 uint32_t fsth0 = fdt0 >> 32; \
3338 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3339 uint32_t fsth1 = fdt1 >> 32; \
3340 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
3341 uint32_t fsth2 = fdt2 >> 32; \
3343 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3344 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
3345 update_fcr31(env, GETPC()); \
3346 return ((uint64_t)fsth0 << 32) | fst0; \
3349 FLOAT_FMA(msub
, float_muladd_negate_c
)
3350 FLOAT_FMA(nmadd
, float_muladd_negate_result
)
3351 FLOAT_FMA(nmsub
, float_muladd_negate_result
| float_muladd_negate_c
)
3354 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
3355 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3356 uint ## bits ## _t fs, \
3357 uint ## bits ## _t ft, \
3358 uint ## bits ## _t fd) \
3360 uint ## bits ## _t fdret; \
3362 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
3363 &env->active_fpu.fp_status); \
3364 update_fcr31(env, GETPC()); \
3368 FLOAT_FMADDSUB(maddf_s
, 32, 0)
3369 FLOAT_FMADDSUB(maddf_d
, 64, 0)
3370 FLOAT_FMADDSUB(msubf_s
, 32, float_muladd_negate_product
)
3371 FLOAT_FMADDSUB(msubf_d
, 64, float_muladd_negate_product
)
3372 #undef FLOAT_FMADDSUB
3374 /* compare operations */
3375 #define FOP_COND_D(op, cond) \
3376 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3377 uint64_t fdt1, int cc) \
3381 update_fcr31(env, GETPC()); \
3383 SET_FP_COND(cc, env->active_fpu); \
3385 CLEAR_FP_COND(cc, env->active_fpu); \
3387 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3388 uint64_t fdt1, int cc) \
3391 fdt0 = float64_abs(fdt0); \
3392 fdt1 = float64_abs(fdt1); \
3394 update_fcr31(env, GETPC()); \
3396 SET_FP_COND(cc, env->active_fpu); \
3398 CLEAR_FP_COND(cc, env->active_fpu); \
3401 /* NOTE: the comma operator will make "cond" to eval to false,
3402 * but float64_unordered_quiet() is still called. */
3403 FOP_COND_D(f
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3404 FOP_COND_D(un
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
3405 FOP_COND_D(eq
, float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3406 FOP_COND_D(ueq
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3407 FOP_COND_D(olt
, float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3408 FOP_COND_D(ult
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3409 FOP_COND_D(ole
, float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3410 FOP_COND_D(ule
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3411 /* NOTE: the comma operator will make "cond" to eval to false,
3412 * but float64_unordered() is still called. */
3413 FOP_COND_D(sf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3414 FOP_COND_D(ngle
,float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
3415 FOP_COND_D(seq
, float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3416 FOP_COND_D(ngl
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3417 FOP_COND_D(lt
, float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3418 FOP_COND_D(nge
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3419 FOP_COND_D(le
, float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3420 FOP_COND_D(ngt
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3422 #define FOP_COND_S(op, cond) \
3423 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3424 uint32_t fst1, int cc) \
3428 update_fcr31(env, GETPC()); \
3430 SET_FP_COND(cc, env->active_fpu); \
3432 CLEAR_FP_COND(cc, env->active_fpu); \
3434 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3435 uint32_t fst1, int cc) \
3438 fst0 = float32_abs(fst0); \
3439 fst1 = float32_abs(fst1); \
3441 update_fcr31(env, GETPC()); \
3443 SET_FP_COND(cc, env->active_fpu); \
3445 CLEAR_FP_COND(cc, env->active_fpu); \
3448 /* NOTE: the comma operator will make "cond" to eval to false,
3449 * but float32_unordered_quiet() is still called. */
3450 FOP_COND_S(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3451 FOP_COND_S(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
))
3452 FOP_COND_S(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3453 FOP_COND_S(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3454 FOP_COND_S(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3455 FOP_COND_S(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3456 FOP_COND_S(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3457 FOP_COND_S(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3458 /* NOTE: the comma operator will make "cond" to eval to false,
3459 * but float32_unordered() is still called. */
3460 FOP_COND_S(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3461 FOP_COND_S(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
))
3462 FOP_COND_S(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3463 FOP_COND_S(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3464 FOP_COND_S(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3465 FOP_COND_S(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3466 FOP_COND_S(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3467 FOP_COND_S(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3469 #define FOP_COND_PS(op, condl, condh) \
3470 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3471 uint64_t fdt1, int cc) \
3473 uint32_t fst0, fsth0, fst1, fsth1; \
3475 fst0 = fdt0 & 0XFFFFFFFF; \
3476 fsth0 = fdt0 >> 32; \
3477 fst1 = fdt1 & 0XFFFFFFFF; \
3478 fsth1 = fdt1 >> 32; \
3481 update_fcr31(env, GETPC()); \
3483 SET_FP_COND(cc, env->active_fpu); \
3485 CLEAR_FP_COND(cc, env->active_fpu); \
3487 SET_FP_COND(cc + 1, env->active_fpu); \
3489 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3491 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3492 uint64_t fdt1, int cc) \
3494 uint32_t fst0, fsth0, fst1, fsth1; \
3496 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3497 fsth0 = float32_abs(fdt0 >> 32); \
3498 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3499 fsth1 = float32_abs(fdt1 >> 32); \
3502 update_fcr31(env, GETPC()); \
3504 SET_FP_COND(cc, env->active_fpu); \
3506 CLEAR_FP_COND(cc, env->active_fpu); \
3508 SET_FP_COND(cc + 1, env->active_fpu); \
3510 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3513 /* NOTE: the comma operator will make "cond" to eval to false,
3514 * but float32_unordered_quiet() is still called. */
3515 FOP_COND_PS(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
3516 (float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
3517 FOP_COND_PS(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
),
3518 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
3519 FOP_COND_PS(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3520 float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3521 FOP_COND_PS(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3522 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3523 FOP_COND_PS(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3524 float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3525 FOP_COND_PS(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3526 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3527 FOP_COND_PS(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3528 float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3529 FOP_COND_PS(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3530 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3531 /* NOTE: the comma operator will make "cond" to eval to false,
3532 * but float32_unordered() is still called. */
3533 FOP_COND_PS(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
3534 (float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
3535 FOP_COND_PS(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
),
3536 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
3537 FOP_COND_PS(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3538 float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3539 FOP_COND_PS(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3540 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3541 FOP_COND_PS(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3542 float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3543 FOP_COND_PS(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3544 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3545 FOP_COND_PS(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3546 float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3547 FOP_COND_PS(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3548 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3550 /* R6 compare operations */
3551 #define FOP_CONDN_D(op, cond) \
3552 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
3557 update_fcr31(env, GETPC()); \
3565 /* NOTE: the comma operator will make "cond" to eval to false,
3566 * but float64_unordered_quiet() is still called. */
3567 FOP_CONDN_D(af
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3568 FOP_CONDN_D(un
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
3569 FOP_CONDN_D(eq
, (float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3570 FOP_CONDN_D(ueq
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3571 || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3572 FOP_CONDN_D(lt
, (float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3573 FOP_CONDN_D(ult
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3574 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3575 FOP_CONDN_D(le
, (float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3576 FOP_CONDN_D(ule
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3577 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3578 /* NOTE: the comma operator will make "cond" to eval to false,
3579 * but float64_unordered() is still called. */
3580 FOP_CONDN_D(saf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3581 FOP_CONDN_D(sun
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
3582 FOP_CONDN_D(seq
, (float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3583 FOP_CONDN_D(sueq
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3584 || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3585 FOP_CONDN_D(slt
, (float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3586 FOP_CONDN_D(sult
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3587 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3588 FOP_CONDN_D(sle
, (float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3589 FOP_CONDN_D(sule
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3590 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3591 FOP_CONDN_D(or, (float64_le_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3592 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3593 FOP_CONDN_D(une
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3594 || float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3595 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3596 FOP_CONDN_D(ne
, (float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3597 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3598 FOP_CONDN_D(sor
, (float64_le(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3599 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3600 FOP_CONDN_D(sune
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3601 || float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3602 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3603 FOP_CONDN_D(sne
, (float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3604 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3606 #define FOP_CONDN_S(op, cond) \
3607 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
3612 update_fcr31(env, GETPC()); \
3620 /* NOTE: the comma operator will make "cond" to eval to false,
3621 * but float32_unordered_quiet() is still called. */
3622 FOP_CONDN_S(af
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3623 FOP_CONDN_S(un
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
3624 FOP_CONDN_S(eq
, (float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3625 FOP_CONDN_S(ueq
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3626 || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3627 FOP_CONDN_S(lt
, (float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3628 FOP_CONDN_S(ult
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3629 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3630 FOP_CONDN_S(le
, (float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3631 FOP_CONDN_S(ule
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3632 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3633 /* NOTE: the comma operator will make "cond" to eval to false,
3634 * but float32_unordered() is still called. */
3635 FOP_CONDN_S(saf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3636 FOP_CONDN_S(sun
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
3637 FOP_CONDN_S(seq
, (float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3638 FOP_CONDN_S(sueq
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3639 || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3640 FOP_CONDN_S(slt
, (float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3641 FOP_CONDN_S(sult
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3642 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3643 FOP_CONDN_S(sle
, (float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3644 FOP_CONDN_S(sule
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3645 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3646 FOP_CONDN_S(or, (float32_le_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3647 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3648 FOP_CONDN_S(une
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3649 || float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3650 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3651 FOP_CONDN_S(ne
, (float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3652 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3653 FOP_CONDN_S(sor
, (float32_le(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3654 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3655 FOP_CONDN_S(sune
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3656 || float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3657 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3658 FOP_CONDN_S(sne
, (float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3659 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3662 /* Data format min and max values */
3663 #define DF_BITS(df) (1 << ((df) + 3))
3665 /* Element-by-element access macros */
3666 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
3668 #if !defined(CONFIG_USER_ONLY)
3669 #define MEMOP_IDX(DF) \
3670 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
3671 cpu_mmu_index(env, false));
3673 #define MEMOP_IDX(DF)
3676 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
3677 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
3678 target_ulong addr) \
3680 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
3684 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
3685 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
3687 memcpy(pwd, &wx, sizeof(wr_t)); \
3690 #if !defined(CONFIG_USER_ONLY)
3691 MSA_LD_DF(DF_BYTE
, b
, helper_ret_ldub_mmu
, oi
, GETRA())
3692 MSA_LD_DF(DF_HALF
, h
, helper_ret_lduw_mmu
, oi
, GETRA())
3693 MSA_LD_DF(DF_WORD
, w
, helper_ret_ldul_mmu
, oi
, GETRA())
3694 MSA_LD_DF(DF_DOUBLE
, d
, helper_ret_ldq_mmu
, oi
, GETRA())
3696 MSA_LD_DF(DF_BYTE
, b
, cpu_ldub_data
)
3697 MSA_LD_DF(DF_HALF
, h
, cpu_lduw_data
)
3698 MSA_LD_DF(DF_WORD
, w
, cpu_ldl_data
)
3699 MSA_LD_DF(DF_DOUBLE
, d
, cpu_ldq_data
)
3702 #define MSA_PAGESPAN(x) \
3703 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
3705 static inline void ensure_writable_pages(CPUMIPSState
*env
,
3710 #if !defined(CONFIG_USER_ONLY)
3711 target_ulong page_addr
;
3712 if (unlikely(MSA_PAGESPAN(addr
))) {
3714 probe_write(env
, addr
, mmu_idx
, retaddr
);
3716 page_addr
= (addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
3717 probe_write(env
, page_addr
, mmu_idx
, retaddr
);
3722 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
3723 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
3724 target_ulong addr) \
3726 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
3727 int mmu_idx = cpu_mmu_index(env, false); \
3730 ensure_writable_pages(env, addr, mmu_idx, GETRA()); \
3731 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
3732 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
3736 #if !defined(CONFIG_USER_ONLY)
3737 MSA_ST_DF(DF_BYTE
, b
, helper_ret_stb_mmu
, oi
, GETRA())
3738 MSA_ST_DF(DF_HALF
, h
, helper_ret_stw_mmu
, oi
, GETRA())
3739 MSA_ST_DF(DF_WORD
, w
, helper_ret_stl_mmu
, oi
, GETRA())
3740 MSA_ST_DF(DF_DOUBLE
, d
, helper_ret_stq_mmu
, oi
, GETRA())
3742 MSA_ST_DF(DF_BYTE
, b
, cpu_stb_data
)
3743 MSA_ST_DF(DF_HALF
, h
, cpu_stw_data
)
3744 MSA_ST_DF(DF_WORD
, w
, cpu_stl_data
)
3745 MSA_ST_DF(DF_DOUBLE
, d
, cpu_stq_data
)