2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: MIPS specific KVM APIs
8 * Copyright (C) 2012-2014 Imagination Technologies Ltd.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include <sys/types.h>
13 #include <sys/ioctl.h>
16 #include <linux/kvm.h>
18 #include "qemu-common.h"
19 #include "qemu/error-report.h"
20 #include "qemu/timer.h"
21 #include "sysemu/sysemu.h"
22 #include "sysemu/kvm.h"
24 #include "sysemu/cpus.h"
26 #include "exec/memattrs.h"
30 #define DPRINTF(fmt, ...) \
31 do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0)
33 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
37 static void kvm_mips_update_state(void *opaque
, int running
, RunState state
);
39 unsigned long kvm_arch_vcpu_id(CPUState
*cs
)
44 int kvm_arch_init(MachineState
*ms
, KVMState
*s
)
46 /* MIPS has 128 signals */
47 kvm_set_sigmask_len(s
, 16);
49 DPRINTF("%s\n", __func__
);
53 int kvm_arch_init_vcpu(CPUState
*cs
)
57 qemu_add_vm_change_state_handler(kvm_mips_update_state
, cs
);
59 DPRINTF("%s\n", __func__
);
63 void kvm_mips_reset_vcpu(MIPSCPU
*cpu
)
65 CPUMIPSState
*env
= &cpu
->env
;
67 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
68 fprintf(stderr
, "Warning: FPU not supported with KVM, disabling\n");
69 env
->CP0_Config1
&= ~(1 << CP0C1_FP
);
72 DPRINTF("%s\n", __func__
);
75 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
77 DPRINTF("%s\n", __func__
);
81 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
83 DPRINTF("%s\n", __func__
);
87 static inline int cpu_mips_io_interrupts_pending(MIPSCPU
*cpu
)
89 CPUMIPSState
*env
= &cpu
->env
;
91 DPRINTF("%s: %#x\n", __func__
, env
->CP0_Cause
& (1 << (2 + CP0Ca_IP
)));
92 return env
->CP0_Cause
& (0x1 << (2 + CP0Ca_IP
));
96 void kvm_arch_pre_run(CPUState
*cs
, struct kvm_run
*run
)
98 MIPSCPU
*cpu
= MIPS_CPU(cs
);
100 struct kvm_mips_interrupt intr
;
102 qemu_mutex_lock_iothread();
104 if ((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
105 cpu_mips_io_interrupts_pending(cpu
)) {
108 r
= kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &intr
);
110 error_report("%s: cpu %d: failed to inject IRQ %x",
111 __func__
, cs
->cpu_index
, intr
.irq
);
115 qemu_mutex_unlock_iothread();
118 MemTxAttrs
kvm_arch_post_run(CPUState
*cs
, struct kvm_run
*run
)
120 DPRINTF("%s\n", __func__
);
121 return MEMTXATTRS_UNSPECIFIED
;
124 int kvm_arch_process_async_events(CPUState
*cs
)
129 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
133 DPRINTF("%s\n", __func__
);
134 switch (run
->exit_reason
) {
136 error_report("%s: unknown exit reason %d",
137 __func__
, run
->exit_reason
);
145 bool kvm_arch_stop_on_emulation_error(CPUState
*cs
)
147 DPRINTF("%s\n", __func__
);
151 int kvm_arch_on_sigbus_vcpu(CPUState
*cs
, int code
, void *addr
)
153 DPRINTF("%s\n", __func__
);
157 int kvm_arch_on_sigbus(int code
, void *addr
)
159 DPRINTF("%s\n", __func__
);
163 void kvm_arch_init_irq_routing(KVMState
*s
)
167 int kvm_mips_set_interrupt(MIPSCPU
*cpu
, int irq
, int level
)
169 CPUState
*cs
= CPU(cpu
);
170 struct kvm_mips_interrupt intr
;
172 if (!kvm_enabled()) {
184 kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &intr
);
189 int kvm_mips_set_ipi_interrupt(MIPSCPU
*cpu
, int irq
, int level
)
191 CPUState
*cs
= current_cpu
;
192 CPUState
*dest_cs
= CPU(cpu
);
193 struct kvm_mips_interrupt intr
;
195 if (!kvm_enabled()) {
199 intr
.cpu
= dest_cs
->cpu_index
;
207 DPRINTF("%s: CPU %d, IRQ: %d\n", __func__
, intr
.cpu
, intr
.irq
);
209 kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &intr
);
214 #define MIPS_CP0_32(_R, _S) \
215 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
217 #define MIPS_CP0_64(_R, _S) \
218 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
220 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
221 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
222 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
223 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
224 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
225 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
226 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
227 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
228 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
229 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
230 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
231 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
232 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
233 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
235 static inline int kvm_mips_put_one_reg(CPUState
*cs
, uint64_t reg_id
,
238 struct kvm_one_reg cp0reg
= {
240 .addr
= (uintptr_t)addr
243 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
246 static inline int kvm_mips_put_one_ulreg(CPUState
*cs
, uint64_t reg_id
,
249 uint64_t val64
= *addr
;
250 struct kvm_one_reg cp0reg
= {
252 .addr
= (uintptr_t)&val64
255 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
258 static inline int kvm_mips_put_one_reg64(CPUState
*cs
, uint64_t reg_id
,
261 struct kvm_one_reg cp0reg
= {
263 .addr
= (uintptr_t)addr
266 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
269 static inline int kvm_mips_get_one_reg(CPUState
*cs
, uint64_t reg_id
,
272 struct kvm_one_reg cp0reg
= {
274 .addr
= (uintptr_t)addr
277 return kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
280 static inline int kvm_mips_get_one_ulreg(CPUState
*cs
, uint64 reg_id
,
285 struct kvm_one_reg cp0reg
= {
287 .addr
= (uintptr_t)&val64
290 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
297 static inline int kvm_mips_get_one_reg64(CPUState
*cs
, uint64 reg_id
,
300 struct kvm_one_reg cp0reg
= {
302 .addr
= (uintptr_t)addr
305 return kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
309 * We freeze the KVM timer when either the VM clock is stopped or the state is
310 * saved (the state is dirty).
314 * Save the state of the KVM timer when VM clock is stopped or state is synced
317 static int kvm_mips_save_count(CPUState
*cs
)
319 MIPSCPU
*cpu
= MIPS_CPU(cs
);
320 CPUMIPSState
*env
= &cpu
->env
;
324 /* freeze KVM timer */
325 err
= kvm_mips_get_one_reg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
327 DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__
, err
);
329 } else if (!(count_ctl
& KVM_REG_MIPS_COUNT_CTL_DC
)) {
330 count_ctl
|= KVM_REG_MIPS_COUNT_CTL_DC
;
331 err
= kvm_mips_put_one_reg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
333 DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__
, err
);
339 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CAUSE
, &env
->CP0_Cause
);
341 DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__
, err
);
346 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_COUNT
, &env
->CP0_Count
);
348 DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__
, err
);
356 * Restore the state of the KVM timer when VM clock is restarted or state is
359 static int kvm_mips_restore_count(CPUState
*cs
)
361 MIPSCPU
*cpu
= MIPS_CPU(cs
);
362 CPUMIPSState
*env
= &cpu
->env
;
364 int err_dc
, err
, ret
= 0;
366 /* check the timer is frozen */
367 err_dc
= kvm_mips_get_one_reg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
369 DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__
, err_dc
);
371 } else if (!(count_ctl
& KVM_REG_MIPS_COUNT_CTL_DC
)) {
372 /* freeze timer (sets COUNT_RESUME for us) */
373 count_ctl
|= KVM_REG_MIPS_COUNT_CTL_DC
;
374 err
= kvm_mips_put_one_reg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
376 DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__
, err
);
382 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_CAUSE
, &env
->CP0_Cause
);
384 DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__
, err
);
389 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_COUNT
, &env
->CP0_Count
);
391 DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__
, err
);
395 /* resume KVM timer */
397 count_ctl
&= ~KVM_REG_MIPS_COUNT_CTL_DC
;
398 err
= kvm_mips_put_one_reg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
400 DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__
, err
);
409 * Handle the VM clock being started or stopped
411 static void kvm_mips_update_state(void *opaque
, int running
, RunState state
)
413 CPUState
*cs
= opaque
;
415 uint64_t count_resume
;
418 * If state is already dirty (synced to QEMU) then the KVM timer state is
419 * already saved and can be restored when it is synced back to KVM.
422 if (!cs
->kvm_vcpu_dirty
) {
423 ret
= kvm_mips_save_count(cs
);
425 fprintf(stderr
, "Failed saving count\n");
429 /* Set clock restore time to now */
430 count_resume
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
431 ret
= kvm_mips_put_one_reg64(cs
, KVM_REG_MIPS_COUNT_RESUME
,
434 fprintf(stderr
, "Failed setting COUNT_RESUME\n");
438 if (!cs
->kvm_vcpu_dirty
) {
439 ret
= kvm_mips_restore_count(cs
);
441 fprintf(stderr
, "Failed restoring count\n");
447 static int kvm_mips_put_cp0_registers(CPUState
*cs
, int level
)
449 MIPSCPU
*cpu
= MIPS_CPU(cs
);
450 CPUMIPSState
*env
= &cpu
->env
;
455 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_INDEX
, &env
->CP0_Index
);
457 DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__
, err
);
460 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_CONTEXT
,
463 DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__
, err
);
466 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_USERLOCAL
,
467 &env
->active_tc
.CP0_UserLocal
);
469 DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__
, err
);
472 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_PAGEMASK
,
475 DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__
, err
);
478 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_WIRED
, &env
->CP0_Wired
);
480 DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__
, err
);
483 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_HWRENA
, &env
->CP0_HWREna
);
485 DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__
, err
);
488 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_BADVADDR
,
491 DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__
, err
);
495 /* If VM clock stopped then state will be restored when it is restarted */
496 if (runstate_is_running()) {
497 err
= kvm_mips_restore_count(cs
);
503 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_ENTRYHI
,
506 DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__
, err
);
509 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_COMPARE
,
512 DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__
, err
);
515 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_STATUS
, &env
->CP0_Status
);
517 DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__
, err
);
520 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_EPC
, &env
->CP0_EPC
);
522 DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__
, err
);
525 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_ERROREPC
,
528 DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__
, err
);
535 static int kvm_mips_get_cp0_registers(CPUState
*cs
)
537 MIPSCPU
*cpu
= MIPS_CPU(cs
);
538 CPUMIPSState
*env
= &cpu
->env
;
541 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_INDEX
, &env
->CP0_Index
);
543 DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__
, err
);
546 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_CONTEXT
,
549 DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__
, err
);
552 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_USERLOCAL
,
553 &env
->active_tc
.CP0_UserLocal
);
555 DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__
, err
);
558 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_PAGEMASK
,
561 DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__
, err
);
564 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_WIRED
, &env
->CP0_Wired
);
566 DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__
, err
);
569 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_HWRENA
, &env
->CP0_HWREna
);
571 DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__
, err
);
574 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_BADVADDR
,
577 DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__
, err
);
580 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_ENTRYHI
,
583 DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__
, err
);
586 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_COMPARE
,
589 DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__
, err
);
592 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_STATUS
, &env
->CP0_Status
);
594 DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__
, err
);
598 /* If VM clock stopped then state was already saved when it was stopped */
599 if (runstate_is_running()) {
600 err
= kvm_mips_save_count(cs
);
606 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_EPC
, &env
->CP0_EPC
);
608 DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__
, err
);
611 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_ERROREPC
,
614 DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__
, err
);
621 int kvm_arch_put_registers(CPUState
*cs
, int level
)
623 MIPSCPU
*cpu
= MIPS_CPU(cs
);
624 CPUMIPSState
*env
= &cpu
->env
;
625 struct kvm_regs regs
;
629 /* Set the registers based on QEMU's view of things */
630 for (i
= 0; i
< 32; i
++) {
631 regs
.gpr
[i
] = (int64_t)(target_long
)env
->active_tc
.gpr
[i
];
634 regs
.hi
= (int64_t)(target_long
)env
->active_tc
.HI
[0];
635 regs
.lo
= (int64_t)(target_long
)env
->active_tc
.LO
[0];
636 regs
.pc
= (int64_t)(target_long
)env
->active_tc
.PC
;
638 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_REGS
, ®s
);
644 ret
= kvm_mips_put_cp0_registers(cs
, level
);
652 int kvm_arch_get_registers(CPUState
*cs
)
654 MIPSCPU
*cpu
= MIPS_CPU(cs
);
655 CPUMIPSState
*env
= &cpu
->env
;
657 struct kvm_regs regs
;
660 /* Get the current register set as KVM seems it */
661 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_REGS
, ®s
);
667 for (i
= 0; i
< 32; i
++) {
668 env
->active_tc
.gpr
[i
] = regs
.gpr
[i
];
671 env
->active_tc
.HI
[0] = regs
.hi
;
672 env
->active_tc
.LO
[0] = regs
.lo
;
673 env
->active_tc
.PC
= regs
.pc
;
675 kvm_mips_get_cp0_registers(cs
);
680 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry
*route
,
681 uint64_t address
, uint32_t data
, PCIDevice
*dev
)
686 int kvm_arch_msi_data_to_gsi(uint32_t data
)