block: Don't call blk_bs() twice in bdrv_lookup_bs()
[qemu.git] / target-mips / gdbstub.c
blob9845d880aebacc621891699df3820cde4fcd1ddd
1 /*
2 * MIPS gdb server stub
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "config.h"
21 #include "qemu-common.h"
22 #include "exec/gdbstub.h"
24 int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
26 MIPSCPU *cpu = MIPS_CPU(cs);
27 CPUMIPSState *env = &cpu->env;
29 if (n < 32) {
30 return gdb_get_regl(mem_buf, env->active_tc.gpr[n]);
32 if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
33 switch (n) {
34 case 70:
35 return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr31);
36 case 71:
37 return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);
38 default:
39 if (env->CP0_Status & (1 << CP0St_FR)) {
40 return gdb_get_regl(mem_buf,
41 env->active_fpu.fpr[n - 38].d);
42 } else {
43 return gdb_get_regl(mem_buf,
44 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
48 switch (n) {
49 case 32:
50 return gdb_get_regl(mem_buf, (int32_t)env->CP0_Status);
51 case 33:
52 return gdb_get_regl(mem_buf, env->active_tc.LO[0]);
53 case 34:
54 return gdb_get_regl(mem_buf, env->active_tc.HI[0]);
55 case 35:
56 return gdb_get_regl(mem_buf, env->CP0_BadVAddr);
57 case 36:
58 return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause);
59 case 37:
60 return gdb_get_regl(mem_buf, env->active_tc.PC |
61 !!(env->hflags & MIPS_HFLAG_M16));
62 case 72:
63 return gdb_get_regl(mem_buf, 0); /* fp */
64 case 89:
65 return gdb_get_regl(mem_buf, (int32_t)env->CP0_PRid);
66 default:
67 if (n > 89) {
68 return 0;
70 /* 16 embedded regs. */
71 return gdb_get_regl(mem_buf, 0);
74 return 0;
77 int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
79 MIPSCPU *cpu = MIPS_CPU(cs);
80 CPUMIPSState *env = &cpu->env;
81 target_ulong tmp;
83 tmp = ldtul_p(mem_buf);
85 if (n < 32) {
86 env->active_tc.gpr[n] = tmp;
87 return sizeof(target_ulong);
89 if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 72) {
90 switch (n) {
91 case 70:
92 env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
93 /* set rounding mode */
94 restore_rounding_mode(env);
95 /* set flush-to-zero mode */
96 restore_flush_mode(env);
97 break;
98 case 71:
99 /* FIR is read-only. Ignore writes. */
100 break;
101 default:
102 if (env->CP0_Status & (1 << CP0St_FR)) {
103 env->active_fpu.fpr[n - 38].d = tmp;
104 } else {
105 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
107 break;
109 return sizeof(target_ulong);
111 switch (n) {
112 case 32:
113 #ifndef CONFIG_USER_ONLY
114 cpu_mips_store_status(env, tmp);
115 #endif
116 break;
117 case 33:
118 env->active_tc.LO[0] = tmp;
119 break;
120 case 34:
121 env->active_tc.HI[0] = tmp;
122 break;
123 case 35:
124 env->CP0_BadVAddr = tmp;
125 break;
126 case 36:
127 #ifndef CONFIG_USER_ONLY
128 cpu_mips_store_cause(env, tmp);
129 #endif
130 break;
131 case 37:
132 env->active_tc.PC = tmp & ~(target_ulong)1;
133 if (tmp & 1) {
134 env->hflags |= MIPS_HFLAG_M16;
135 } else {
136 env->hflags &= ~(MIPS_HFLAG_M16);
138 break;
139 case 72: /* fp, ignored */
140 break;
141 default:
142 if (n > 89) {
143 return 0;
145 /* Other registers are readonly. Ignore writes. */
146 break;
149 return sizeof(target_ulong);