hw/xilinx_timer.c

   1 /*
   2  * QEMU model of the Xilinx timer block.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26 #include "qemu-timer.h"
  27
  28 #define D(x)
  29
  30 #define R_TCSR     0
  31 #define R_TLR      1
  32 #define R_TCR      2
  33 #define R_MAX      4
  34
  35 #define TCSR_MDT        (1<<0)
  36 #define TCSR_UDT        (1<<1)
  37 #define TCSR_GENT       (1<<2)
  38 #define TCSR_CAPT       (1<<3)
  39 #define TCSR_ARHT       (1<<4)
  40 #define TCSR_LOAD       (1<<5)
  41 #define TCSR_ENIT       (1<<6)
  42 #define TCSR_ENT        (1<<7)
  43 #define TCSR_TINT       (1<<8)
  44 #define TCSR_PWMA       (1<<9)
  45 #define TCSR_ENALL      (1<<10)
  46
  47 struct xlx_timer
  48 {
  49     QEMUBH *bh;
  50     ptimer_state *ptimer;
  51     void *parent;
  52     int nr; /* for debug.  */
  53
  54     unsigned long timer_div;
  55
  56     uint32_t regs[R_MAX];
  57 };
  58
  59 struct timerblock
  60 {
  61     SysBusDevice busdev;
  62     MemoryRegion mmio;
  63     qemu_irq irq;
  64     uint32_t nr_timers;
  65     uint32_t freq_hz;
  66     struct xlx_timer *timers;
  67 };
  68
  69 static inline unsigned int timer_from_addr(target_phys_addr_t addr)
  70 {
  71     /* Timers get a 4x32bit control reg area each.  */
  72     return addr >> 2;
  73 }
  74
  75 static void timer_update_irq(struct timerblock *t)
  76 {
  77     unsigned int i, irq = 0;
  78     uint32_t csr;
  79
  80     for (i = 0; i < t->nr_timers; i++) {
  81         csr = t->timers[i].regs[R_TCSR];
  82         irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
  83     }
  84
  85     /* All timers within the same slave share a single IRQ line.  */
  86     qemu_set_irq(t->irq, !!irq);
  87 }
  88
  89 static uint64_t
  90 timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
  91 {
  92     struct timerblock *t = opaque;
  93     struct xlx_timer *xt;
  94     uint32_t r = 0;
  95     unsigned int timer;
  96
  97     addr >>= 2;
  98     timer = timer_from_addr(addr);
  99     xt = &t->timers[timer];
 100     /* Further decoding to address a specific timers reg.  */
 101     addr &= 0x3;
 102     switch (addr)
 103     {
 104         case R_TCR:
 105                 r = ptimer_get_count(xt->ptimer);
 106                 if (!(xt->regs[R_TCSR] & TCSR_UDT))
 107                     r = ~r;
 108                 D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
 109                          timer, r, xt->regs[R_TCSR] & TCSR_UDT));
 110             break;
 111         default:
 112             if (addr < ARRAY_SIZE(xt->regs))
 113                 r = xt->regs[addr];
 114             break;
 115
 116     }
 117     D(printf("%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
 118     return r;
 119 }
 120
 121 static void timer_enable(struct xlx_timer *xt)
 122 {
 123     uint64_t count;
 124
 125     D(printf("%s timer=%d down=%d\n", __func__,
 126               xt->nr, xt->regs[R_TCSR] & TCSR_UDT));
 127
 128     ptimer_stop(xt->ptimer);
 129
 130     if (xt->regs[R_TCSR] & TCSR_UDT)
 131         count = xt->regs[R_TLR];
 132     else
 133         count = ~0 - xt->regs[R_TLR];
 134     ptimer_set_count(xt->ptimer, count);
 135     ptimer_run(xt->ptimer, 1);
 136 }
 137
 138 static void
 139 timer_write(void *opaque, target_phys_addr_t addr,
 140             uint64_t val64, unsigned int size)
 141 {
 142     struct timerblock *t = opaque;
 143     struct xlx_timer *xt;
 144     unsigned int timer;
 145     uint32_t value = val64;
 146
 147     addr >>= 2;
 148     timer = timer_from_addr(addr);
 149     xt = &t->timers[timer];
 150     D(printf("%s addr=%x val=%x (timer=%d off=%d)\n",
 151              __func__, addr * 4, value, timer, addr & 3));
 152     /* Further decoding to address a specific timers reg.  */
 153     addr &= 3;
 154     switch (addr)
 155     {
 156         case R_TCSR:
 157             if (value & TCSR_TINT)
 158                 value &= ~TCSR_TINT;
 159
 160             xt->regs[addr] = value;
 161             if (value & TCSR_ENT)
 162                 timer_enable(xt);
 163             break;
 164
 165         default:
 166             if (addr < ARRAY_SIZE(xt->regs))
 167                 xt->regs[addr] = value;
 168             break;
 169     }
 170     timer_update_irq(t);
 171 }
 172
 173 static const MemoryRegionOps timer_ops = {
 174     .read = timer_read,
 175     .write = timer_write,
 176     .endianness = DEVICE_NATIVE_ENDIAN,
 177     .valid = {
 178         .min_access_size = 4,
 179         .max_access_size = 4
 180     }
 181 };
 182
 183 static void timer_hit(void *opaque)
 184 {
 185     struct xlx_timer *xt = opaque;
 186     struct timerblock *t = xt->parent;
 187     D(printf("%s %d\n", __func__, timer));
 188     xt->regs[R_TCSR] |= TCSR_TINT;
 189
 190     if (xt->regs[R_TCSR] & TCSR_ARHT)
 191         timer_enable(xt);
 192     timer_update_irq(t);
 193 }
 194
 195 static int xilinx_timer_init(SysBusDevice *dev)
 196 {
 197     struct timerblock *t = FROM_SYSBUS(typeof (*t), dev);
 198     unsigned int i;
 199
 200     /* All timers share a single irq line.  */
 201     sysbus_init_irq(dev, &t->irq);
 202
 203     /* Init all the ptimers.  */
 204     t->timers = g_malloc0(sizeof t->timers[0] * t->nr_timers);
 205     for (i = 0; i < t->nr_timers; i++) {
 206         struct xlx_timer *xt = &t->timers[i];
 207
 208         xt->parent = t;
 209         xt->nr = i;
 210         xt->bh = qemu_bh_new(timer_hit, xt);
 211         xt->ptimer = ptimer_init(xt->bh);
 212         ptimer_set_freq(xt->ptimer, t->freq_hz);
 213     }
 214
 215     memory_region_init_io(&t->mmio, &timer_ops, t, "xilinx-timer",
 216                           R_MAX * 4 * t->nr_timers);
 217     sysbus_init_mmio(dev, &t->mmio);
 218     return 0;
 219 }
 220
 221 static SysBusDeviceInfo xilinx_timer_info = {
 222     .init = xilinx_timer_init,
 223     .qdev.name  = "xilinx,timer",
 224     .qdev.size  = sizeof(struct timerblock),
 225     .qdev.props = (Property[]) {
 226         DEFINE_PROP_UINT32("frequency", struct timerblock, freq_hz,   0),
 227         DEFINE_PROP_UINT32("nr-timers", struct timerblock, nr_timers, 0),
 228         DEFINE_PROP_END_OF_LIST(),
 229     }
 230 };
 231
 232 static void xilinx_timer_register(void)
 233 {
 234     sysbus_register_withprop(&xilinx_timer_info);
 235 }
 236
 237 device_init(xilinx_timer_register)