hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pc.h"
  27 #include "nvram.h"
  28 #include "fdc.h"
  29 #include "net.h"
  30 #include "qemu-timer.h"
  31 #include "sysemu.h"
  32 #include "boards.h"
  33 #include "firmware_abi.h"
  34 #include "fw_cfg.h"
  35
  36 //#define DEBUG_IRQ
  37
  38 #ifdef DEBUG_IRQ
  39 #define DPRINTF(fmt, ...)                                       \
  40     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  41 #else
  42 #define DPRINTF(fmt, ...)
  43 #endif
  44
  45 #define KERNEL_LOAD_ADDR     0x00404000
  46 #define CMDLINE_ADDR         0x003ff000
  47 #define INITRD_LOAD_ADDR     0x00300000
  48 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  49 #define PROM_VADDR           0x000ffd00000ULL
  50 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  51 #define APB_MEM_BASE         0x1ff00000000ULL
  52 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  53 #define PROM_FILENAME        "openbios-sparc64"
  54 #define NVRAM_SIZE           0x2000
  55 #define MAX_IDE_BUS          2
  56 #define BIOS_CFG_IOPORT      0x510
  57
  58 #define MAX_PILS 16
  59
  60 #define TICK_INT_DIS         0x8000000000000000ULL
  61 #define TICK_MAX             0x7fffffffffffffffULL
  62
  63 struct hwdef {
  64     const char * const default_cpu_model;
  65     uint16_t machine_id;
  66     uint64_t prom_addr;
  67     uint64_t console_serial_base;
  68 };
  69
  70 int DMA_get_channel_mode (int nchan)
  71 {
  72     return 0;
  73 }
  74 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  75 {
  76     return 0;
  77 }
  78 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  79 {
  80     return 0;
  81 }
  82 void DMA_hold_DREQ (int nchan) {}
  83 void DMA_release_DREQ (int nchan) {}
  84 void DMA_schedule(int nchan) {}
  85 void DMA_init (int high_page_enable) {}
  86 void DMA_register_channel (int nchan,
  87                            DMA_transfer_handler transfer_handler,
  88                            void *opaque)
  89 {
  90 }
  91
  92 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
  93 {
  94     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
  95     return 0;
  96 }
  97
  98 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
  99                                    const char *arch,
 100                                    ram_addr_t RAM_size,
 101                                    const char *boot_devices,
 102                                    uint32_t kernel_image, uint32_t kernel_size,
 103                                    const char *cmdline,
 104                                    uint32_t initrd_image, uint32_t initrd_size,
 105                                    uint32_t NVRAM_image,
 106                                    int width, int height, int depth,
 107                                    const uint8_t *macaddr)
 108 {
 109     unsigned int i;
 110     uint32_t start, end;
 111     uint8_t image[0x1ff0];
 112     struct OpenBIOS_nvpart_v1 *part_header;
 113
 114     memset(image, '\0', sizeof(image));
 115
 116     start = 0;
 117
 118     // OpenBIOS nvram variables
 119     // Variable partition
 120     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 121     part_header->signature = OPENBIOS_PART_SYSTEM;
 122     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 123
 124     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 125     for (i = 0; i < nb_prom_envs; i++)
 126         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 127
 128     // End marker
 129     image[end++] = '\0';
 130
 131     end = start + ((end - start + 15) & ~15);
 132     OpenBIOS_finish_partition(part_header, end - start);
 133
 134     // free partition
 135     start = end;
 136     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 137     part_header->signature = OPENBIOS_PART_FREE;
 138     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 139
 140     end = 0x1fd0;
 141     OpenBIOS_finish_partition(part_header, end - start);
 142
 143     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 144
 145     for (i = 0; i < sizeof(image); i++)
 146         m48t59_write(nvram, i, image[i]);
 147
 148     return 0;
 149 }
 150
 151 void pic_info(Monitor *mon)
 152 {
 153 }
 154
 155 void irq_info(Monitor *mon)
 156 {
 157 }
 158
 159 void cpu_check_irqs(CPUState *env)
 160 {
 161     uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) |
 162         ((env->softint & SOFTINT_TIMER) << 14);
 163
 164     if (pil && (env->interrupt_index == 0 ||
 165                 (env->interrupt_index & ~15) == TT_EXTINT)) {
 166         unsigned int i;
 167
 168         for (i = 15; i > 0; i--) {
 169             if (pil & (1 << i)) {
 170                 int old_interrupt = env->interrupt_index;
 171
 172                 env->interrupt_index = TT_EXTINT | i;
 173                 if (old_interrupt != env->interrupt_index) {
 174                     DPRINTF("Set CPU IRQ %d\n", i);
 175                     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 176                 }
 177                 break;
 178             }
 179         }
 180     } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) {
 181         DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
 182         env->interrupt_index = 0;
 183         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 184     }
 185 }
 186
 187 static void cpu_set_irq(void *opaque, int irq, int level)
 188 {
 189     CPUState *env = opaque;
 190
 191     if (level) {
 192         DPRINTF("Raise CPU IRQ %d\n", irq);
 193         env->halted = 0;
 194         env->pil_in |= 1 << irq;
 195         cpu_check_irqs(env);
 196     } else {
 197         DPRINTF("Lower CPU IRQ %d\n", irq);
 198         env->pil_in &= ~(1 << irq);
 199         cpu_check_irqs(env);
 200     }
 201 }
 202
 203 void qemu_system_powerdown(void)
 204 {
 205 }
 206
 207 typedef struct ResetData {
 208     CPUState *env;
 209     uint64_t reset_addr;
 210 } ResetData;
 211
 212 static void main_cpu_reset(void *opaque)
 213 {
 214     ResetData *s = (ResetData *)opaque;
 215     CPUState *env = s->env;
 216
 217     cpu_reset(env);
 218     env->tick_cmpr = TICK_INT_DIS | 0;
 219     ptimer_set_limit(env->tick, TICK_MAX, 1);
 220     ptimer_run(env->tick, 1);
 221     env->stick_cmpr = TICK_INT_DIS | 0;
 222     ptimer_set_limit(env->stick, TICK_MAX, 1);
 223     ptimer_run(env->stick, 1);
 224     env->hstick_cmpr = TICK_INT_DIS | 0;
 225     ptimer_set_limit(env->hstick, TICK_MAX, 1);
 226     ptimer_run(env->hstick, 1);
 227     env->gregs[1] = 0; // Memory start
 228     env->gregs[2] = ram_size; // Memory size
 229     env->gregs[3] = 0; // Machine description XXX
 230     env->pc = s->reset_addr;
 231     env->npc = env->pc + 4;
 232 }
 233
 234 static void tick_irq(void *opaque)
 235 {
 236     CPUState *env = opaque;
 237
 238     if (!(env->tick_cmpr & TICK_INT_DIS)) {
 239         env->softint |= SOFTINT_TIMER;
 240         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 241     }
 242 }
 243
 244 static void stick_irq(void *opaque)
 245 {
 246     CPUState *env = opaque;
 247
 248     if (!(env->stick_cmpr & TICK_INT_DIS)) {
 249         env->softint |= SOFTINT_STIMER;
 250         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 251     }
 252 }
 253
 254 static void hstick_irq(void *opaque)
 255 {
 256     CPUState *env = opaque;
 257
 258     if (!(env->hstick_cmpr & TICK_INT_DIS)) {
 259         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 260     }
 261 }
 262
 263 void cpu_tick_set_count(void *opaque, uint64_t count)
 264 {
 265     ptimer_set_count(opaque, -count);
 266 }
 267
 268 uint64_t cpu_tick_get_count(void *opaque)
 269 {
 270     return -ptimer_get_count(opaque);
 271 }
 272
 273 void cpu_tick_set_limit(void *opaque, uint64_t limit)
 274 {
 275     ptimer_set_limit(opaque, -limit, 0);
 276 }
 277
 278 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 279 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 280 static const int ide_irq[2] = { 14, 15 };
 281
 282 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 283 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 284
 285 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 286 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 287
 288 static fdctrl_t *floppy_controller;
 289
 290 static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
 291                               uint32_t addr, uint32_t size, int type)
 292 {
 293     DPRINTF("Mapping region %d registers at %08x\n", region_num, addr);
 294     switch (region_num) {
 295     case 0:
 296         isa_mmio_init(addr, 0x1000000);
 297         break;
 298     case 1:
 299         isa_mmio_init(addr, 0x800000);
 300         break;
 301     }
 302 }
 303
 304 /* EBUS (Eight bit bus) bridge */
 305 static void
 306 pci_ebus_init(PCIBus *bus, int devfn)
 307 {
 308     PCIDevice *s;
 309
 310     s = pci_register_device(bus, "EBUS", sizeof(*s), devfn, NULL, NULL);
 311     pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
 312     pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
 313     s->config[0x04] = 0x06; // command = bus master, pci mem
 314     s->config[0x05] = 0x00;
 315     s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 316     s->config[0x07] = 0x03; // status = medium devsel
 317     s->config[0x08] = 0x01; // revision
 318     s->config[0x09] = 0x00; // programming i/f
 319     pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
 320     s->config[0x0D] = 0x0a; // latency_timer
 321     s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 322
 323     pci_register_io_region(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM,
 324                            ebus_mmio_mapfunc);
 325     pci_register_io_region(s, 1, 0x800000,  PCI_ADDRESS_SPACE_MEM,
 326                            ebus_mmio_mapfunc);
 327 }
 328
 329 static void sun4uv_init(ram_addr_t RAM_size,
 330                         const char *boot_devices,
 331                         const char *kernel_filename, const char *kernel_cmdline,
 332                         const char *initrd_filename, const char *cpu_model,
 333                         const struct hwdef *hwdef)
 334 {
 335     CPUState *env;
 336     char buf[1024];
 337     m48t59_t *nvram;
 338     int ret, linux_boot;
 339     unsigned int i;
 340     ram_addr_t ram_offset, prom_offset;
 341     long initrd_size, kernel_size;
 342     PCIBus *pci_bus, *pci_bus2, *pci_bus3;
 343     QEMUBH *bh;
 344     qemu_irq *irq;
 345     int drive_index;
 346     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 347     BlockDriverState *fd[MAX_FD];
 348     void *fw_cfg;
 349     ResetData *reset_info;
 350
 351     linux_boot = (kernel_filename != NULL);
 352
 353     /* init CPUs */
 354     if (!cpu_model)
 355         cpu_model = hwdef->default_cpu_model;
 356
 357     env = cpu_init(cpu_model);
 358     if (!env) {
 359         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 360         exit(1);
 361     }
 362     bh = qemu_bh_new(tick_irq, env);
 363     env->tick = ptimer_init(bh);
 364     ptimer_set_period(env->tick, 1ULL);
 365
 366     bh = qemu_bh_new(stick_irq, env);
 367     env->stick = ptimer_init(bh);
 368     ptimer_set_period(env->stick, 1ULL);
 369
 370     bh = qemu_bh_new(hstick_irq, env);
 371     env->hstick = ptimer_init(bh);
 372     ptimer_set_period(env->hstick, 1ULL);
 373
 374     reset_info = qemu_mallocz(sizeof(ResetData));
 375     reset_info->env = env;
 376     reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
 377     qemu_register_reset(main_cpu_reset, reset_info);
 378     main_cpu_reset(reset_info);
 379     // Override warm reset address with cold start address
 380     env->pc = hwdef->prom_addr + 0x20ULL;
 381     env->npc = env->pc + 4;
 382
 383     /* allocate RAM */
 384     ram_offset = qemu_ram_alloc(RAM_size);
 385     cpu_register_physical_memory(0, RAM_size, ram_offset);
 386
 387     prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
 388     cpu_register_physical_memory(hwdef->prom_addr,
 389                                  (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
 390                                  TARGET_PAGE_MASK,
 391                                  prom_offset | IO_MEM_ROM);
 392
 393     if (bios_name == NULL)
 394         bios_name = PROM_FILENAME;
 395     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 396     ret = load_elf(buf, hwdef->prom_addr - PROM_VADDR, NULL, NULL, NULL);
 397     if (ret < 0) {
 398         ret = load_image_targphys(buf, hwdef->prom_addr,
 399                                   (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
 400                                   TARGET_PAGE_MASK);
 401         if (ret < 0) {
 402             fprintf(stderr, "qemu: could not load prom '%s'\n",
 403                     buf);
 404             exit(1);
 405         }
 406     }
 407
 408     kernel_size = 0;
 409     initrd_size = 0;
 410     if (linux_boot) {
 411         /* XXX: put correct offset */
 412         kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
 413         if (kernel_size < 0)
 414             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 415                                     ram_size - KERNEL_LOAD_ADDR);
 416         if (kernel_size < 0)
 417             kernel_size = load_image_targphys(kernel_filename,
 418                                               KERNEL_LOAD_ADDR,
 419                                               ram_size - KERNEL_LOAD_ADDR);
 420         if (kernel_size < 0) {
 421             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 422                     kernel_filename);
 423             exit(1);
 424         }
 425
 426         /* load initrd */
 427         if (initrd_filename) {
 428             initrd_size = load_image_targphys(initrd_filename,
 429                                               INITRD_LOAD_ADDR,
 430                                               ram_size - INITRD_LOAD_ADDR);
 431             if (initrd_size < 0) {
 432                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 433                         initrd_filename);
 434                 exit(1);
 435             }
 436         }
 437         if (initrd_size > 0) {
 438             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 439                 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
 440                     stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 441                     stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
 442                     break;
 443                 }
 444             }
 445         }
 446     }
 447     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL, &pci_bus2,
 448                            &pci_bus3);
 449     isa_mem_base = VGA_BASE;
 450     pci_vga_init(pci_bus, 0, 0);
 451
 452     // XXX Should be pci_bus3
 453     pci_ebus_init(pci_bus, -1);
 454
 455     i = 0;
 456     if (hwdef->console_serial_base) {
 457         serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
 458                        serial_hds[i], 1);
 459         i++;
 460     }
 461     for(; i < MAX_SERIAL_PORTS; i++) {
 462         if (serial_hds[i]) {
 463             serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
 464                         serial_hds[i]);
 465         }
 466     }
 467
 468     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 469         if (parallel_hds[i]) {
 470             parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
 471                           parallel_hds[i]);
 472         }
 473     }
 474
 475     for(i = 0; i < nb_nics; i++)
 476         pci_nic_init(pci_bus, &nd_table[i], -1, "ne2k_pci");
 477
 478     irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
 479     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 480         fprintf(stderr, "qemu: too many IDE bus\n");
 481         exit(1);
 482     }
 483     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 484         drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS,
 485                                       i % MAX_IDE_DEVS);
 486        if (drive_index != -1)
 487            hd[i] = drives_table[drive_index].bdrv;
 488        else
 489            hd[i] = NULL;
 490     }
 491
 492     pci_cmd646_ide_init(pci_bus, hd, 1);
 493
 494     /* FIXME: wire up interrupts.  */
 495     i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
 496     for(i = 0; i < MAX_FD; i++) {
 497         drive_index = drive_get_index(IF_FLOPPY, 0, i);
 498        if (drive_index != -1)
 499            fd[i] = drives_table[drive_index].bdrv;
 500        else
 501            fd[i] = NULL;
 502     }
 503     floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);
 504     nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
 505     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 506                            KERNEL_LOAD_ADDR, kernel_size,
 507                            kernel_cmdline,
 508                            INITRD_LOAD_ADDR, initrd_size,
 509                            /* XXX: need an option to load a NVRAM image */
 510                            0,
 511                            graphic_width, graphic_height, graphic_depth,
 512                            (uint8_t *)&nd_table[0].macaddr);
 513
 514     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 515     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 516     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 517     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 518     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
 519     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 520     if (kernel_cmdline) {
 521         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 522         pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
 523     } else {
 524         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 525     }
 526     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
 527     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 528     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
 529     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 530 }
 531
 532 enum {
 533     sun4u_id = 0,
 534     sun4v_id = 64,
 535     niagara_id,
 536 };
 537
 538 static const struct hwdef hwdefs[] = {
 539     /* Sun4u generic PC-like machine */
 540     {
 541         .default_cpu_model = "TI UltraSparc II",
 542         .machine_id = sun4u_id,
 543         .prom_addr = 0x1fff0000000ULL,
 544         .console_serial_base = 0,
 545     },
 546     /* Sun4v generic PC-like machine */
 547     {
 548         .default_cpu_model = "Sun UltraSparc T1",
 549         .machine_id = sun4v_id,
 550         .prom_addr = 0x1fff0000000ULL,
 551         .console_serial_base = 0,
 552     },
 553     /* Sun4v generic Niagara machine */
 554     {
 555         .default_cpu_model = "Sun UltraSparc T1",
 556         .machine_id = niagara_id,
 557         .prom_addr = 0xfff0000000ULL,
 558         .console_serial_base = 0xfff0c2c000ULL,
 559     },
 560 };
 561
 562 /* Sun4u hardware initialisation */
 563 static void sun4u_init(ram_addr_t RAM_size,
 564                        const char *boot_devices,
 565                        const char *kernel_filename, const char *kernel_cmdline,
 566                        const char *initrd_filename, const char *cpu_model)
 567 {
 568     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 569                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 570 }
 571
 572 /* Sun4v hardware initialisation */
 573 static void sun4v_init(ram_addr_t RAM_size,
 574                        const char *boot_devices,
 575                        const char *kernel_filename, const char *kernel_cmdline,
 576                        const char *initrd_filename, const char *cpu_model)
 577 {
 578     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 579                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 580 }
 581
 582 /* Niagara hardware initialisation */
 583 static void niagara_init(ram_addr_t RAM_size,
 584                          const char *boot_devices,
 585                          const char *kernel_filename, const char *kernel_cmdline,
 586                          const char *initrd_filename, const char *cpu_model)
 587 {
 588     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 589                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
 590 }
 591
 592 QEMUMachine sun4u_machine = {
 593     .name = "sun4u",
 594     .desc = "Sun4u platform",
 595     .init = sun4u_init,
 596     .max_cpus = 1, // XXX for now
 597 };
 598
 599 QEMUMachine sun4v_machine = {
 600     .name = "sun4v",
 601     .desc = "Sun4v platform",
 602     .init = sun4v_init,
 603     .max_cpus = 1, // XXX for now
 604 };
 605
 606 QEMUMachine niagara_machine = {
 607     .name = "Niagara",
 608     .desc = "Sun4v platform, Niagara",
 609     .init = niagara_init,
 610     .max_cpus = 1, // XXX for now
 611 };