hw/arm/msf2-soc.c

   1 /*
   2  * SmartFusion2 SoC emulation.
   3  *
   4  * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qapi/error.h"
  27 #include "qemu-common.h"
  28 #include "hw/arm/arm.h"
  29 #include "exec/address-spaces.h"
  30 #include "hw/char/serial.h"
  31 #include "hw/boards.h"
  32 #include "sysemu/block-backend.h"
  33 #include "qemu/cutils.h"
  34 #include "hw/arm/msf2-soc.h"
  35 #include "hw/misc/unimp.h"
  36
  37 #define MSF2_TIMER_BASE       0x40004000
  38 #define MSF2_SYSREG_BASE      0x40038000
  39
  40 #define ENVM_BASE_ADDRESS     0x60000000
  41
  42 #define SRAM_BASE_ADDRESS     0x20000000
  43
  44 #define MSF2_ENVM_MAX_SIZE    (512 * K_BYTE)
  45
  46 /*
  47  * eSRAM max size is 80k without SECDED(Single error correction and
  48  * dual error detection) feature and 64k with SECDED.
  49  * We do not support SECDED now.
  50  */
  51 #define MSF2_ESRAM_MAX_SIZE       (80 * K_BYTE)
  52
  53 static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
  54 static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
  55
  56 static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
  57 static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
  58 static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };
  59
  60 static void m2sxxx_soc_initfn(Object *obj)
  61 {
  62     MSF2State *s = MSF2_SOC(obj);
  63     int i;
  64
  65     object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
  66     qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
  67
  68     object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
  69     qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
  70
  71     object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
  72     qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
  73
  74     for (i = 0; i < MSF2_NUM_SPIS; i++) {
  75         object_initialize(&s->spi[i], sizeof(s->spi[i]),
  76                           TYPE_MSS_SPI);
  77         qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
  78     }
  79 }
  80
  81 static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
  82 {
  83     MSF2State *s = MSF2_SOC(dev_soc);
  84     DeviceState *dev, *armv7m;
  85     SysBusDevice *busdev;
  86     Error *err = NULL;
  87     int i;
  88
  89     MemoryRegion *system_memory = get_system_memory();
  90     MemoryRegion *nvm = g_new(MemoryRegion, 1);
  91     MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
  92     MemoryRegion *sram = g_new(MemoryRegion, 1);
  93
  94     memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size,
  95                            &error_fatal);
  96     /*
  97      * On power-on, the eNVM region 0x60000000 is automatically
  98      * remapped to the Cortex-M3 processor executable region
  99      * start address (0x0). We do not support remapping other eNVM,
 100      * eSRAM and DDR regions by guest(via Sysreg) currently.
 101      */
 102     memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM",
 103                              nvm, 0, s->envm_size);
 104
 105     memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
 106     memory_region_add_subregion(system_memory, 0, nvm_alias);
 107
 108     memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
 109                            &error_fatal);
 110     memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
 111
 112     armv7m = DEVICE(&s->armv7m);
 113     qdev_prop_set_uint32(armv7m, "num-irq", 81);
 114     qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
 115     object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
 116                                      "memory", &error_abort);
 117     object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
 118     if (err != NULL) {
 119         error_propagate(errp, err);
 120         return;
 121     }
 122
 123     if (!s->m3clk) {
 124         error_setg(errp, "Invalid m3clk value");
 125         error_append_hint(errp, "m3clk can not be zero\n");
 126         return;
 127     }
 128     system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
 129
 130     for (i = 0; i < MSF2_NUM_UARTS; i++) {
 131         if (serial_hds[i]) {
 132             serial_mm_init(get_system_memory(), uart_addr[i], 2,
 133                            qdev_get_gpio_in(armv7m, uart_irq[i]),
 134                            115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
 135         }
 136     }
 137
 138     dev = DEVICE(&s->timer);
 139     /* APB0 clock is the timer input clock */
 140     qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
 141     object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
 142     if (err != NULL) {
 143         error_propagate(errp, err);
 144         return;
 145     }
 146     busdev = SYS_BUS_DEVICE(dev);
 147     sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
 148     sysbus_connect_irq(busdev, 0,
 149                            qdev_get_gpio_in(armv7m, timer_irq[0]));
 150     sysbus_connect_irq(busdev, 1,
 151                            qdev_get_gpio_in(armv7m, timer_irq[1]));
 152
 153     dev = DEVICE(&s->sysreg);
 154     qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);
 155     qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);
 156     object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
 157     if (err != NULL) {
 158         error_propagate(errp, err);
 159         return;
 160     }
 161     busdev = SYS_BUS_DEVICE(dev);
 162     sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
 163
 164     for (i = 0; i < MSF2_NUM_SPIS; i++) {
 165         gchar *bus_name;
 166
 167         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
 168         if (err != NULL) {
 169             error_propagate(errp, err);
 170             return;
 171         }
 172
 173         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
 174         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 175                            qdev_get_gpio_in(armv7m, spi_irq[i]));
 176
 177         /* Alias controller SPI bus to the SoC itself */
 178         bus_name = g_strdup_printf("spi%d", i);
 179         object_property_add_alias(OBJECT(s), bus_name,
 180                                   OBJECT(&s->spi[i]), "spi",
 181                                   &error_abort);
 182         g_free(bus_name);
 183     }
 184
 185     /* Below devices are not modelled yet. */
 186     create_unimplemented_device("i2c_0", 0x40002000, 0x1000);
 187     create_unimplemented_device("dma", 0x40003000, 0x1000);
 188     create_unimplemented_device("watchdog", 0x40005000, 0x1000);
 189     create_unimplemented_device("i2c_1", 0x40012000, 0x1000);
 190     create_unimplemented_device("gpio", 0x40013000, 0x1000);
 191     create_unimplemented_device("hs-dma", 0x40014000, 0x1000);
 192     create_unimplemented_device("can", 0x40015000, 0x1000);
 193     create_unimplemented_device("rtc", 0x40017000, 0x1000);
 194     create_unimplemented_device("apb_config", 0x40020000, 0x10000);
 195     create_unimplemented_device("emac", 0x40041000, 0x1000);
 196     create_unimplemented_device("usb", 0x40043000, 0x1000);
 197 }
 198
 199 static Property m2sxxx_soc_properties[] = {
 200     /*
 201      * part name specifies the type of SmartFusion2 device variant(this
 202      * property is for information purpose only.
 203      */
 204     DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),
 205     DEFINE_PROP_STRING("part-name", MSF2State, part_name),
 206     DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
 207     DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
 208                         MSF2_ESRAM_MAX_SIZE),
 209     /* Libero GUI shows 100Mhz as default for clocks */
 210     DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
 211     /* default divisors in Libero GUI */
 212     DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
 213     DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
 214     DEFINE_PROP_END_OF_LIST(),
 215 };
 216
 217 static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
 218 {
 219     DeviceClass *dc = DEVICE_CLASS(klass);
 220
 221     dc->realize = m2sxxx_soc_realize;
 222     dc->props = m2sxxx_soc_properties;
 223 }
 224
 225 static const TypeInfo m2sxxx_soc_info = {
 226     .name          = TYPE_MSF2_SOC,
 227     .parent        = TYPE_SYS_BUS_DEVICE,
 228     .instance_size = sizeof(MSF2State),
 229     .instance_init = m2sxxx_soc_initfn,
 230     .class_init    = m2sxxx_soc_class_init,
 231 };
 232
 233 static void m2sxxx_soc_types(void)
 234 {
 235     type_register_static(&m2sxxx_soc_info);
 236 }
 237
 238 type_init(m2sxxx_soc_types)