target-microblaze/helper.c

   1 /*
   2  *  MicroBlaze helper routines.
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <stdio.h>
  21 #include <string.h>
  22 #include <assert.h>
  23
  24 #include "config.h"
  25 #include "cpu.h"
  26 #include "exec-all.h"
  27 #include "host-utils.h"
  28
  29 #define D(x)
  30 #define DMMU(x)
  31
  32 #if defined(CONFIG_USER_ONLY)
  33
  34 void do_interrupt (CPUState *env)
  35 {
  36     env->exception_index = -1;
  37     env->regs[14] = env->sregs[SR_PC];
  38 }
  39
  40 int cpu_mb_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
  41                              int mmu_idx, int is_softmmu)
  42 {
  43     env->exception_index = 0xaa;
  44     cpu_dump_state(env, stderr, fprintf, 0);
  45     return 1;
  46 }
  47
  48 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
  49 {
  50     return addr;
  51 }
  52
  53 #else /* !CONFIG_USER_ONLY */
  54
  55 int cpu_mb_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
  56                                int mmu_idx, int is_softmmu)
  57 {
  58     unsigned int hit;
  59     unsigned int mmu_available;
  60     int r = 1;
  61     int prot;
  62
  63     mmu_available = 0;
  64     if (env->pvr.regs[0] & PVR0_USE_MMU) {
  65         mmu_available = 1;
  66         if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
  67             && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
  68             mmu_available = 0;
  69         }
  70     }
  71
  72     /* Translate if the MMU is available and enabled.  */
  73     if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
  74         target_ulong vaddr, paddr;
  75         struct microblaze_mmu_lookup lu;
  76
  77         hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
  78         if (hit) {
  79             vaddr = address & TARGET_PAGE_MASK;
  80             paddr = lu.paddr + vaddr - lu.vaddr;
  81
  82             DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",
  83                      mmu_idx, vaddr, paddr, lu.prot));
  84             r = tlb_set_page(env, vaddr,
  85                              paddr, lu.prot, mmu_idx, is_softmmu);
  86         } else {
  87             env->sregs[SR_EAR] = address;
  88             DMMU(qemu_log("mmu=%d miss v=%x\n", mmu_idx, address));
  89
  90             switch (lu.err) {
  91                 case ERR_PROT:
  92                     env->sregs[SR_ESR] = rw == 2 ? 17 : 16;
  93                     env->sregs[SR_ESR] |= (rw == 1) << 10;
  94                     break;
  95                 case ERR_MISS:
  96                     env->sregs[SR_ESR] = rw == 2 ? 19 : 18;
  97                     env->sregs[SR_ESR] |= (rw == 1) << 10;
  98                     break;
  99                 default:
 100                     abort();
 101                     break;
 102             }
 103
 104             if (env->exception_index == EXCP_MMU) {
 105                 cpu_abort(env, "recursive faults\n");
 106             }
 107
 108             /* TLB miss.  */
 109             env->exception_index = EXCP_MMU;
 110         }
 111     } else {
 112         /* MMU disabled or not available.  */
 113         address &= TARGET_PAGE_MASK;
 114         prot = PAGE_BITS;
 115         r = tlb_set_page(env, address, address, prot, mmu_idx, is_softmmu);
 116     }
 117     return r;
 118 }
 119
 120 void do_interrupt(CPUState *env)
 121 {
 122     uint32_t t;
 123
 124     /* IMM flag cannot propagate accross a branch and into the dslot.  */
 125     assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
 126     assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
 127 /*    assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions.  */
 128     switch (env->exception_index) {
 129         case EXCP_HW_EXCP:
 130             if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
 131                 qemu_log("Exception raised on system without exceptions!\n");
 132                 return;
 133             }
 134
 135             env->regs[17] = env->sregs[SR_PC] + 4;
 136             env->sregs[SR_ESR] &= ~(1 << 12);
 137
 138             /* Exception breaks branch + dslot sequence?  */
 139             if (env->iflags & D_FLAG) {
 140                 env->sregs[SR_ESR] |= 1 << 12 ;
 141                 env->sregs[SR_BTR] = env->btarget;
 142             }
 143
 144             /* Disable the MMU.  */
 145             t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 146             env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 147             env->sregs[SR_MSR] |= t;
 148             /* Exception in progress.  */
 149             env->sregs[SR_MSR] |= MSR_EIP;
 150
 151             qemu_log_mask(CPU_LOG_INT,
 152                           "hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
 153                           env->sregs[SR_PC], env->sregs[SR_EAR],
 154                           env->sregs[SR_ESR], env->iflags);
 155             log_cpu_state_mask(CPU_LOG_INT, env, 0);
 156             env->iflags &= ~(IMM_FLAG | D_FLAG);
 157             env->sregs[SR_PC] = 0x20;
 158             break;
 159
 160         case EXCP_MMU:
 161             env->regs[17] = env->sregs[SR_PC];
 162
 163             env->sregs[SR_ESR] &= ~(1 << 12);
 164             /* Exception breaks branch + dslot sequence?  */
 165             if (env->iflags & D_FLAG) {
 166                 D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
 167                 env->sregs[SR_ESR] |= 1 << 12 ;
 168                 env->sregs[SR_BTR] = env->btarget;
 169
 170                 /* Reexecute the branch.  */
 171                 env->regs[17] -= 4;
 172                 /* was the branch immprefixed?.  */
 173                 if (env->bimm) {
 174                     qemu_log_mask(CPU_LOG_INT,
 175                                   "bimm exception at pc=%x iflags=%x\n",
 176                                   env->sregs[SR_PC], env->iflags);
 177                     env->regs[17] -= 4;
 178                     log_cpu_state_mask(CPU_LOG_INT, env, 0);
 179                 }
 180             } else if (env->iflags & IMM_FLAG) {
 181                 D(qemu_log("IMM_FLAG set at exception\n"));
 182                 env->regs[17] -= 4;
 183             }
 184
 185             /* Disable the MMU.  */
 186             t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 187             env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 188             env->sregs[SR_MSR] |= t;
 189             /* Exception in progress.  */
 190             env->sregs[SR_MSR] |= MSR_EIP;
 191
 192             qemu_log_mask(CPU_LOG_INT,
 193                           "exception at pc=%x ear=%x iflags=%x\n",
 194                           env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
 195             log_cpu_state_mask(CPU_LOG_INT, env, 0);
 196             env->iflags &= ~(IMM_FLAG | D_FLAG);
 197             env->sregs[SR_PC] = 0x20;
 198             break;
 199
 200         case EXCP_IRQ:
 201             assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)));
 202             assert(env->sregs[SR_MSR] & MSR_IE);
 203             assert(!(env->iflags & D_FLAG));
 204
 205             t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 206
 207 #if 0
 208 #include "disas.h"
 209
 210 /* Useful instrumentation when debugging interrupt issues in either
 211    the models or in sw.  */
 212             {
 213                 const char *sym;
 214
 215                 sym = lookup_symbol(env->sregs[SR_PC]);
 216                 if (sym
 217                     && (!strcmp("netif_rx", sym)
 218                         || !strcmp("process_backlog", sym))) {
 219
 220                     qemu_log(
 221                          "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
 222                          env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
 223                          sym);
 224
 225                     log_cpu_state(env, 0);
 226                 }
 227             }
 228 #endif
 229             qemu_log_mask(CPU_LOG_INT,
 230                          "interrupt at pc=%x msr=%x %x iflags=%x\n",
 231                          env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
 232
 233             env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
 234                                     | MSR_UM | MSR_IE);
 235             env->sregs[SR_MSR] |= t;
 236
 237             env->regs[14] = env->sregs[SR_PC];
 238             env->sregs[SR_PC] = 0x10;
 239             //log_cpu_state_mask(CPU_LOG_INT, env, 0);
 240             break;
 241
 242         case EXCP_BREAK:
 243         case EXCP_HW_BREAK:
 244             assert(!(env->iflags & IMM_FLAG));
 245             assert(!(env->iflags & D_FLAG));
 246             t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 247             qemu_log_mask(CPU_LOG_INT,
 248                         "break at pc=%x msr=%x %x iflags=%x\n",
 249                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
 250             log_cpu_state_mask(CPU_LOG_INT, env, 0);
 251             env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 252             env->sregs[SR_MSR] |= t;
 253             env->sregs[SR_MSR] |= MSR_BIP;
 254             if (env->exception_index == EXCP_HW_BREAK) {
 255                 env->regs[16] = env->sregs[SR_PC];
 256                 env->sregs[SR_MSR] |= MSR_BIP;
 257                 env->sregs[SR_PC] = 0x18;
 258             } else
 259                 env->sregs[SR_PC] = env->btarget;
 260             break;
 261         default:
 262             cpu_abort(env, "unhandled exception type=%d\n",
 263                       env->exception_index);
 264             break;
 265     }
 266 }
 267
 268 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
 269 {
 270     target_ulong vaddr, paddr = 0;
 271     struct microblaze_mmu_lookup lu;
 272     unsigned int hit;
 273
 274     if (env->sregs[SR_MSR] & MSR_VM) {
 275         hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
 276         if (hit) {
 277             vaddr = addr & TARGET_PAGE_MASK;
 278             paddr = lu.paddr + vaddr - lu.vaddr;
 279         } else
 280             paddr = 0; /* ???.  */
 281     } else
 282         paddr = addr & TARGET_PAGE_MASK;
 283
 284     return paddr;
 285 }
 286 #endif