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hw: set interrupts using pci irq wrappers
[qemu.git] / hw / usb / hcd-xhci.c
blobcffefd7227caea510eb8de72948133afc3d3dcf4
1 /*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include "hw/hw.h"
22 #include "qemu/timer.h"
23 #include "hw/usb.h"
24 #include "hw/pci/pci.h"
25 #include "hw/pci/msi.h"
26 #include "hw/pci/msix.h"
27 #include "trace.h"
28
29 //#define DEBUG_XHCI
30 //#define DEBUG_DATA
31
32 #ifdef DEBUG_XHCI
33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
34 #else
35 #define DPRINTF(...) do {} while (0)
36 #endif
37 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
38 __func__, __LINE__, _msg); abort(); } while (0)
39
40 #define MAXPORTS_2 15
41 #define MAXPORTS_3 15
42
43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
44 #define MAXSLOTS 64
45 #define MAXINTRS 16
46
47 #define TD_QUEUE 24
48
49 /* Very pessimistic, let's hope it's enough for all cases */
50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
51 /* Do not deliver ER Full events. NEC's driver does some things not bound
52 * to the specs when it gets them */
53 #define ER_FULL_HACK
54
55 #define LEN_CAP 0x40
56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
59
60 #define OFF_OPER LEN_CAP
61 #define OFF_RUNTIME 0x1000
62 #define OFF_DOORBELL 0x2000
63 #define OFF_MSIX_TABLE 0x3000
64 #define OFF_MSIX_PBA 0x3800
65 /* must be power of 2 */
66 #define LEN_REGS 0x4000
67
68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
69 #error Increase OFF_RUNTIME
70 #endif
71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
72 #error Increase OFF_DOORBELL
73 #endif
74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
75 # error Increase LEN_REGS
76 #endif
77
78 /* bit definitions */
79 #define USBCMD_RS (1<<0)
80 #define USBCMD_HCRST (1<<1)
81 #define USBCMD_INTE (1<<2)
82 #define USBCMD_HSEE (1<<3)
83 #define USBCMD_LHCRST (1<<7)
84 #define USBCMD_CSS (1<<8)
85 #define USBCMD_CRS (1<<9)
86 #define USBCMD_EWE (1<<10)
87 #define USBCMD_EU3S (1<<11)
88
89 #define USBSTS_HCH (1<<0)
90 #define USBSTS_HSE (1<<2)
91 #define USBSTS_EINT (1<<3)
92 #define USBSTS_PCD (1<<4)
93 #define USBSTS_SSS (1<<8)
94 #define USBSTS_RSS (1<<9)
95 #define USBSTS_SRE (1<<10)
96 #define USBSTS_CNR (1<<11)
97 #define USBSTS_HCE (1<<12)
98
99
100 #define PORTSC_CCS (1<<0)
101 #define PORTSC_PED (1<<1)
102 #define PORTSC_OCA (1<<3)
103 #define PORTSC_PR (1<<4)
104 #define PORTSC_PLS_SHIFT 5
105 #define PORTSC_PLS_MASK 0xf
106 #define PORTSC_PP (1<<9)
107 #define PORTSC_SPEED_SHIFT 10
108 #define PORTSC_SPEED_MASK 0xf
109 #define PORTSC_SPEED_FULL (1<<10)
110 #define PORTSC_SPEED_LOW (2<<10)
111 #define PORTSC_SPEED_HIGH (3<<10)
112 #define PORTSC_SPEED_SUPER (4<<10)
113 #define PORTSC_PIC_SHIFT 14
114 #define PORTSC_PIC_MASK 0x3
115 #define PORTSC_LWS (1<<16)
116 #define PORTSC_CSC (1<<17)
117 #define PORTSC_PEC (1<<18)
118 #define PORTSC_WRC (1<<19)
119 #define PORTSC_OCC (1<<20)
120 #define PORTSC_PRC (1<<21)
121 #define PORTSC_PLC (1<<22)
122 #define PORTSC_CEC (1<<23)
123 #define PORTSC_CAS (1<<24)
124 #define PORTSC_WCE (1<<25)
125 #define PORTSC_WDE (1<<26)
126 #define PORTSC_WOE (1<<27)
127 #define PORTSC_DR (1<<30)
128 #define PORTSC_WPR (1<<31)
129
130 #define CRCR_RCS (1<<0)
131 #define CRCR_CS (1<<1)
132 #define CRCR_CA (1<<2)
133 #define CRCR_CRR (1<<3)
134
135 #define IMAN_IP (1<<0)
136 #define IMAN_IE (1<<1)
137
138 #define ERDP_EHB (1<<3)
139
140 #define TRB_SIZE 16
141 typedef struct XHCITRB {
142 uint64_t parameter;
143 uint32_t status;
144 uint32_t control;
145 dma_addr_t addr;
146 bool ccs;
147 } XHCITRB;
148
149 enum {
150 PLS_U0 = 0,
151 PLS_U1 = 1,
152 PLS_U2 = 2,
153 PLS_U3 = 3,
154 PLS_DISABLED = 4,
155 PLS_RX_DETECT = 5,
156 PLS_INACTIVE = 6,
157 PLS_POLLING = 7,
158 PLS_RECOVERY = 8,
159 PLS_HOT_RESET = 9,
160 PLS_COMPILANCE_MODE = 10,
161 PLS_TEST_MODE = 11,
162 PLS_RESUME = 15,
163 };
164
165 typedef enum TRBType {
166 TRB_RESERVED = 0,
167 TR_NORMAL,
168 TR_SETUP,
169 TR_DATA,
170 TR_STATUS,
171 TR_ISOCH,
172 TR_LINK,
173 TR_EVDATA,
174 TR_NOOP,
175 CR_ENABLE_SLOT,
176 CR_DISABLE_SLOT,
177 CR_ADDRESS_DEVICE,
178 CR_CONFIGURE_ENDPOINT,
179 CR_EVALUATE_CONTEXT,
180 CR_RESET_ENDPOINT,
181 CR_STOP_ENDPOINT,
182 CR_SET_TR_DEQUEUE,
183 CR_RESET_DEVICE,
184 CR_FORCE_EVENT,
185 CR_NEGOTIATE_BW,
186 CR_SET_LATENCY_TOLERANCE,
187 CR_GET_PORT_BANDWIDTH,
188 CR_FORCE_HEADER,
189 CR_NOOP,
190 ER_TRANSFER = 32,
191 ER_COMMAND_COMPLETE,
192 ER_PORT_STATUS_CHANGE,
193 ER_BANDWIDTH_REQUEST,
194 ER_DOORBELL,
195 ER_HOST_CONTROLLER,
196 ER_DEVICE_NOTIFICATION,
197 ER_MFINDEX_WRAP,
198 /* vendor specific bits */
199 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
200 CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
201 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
202 } TRBType;
203
204 #define CR_LINK TR_LINK
205
206 typedef enum TRBCCode {
207 CC_INVALID = 0,
208 CC_SUCCESS,
209 CC_DATA_BUFFER_ERROR,
210 CC_BABBLE_DETECTED,
211 CC_USB_TRANSACTION_ERROR,
212 CC_TRB_ERROR,
213 CC_STALL_ERROR,
214 CC_RESOURCE_ERROR,
215 CC_BANDWIDTH_ERROR,
216 CC_NO_SLOTS_ERROR,
217 CC_INVALID_STREAM_TYPE_ERROR,
218 CC_SLOT_NOT_ENABLED_ERROR,
219 CC_EP_NOT_ENABLED_ERROR,
220 CC_SHORT_PACKET,
221 CC_RING_UNDERRUN,
222 CC_RING_OVERRUN,
223 CC_VF_ER_FULL,
224 CC_PARAMETER_ERROR,
225 CC_BANDWIDTH_OVERRUN,
226 CC_CONTEXT_STATE_ERROR,
227 CC_NO_PING_RESPONSE_ERROR,
228 CC_EVENT_RING_FULL_ERROR,
229 CC_INCOMPATIBLE_DEVICE_ERROR,
230 CC_MISSED_SERVICE_ERROR,
231 CC_COMMAND_RING_STOPPED,
232 CC_COMMAND_ABORTED,
233 CC_STOPPED,
234 CC_STOPPED_LENGTH_INVALID,
235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
236 CC_ISOCH_BUFFER_OVERRUN = 31,
237 CC_EVENT_LOST_ERROR,
238 CC_UNDEFINED_ERROR,
239 CC_INVALID_STREAM_ID_ERROR,
240 CC_SECONDARY_BANDWIDTH_ERROR,
241 CC_SPLIT_TRANSACTION_ERROR
242 } TRBCCode;
243
244 #define TRB_C (1<<0)
245 #define TRB_TYPE_SHIFT 10
246 #define TRB_TYPE_MASK 0x3f
247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
248
249 #define TRB_EV_ED (1<<2)
250
251 #define TRB_TR_ENT (1<<1)
252 #define TRB_TR_ISP (1<<2)
253 #define TRB_TR_NS (1<<3)
254 #define TRB_TR_CH (1<<4)
255 #define TRB_TR_IOC (1<<5)
256 #define TRB_TR_IDT (1<<6)
257 #define TRB_TR_TBC_SHIFT 7
258 #define TRB_TR_TBC_MASK 0x3
259 #define TRB_TR_BEI (1<<9)
260 #define TRB_TR_TLBPC_SHIFT 16
261 #define TRB_TR_TLBPC_MASK 0xf
262 #define TRB_TR_FRAMEID_SHIFT 20
263 #define TRB_TR_FRAMEID_MASK 0x7ff
264 #define TRB_TR_SIA (1<<31)
265
266 #define TRB_TR_DIR (1<<16)
267
268 #define TRB_CR_SLOTID_SHIFT 24
269 #define TRB_CR_SLOTID_MASK 0xff
270 #define TRB_CR_EPID_SHIFT 16
271 #define TRB_CR_EPID_MASK 0x1f
272
273 #define TRB_CR_BSR (1<<9)
274 #define TRB_CR_DC (1<<9)
275
276 #define TRB_LK_TC (1<<1)
277
278 #define TRB_INTR_SHIFT 22
279 #define TRB_INTR_MASK 0x3ff
280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
281
282 #define EP_TYPE_MASK 0x7
283 #define EP_TYPE_SHIFT 3
284
285 #define EP_STATE_MASK 0x7
286 #define EP_DISABLED (0<<0)
287 #define EP_RUNNING (1<<0)
288 #define EP_HALTED (2<<0)
289 #define EP_STOPPED (3<<0)
290 #define EP_ERROR (4<<0)
291
292 #define SLOT_STATE_MASK 0x1f
293 #define SLOT_STATE_SHIFT 27
294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
295 #define SLOT_ENABLED 0
296 #define SLOT_DEFAULT 1
297 #define SLOT_ADDRESSED 2
298 #define SLOT_CONFIGURED 3
299
300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
302
303 typedef struct XHCIState XHCIState;
304 typedef struct XHCIStreamContext XHCIStreamContext;
305 typedef struct XHCIEPContext XHCIEPContext;
306
307 #define get_field(data, field) \
308 (((data) >> field##_SHIFT) & field##_MASK)
309
310 #define set_field(data, newval, field) do { \
311 uint32_t val = *data; \
312 val &= ~(field##_MASK << field##_SHIFT); \
313 val |= ((newval) & field##_MASK) << field##_SHIFT; \
314 *data = val; \
315 } while (0)
316
317 typedef enum EPType {
318 ET_INVALID = 0,
319 ET_ISO_OUT,
320 ET_BULK_OUT,
321 ET_INTR_OUT,
322 ET_CONTROL,
323 ET_ISO_IN,
324 ET_BULK_IN,
325 ET_INTR_IN,
326 } EPType;
327
328 typedef struct XHCIRing {
329 dma_addr_t dequeue;
330 bool ccs;
331 } XHCIRing;
332
333 typedef struct XHCIPort {
334 XHCIState *xhci;
335 uint32_t portsc;
336 uint32_t portnr;
337 USBPort *uport;
338 uint32_t speedmask;
339 char name[16];
340 MemoryRegion mem;
341 } XHCIPort;
342
343 typedef struct XHCITransfer {
344 XHCIState *xhci;
345 USBPacket packet;
346 QEMUSGList sgl;
347 bool running_async;
348 bool running_retry;
349 bool cancelled;
350 bool complete;
351 bool int_req;
352 unsigned int iso_pkts;
353 unsigned int slotid;
354 unsigned int epid;
355 unsigned int streamid;
356 bool in_xfer;
357 bool iso_xfer;
358 bool timed_xfer;
359
360 unsigned int trb_count;
361 unsigned int trb_alloced;
362 XHCITRB *trbs;
363
364 TRBCCode status;
365
366 unsigned int pkts;
367 unsigned int pktsize;
368 unsigned int cur_pkt;
369
370 uint64_t mfindex_kick;
371 } XHCITransfer;
372
373 struct XHCIStreamContext {
374 dma_addr_t pctx;
375 unsigned int sct;
376 XHCIRing ring;
377 XHCIStreamContext *sstreams;
378 };
379
380 struct XHCIEPContext {
381 XHCIState *xhci;
382 unsigned int slotid;
383 unsigned int epid;
384
385 XHCIRing ring;
386 unsigned int next_xfer;
387 unsigned int comp_xfer;
388 XHCITransfer transfers[TD_QUEUE];
389 XHCITransfer *retry;
390 EPType type;
391 dma_addr_t pctx;
392 unsigned int max_psize;
393 uint32_t state;
394
395 /* streams */
396 unsigned int max_pstreams;
397 bool lsa;
398 unsigned int nr_pstreams;
399 XHCIStreamContext *pstreams;
400
401 /* iso xfer scheduling */
402 unsigned int interval;
403 int64_t mfindex_last;
404 QEMUTimer *kick_timer;
405 };
406
407 typedef struct XHCISlot {
408 bool enabled;
409 bool addressed;
410 dma_addr_t ctx;
411 USBPort *uport;
412 XHCIEPContext * eps[31];
413 } XHCISlot;
414
415 typedef struct XHCIEvent {
416 TRBType type;
417 TRBCCode ccode;
418 uint64_t ptr;
419 uint32_t length;
420 uint32_t flags;
421 uint8_t slotid;
422 uint8_t epid;
423 } XHCIEvent;
424
425 typedef struct XHCIInterrupter {
426 uint32_t iman;
427 uint32_t imod;
428 uint32_t erstsz;
429 uint32_t erstba_low;
430 uint32_t erstba_high;
431 uint32_t erdp_low;
432 uint32_t erdp_high;
433
434 bool msix_used, er_pcs, er_full;
435
436 dma_addr_t er_start;
437 uint32_t er_size;
438 unsigned int er_ep_idx;
439
440 XHCIEvent ev_buffer[EV_QUEUE];
441 unsigned int ev_buffer_put;
442 unsigned int ev_buffer_get;
443
444 } XHCIInterrupter;
445
446 struct XHCIState {
447 /*< private >*/
448 PCIDevice parent_obj;
449 /*< public >*/
450
451 USBBus bus;
452 MemoryRegion mem;
453 MemoryRegion mem_cap;
454 MemoryRegion mem_oper;
455 MemoryRegion mem_runtime;
456 MemoryRegion mem_doorbell;
457
458 /* properties */
459 uint32_t numports_2;
460 uint32_t numports_3;
461 uint32_t numintrs;
462 uint32_t numslots;
463 uint32_t flags;
464
465 /* Operational Registers */
466 uint32_t usbcmd;
467 uint32_t usbsts;
468 uint32_t dnctrl;
469 uint32_t crcr_low;
470 uint32_t crcr_high;
471 uint32_t dcbaap_low;
472 uint32_t dcbaap_high;
473 uint32_t config;
474
475 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)];
476 XHCIPort ports[MAXPORTS];
477 XHCISlot slots[MAXSLOTS];
478 uint32_t numports;
479
480 /* Runtime Registers */
481 int64_t mfindex_start;
482 QEMUTimer *mfwrap_timer;
483 XHCIInterrupter intr[MAXINTRS];
484
485 XHCIRing cmd_ring;
486 };
487
488 #define TYPE_XHCI "nec-usb-xhci"
489
490 #define XHCI(obj) \
491 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI)
492
493 typedef struct XHCIEvRingSeg {
494 uint32_t addr_low;
495 uint32_t addr_high;
496 uint32_t size;
497 uint32_t rsvd;
498 } XHCIEvRingSeg;
499
500 enum xhci_flags {
501 XHCI_FLAG_USE_MSI = 1,
502 XHCI_FLAG_USE_MSI_X,
503 };
504
505 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
506 unsigned int epid, unsigned int streamid);
507 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
508 unsigned int epid);
509 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v);
510 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v);
511
512 static const char *TRBType_names[] = {
513 [TRB_RESERVED] = "TRB_RESERVED",
514 [TR_NORMAL] = "TR_NORMAL",
515 [TR_SETUP] = "TR_SETUP",
516 [TR_DATA] = "TR_DATA",
517 [TR_STATUS] = "TR_STATUS",
518 [TR_ISOCH] = "TR_ISOCH",
519 [TR_LINK] = "TR_LINK",
520 [TR_EVDATA] = "TR_EVDATA",
521 [TR_NOOP] = "TR_NOOP",
522 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
523 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
524 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
525 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
526 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
527 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
528 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
529 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
530 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
531 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
532 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
533 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
534 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
535 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
536 [CR_NOOP] = "CR_NOOP",
537 [ER_TRANSFER] = "ER_TRANSFER",
538 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
539 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
540 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
541 [ER_DOORBELL] = "ER_DOORBELL",
542 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
543 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
544 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
545 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
546 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
547 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
548 };
549
550 static const char *TRBCCode_names[] = {
551 [CC_INVALID] = "CC_INVALID",
552 [CC_SUCCESS] = "CC_SUCCESS",
553 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
554 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
555 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
556 [CC_TRB_ERROR] = "CC_TRB_ERROR",
557 [CC_STALL_ERROR] = "CC_STALL_ERROR",
558 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
559 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
560 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
561 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
562 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
563 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
564 [CC_SHORT_PACKET] = "CC_SHORT_PACKET",
565 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
566 [CC_RING_OVERRUN] = "CC_RING_OVERRUN",
567 [CC_VF_ER_FULL] = "CC_VF_ER_FULL",
568 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
569 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
570 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
571 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
572 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
573 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
574 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
575 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
576 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
577 [CC_STOPPED] = "CC_STOPPED",
578 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
579 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR]
580 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
581 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
582 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
583 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
584 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
585 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
586 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
587 };
588
589 static const char *ep_state_names[] = {
590 [EP_DISABLED] = "disabled",
591 [EP_RUNNING] = "running",
592 [EP_HALTED] = "halted",
593 [EP_STOPPED] = "stopped",
594 [EP_ERROR] = "error",
595 };
596
597 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
598 {
599 if (index >= llen || list[index] == NULL) {
600 return "???";
601 }
602 return list[index];
603 }
604
605 static const char *trb_name(XHCITRB *trb)
606 {
607 return lookup_name(TRB_TYPE(*trb), TRBType_names,
608 ARRAY_SIZE(TRBType_names));
609 }
610
611 static const char *event_name(XHCIEvent *event)
612 {
613 return lookup_name(event->ccode, TRBCCode_names,
614 ARRAY_SIZE(TRBCCode_names));
615 }
616
617 static const char *ep_state_name(uint32_t state)
618 {
619 return lookup_name(state, ep_state_names,
620 ARRAY_SIZE(ep_state_names));
621 }
622
623 static uint64_t xhci_mfindex_get(XHCIState *xhci)
624 {
625 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
626 return (now - xhci->mfindex_start) / 125000;
627 }
628
629 static void xhci_mfwrap_update(XHCIState *xhci)
630 {
631 const uint32_t bits = USBCMD_RS | USBCMD_EWE;
632 uint32_t mfindex, left;
633 int64_t now;
634
635 if ((xhci->usbcmd & bits) == bits) {
636 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
637 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
638 left = 0x4000 - mfindex;
639 timer_mod(xhci->mfwrap_timer, now + left * 125000);
640 } else {
641 timer_del(xhci->mfwrap_timer);
642 }
643 }
644
645 static void xhci_mfwrap_timer(void *opaque)
646 {
647 XHCIState *xhci = opaque;
648 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
649
650 xhci_event(xhci, &wrap, 0);
651 xhci_mfwrap_update(xhci);
652 }
653
654 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
655 {
656 if (sizeof(dma_addr_t) == 4) {
657 return low;
658 } else {
659 return low | (((dma_addr_t)high << 16) << 16);
660 }
661 }
662
663 static inline dma_addr_t xhci_mask64(uint64_t addr)
664 {
665 if (sizeof(dma_addr_t) == 4) {
666 return addr & 0xffffffff;
667 } else {
668 return addr;
669 }
670 }
671
672 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
673 uint32_t *buf, size_t len)
674 {
675 int i;
676
677 assert((len % sizeof(uint32_t)) == 0);
678
679 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len);
680
681 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
682 buf[i] = le32_to_cpu(buf[i]);
683 }
684 }
685
686 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
687 uint32_t *buf, size_t len)
688 {
689 int i;
690 uint32_t tmp[len / sizeof(uint32_t)];
691
692 assert((len % sizeof(uint32_t)) == 0);
693
694 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
695 tmp[i] = cpu_to_le32(buf[i]);
696 }
697 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len);
698 }
699
700 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
701 {
702 int index;
703
704 if (!uport->dev) {
705 return NULL;
706 }
707 switch (uport->dev->speed) {
708 case USB_SPEED_LOW:
709 case USB_SPEED_FULL:
710 case USB_SPEED_HIGH:
711 index = uport->index;
712 break;
713 case USB_SPEED_SUPER:
714 index = uport->index + xhci->numports_2;
715 break;
716 default:
717 return NULL;
718 }
719 return &xhci->ports[index];
720 }
721
722 static void xhci_intx_update(XHCIState *xhci)
723 {
724 PCIDevice *pci_dev = PCI_DEVICE(xhci);
725 int level = 0;
726
727 if (msix_enabled(pci_dev) ||
728 msi_enabled(pci_dev)) {
729 return;
730 }
731
732 if (xhci->intr[0].iman & IMAN_IP &&
733 xhci->intr[0].iman & IMAN_IE &&
734 xhci->usbcmd & USBCMD_INTE) {
735 level = 1;
736 }
737
738 trace_usb_xhci_irq_intx(level);
739 pci_set_irq(pci_dev, level);
740 }
741
742 static void xhci_msix_update(XHCIState *xhci, int v)
743 {
744 PCIDevice *pci_dev = PCI_DEVICE(xhci);
745 bool enabled;
746
747 if (!msix_enabled(pci_dev)) {
748 return;
749 }
750
751 enabled = xhci->intr[v].iman & IMAN_IE;
752 if (enabled == xhci->intr[v].msix_used) {
753 return;
754 }
755
756 if (enabled) {
757 trace_usb_xhci_irq_msix_use(v);
758 msix_vector_use(pci_dev, v);
759 xhci->intr[v].msix_used = true;
760 } else {
761 trace_usb_xhci_irq_msix_unuse(v);
762 msix_vector_unuse(pci_dev, v);
763 xhci->intr[v].msix_used = false;
764 }
765 }
766
767 static void xhci_intr_raise(XHCIState *xhci, int v)
768 {
769 PCIDevice *pci_dev = PCI_DEVICE(xhci);
770
771 xhci->intr[v].erdp_low |= ERDP_EHB;
772 xhci->intr[v].iman |= IMAN_IP;
773 xhci->usbsts |= USBSTS_EINT;
774
775 if (!(xhci->intr[v].iman & IMAN_IE)) {
776 return;
777 }
778
779 if (!(xhci->usbcmd & USBCMD_INTE)) {
780 return;
781 }
782
783 if (msix_enabled(pci_dev)) {
784 trace_usb_xhci_irq_msix(v);
785 msix_notify(pci_dev, v);
786 return;
787 }
788
789 if (msi_enabled(pci_dev)) {
790 trace_usb_xhci_irq_msi(v);
791 msi_notify(pci_dev, v);
792 return;
793 }
794
795 if (v == 0) {
796 trace_usb_xhci_irq_intx(1);
797 pci_irq_assert(pci_dev);
798 }
799 }
800
801 static inline int xhci_running(XHCIState *xhci)
802 {
803 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full;
804 }
805
806 static void xhci_die(XHCIState *xhci)
807 {
808 xhci->usbsts |= USBSTS_HCE;
809 fprintf(stderr, "xhci: asserted controller error\n");
810 }
811
812 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
813 {
814 PCIDevice *pci_dev = PCI_DEVICE(xhci);
815 XHCIInterrupter *intr = &xhci->intr[v];
816 XHCITRB ev_trb;
817 dma_addr_t addr;
818
819 ev_trb.parameter = cpu_to_le64(event->ptr);
820 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
821 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
822 event->flags | (event->type << TRB_TYPE_SHIFT);
823 if (intr->er_pcs) {
824 ev_trb.control |= TRB_C;
825 }
826 ev_trb.control = cpu_to_le32(ev_trb.control);
827
828 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb),
829 event_name(event), ev_trb.parameter,
830 ev_trb.status, ev_trb.control);
831
832 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
833 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE);
834
835 intr->er_ep_idx++;
836 if (intr->er_ep_idx >= intr->er_size) {
837 intr->er_ep_idx = 0;
838 intr->er_pcs = !intr->er_pcs;
839 }
840 }
841
842 static void xhci_events_update(XHCIState *xhci, int v)
843 {
844 XHCIInterrupter *intr = &xhci->intr[v];
845 dma_addr_t erdp;
846 unsigned int dp_idx;
847 bool do_irq = 0;
848
849 if (xhci->usbsts & USBSTS_HCH) {
850 return;
851 }
852
853 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
854 if (erdp < intr->er_start ||
855 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
856 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
857 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
858 v, intr->er_start, intr->er_size);
859 xhci_die(xhci);
860 return;
861 }
862 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
863 assert(dp_idx < intr->er_size);
864
865 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
866 * deadlocks when the ER is full. Hack it by holding off events until
867 * the driver decides to free at least half of the ring */
868 if (intr->er_full) {
869 int er_free = dp_idx - intr->er_ep_idx;
870 if (er_free <= 0) {
871 er_free += intr->er_size;
872 }
873 if (er_free < (intr->er_size/2)) {
874 DPRINTF("xhci_events_update(): event ring still "
875 "more than half full (hack)\n");
876 return;
877 }
878 }
879
880 while (intr->ev_buffer_put != intr->ev_buffer_get) {
881 assert(intr->er_full);
882 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) {
883 DPRINTF("xhci_events_update(): event ring full again\n");
884 #ifndef ER_FULL_HACK
885 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
886 xhci_write_event(xhci, &full, v);
887 #endif
888 do_irq = 1;
889 break;
890 }
891 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get];
892 xhci_write_event(xhci, event, v);
893 intr->ev_buffer_get++;
894 do_irq = 1;
895 if (intr->ev_buffer_get == EV_QUEUE) {
896 intr->ev_buffer_get = 0;
897 }
898 }
899
900 if (do_irq) {
901 xhci_intr_raise(xhci, v);
902 }
903
904 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) {
905 DPRINTF("xhci_events_update(): event ring no longer full\n");
906 intr->er_full = 0;
907 }
908 }
909
910 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v)
911 {
912 XHCIInterrupter *intr;
913 dma_addr_t erdp;
914 unsigned int dp_idx;
915
916 if (v >= xhci->numintrs) {
917 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs);
918 return;
919 }
920 intr = &xhci->intr[v];
921
922 if (intr->er_full) {
923 DPRINTF("xhci_event(): ER full, queueing\n");
924 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
925 fprintf(stderr, "xhci: event queue full, dropping event!\n");
926 return;
927 }
928 intr->ev_buffer[intr->ev_buffer_put++] = *event;
929 if (intr->ev_buffer_put == EV_QUEUE) {
930 intr->ev_buffer_put = 0;
931 }
932 return;
933 }
934
935 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
936 if (erdp < intr->er_start ||
937 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
938 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
939 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
940 v, intr->er_start, intr->er_size);
941 xhci_die(xhci);
942 return;
943 }
944
945 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
946 assert(dp_idx < intr->er_size);
947
948 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) {
949 DPRINTF("xhci_event(): ER full, queueing\n");
950 #ifndef ER_FULL_HACK
951 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
952 xhci_write_event(xhci, &full);
953 #endif
954 intr->er_full = 1;
955 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
956 fprintf(stderr, "xhci: event queue full, dropping event!\n");
957 return;
958 }
959 intr->ev_buffer[intr->ev_buffer_put++] = *event;
960 if (intr->ev_buffer_put == EV_QUEUE) {
961 intr->ev_buffer_put = 0;
962 }
963 } else {
964 xhci_write_event(xhci, event, v);
965 }
966
967 xhci_intr_raise(xhci, v);
968 }
969
970 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
971 dma_addr_t base)
972 {
973 ring->dequeue = base;
974 ring->ccs = 1;
975 }
976
977 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
978 dma_addr_t *addr)
979 {
980 PCIDevice *pci_dev = PCI_DEVICE(xhci);
981
982 while (1) {
983 TRBType type;
984 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE);
985 trb->addr = ring->dequeue;
986 trb->ccs = ring->ccs;
987 le64_to_cpus(&trb->parameter);
988 le32_to_cpus(&trb->status);
989 le32_to_cpus(&trb->control);
990
991 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
992 trb->parameter, trb->status, trb->control);
993
994 if ((trb->control & TRB_C) != ring->ccs) {
995 return 0;
996 }
997
998 type = TRB_TYPE(*trb);
999
1000 if (type != TR_LINK) {
1001 if (addr) {
1002 *addr = ring->dequeue;
1003 }
1004 ring->dequeue += TRB_SIZE;
1005 return type;
1006 } else {
1007 ring->dequeue = xhci_mask64(trb->parameter);
1008 if (trb->control & TRB_LK_TC) {
1009 ring->ccs = !ring->ccs;
1010 }
1011 }
1012 }
1013 }
1014
1015 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
1016 {
1017 PCIDevice *pci_dev = PCI_DEVICE(xhci);
1018 XHCITRB trb;
1019 int length = 0;
1020 dma_addr_t dequeue = ring->dequeue;
1021 bool ccs = ring->ccs;
1022 /* hack to bundle together the two/three TDs that make a setup transfer */
1023 bool control_td_set = 0;
1024
1025 while (1) {
1026 TRBType type;
1027 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE);
1028 le64_to_cpus(&trb.parameter);
1029 le32_to_cpus(&trb.status);
1030 le32_to_cpus(&trb.control);
1031
1032 if ((trb.control & TRB_C) != ccs) {
1033 return -length;
1034 }
1035
1036 type = TRB_TYPE(trb);
1037
1038 if (type == TR_LINK) {
1039 dequeue = xhci_mask64(trb.parameter);
1040 if (trb.control & TRB_LK_TC) {
1041 ccs = !ccs;
1042 }
1043 continue;
1044 }
1045
1046 length += 1;
1047 dequeue += TRB_SIZE;
1048
1049 if (type == TR_SETUP) {
1050 control_td_set = 1;
1051 } else if (type == TR_STATUS) {
1052 control_td_set = 0;
1053 }
1054
1055 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
1056 return length;
1057 }
1058 }
1059 }
1060
1061 static void xhci_er_reset(XHCIState *xhci, int v)
1062 {
1063 XHCIInterrupter *intr = &xhci->intr[v];
1064 XHCIEvRingSeg seg;
1065
1066 if (intr->erstsz == 0) {
1067 /* disabled */
1068 intr->er_start = 0;
1069 intr->er_size = 0;
1070 return;
1071 }
1072 /* cache the (sole) event ring segment location */
1073 if (intr->erstsz != 1) {
1074 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz);
1075 xhci_die(xhci);
1076 return;
1077 }
1078 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
1079 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg));
1080 le32_to_cpus(&seg.addr_low);
1081 le32_to_cpus(&seg.addr_high);
1082 le32_to_cpus(&seg.size);
1083 if (seg.size < 16 || seg.size > 4096) {
1084 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size);
1085 xhci_die(xhci);
1086 return;
1087 }
1088 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
1089 intr->er_size = seg.size;
1090
1091 intr->er_ep_idx = 0;
1092 intr->er_pcs = 1;
1093 intr->er_full = 0;
1094
1095 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n",
1096 v, intr->er_start, intr->er_size);
1097 }
1098
1099 static void xhci_run(XHCIState *xhci)
1100 {
1101 trace_usb_xhci_run();
1102 xhci->usbsts &= ~USBSTS_HCH;
1103 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1104 }
1105
1106 static void xhci_stop(XHCIState *xhci)
1107 {
1108 trace_usb_xhci_stop();
1109 xhci->usbsts |= USBSTS_HCH;
1110 xhci->crcr_low &= ~CRCR_CRR;
1111 }
1112
1113 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count,
1114 dma_addr_t base)
1115 {
1116 XHCIStreamContext *stctx;
1117 unsigned int i;
1118
1119 stctx = g_new0(XHCIStreamContext, count);
1120 for (i = 0; i < count; i++) {
1121 stctx[i].pctx = base + i * 16;
1122 stctx[i].sct = -1;
1123 }
1124 return stctx;
1125 }
1126
1127 static void xhci_reset_streams(XHCIEPContext *epctx)
1128 {
1129 unsigned int i;
1130
1131 for (i = 0; i < epctx->nr_pstreams; i++) {
1132 epctx->pstreams[i].sct = -1;
1133 g_free(epctx->pstreams[i].sstreams);
1134 }
1135 }
1136
1137 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base)
1138 {
1139 assert(epctx->pstreams == NULL);
1140 epctx->nr_pstreams = 2 << epctx->max_pstreams;
1141 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base);
1142 }
1143
1144 static void xhci_free_streams(XHCIEPContext *epctx)
1145 {
1146 int i;
1147
1148 assert(epctx->pstreams != NULL);
1149
1150 if (!epctx->lsa) {
1151 for (i = 0; i < epctx->nr_pstreams; i++) {
1152 g_free(epctx->pstreams[i].sstreams);
1153 }
1154 }
1155 g_free(epctx->pstreams);
1156 epctx->pstreams = NULL;
1157 epctx->nr_pstreams = 0;
1158 }
1159
1160 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx,
1161 unsigned int streamid,
1162 uint32_t *cc_error)
1163 {
1164 XHCIStreamContext *sctx;
1165 dma_addr_t base;
1166 uint32_t ctx[2], sct;
1167
1168 assert(streamid != 0);
1169 if (epctx->lsa) {
1170 if (streamid >= epctx->nr_pstreams) {
1171 *cc_error = CC_INVALID_STREAM_ID_ERROR;
1172 return NULL;
1173 }
1174 sctx = epctx->pstreams + streamid;
1175 } else {
1176 FIXME("secondary streams not implemented yet");
1177 }
1178
1179 if (sctx->sct == -1) {
1180 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx));
1181 sct = (ctx[0] >> 1) & 0x07;
1182 if (epctx->lsa && sct != 1) {
1183 *cc_error = CC_INVALID_STREAM_TYPE_ERROR;
1184 return NULL;
1185 }
1186 sctx->sct = sct;
1187 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]);
1188 xhci_ring_init(epctx->xhci, &sctx->ring, base);
1189 }
1190 return sctx;
1191 }
1192
1193 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
1194 XHCIStreamContext *sctx, uint32_t state)
1195 {
1196 uint32_t ctx[5];
1197 uint32_t ctx2[2];
1198
1199 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1200 ctx[0] &= ~EP_STATE_MASK;
1201 ctx[0] |= state;
1202
1203 /* update ring dequeue ptr */
1204 if (epctx->nr_pstreams) {
1205 if (sctx != NULL) {
1206 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1207 ctx2[0] &= 0xe;
1208 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs;
1209 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16;
1210 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1211 }
1212 } else {
1213 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs;
1214 ctx[3] = (epctx->ring.dequeue >> 16) >> 16;
1215 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
1216 epctx->pctx, state, ctx[3], ctx[2]);
1217 }
1218
1219 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1220 if (epctx->state != state) {
1221 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid,
1222 ep_state_name(epctx->state),
1223 ep_state_name(state));
1224 }
1225 epctx->state = state;
1226 }
1227
1228 static void xhci_ep_kick_timer(void *opaque)
1229 {
1230 XHCIEPContext *epctx = opaque;
1231 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0);
1232 }
1233
1234 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci,
1235 unsigned int slotid,
1236 unsigned int epid)
1237 {
1238 XHCIEPContext *epctx;
1239 int i;
1240
1241 epctx = g_new0(XHCIEPContext, 1);
1242 epctx->xhci = xhci;
1243 epctx->slotid = slotid;
1244 epctx->epid = epid;
1245
1246 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
1247 usb_packet_init(&epctx->transfers[i].packet);
1248 }
1249 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx);
1250
1251 return epctx;
1252 }
1253
1254 static void xhci_init_epctx(XHCIEPContext *epctx,
1255 dma_addr_t pctx, uint32_t *ctx)
1256 {
1257 dma_addr_t dequeue;
1258
1259 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
1260
1261 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
1262 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type);
1263 epctx->pctx = pctx;
1264 epctx->max_psize = ctx[1]>>16;
1265 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
1266 epctx->max_pstreams = (ctx[0] >> 10) & 0xf;
1267 epctx->lsa = (ctx[0] >> 15) & 1;
1268 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
1269 epid/2, epid%2, epctx->max_psize);
1270 if (epctx->max_pstreams) {
1271 xhci_alloc_streams(epctx, dequeue);
1272 } else {
1273 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue);
1274 epctx->ring.ccs = ctx[2] & 1;
1275 }
1276
1277 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff);
1278 }
1279
1280 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
1281 unsigned int epid, dma_addr_t pctx,
1282 uint32_t *ctx)
1283 {
1284 XHCISlot *slot;
1285 XHCIEPContext *epctx;
1286
1287 trace_usb_xhci_ep_enable(slotid, epid);
1288 assert(slotid >= 1 && slotid <= xhci->numslots);
1289 assert(epid >= 1 && epid <= 31);
1290
1291 slot = &xhci->slots[slotid-1];
1292 if (slot->eps[epid-1]) {
1293 xhci_disable_ep(xhci, slotid, epid);
1294 }
1295
1296 epctx = xhci_alloc_epctx(xhci, slotid, epid);
1297 slot->eps[epid-1] = epctx;
1298 xhci_init_epctx(epctx, pctx, ctx);
1299
1300 epctx->mfindex_last = 0;
1301
1302 epctx->state = EP_RUNNING;
1303 ctx[0] &= ~EP_STATE_MASK;
1304 ctx[0] |= EP_RUNNING;
1305
1306 return CC_SUCCESS;
1307 }
1308
1309 static int xhci_ep_nuke_one_xfer(XHCITransfer *t)
1310 {
1311 int killed = 0;
1312
1313 if (t->running_async) {
1314 usb_cancel_packet(&t->packet);
1315 t->running_async = 0;
1316 t->cancelled = 1;
1317 DPRINTF("xhci: cancelling transfer, waiting for it to complete\n");
1318 killed = 1;
1319 }
1320 if (t->running_retry) {
1321 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1];
1322 if (epctx) {
1323 epctx->retry = NULL;
1324 timer_del(epctx->kick_timer);
1325 }
1326 t->running_retry = 0;
1327 }
1328 if (t->trbs) {
1329 g_free(t->trbs);
1330 }
1331
1332 t->trbs = NULL;
1333 t->trb_count = t->trb_alloced = 0;
1334
1335 return killed;
1336 }
1337
1338 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
1339 unsigned int epid)
1340 {
1341 XHCISlot *slot;
1342 XHCIEPContext *epctx;
1343 int i, xferi, killed = 0;
1344 USBEndpoint *ep = NULL;
1345 assert(slotid >= 1 && slotid <= xhci->numslots);
1346 assert(epid >= 1 && epid <= 31);
1347
1348 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
1349
1350 slot = &xhci->slots[slotid-1];
1351
1352 if (!slot->eps[epid-1]) {
1353 return 0;
1354 }
1355
1356 epctx = slot->eps[epid-1];
1357
1358 xferi = epctx->next_xfer;
1359 for (i = 0; i < TD_QUEUE; i++) {
1360 if (epctx->transfers[xferi].packet.ep) {
1361 ep = epctx->transfers[xferi].packet.ep;
1362 }
1363 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi]);
1364 epctx->transfers[xferi].packet.ep = NULL;
1365 xferi = (xferi + 1) % TD_QUEUE;
1366 }
1367 if (ep) {
1368 usb_device_ep_stopped(ep->dev, ep);
1369 }
1370 return killed;
1371 }
1372
1373 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
1374 unsigned int epid)
1375 {
1376 XHCISlot *slot;
1377 XHCIEPContext *epctx;
1378
1379 trace_usb_xhci_ep_disable(slotid, epid);
1380 assert(slotid >= 1 && slotid <= xhci->numslots);
1381 assert(epid >= 1 && epid <= 31);
1382
1383 slot = &xhci->slots[slotid-1];
1384
1385 if (!slot->eps[epid-1]) {
1386 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
1387 return CC_SUCCESS;
1388 }
1389
1390 xhci_ep_nuke_xfers(xhci, slotid, epid);
1391
1392 epctx = slot->eps[epid-1];
1393
1394 if (epctx->nr_pstreams) {
1395 xhci_free_streams(epctx);
1396 }
1397
1398 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED);
1399
1400 timer_free(epctx->kick_timer);
1401 g_free(epctx);
1402 slot->eps[epid-1] = NULL;
1403
1404 return CC_SUCCESS;
1405 }
1406
1407 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1408 unsigned int epid)
1409 {
1410 XHCISlot *slot;
1411 XHCIEPContext *epctx;
1412
1413 trace_usb_xhci_ep_stop(slotid, epid);
1414 assert(slotid >= 1 && slotid <= xhci->numslots);
1415
1416 if (epid < 1 || epid > 31) {
1417 fprintf(stderr, "xhci: bad ep %d\n", epid);
1418 return CC_TRB_ERROR;
1419 }
1420
1421 slot = &xhci->slots[slotid-1];
1422
1423 if (!slot->eps[epid-1]) {
1424 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1425 return CC_EP_NOT_ENABLED_ERROR;
1426 }
1427
1428 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1429 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, "
1430 "data might be lost\n");
1431 }
1432
1433 epctx = slot->eps[epid-1];
1434
1435 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1436
1437 if (epctx->nr_pstreams) {
1438 xhci_reset_streams(epctx);
1439 }
1440
1441 return CC_SUCCESS;
1442 }
1443
1444 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1445 unsigned int epid)
1446 {
1447 XHCISlot *slot;
1448 XHCIEPContext *epctx;
1449
1450 trace_usb_xhci_ep_reset(slotid, epid);
1451 assert(slotid >= 1 && slotid <= xhci->numslots);
1452
1453 if (epid < 1 || epid > 31) {
1454 fprintf(stderr, "xhci: bad ep %d\n", epid);
1455 return CC_TRB_ERROR;
1456 }
1457
1458 slot = &xhci->slots[slotid-1];
1459
1460 if (!slot->eps[epid-1]) {
1461 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1462 return CC_EP_NOT_ENABLED_ERROR;
1463 }
1464
1465 epctx = slot->eps[epid-1];
1466
1467 if (epctx->state != EP_HALTED) {
1468 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n",
1469 epid, epctx->state);
1470 return CC_CONTEXT_STATE_ERROR;
1471 }
1472
1473 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1474 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, "
1475 "data might be lost\n");
1476 }
1477
1478 uint8_t ep = epid>>1;
1479
1480 if (epid & 1) {
1481 ep |= 0x80;
1482 }
1483
1484 if (!xhci->slots[slotid-1].uport ||
1485 !xhci->slots[slotid-1].uport->dev) {
1486 return CC_USB_TRANSACTION_ERROR;
1487 }
1488
1489 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1490
1491 if (epctx->nr_pstreams) {
1492 xhci_reset_streams(epctx);
1493 }
1494
1495 return CC_SUCCESS;
1496 }
1497
1498 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1499 unsigned int epid, unsigned int streamid,
1500 uint64_t pdequeue)
1501 {
1502 XHCISlot *slot;
1503 XHCIEPContext *epctx;
1504 XHCIStreamContext *sctx;
1505 dma_addr_t dequeue;
1506
1507 assert(slotid >= 1 && slotid <= xhci->numslots);
1508
1509 if (epid < 1 || epid > 31) {
1510 fprintf(stderr, "xhci: bad ep %d\n", epid);
1511 return CC_TRB_ERROR;
1512 }
1513
1514 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue);
1515 dequeue = xhci_mask64(pdequeue);
1516
1517 slot = &xhci->slots[slotid-1];
1518
1519 if (!slot->eps[epid-1]) {
1520 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1521 return CC_EP_NOT_ENABLED_ERROR;
1522 }
1523
1524 epctx = slot->eps[epid-1];
1525
1526 if (epctx->state != EP_STOPPED) {
1527 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1528 return CC_CONTEXT_STATE_ERROR;
1529 }
1530
1531 if (epctx->nr_pstreams) {
1532 uint32_t err;
1533 sctx = xhci_find_stream(epctx, streamid, &err);
1534 if (sctx == NULL) {
1535 return err;
1536 }
1537 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf);
1538 sctx->ring.ccs = dequeue & 1;
1539 } else {
1540 sctx = NULL;
1541 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1542 epctx->ring.ccs = dequeue & 1;
1543 }
1544
1545 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED);
1546
1547 return CC_SUCCESS;
1548 }
1549
1550 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
1551 {
1552 XHCIState *xhci = xfer->xhci;
1553 int i;
1554
1555 xfer->int_req = false;
1556 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count);
1557 for (i = 0; i < xfer->trb_count; i++) {
1558 XHCITRB *trb = &xfer->trbs[i];
1559 dma_addr_t addr;
1560 unsigned int chunk = 0;
1561
1562 if (trb->control & TRB_TR_IOC) {
1563 xfer->int_req = true;
1564 }
1565
1566 switch (TRB_TYPE(*trb)) {
1567 case TR_DATA:
1568 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1569 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n");
1570 goto err;
1571 }
1572 /* fallthrough */
1573 case TR_NORMAL:
1574 case TR_ISOCH:
1575 addr = xhci_mask64(trb->parameter);
1576 chunk = trb->status & 0x1ffff;
1577 if (trb->control & TRB_TR_IDT) {
1578 if (chunk > 8 || in_xfer) {
1579 fprintf(stderr, "xhci: invalid immediate data TRB\n");
1580 goto err;
1581 }
1582 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1583 } else {
1584 qemu_sglist_add(&xfer->sgl, addr, chunk);
1585 }
1586 break;
1587 }
1588 }
1589
1590 return 0;
1591
1592 err:
1593 qemu_sglist_destroy(&xfer->sgl);
1594 xhci_die(xhci);
1595 return -1;
1596 }
1597
1598 static void xhci_xfer_unmap(XHCITransfer *xfer)
1599 {
1600 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1601 qemu_sglist_destroy(&xfer->sgl);
1602 }
1603
1604 static void xhci_xfer_report(XHCITransfer *xfer)
1605 {
1606 uint32_t edtla = 0;
1607 unsigned int left;
1608 bool reported = 0;
1609 bool shortpkt = 0;
1610 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1611 XHCIState *xhci = xfer->xhci;
1612 int i;
1613
1614 left = xfer->packet.actual_length;
1615
1616 for (i = 0; i < xfer->trb_count; i++) {
1617 XHCITRB *trb = &xfer->trbs[i];
1618 unsigned int chunk = 0;
1619
1620 switch (TRB_TYPE(*trb)) {
1621 case TR_DATA:
1622 case TR_NORMAL:
1623 case TR_ISOCH:
1624 chunk = trb->status & 0x1ffff;
1625 if (chunk > left) {
1626 chunk = left;
1627 if (xfer->status == CC_SUCCESS) {
1628 shortpkt = 1;
1629 }
1630 }
1631 left -= chunk;
1632 edtla += chunk;
1633 break;
1634 case TR_STATUS:
1635 reported = 0;
1636 shortpkt = 0;
1637 break;
1638 }
1639
1640 if (!reported && ((trb->control & TRB_TR_IOC) ||
1641 (shortpkt && (trb->control & TRB_TR_ISP)) ||
1642 (xfer->status != CC_SUCCESS && left == 0))) {
1643 event.slotid = xfer->slotid;
1644 event.epid = xfer->epid;
1645 event.length = (trb->status & 0x1ffff) - chunk;
1646 event.flags = 0;
1647 event.ptr = trb->addr;
1648 if (xfer->status == CC_SUCCESS) {
1649 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1650 } else {
1651 event.ccode = xfer->status;
1652 }
1653 if (TRB_TYPE(*trb) == TR_EVDATA) {
1654 event.ptr = trb->parameter;
1655 event.flags |= TRB_EV_ED;
1656 event.length = edtla & 0xffffff;
1657 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1658 edtla = 0;
1659 }
1660 xhci_event(xhci, &event, TRB_INTR(*trb));
1661 reported = 1;
1662 if (xfer->status != CC_SUCCESS) {
1663 return;
1664 }
1665 }
1666 }
1667 }
1668
1669 static void xhci_stall_ep(XHCITransfer *xfer)
1670 {
1671 XHCIState *xhci = xfer->xhci;
1672 XHCISlot *slot = &xhci->slots[xfer->slotid-1];
1673 XHCIEPContext *epctx = slot->eps[xfer->epid-1];
1674 uint32_t err;
1675 XHCIStreamContext *sctx;
1676
1677 if (epctx->nr_pstreams) {
1678 sctx = xhci_find_stream(epctx, xfer->streamid, &err);
1679 if (sctx == NULL) {
1680 return;
1681 }
1682 sctx->ring.dequeue = xfer->trbs[0].addr;
1683 sctx->ring.ccs = xfer->trbs[0].ccs;
1684 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED);
1685 } else {
1686 epctx->ring.dequeue = xfer->trbs[0].addr;
1687 epctx->ring.ccs = xfer->trbs[0].ccs;
1688 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED);
1689 }
1690 }
1691
1692 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer,
1693 XHCIEPContext *epctx);
1694
1695 static int xhci_setup_packet(XHCITransfer *xfer)
1696 {
1697 XHCIState *xhci = xfer->xhci;
1698 USBDevice *dev;
1699 USBEndpoint *ep;
1700 int dir;
1701
1702 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
1703
1704 if (xfer->packet.ep) {
1705 ep = xfer->packet.ep;
1706 dev = ep->dev;
1707 } else {
1708 if (!xhci->slots[xfer->slotid-1].uport) {
1709 fprintf(stderr, "xhci: slot %d has no device\n",
1710 xfer->slotid);
1711 return -1;
1712 }
1713 dev = xhci->slots[xfer->slotid-1].uport->dev;
1714 ep = usb_ep_get(dev, dir, xfer->epid >> 1);
1715 }
1716
1717 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */
1718 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid,
1719 xfer->trbs[0].addr, false, xfer->int_req);
1720 usb_packet_map(&xfer->packet, &xfer->sgl);
1721 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1722 xfer->packet.pid, dev->addr, ep->nr);
1723 return 0;
1724 }
1725
1726 static int xhci_complete_packet(XHCITransfer *xfer)
1727 {
1728 if (xfer->packet.status == USB_RET_ASYNC) {
1729 trace_usb_xhci_xfer_async(xfer);
1730 xfer->running_async = 1;
1731 xfer->running_retry = 0;
1732 xfer->complete = 0;
1733 xfer->cancelled = 0;
1734 return 0;
1735 } else if (xfer->packet.status == USB_RET_NAK) {
1736 trace_usb_xhci_xfer_nak(xfer);
1737 xfer->running_async = 0;
1738 xfer->running_retry = 1;
1739 xfer->complete = 0;
1740 xfer->cancelled = 0;
1741 return 0;
1742 } else {
1743 xfer->running_async = 0;
1744 xfer->running_retry = 0;
1745 xfer->complete = 1;
1746 xhci_xfer_unmap(xfer);
1747 }
1748
1749 if (xfer->packet.status == USB_RET_SUCCESS) {
1750 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length);
1751 xfer->status = CC_SUCCESS;
1752 xhci_xfer_report(xfer);
1753 return 0;
1754 }
1755
1756 /* error */
1757 trace_usb_xhci_xfer_error(xfer, xfer->packet.status);
1758 switch (xfer->packet.status) {
1759 case USB_RET_NODEV:
1760 case USB_RET_IOERROR:
1761 xfer->status = CC_USB_TRANSACTION_ERROR;
1762 xhci_xfer_report(xfer);
1763 xhci_stall_ep(xfer);
1764 break;
1765 case USB_RET_STALL:
1766 xfer->status = CC_STALL_ERROR;
1767 xhci_xfer_report(xfer);
1768 xhci_stall_ep(xfer);
1769 break;
1770 case USB_RET_BABBLE:
1771 xfer->status = CC_BABBLE_DETECTED;
1772 xhci_xfer_report(xfer);
1773 xhci_stall_ep(xfer);
1774 break;
1775 default:
1776 fprintf(stderr, "%s: FIXME: status = %d\n", __func__,
1777 xfer->packet.status);
1778 FIXME("unhandled USB_RET_*");
1779 }
1780 return 0;
1781 }
1782
1783 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1784 {
1785 XHCITRB *trb_setup, *trb_status;
1786 uint8_t bmRequestType;
1787
1788 trb_setup = &xfer->trbs[0];
1789 trb_status = &xfer->trbs[xfer->trb_count-1];
1790
1791 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid);
1792
1793 /* at most one Event Data TRB allowed after STATUS */
1794 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1795 trb_status--;
1796 }
1797
1798 /* do some sanity checks */
1799 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1800 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n",
1801 TRB_TYPE(*trb_setup));
1802 return -1;
1803 }
1804 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1805 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n",
1806 TRB_TYPE(*trb_status));
1807 return -1;
1808 }
1809 if (!(trb_setup->control & TRB_TR_IDT)) {
1810 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n");
1811 return -1;
1812 }
1813 if ((trb_setup->status & 0x1ffff) != 8) {
1814 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n",
1815 (trb_setup->status & 0x1ffff));
1816 return -1;
1817 }
1818
1819 bmRequestType = trb_setup->parameter;
1820
1821 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1822 xfer->iso_xfer = false;
1823 xfer->timed_xfer = false;
1824
1825 if (xhci_setup_packet(xfer) < 0) {
1826 return -1;
1827 }
1828 xfer->packet.parameter = trb_setup->parameter;
1829
1830 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1831
1832 xhci_complete_packet(xfer);
1833 if (!xfer->running_async && !xfer->running_retry) {
1834 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0);
1835 }
1836 return 0;
1837 }
1838
1839 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer,
1840 XHCIEPContext *epctx, uint64_t mfindex)
1841 {
1842 uint64_t asap = ((mfindex + epctx->interval - 1) &
1843 ~(epctx->interval-1));
1844 uint64_t kick = epctx->mfindex_last + epctx->interval;
1845
1846 assert(epctx->interval != 0);
1847 xfer->mfindex_kick = MAX(asap, kick);
1848 }
1849
1850 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1851 XHCIEPContext *epctx, uint64_t mfindex)
1852 {
1853 if (xfer->trbs[0].control & TRB_TR_SIA) {
1854 uint64_t asap = ((mfindex + epctx->interval - 1) &
1855 ~(epctx->interval-1));
1856 if (asap >= epctx->mfindex_last &&
1857 asap <= epctx->mfindex_last + epctx->interval * 4) {
1858 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
1859 } else {
1860 xfer->mfindex_kick = asap;
1861 }
1862 } else {
1863 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
1864 & TRB_TR_FRAMEID_MASK;
1865 xfer->mfindex_kick |= mfindex & ~0x3fff;
1866 if (xfer->mfindex_kick < mfindex) {
1867 xfer->mfindex_kick += 0x4000;
1868 }
1869 }
1870 }
1871
1872 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1873 XHCIEPContext *epctx, uint64_t mfindex)
1874 {
1875 if (xfer->mfindex_kick > mfindex) {
1876 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1877 (xfer->mfindex_kick - mfindex) * 125000);
1878 xfer->running_retry = 1;
1879 } else {
1880 epctx->mfindex_last = xfer->mfindex_kick;
1881 timer_del(epctx->kick_timer);
1882 xfer->running_retry = 0;
1883 }
1884 }
1885
1886
1887 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1888 {
1889 uint64_t mfindex;
1890
1891 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
1892
1893 xfer->in_xfer = epctx->type>>2;
1894
1895 switch(epctx->type) {
1896 case ET_INTR_OUT:
1897 case ET_INTR_IN:
1898 xfer->pkts = 0;
1899 xfer->iso_xfer = false;
1900 xfer->timed_xfer = true;
1901 mfindex = xhci_mfindex_get(xhci);
1902 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex);
1903 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1904 if (xfer->running_retry) {
1905 return -1;
1906 }
1907 break;
1908 case ET_BULK_OUT:
1909 case ET_BULK_IN:
1910 xfer->pkts = 0;
1911 xfer->iso_xfer = false;
1912 xfer->timed_xfer = false;
1913 break;
1914 case ET_ISO_OUT:
1915 case ET_ISO_IN:
1916 xfer->pkts = 1;
1917 xfer->iso_xfer = true;
1918 xfer->timed_xfer = true;
1919 mfindex = xhci_mfindex_get(xhci);
1920 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
1921 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1922 if (xfer->running_retry) {
1923 return -1;
1924 }
1925 break;
1926 default:
1927 fprintf(stderr, "xhci: unknown or unhandled EP "
1928 "(type %d, in %d, ep %02x)\n",
1929 epctx->type, xfer->in_xfer, xfer->epid);
1930 return -1;
1931 }
1932
1933 if (xhci_setup_packet(xfer) < 0) {
1934 return -1;
1935 }
1936 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1937
1938 xhci_complete_packet(xfer);
1939 if (!xfer->running_async && !xfer->running_retry) {
1940 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid);
1941 }
1942 return 0;
1943 }
1944
1945 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1946 {
1947 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid);
1948 return xhci_submit(xhci, xfer, epctx);
1949 }
1950
1951 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
1952 unsigned int epid, unsigned int streamid)
1953 {
1954 XHCIStreamContext *stctx;
1955 XHCIEPContext *epctx;
1956 XHCIRing *ring;
1957 USBEndpoint *ep = NULL;
1958 uint64_t mfindex;
1959 int length;
1960 int i;
1961
1962 trace_usb_xhci_ep_kick(slotid, epid, streamid);
1963 assert(slotid >= 1 && slotid <= xhci->numslots);
1964 assert(epid >= 1 && epid <= 31);
1965
1966 if (!xhci->slots[slotid-1].enabled) {
1967 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid);
1968 return;
1969 }
1970 epctx = xhci->slots[slotid-1].eps[epid-1];
1971 if (!epctx) {
1972 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1973 epid, slotid);
1974 return;
1975 }
1976
1977 if (epctx->retry) {
1978 XHCITransfer *xfer = epctx->retry;
1979
1980 trace_usb_xhci_xfer_retry(xfer);
1981 assert(xfer->running_retry);
1982 if (xfer->timed_xfer) {
1983 /* time to kick the transfer? */
1984 mfindex = xhci_mfindex_get(xhci);
1985 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1986 if (xfer->running_retry) {
1987 return;
1988 }
1989 xfer->timed_xfer = 0;
1990 xfer->running_retry = 1;
1991 }
1992 if (xfer->iso_xfer) {
1993 /* retry iso transfer */
1994 if (xhci_setup_packet(xfer) < 0) {
1995 return;
1996 }
1997 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1998 assert(xfer->packet.status != USB_RET_NAK);
1999 xhci_complete_packet(xfer);
2000 } else {
2001 /* retry nak'ed transfer */
2002 if (xhci_setup_packet(xfer) < 0) {
2003 return;
2004 }
2005 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2006 if (xfer->packet.status == USB_RET_NAK) {
2007 return;
2008 }
2009 xhci_complete_packet(xfer);
2010 }
2011 assert(!xfer->running_retry);
2012 epctx->retry = NULL;
2013 }
2014
2015 if (epctx->state == EP_HALTED) {
2016 DPRINTF("xhci: ep halted, not running schedule\n");
2017 return;
2018 }
2019
2020
2021 if (epctx->nr_pstreams) {
2022 uint32_t err;
2023 stctx = xhci_find_stream(epctx, streamid, &err);
2024 if (stctx == NULL) {
2025 return;
2026 }
2027 ring = &stctx->ring;
2028 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING);
2029 } else {
2030 ring = &epctx->ring;
2031 streamid = 0;
2032 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING);
2033 }
2034 assert(ring->dequeue != 0);
2035
2036 while (1) {
2037 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer];
2038 if (xfer->running_async || xfer->running_retry) {
2039 break;
2040 }
2041 length = xhci_ring_chain_length(xhci, ring);
2042 if (length < 0) {
2043 break;
2044 } else if (length == 0) {
2045 break;
2046 }
2047 if (xfer->trbs && xfer->trb_alloced < length) {
2048 xfer->trb_count = 0;
2049 xfer->trb_alloced = 0;
2050 g_free(xfer->trbs);
2051 xfer->trbs = NULL;
2052 }
2053 if (!xfer->trbs) {
2054 xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
2055 xfer->trb_alloced = length;
2056 }
2057 xfer->trb_count = length;
2058
2059 for (i = 0; i < length; i++) {
2060 assert(xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL));
2061 }
2062 xfer->xhci = xhci;
2063 xfer->epid = epid;
2064 xfer->slotid = slotid;
2065 xfer->streamid = streamid;
2066
2067 if (epid == 1) {
2068 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) {
2069 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
2070 ep = xfer->packet.ep;
2071 } else {
2072 fprintf(stderr, "xhci: error firing CTL transfer\n");
2073 }
2074 } else {
2075 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) {
2076 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
2077 ep = xfer->packet.ep;
2078 } else {
2079 if (!xfer->timed_xfer) {
2080 fprintf(stderr, "xhci: error firing data transfer\n");
2081 }
2082 }
2083 }
2084
2085 if (epctx->state == EP_HALTED) {
2086 break;
2087 }
2088 if (xfer->running_retry) {
2089 DPRINTF("xhci: xfer nacked, stopping schedule\n");
2090 epctx->retry = xfer;
2091 break;
2092 }
2093 }
2094 if (ep) {
2095 usb_device_flush_ep_queue(ep->dev, ep);
2096 }
2097 }
2098
2099 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
2100 {
2101 trace_usb_xhci_slot_enable(slotid);
2102 assert(slotid >= 1 && slotid <= xhci->numslots);
2103 xhci->slots[slotid-1].enabled = 1;
2104 xhci->slots[slotid-1].uport = NULL;
2105 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
2106
2107 return CC_SUCCESS;
2108 }
2109
2110 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
2111 {
2112 int i;
2113
2114 trace_usb_xhci_slot_disable(slotid);
2115 assert(slotid >= 1 && slotid <= xhci->numslots);
2116
2117 for (i = 1; i <= 31; i++) {
2118 if (xhci->slots[slotid-1].eps[i-1]) {
2119 xhci_disable_ep(xhci, slotid, i);
2120 }
2121 }
2122
2123 xhci->slots[slotid-1].enabled = 0;
2124 xhci->slots[slotid-1].addressed = 0;
2125 xhci->slots[slotid-1].uport = NULL;
2126 return CC_SUCCESS;
2127 }
2128
2129 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx)
2130 {
2131 USBPort *uport;
2132 char path[32];
2133 int i, pos, port;
2134
2135 port = (slot_ctx[1]>>16) & 0xFF;
2136 port = xhci->ports[port-1].uport->index+1;
2137 pos = snprintf(path, sizeof(path), "%d", port);
2138 for (i = 0; i < 5; i++) {
2139 port = (slot_ctx[0] >> 4*i) & 0x0f;
2140 if (!port) {
2141 break;
2142 }
2143 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port);
2144 }
2145
2146 QTAILQ_FOREACH(uport, &xhci->bus.used, next) {
2147 if (strcmp(uport->path, path) == 0) {
2148 return uport;
2149 }
2150 }
2151 return NULL;
2152 }
2153
2154 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
2155 uint64_t pictx, bool bsr)
2156 {
2157 XHCISlot *slot;
2158 USBPort *uport;
2159 USBDevice *dev;
2160 dma_addr_t ictx, octx, dcbaap;
2161 uint64_t poctx;
2162 uint32_t ictl_ctx[2];
2163 uint32_t slot_ctx[4];
2164 uint32_t ep0_ctx[5];
2165 int i;
2166 TRBCCode res;
2167
2168 assert(slotid >= 1 && slotid <= xhci->numslots);
2169
2170 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
2171 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid);
2172 ictx = xhci_mask64(pictx);
2173 octx = xhci_mask64(poctx);
2174
2175 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2176 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2177
2178 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2179
2180 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
2181 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
2182 ictl_ctx[0], ictl_ctx[1]);
2183 return CC_TRB_ERROR;
2184 }
2185
2186 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx));
2187 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx));
2188
2189 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2190 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2191
2192 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2193 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2194
2195 uport = xhci_lookup_uport(xhci, slot_ctx);
2196 if (uport == NULL) {
2197 fprintf(stderr, "xhci: port not found\n");
2198 return CC_TRB_ERROR;
2199 }
2200 trace_usb_xhci_slot_address(slotid, uport->path);
2201
2202 dev = uport->dev;
2203 if (!dev) {
2204 fprintf(stderr, "xhci: port %s not connected\n", uport->path);
2205 return CC_USB_TRANSACTION_ERROR;
2206 }
2207
2208 for (i = 0; i < xhci->numslots; i++) {
2209 if (i == slotid-1) {
2210 continue;
2211 }
2212 if (xhci->slots[i].uport == uport) {
2213 fprintf(stderr, "xhci: port %s already assigned to slot %d\n",
2214 uport->path, i+1);
2215 return CC_TRB_ERROR;
2216 }
2217 }
2218
2219 slot = &xhci->slots[slotid-1];
2220 slot->uport = uport;
2221 slot->ctx = octx;
2222
2223 if (bsr) {
2224 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
2225 } else {
2226 USBPacket p;
2227 uint8_t buf[1];
2228
2229 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid;
2230 usb_device_reset(dev);
2231 memset(&p, 0, sizeof(p));
2232 usb_packet_addbuf(&p, buf, sizeof(buf));
2233 usb_packet_setup(&p, USB_TOKEN_OUT,
2234 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0,
2235 0, false, false);
2236 usb_device_handle_control(dev, &p,
2237 DeviceOutRequest | USB_REQ_SET_ADDRESS,
2238 slotid, 0, 0, NULL);
2239 assert(p.status != USB_RET_ASYNC);
2240 }
2241
2242 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
2243
2244 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2245 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2246 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2247 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2248
2249 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2250 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2251
2252 xhci->slots[slotid-1].addressed = 1;
2253 return res;
2254 }
2255
2256
2257 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
2258 uint64_t pictx, bool dc)
2259 {
2260 dma_addr_t ictx, octx;
2261 uint32_t ictl_ctx[2];
2262 uint32_t slot_ctx[4];
2263 uint32_t islot_ctx[4];
2264 uint32_t ep_ctx[5];
2265 int i;
2266 TRBCCode res;
2267
2268 trace_usb_xhci_slot_configure(slotid);
2269 assert(slotid >= 1 && slotid <= xhci->numslots);
2270
2271 ictx = xhci_mask64(pictx);
2272 octx = xhci->slots[slotid-1].ctx;
2273
2274 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2275 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2276
2277 if (dc) {
2278 for (i = 2; i <= 31; i++) {
2279 if (xhci->slots[slotid-1].eps[i-1]) {
2280 xhci_disable_ep(xhci, slotid, i);
2281 }
2282 }
2283
2284 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2285 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2286 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
2287 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2288 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2289 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2290
2291 return CC_SUCCESS;
2292 }
2293
2294 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2295
2296 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
2297 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
2298 ictl_ctx[0], ictl_ctx[1]);
2299 return CC_TRB_ERROR;
2300 }
2301
2302 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2303 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2304
2305 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
2306 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]);
2307 return CC_CONTEXT_STATE_ERROR;
2308 }
2309
2310 for (i = 2; i <= 31; i++) {
2311 if (ictl_ctx[0] & (1<<i)) {
2312 xhci_disable_ep(xhci, slotid, i);
2313 }
2314 if (ictl_ctx[1] & (1<<i)) {
2315 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx));
2316 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2317 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2318 ep_ctx[3], ep_ctx[4]);
2319 xhci_disable_ep(xhci, slotid, i);
2320 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
2321 if (res != CC_SUCCESS) {
2322 return res;
2323 }
2324 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2325 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2326 ep_ctx[3], ep_ctx[4]);
2327 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx));
2328 }
2329 }
2330
2331 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2332 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
2333 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
2334 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
2335 SLOT_CONTEXT_ENTRIES_SHIFT);
2336 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2337 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2338
2339 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2340
2341 return CC_SUCCESS;
2342 }
2343
2344
2345 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
2346 uint64_t pictx)
2347 {
2348 dma_addr_t ictx, octx;
2349 uint32_t ictl_ctx[2];
2350 uint32_t iep0_ctx[5];
2351 uint32_t ep0_ctx[5];
2352 uint32_t islot_ctx[4];
2353 uint32_t slot_ctx[4];
2354
2355 trace_usb_xhci_slot_evaluate(slotid);
2356 assert(slotid >= 1 && slotid <= xhci->numslots);
2357
2358 ictx = xhci_mask64(pictx);
2359 octx = xhci->slots[slotid-1].ctx;
2360
2361 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2362 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2363
2364 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2365
2366 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
2367 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
2368 ictl_ctx[0], ictl_ctx[1]);
2369 return CC_TRB_ERROR;
2370 }
2371
2372 if (ictl_ctx[1] & 0x1) {
2373 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2374
2375 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2376 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
2377
2378 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2379
2380 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
2381 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
2382 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
2383 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
2384
2385 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2386 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2387
2388 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2389 }
2390
2391 if (ictl_ctx[1] & 0x2) {
2392 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx));
2393
2394 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2395 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
2396 iep0_ctx[3], iep0_ctx[4]);
2397
2398 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2399
2400 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2401 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2402
2403 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2404 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2405
2406 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2407 }
2408
2409 return CC_SUCCESS;
2410 }
2411
2412 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2413 {
2414 uint32_t slot_ctx[4];
2415 dma_addr_t octx;
2416 int i;
2417
2418 trace_usb_xhci_slot_reset(slotid);
2419 assert(slotid >= 1 && slotid <= xhci->numslots);
2420
2421 octx = xhci->slots[slotid-1].ctx;
2422
2423 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2424
2425 for (i = 2; i <= 31; i++) {
2426 if (xhci->slots[slotid-1].eps[i-1]) {
2427 xhci_disable_ep(xhci, slotid, i);
2428 }
2429 }
2430
2431 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2432 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2433 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
2434 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2435 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2436 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2437
2438 return CC_SUCCESS;
2439 }
2440
2441 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2442 {
2443 unsigned int slotid;
2444 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
2445 if (slotid < 1 || slotid > xhci->numslots) {
2446 fprintf(stderr, "xhci: bad slot id %d\n", slotid);
2447 event->ccode = CC_TRB_ERROR;
2448 return 0;
2449 } else if (!xhci->slots[slotid-1].enabled) {
2450 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid);
2451 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2452 return 0;
2453 }
2454 return slotid;
2455 }
2456
2457 /* cleanup slot state on usb device detach */
2458 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport)
2459 {
2460 int slot, ep;
2461
2462 for (slot = 0; slot < xhci->numslots; slot++) {
2463 if (xhci->slots[slot].uport == uport) {
2464 break;
2465 }
2466 }
2467 if (slot == xhci->numslots) {
2468 return;
2469 }
2470
2471 for (ep = 0; ep < 31; ep++) {
2472 if (xhci->slots[slot].eps[ep]) {
2473 xhci_ep_nuke_xfers(xhci, slot+1, ep+1);
2474 }
2475 }
2476 xhci->slots[slot].uport = NULL;
2477 }
2478
2479 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2480 {
2481 dma_addr_t ctx;
2482 uint8_t bw_ctx[xhci->numports+1];
2483
2484 DPRINTF("xhci_get_port_bandwidth()\n");
2485
2486 ctx = xhci_mask64(pctx);
2487
2488 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
2489
2490 /* TODO: actually implement real values here */
2491 bw_ctx[0] = 0;
2492 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
2493 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx));
2494
2495 return CC_SUCCESS;
2496 }
2497
2498 static uint32_t rotl(uint32_t v, unsigned count)
2499 {
2500 count &= 31;
2501 return (v << count) | (v >> (32 - count));
2502 }
2503
2504
2505 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2506 {
2507 uint32_t val;
2508 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2509 val += rotl(lo + 0x49434878, hi & 0x1F);
2510 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2511 return ~val;
2512 }
2513
2514 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
2515 {
2516 PCIDevice *pci_dev = PCI_DEVICE(xhci);
2517 uint32_t buf[8];
2518 uint32_t obuf[8];
2519 dma_addr_t paddr = xhci_mask64(addr);
2520
2521 pci_dma_read(pci_dev, paddr, &buf, 32);
2522
2523 memcpy(obuf, buf, sizeof(obuf));
2524
2525 if ((buf[0] & 0xff) == 2) {
2526 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3];
2527 obuf[0] |= (buf[2] * buf[3]) & 0xff;
2528 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3];
2529 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3];
2530 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3];
2531 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3];
2532 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3];
2533 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956;
2534 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
2535 }
2536
2537 pci_dma_write(pci_dev, paddr, &obuf, 32);
2538 }
2539
2540 static void xhci_process_commands(XHCIState *xhci)
2541 {
2542 XHCITRB trb;
2543 TRBType type;
2544 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
2545 dma_addr_t addr;
2546 unsigned int i, slotid = 0;
2547
2548 DPRINTF("xhci_process_commands()\n");
2549 if (!xhci_running(xhci)) {
2550 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2551 return;
2552 }
2553
2554 xhci->crcr_low |= CRCR_CRR;
2555
2556 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2557 event.ptr = addr;
2558 switch (type) {
2559 case CR_ENABLE_SLOT:
2560 for (i = 0; i < xhci->numslots; i++) {
2561 if (!xhci->slots[i].enabled) {
2562 break;
2563 }
2564 }
2565 if (i >= xhci->numslots) {
2566 fprintf(stderr, "xhci: no device slots available\n");
2567 event.ccode = CC_NO_SLOTS_ERROR;
2568 } else {
2569 slotid = i+1;
2570 event.ccode = xhci_enable_slot(xhci, slotid);
2571 }
2572 break;
2573 case CR_DISABLE_SLOT:
2574 slotid = xhci_get_slot(xhci, &event, &trb);
2575 if (slotid) {
2576 event.ccode = xhci_disable_slot(xhci, slotid);
2577 }
2578 break;
2579 case CR_ADDRESS_DEVICE:
2580 slotid = xhci_get_slot(xhci, &event, &trb);
2581 if (slotid) {
2582 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2583 trb.control & TRB_CR_BSR);
2584 }
2585 break;
2586 case CR_CONFIGURE_ENDPOINT:
2587 slotid = xhci_get_slot(xhci, &event, &trb);
2588 if (slotid) {
2589 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2590 trb.control & TRB_CR_DC);
2591 }
2592 break;
2593 case CR_EVALUATE_CONTEXT:
2594 slotid = xhci_get_slot(xhci, &event, &trb);
2595 if (slotid) {
2596 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2597 }
2598 break;
2599 case CR_STOP_ENDPOINT:
2600 slotid = xhci_get_slot(xhci, &event, &trb);
2601 if (slotid) {
2602 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2603 & TRB_CR_EPID_MASK;
2604 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2605 }
2606 break;
2607 case CR_RESET_ENDPOINT:
2608 slotid = xhci_get_slot(xhci, &event, &trb);
2609 if (slotid) {
2610 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2611 & TRB_CR_EPID_MASK;
2612 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2613 }
2614 break;
2615 case CR_SET_TR_DEQUEUE:
2616 slotid = xhci_get_slot(xhci, &event, &trb);
2617 if (slotid) {
2618 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2619 & TRB_CR_EPID_MASK;
2620 unsigned int streamid = (trb.status >> 16) & 0xffff;
2621 event.ccode = xhci_set_ep_dequeue(xhci, slotid,
2622 epid, streamid,
2623 trb.parameter);
2624 }
2625 break;
2626 case CR_RESET_DEVICE:
2627 slotid = xhci_get_slot(xhci, &event, &trb);
2628 if (slotid) {
2629 event.ccode = xhci_reset_slot(xhci, slotid);
2630 }
2631 break;
2632 case CR_GET_PORT_BANDWIDTH:
2633 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2634 break;
2635 case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
2636 xhci_via_challenge(xhci, trb.parameter);
2637 break;
2638 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2639 event.type = 48; /* NEC reply */
2640 event.length = 0x3025;
2641 break;
2642 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2643 {
2644 uint32_t chi = trb.parameter >> 32;
2645 uint32_t clo = trb.parameter;
2646 uint32_t val = xhci_nec_challenge(chi, clo);
2647 event.length = val & 0xFFFF;
2648 event.epid = val >> 16;
2649 slotid = val >> 24;
2650 event.type = 48; /* NEC reply */
2651 }
2652 break;
2653 default:
2654 trace_usb_xhci_unimplemented("command", type);
2655 event.ccode = CC_TRB_ERROR;
2656 break;
2657 }
2658 event.slotid = slotid;
2659 xhci_event(xhci, &event, 0);
2660 }
2661 }
2662
2663 static bool xhci_port_have_device(XHCIPort *port)
2664 {
2665 if (!port->uport->dev || !port->uport->dev->attached) {
2666 return false; /* no device present */
2667 }
2668 if (!((1 << port->uport->dev->speed) & port->speedmask)) {
2669 return false; /* speed mismatch */
2670 }
2671 return true;
2672 }
2673
2674 static void xhci_port_notify(XHCIPort *port, uint32_t bits)
2675 {
2676 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2677 port->portnr << 24 };
2678
2679 if ((port->portsc & bits) == bits) {
2680 return;
2681 }
2682 trace_usb_xhci_port_notify(port->portnr, bits);
2683 port->portsc |= bits;
2684 if (!xhci_running(port->xhci)) {
2685 return;
2686 }
2687 xhci_event(port->xhci, &ev, 0);
2688 }
2689
2690 static void xhci_port_update(XHCIPort *port, int is_detach)
2691 {
2692 uint32_t pls = PLS_RX_DETECT;
2693
2694 port->portsc = PORTSC_PP;
2695 if (!is_detach && xhci_port_have_device(port)) {
2696 port->portsc |= PORTSC_CCS;
2697 switch (port->uport->dev->speed) {
2698 case USB_SPEED_LOW:
2699 port->portsc |= PORTSC_SPEED_LOW;
2700 pls = PLS_POLLING;
2701 break;
2702 case USB_SPEED_FULL:
2703 port->portsc |= PORTSC_SPEED_FULL;
2704 pls = PLS_POLLING;
2705 break;
2706 case USB_SPEED_HIGH:
2707 port->portsc |= PORTSC_SPEED_HIGH;
2708 pls = PLS_POLLING;
2709 break;
2710 case USB_SPEED_SUPER:
2711 port->portsc |= PORTSC_SPEED_SUPER;
2712 port->portsc |= PORTSC_PED;
2713 pls = PLS_U0;
2714 break;
2715 }
2716 }
2717 set_field(&port->portsc, pls, PORTSC_PLS);
2718 trace_usb_xhci_port_link(port->portnr, pls);
2719 xhci_port_notify(port, PORTSC_CSC);
2720 }
2721
2722 static void xhci_port_reset(XHCIPort *port, bool warm_reset)
2723 {
2724 trace_usb_xhci_port_reset(port->portnr);
2725
2726 if (!xhci_port_have_device(port)) {
2727 return;
2728 }
2729
2730 usb_device_reset(port->uport->dev);
2731
2732 switch (port->uport->dev->speed) {
2733 case USB_SPEED_SUPER:
2734 if (warm_reset) {
2735 port->portsc |= PORTSC_WRC;
2736 }
2737 /* fall through */
2738 case USB_SPEED_LOW:
2739 case USB_SPEED_FULL:
2740 case USB_SPEED_HIGH:
2741 set_field(&port->portsc, PLS_U0, PORTSC_PLS);
2742 trace_usb_xhci_port_link(port->portnr, PLS_U0);
2743 port->portsc |= PORTSC_PED;
2744 break;
2745 }
2746
2747 port->portsc &= ~PORTSC_PR;
2748 xhci_port_notify(port, PORTSC_PRC);
2749 }
2750
2751 static void xhci_reset(DeviceState *dev)
2752 {
2753 XHCIState *xhci = XHCI(dev);
2754 int i;
2755
2756 trace_usb_xhci_reset();
2757 if (!(xhci->usbsts & USBSTS_HCH)) {
2758 fprintf(stderr, "xhci: reset while running!\n");
2759 }
2760
2761 xhci->usbcmd = 0;
2762 xhci->usbsts = USBSTS_HCH;
2763 xhci->dnctrl = 0;
2764 xhci->crcr_low = 0;
2765 xhci->crcr_high = 0;
2766 xhci->dcbaap_low = 0;
2767 xhci->dcbaap_high = 0;
2768 xhci->config = 0;
2769
2770 for (i = 0; i < xhci->numslots; i++) {
2771 xhci_disable_slot(xhci, i+1);
2772 }
2773
2774 for (i = 0; i < xhci->numports; i++) {
2775 xhci_port_update(xhci->ports + i, 0);
2776 }
2777
2778 for (i = 0; i < xhci->numintrs; i++) {
2779 xhci->intr[i].iman = 0;
2780 xhci->intr[i].imod = 0;
2781 xhci->intr[i].erstsz = 0;
2782 xhci->intr[i].erstba_low = 0;
2783 xhci->intr[i].erstba_high = 0;
2784 xhci->intr[i].erdp_low = 0;
2785 xhci->intr[i].erdp_high = 0;
2786 xhci->intr[i].msix_used = 0;
2787
2788 xhci->intr[i].er_ep_idx = 0;
2789 xhci->intr[i].er_pcs = 1;
2790 xhci->intr[i].er_full = 0;
2791 xhci->intr[i].ev_buffer_put = 0;
2792 xhci->intr[i].ev_buffer_get = 0;
2793 }
2794
2795 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2796 xhci_mfwrap_update(xhci);
2797 }
2798
2799 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
2800 {
2801 XHCIState *xhci = ptr;
2802 uint32_t ret;
2803
2804 switch (reg) {
2805 case 0x00: /* HCIVERSION, CAPLENGTH */
2806 ret = 0x01000000 | LEN_CAP;
2807 break;
2808 case 0x04: /* HCSPARAMS 1 */
2809 ret = ((xhci->numports_2+xhci->numports_3)<<24)
2810 | (xhci->numintrs<<8) | xhci->numslots;
2811 break;
2812 case 0x08: /* HCSPARAMS 2 */
2813 ret = 0x0000000f;
2814 break;
2815 case 0x0c: /* HCSPARAMS 3 */
2816 ret = 0x00000000;
2817 break;
2818 case 0x10: /* HCCPARAMS */
2819 if (sizeof(dma_addr_t) == 4) {
2820 ret = 0x00087000;
2821 } else {
2822 ret = 0x00087001;
2823 }
2824 break;
2825 case 0x14: /* DBOFF */
2826 ret = OFF_DOORBELL;
2827 break;
2828 case 0x18: /* RTSOFF */
2829 ret = OFF_RUNTIME;
2830 break;
2831
2832 /* extended capabilities */
2833 case 0x20: /* Supported Protocol:00 */
2834 ret = 0x02000402; /* USB 2.0 */
2835 break;
2836 case 0x24: /* Supported Protocol:04 */
2837 ret = 0x20425355; /* "USB " */
2838 break;
2839 case 0x28: /* Supported Protocol:08 */
2840 ret = 0x00000001 | (xhci->numports_2<<8);
2841 break;
2842 case 0x2c: /* Supported Protocol:0c */
2843 ret = 0x00000000; /* reserved */
2844 break;
2845 case 0x30: /* Supported Protocol:00 */
2846 ret = 0x03000002; /* USB 3.0 */
2847 break;
2848 case 0x34: /* Supported Protocol:04 */
2849 ret = 0x20425355; /* "USB " */
2850 break;
2851 case 0x38: /* Supported Protocol:08 */
2852 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8);
2853 break;
2854 case 0x3c: /* Supported Protocol:0c */
2855 ret = 0x00000000; /* reserved */
2856 break;
2857 default:
2858 trace_usb_xhci_unimplemented("cap read", reg);
2859 ret = 0;
2860 }
2861
2862 trace_usb_xhci_cap_read(reg, ret);
2863 return ret;
2864 }
2865
2866 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
2867 {
2868 XHCIPort *port = ptr;
2869 uint32_t ret;
2870
2871 switch (reg) {
2872 case 0x00: /* PORTSC */
2873 ret = port->portsc;
2874 break;
2875 case 0x04: /* PORTPMSC */
2876 case 0x08: /* PORTLI */
2877 ret = 0;
2878 break;
2879 case 0x0c: /* reserved */
2880 default:
2881 trace_usb_xhci_unimplemented("port read", reg);
2882 ret = 0;
2883 }
2884
2885 trace_usb_xhci_port_read(port->portnr, reg, ret);
2886 return ret;
2887 }
2888
2889 static void xhci_port_write(void *ptr, hwaddr reg,
2890 uint64_t val, unsigned size)
2891 {
2892 XHCIPort *port = ptr;
2893 uint32_t portsc, notify;
2894
2895 trace_usb_xhci_port_write(port->portnr, reg, val);
2896
2897 switch (reg) {
2898 case 0x00: /* PORTSC */
2899 /* write-1-to-start bits */
2900 if (val & PORTSC_WPR) {
2901 xhci_port_reset(port, true);
2902 break;
2903 }
2904 if (val & PORTSC_PR) {
2905 xhci_port_reset(port, false);
2906 break;
2907 }
2908
2909 portsc = port->portsc;
2910 notify = 0;
2911 /* write-1-to-clear bits*/
2912 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
2913 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
2914 if (val & PORTSC_LWS) {
2915 /* overwrite PLS only when LWS=1 */
2916 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS);
2917 uint32_t new_pls = get_field(val, PORTSC_PLS);
2918 switch (new_pls) {
2919 case PLS_U0:
2920 if (old_pls != PLS_U0) {
2921 set_field(&portsc, new_pls, PORTSC_PLS);
2922 trace_usb_xhci_port_link(port->portnr, new_pls);
2923 notify = PORTSC_PLC;
2924 }
2925 break;
2926 case PLS_U3:
2927 if (old_pls < PLS_U3) {
2928 set_field(&portsc, new_pls, PORTSC_PLS);
2929 trace_usb_xhci_port_link(port->portnr, new_pls);
2930 }
2931 break;
2932 case PLS_RESUME:
2933 /* windows does this for some reason, don't spam stderr */
2934 break;
2935 default:
2936 fprintf(stderr, "%s: ignore pls write (old %d, new %d)\n",
2937 __func__, old_pls, new_pls);
2938 break;
2939 }
2940 }
2941 /* read/write bits */
2942 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
2943 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
2944 port->portsc = portsc;
2945 if (notify) {
2946 xhci_port_notify(port, notify);
2947 }
2948 break;
2949 case 0x04: /* PORTPMSC */
2950 case 0x08: /* PORTLI */
2951 default:
2952 trace_usb_xhci_unimplemented("port write", reg);
2953 }
2954 }
2955
2956 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
2957 {
2958 XHCIState *xhci = ptr;
2959 uint32_t ret;
2960
2961 switch (reg) {
2962 case 0x00: /* USBCMD */
2963 ret = xhci->usbcmd;
2964 break;
2965 case 0x04: /* USBSTS */
2966 ret = xhci->usbsts;
2967 break;
2968 case 0x08: /* PAGESIZE */
2969 ret = 1; /* 4KiB */
2970 break;
2971 case 0x14: /* DNCTRL */
2972 ret = xhci->dnctrl;
2973 break;
2974 case 0x18: /* CRCR low */
2975 ret = xhci->crcr_low & ~0xe;
2976 break;
2977 case 0x1c: /* CRCR high */
2978 ret = xhci->crcr_high;
2979 break;
2980 case 0x30: /* DCBAAP low */
2981 ret = xhci->dcbaap_low;
2982 break;
2983 case 0x34: /* DCBAAP high */
2984 ret = xhci->dcbaap_high;
2985 break;
2986 case 0x38: /* CONFIG */
2987 ret = xhci->config;
2988 break;
2989 default:
2990 trace_usb_xhci_unimplemented("oper read", reg);
2991 ret = 0;
2992 }
2993
2994 trace_usb_xhci_oper_read(reg, ret);
2995 return ret;
2996 }
2997
2998 static void xhci_oper_write(void *ptr, hwaddr reg,
2999 uint64_t val, unsigned size)
3000 {
3001 XHCIState *xhci = ptr;
3002 DeviceState *d = DEVICE(ptr);
3003
3004 trace_usb_xhci_oper_write(reg, val);
3005
3006 switch (reg) {
3007 case 0x00: /* USBCMD */
3008 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
3009 xhci_run(xhci);
3010 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
3011 xhci_stop(xhci);
3012 }
3013 xhci->usbcmd = val & 0xc0f;
3014 xhci_mfwrap_update(xhci);
3015 if (val & USBCMD_HCRST) {
3016 xhci_reset(d);
3017 }
3018 xhci_intx_update(xhci);
3019 break;
3020
3021 case 0x04: /* USBSTS */
3022 /* these bits are write-1-to-clear */
3023 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
3024 xhci_intx_update(xhci);
3025 break;
3026
3027 case 0x14: /* DNCTRL */
3028 xhci->dnctrl = val & 0xffff;
3029 break;
3030 case 0x18: /* CRCR low */
3031 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
3032 break;
3033 case 0x1c: /* CRCR high */
3034 xhci->crcr_high = val;
3035 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
3036 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
3037 xhci->crcr_low &= ~CRCR_CRR;
3038 xhci_event(xhci, &event, 0);
3039 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
3040 } else {
3041 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
3042 xhci_ring_init(xhci, &xhci->cmd_ring, base);
3043 }
3044 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
3045 break;
3046 case 0x30: /* DCBAAP low */
3047 xhci->dcbaap_low = val & 0xffffffc0;
3048 break;
3049 case 0x34: /* DCBAAP high */
3050 xhci->dcbaap_high = val;
3051 break;
3052 case 0x38: /* CONFIG */
3053 xhci->config = val & 0xff;
3054 break;
3055 default:
3056 trace_usb_xhci_unimplemented("oper write", reg);
3057 }
3058 }
3059
3060 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
3061 unsigned size)
3062 {
3063 XHCIState *xhci = ptr;
3064 uint32_t ret = 0;
3065
3066 if (reg < 0x20) {
3067 switch (reg) {
3068 case 0x00: /* MFINDEX */
3069 ret = xhci_mfindex_get(xhci) & 0x3fff;
3070 break;
3071 default:
3072 trace_usb_xhci_unimplemented("runtime read", reg);
3073 break;
3074 }
3075 } else {
3076 int v = (reg - 0x20) / 0x20;
3077 XHCIInterrupter *intr = &xhci->intr[v];
3078 switch (reg & 0x1f) {
3079 case 0x00: /* IMAN */
3080 ret = intr->iman;
3081 break;
3082 case 0x04: /* IMOD */
3083 ret = intr->imod;
3084 break;
3085 case 0x08: /* ERSTSZ */
3086 ret = intr->erstsz;
3087 break;
3088 case 0x10: /* ERSTBA low */
3089 ret = intr->erstba_low;
3090 break;
3091 case 0x14: /* ERSTBA high */
3092 ret = intr->erstba_high;
3093 break;
3094 case 0x18: /* ERDP low */
3095 ret = intr->erdp_low;
3096 break;
3097 case 0x1c: /* ERDP high */
3098 ret = intr->erdp_high;
3099 break;
3100 }
3101 }
3102
3103 trace_usb_xhci_runtime_read(reg, ret);
3104 return ret;
3105 }
3106
3107 static void xhci_runtime_write(void *ptr, hwaddr reg,
3108 uint64_t val, unsigned size)
3109 {
3110 XHCIState *xhci = ptr;
3111 int v = (reg - 0x20) / 0x20;
3112 XHCIInterrupter *intr = &xhci->intr[v];
3113 trace_usb_xhci_runtime_write(reg, val);
3114
3115 if (reg < 0x20) {
3116 trace_usb_xhci_unimplemented("runtime write", reg);
3117 return;
3118 }
3119
3120 switch (reg & 0x1f) {
3121 case 0x00: /* IMAN */
3122 if (val & IMAN_IP) {
3123 intr->iman &= ~IMAN_IP;
3124 }
3125 intr->iman &= ~IMAN_IE;
3126 intr->iman |= val & IMAN_IE;
3127 if (v == 0) {
3128 xhci_intx_update(xhci);
3129 }
3130 xhci_msix_update(xhci, v);
3131 break;
3132 case 0x04: /* IMOD */
3133 intr->imod = val;
3134 break;
3135 case 0x08: /* ERSTSZ */
3136 intr->erstsz = val & 0xffff;
3137 break;
3138 case 0x10: /* ERSTBA low */
3139 /* XXX NEC driver bug: it doesn't align this to 64 bytes
3140 intr->erstba_low = val & 0xffffffc0; */
3141 intr->erstba_low = val & 0xfffffff0;
3142 break;
3143 case 0x14: /* ERSTBA high */
3144 intr->erstba_high = val;
3145 xhci_er_reset(xhci, v);
3146 break;
3147 case 0x18: /* ERDP low */
3148 if (val & ERDP_EHB) {
3149 intr->erdp_low &= ~ERDP_EHB;
3150 }
3151 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB);
3152 break;
3153 case 0x1c: /* ERDP high */
3154 intr->erdp_high = val;
3155 xhci_events_update(xhci, v);
3156 break;
3157 default:
3158 trace_usb_xhci_unimplemented("oper write", reg);
3159 }
3160 }
3161
3162 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg,
3163 unsigned size)
3164 {
3165 /* doorbells always read as 0 */
3166 trace_usb_xhci_doorbell_read(reg, 0);
3167 return 0;
3168 }
3169
3170 static void xhci_doorbell_write(void *ptr, hwaddr reg,
3171 uint64_t val, unsigned size)
3172 {
3173 XHCIState *xhci = ptr;
3174 unsigned int epid, streamid;
3175
3176 trace_usb_xhci_doorbell_write(reg, val);
3177
3178 if (!xhci_running(xhci)) {
3179 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n");
3180 return;
3181 }
3182
3183 reg >>= 2;
3184
3185 if (reg == 0) {
3186 if (val == 0) {
3187 xhci_process_commands(xhci);
3188 } else {
3189 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n",
3190 (uint32_t)val);
3191 }
3192 } else {
3193 epid = val & 0xff;
3194 streamid = (val >> 16) & 0xffff;
3195 if (reg > xhci->numslots) {
3196 fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg);
3197 } else if (epid > 31) {
3198 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n",
3199 (int)reg, (uint32_t)val);
3200 } else {
3201 xhci_kick_ep(xhci, reg, epid, streamid);
3202 }
3203 }
3204 }
3205
3206 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val,
3207 unsigned width)
3208 {
3209 /* nothing */
3210 }
3211
3212 static const MemoryRegionOps xhci_cap_ops = {
3213 .read = xhci_cap_read,
3214 .write = xhci_cap_write,
3215 .valid.min_access_size = 1,
3216 .valid.max_access_size = 4,
3217 .impl.min_access_size = 4,
3218 .impl.max_access_size = 4,
3219 .endianness = DEVICE_LITTLE_ENDIAN,
3220 };
3221
3222 static const MemoryRegionOps xhci_oper_ops = {
3223 .read = xhci_oper_read,
3224 .write = xhci_oper_write,
3225 .valid.min_access_size = 4,
3226 .valid.max_access_size = 4,
3227 .endianness = DEVICE_LITTLE_ENDIAN,
3228 };
3229
3230 static const MemoryRegionOps xhci_port_ops = {
3231 .read = xhci_port_read,
3232 .write = xhci_port_write,
3233 .valid.min_access_size = 4,
3234 .valid.max_access_size = 4,
3235 .endianness = DEVICE_LITTLE_ENDIAN,
3236 };
3237
3238 static const MemoryRegionOps xhci_runtime_ops = {
3239 .read = xhci_runtime_read,
3240 .write = xhci_runtime_write,
3241 .valid.min_access_size = 4,
3242 .valid.max_access_size = 4,
3243 .endianness = DEVICE_LITTLE_ENDIAN,
3244 };
3245
3246 static const MemoryRegionOps xhci_doorbell_ops = {
3247 .read = xhci_doorbell_read,
3248 .write = xhci_doorbell_write,
3249 .valid.min_access_size = 4,
3250 .valid.max_access_size = 4,
3251 .endianness = DEVICE_LITTLE_ENDIAN,
3252 };
3253
3254 static void xhci_attach(USBPort *usbport)
3255 {
3256 XHCIState *xhci = usbport->opaque;
3257 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3258
3259 xhci_port_update(port, 0);
3260 }
3261
3262 static void xhci_detach(USBPort *usbport)
3263 {
3264 XHCIState *xhci = usbport->opaque;
3265 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3266
3267 xhci_detach_slot(xhci, usbport);
3268 xhci_port_update(port, 1);
3269 }
3270
3271 static void xhci_wakeup(USBPort *usbport)
3272 {
3273 XHCIState *xhci = usbport->opaque;
3274 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3275
3276 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) {
3277 return;
3278 }
3279 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS);
3280 xhci_port_notify(port, PORTSC_PLC);
3281 }
3282
3283 static void xhci_complete(USBPort *port, USBPacket *packet)
3284 {
3285 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
3286
3287 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
3288 xhci_ep_nuke_one_xfer(xfer);
3289 return;
3290 }
3291 xhci_complete_packet(xfer);
3292 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid, xfer->streamid);
3293 }
3294
3295 static void xhci_child_detach(USBPort *uport, USBDevice *child)
3296 {
3297 USBBus *bus = usb_bus_from_device(child);
3298 XHCIState *xhci = container_of(bus, XHCIState, bus);
3299
3300 xhci_detach_slot(xhci, uport);
3301 }
3302
3303 static USBPortOps xhci_uport_ops = {
3304 .attach = xhci_attach,
3305 .detach = xhci_detach,
3306 .wakeup = xhci_wakeup,
3307 .complete = xhci_complete,
3308 .child_detach = xhci_child_detach,
3309 };
3310
3311 static int xhci_find_epid(USBEndpoint *ep)
3312 {
3313 if (ep->nr == 0) {
3314 return 1;
3315 }
3316 if (ep->pid == USB_TOKEN_IN) {
3317 return ep->nr * 2 + 1;
3318 } else {
3319 return ep->nr * 2;
3320 }
3321 }
3322
3323 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
3324 unsigned int stream)
3325 {
3326 XHCIState *xhci = container_of(bus, XHCIState, bus);
3327 int slotid;
3328
3329 DPRINTF("%s\n", __func__);
3330 slotid = ep->dev->addr;
3331 if (slotid == 0 || !xhci->slots[slotid-1].enabled) {
3332 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
3333 return;
3334 }
3335 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream);
3336 }
3337
3338 static USBBusOps xhci_bus_ops = {
3339 .wakeup_endpoint = xhci_wakeup_endpoint,
3340 };
3341
3342 static void usb_xhci_init(XHCIState *xhci)
3343 {
3344 DeviceState *dev = DEVICE(xhci);
3345 XHCIPort *port;
3346 int i, usbports, speedmask;
3347
3348 xhci->usbsts = USBSTS_HCH;
3349
3350 if (xhci->numports_2 > MAXPORTS_2) {
3351 xhci->numports_2 = MAXPORTS_2;
3352 }
3353 if (xhci->numports_3 > MAXPORTS_3) {
3354 xhci->numports_3 = MAXPORTS_3;
3355 }
3356 usbports = MAX(xhci->numports_2, xhci->numports_3);
3357 xhci->numports = xhci->numports_2 + xhci->numports_3;
3358
3359 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev);
3360
3361 for (i = 0; i < usbports; i++) {
3362 speedmask = 0;
3363 if (i < xhci->numports_2) {
3364 port = &xhci->ports[i];
3365 port->portnr = i + 1;
3366 port->uport = &xhci->uports[i];
3367 port->speedmask =
3368 USB_SPEED_MASK_LOW |
3369 USB_SPEED_MASK_FULL |
3370 USB_SPEED_MASK_HIGH;
3371 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1);
3372 speedmask |= port->speedmask;
3373 }
3374 if (i < xhci->numports_3) {
3375 port = &xhci->ports[i + xhci->numports_2];
3376 port->portnr = i + 1 + xhci->numports_2;
3377 port->uport = &xhci->uports[i];
3378 port->speedmask = USB_SPEED_MASK_SUPER;
3379 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1);
3380 speedmask |= port->speedmask;
3381 }
3382 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
3383 &xhci_uport_ops, speedmask);
3384 }
3385 }
3386
3387 static int usb_xhci_initfn(struct PCIDevice *dev)
3388 {
3389 int i, ret;
3390
3391 XHCIState *xhci = XHCI(dev);
3392
3393 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */
3394 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
3395 dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
3396 dev->config[0x60] = 0x30; /* release number */
3397
3398 usb_xhci_init(xhci);
3399
3400 if (xhci->numintrs > MAXINTRS) {
3401 xhci->numintrs = MAXINTRS;
3402 }
3403 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */
3404 xhci->numintrs++;
3405 }
3406 if (xhci->numintrs < 1) {
3407 xhci->numintrs = 1;
3408 }
3409 if (xhci->numslots > MAXSLOTS) {
3410 xhci->numslots = MAXSLOTS;
3411 }
3412 if (xhci->numslots < 1) {
3413 xhci->numslots = 1;
3414 }
3415
3416 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
3417
3418 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
3419 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci,
3420 "capabilities", LEN_CAP);
3421 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci,
3422 "operational", 0x400);
3423 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci,
3424 "runtime", LEN_RUNTIME);
3425 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci,
3426 "doorbell", LEN_DOORBELL);
3427
3428 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
3429 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper);
3430 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime);
3431 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell);
3432
3433 for (i = 0; i < xhci->numports; i++) {
3434 XHCIPort *port = &xhci->ports[i];
3435 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
3436 port->xhci = xhci;
3437 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port,
3438 port->name, 0x10);
3439 memory_region_add_subregion(&xhci->mem, offset, &port->mem);
3440 }
3441
3442 pci_register_bar(dev, 0,
3443 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
3444 &xhci->mem);
3445
3446 ret = pcie_endpoint_cap_init(dev, 0xa0);
3447 assert(ret >= 0);
3448
3449 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) {
3450 msi_init(dev, 0x70, xhci->numintrs, true, false);
3451 }
3452 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) {
3453 msix_init(dev, xhci->numintrs,
3454 &xhci->mem, 0, OFF_MSIX_TABLE,
3455 &xhci->mem, 0, OFF_MSIX_PBA,
3456 0x90);
3457 }
3458
3459 return 0;
3460 }
3461
3462 static int usb_xhci_post_load(void *opaque, int version_id)
3463 {
3464 XHCIState *xhci = opaque;
3465 PCIDevice *pci_dev = PCI_DEVICE(xhci);
3466 XHCISlot *slot;
3467 XHCIEPContext *epctx;
3468 dma_addr_t dcbaap, pctx;
3469 uint32_t slot_ctx[4];
3470 uint32_t ep_ctx[5];
3471 int slotid, epid, state, intr;
3472
3473 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
3474
3475 for (slotid = 1; slotid <= xhci->numslots; slotid++) {
3476 slot = &xhci->slots[slotid-1];
3477 if (!slot->addressed) {
3478 continue;
3479 }
3480 slot->ctx =
3481 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid));
3482 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
3483 slot->uport = xhci_lookup_uport(xhci, slot_ctx);
3484 assert(slot->uport && slot->uport->dev);
3485
3486 for (epid = 1; epid <= 32; epid++) {
3487 pctx = slot->ctx + 32 * epid;
3488 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx));
3489 state = ep_ctx[0] & EP_STATE_MASK;
3490 if (state == EP_DISABLED) {
3491 continue;
3492 }
3493 epctx = xhci_alloc_epctx(xhci, slotid, epid);
3494 slot->eps[epid-1] = epctx;
3495 xhci_init_epctx(epctx, pctx, ep_ctx);
3496 epctx->state = state;
3497 if (state == EP_RUNNING) {
3498 /* kick endpoint after vmload is finished */
3499 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
3500 }
3501 }
3502 }
3503
3504 for (intr = 0; intr < xhci->numintrs; intr++) {
3505 if (xhci->intr[intr].msix_used) {
3506 msix_vector_use(pci_dev, intr);
3507 } else {
3508 msix_vector_unuse(pci_dev, intr);
3509 }
3510 }
3511
3512 return 0;
3513 }
3514
3515 static const VMStateDescription vmstate_xhci_ring = {
3516 .name = "xhci-ring",
3517 .version_id = 1,
3518 .fields = (VMStateField[]) {
3519 VMSTATE_UINT64(dequeue, XHCIRing),
3520 VMSTATE_BOOL(ccs, XHCIRing),
3521 VMSTATE_END_OF_LIST()
3522 }
3523 };
3524
3525 static const VMStateDescription vmstate_xhci_port = {
3526 .name = "xhci-port",
3527 .version_id = 1,
3528 .fields = (VMStateField[]) {
3529 VMSTATE_UINT32(portsc, XHCIPort),
3530 VMSTATE_END_OF_LIST()
3531 }
3532 };
3533
3534 static const VMStateDescription vmstate_xhci_slot = {
3535 .name = "xhci-slot",
3536 .version_id = 1,
3537 .fields = (VMStateField[]) {
3538 VMSTATE_BOOL(enabled, XHCISlot),
3539 VMSTATE_BOOL(addressed, XHCISlot),
3540 VMSTATE_END_OF_LIST()
3541 }
3542 };
3543
3544 static const VMStateDescription vmstate_xhci_event = {
3545 .name = "xhci-event",
3546 .version_id = 1,
3547 .fields = (VMStateField[]) {
3548 VMSTATE_UINT32(type, XHCIEvent),
3549 VMSTATE_UINT32(ccode, XHCIEvent),
3550 VMSTATE_UINT64(ptr, XHCIEvent),
3551 VMSTATE_UINT32(length, XHCIEvent),
3552 VMSTATE_UINT32(flags, XHCIEvent),
3553 VMSTATE_UINT8(slotid, XHCIEvent),
3554 VMSTATE_UINT8(epid, XHCIEvent),
3555 }
3556 };
3557
3558 static bool xhci_er_full(void *opaque, int version_id)
3559 {
3560 struct XHCIInterrupter *intr = opaque;
3561 return intr->er_full;
3562 }
3563
3564 static const VMStateDescription vmstate_xhci_intr = {
3565 .name = "xhci-intr",
3566 .version_id = 1,
3567 .fields = (VMStateField[]) {
3568 /* registers */
3569 VMSTATE_UINT32(iman, XHCIInterrupter),
3570 VMSTATE_UINT32(imod, XHCIInterrupter),
3571 VMSTATE_UINT32(erstsz, XHCIInterrupter),
3572 VMSTATE_UINT32(erstba_low, XHCIInterrupter),
3573 VMSTATE_UINT32(erstba_high, XHCIInterrupter),
3574 VMSTATE_UINT32(erdp_low, XHCIInterrupter),
3575 VMSTATE_UINT32(erdp_high, XHCIInterrupter),
3576
3577 /* state */
3578 VMSTATE_BOOL(msix_used, XHCIInterrupter),
3579 VMSTATE_BOOL(er_pcs, XHCIInterrupter),
3580 VMSTATE_UINT64(er_start, XHCIInterrupter),
3581 VMSTATE_UINT32(er_size, XHCIInterrupter),
3582 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter),
3583
3584 /* event queue (used if ring is full) */
3585 VMSTATE_BOOL(er_full, XHCIInterrupter),
3586 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full),
3587 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full),
3588 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE,
3589 xhci_er_full, 1,
3590 vmstate_xhci_event, XHCIEvent),
3591
3592 VMSTATE_END_OF_LIST()
3593 }
3594 };
3595
3596 static const VMStateDescription vmstate_xhci = {
3597 .name = "xhci",
3598 .version_id = 1,
3599 .post_load = usb_xhci_post_load,
3600 .fields = (VMStateField[]) {
3601 VMSTATE_PCIE_DEVICE(parent_obj, XHCIState),
3602 VMSTATE_MSIX(parent_obj, XHCIState),
3603
3604 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
3605 vmstate_xhci_port, XHCIPort),
3606 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1,
3607 vmstate_xhci_slot, XHCISlot),
3608 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1,
3609 vmstate_xhci_intr, XHCIInterrupter),
3610
3611 /* Operational Registers */
3612 VMSTATE_UINT32(usbcmd, XHCIState),
3613 VMSTATE_UINT32(usbsts, XHCIState),
3614 VMSTATE_UINT32(dnctrl, XHCIState),
3615 VMSTATE_UINT32(crcr_low, XHCIState),
3616 VMSTATE_UINT32(crcr_high, XHCIState),
3617 VMSTATE_UINT32(dcbaap_low, XHCIState),
3618 VMSTATE_UINT32(dcbaap_high, XHCIState),
3619 VMSTATE_UINT32(config, XHCIState),
3620
3621 /* Runtime Registers & state */
3622 VMSTATE_INT64(mfindex_start, XHCIState),
3623 VMSTATE_TIMER(mfwrap_timer, XHCIState),
3624 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing),
3625
3626 VMSTATE_END_OF_LIST()
3627 }
3628 };
3629
3630 static Property xhci_properties[] = {
3631 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true),
3632 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true),
3633 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS),
3634 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS),
3635 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
3636 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),
3637 DEFINE_PROP_END_OF_LIST(),
3638 };
3639
3640 static void xhci_class_init(ObjectClass *klass, void *data)
3641 {
3642 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3643 DeviceClass *dc = DEVICE_CLASS(klass);
3644
3645 dc->vmsd = &vmstate_xhci;
3646 dc->props = xhci_properties;
3647 dc->reset = xhci_reset;
3648 set_bit(DEVICE_CATEGORY_USB, dc->categories);
3649 k->init = usb_xhci_initfn;
3650 k->vendor_id = PCI_VENDOR_ID_NEC;
3651 k->device_id = PCI_DEVICE_ID_NEC_UPD720200;
3652 k->class_id = PCI_CLASS_SERIAL_USB;
3653 k->revision = 0x03;
3654 k->is_express = 1;
3655 k->no_hotplug = 1;
3656 }
3657
3658 static const TypeInfo xhci_info = {
3659 .name = TYPE_XHCI,
3660 .parent = TYPE_PCI_DEVICE,
3661 .instance_size = sizeof(XHCIState),
3662 .class_init = xhci_class_init,
3663 };
3664
3665 static void xhci_register_types(void)
3666 {
3667 type_register_static(&xhci_info);
3668 }
3669
3670 type_init(xhci_register_types)
QEmu