cpu-exec.c

   1 /*
   2  *  i386 emulator main execution loop
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "config.h"
  21 #include "exec.h"
  22 #include "disas.h"
  23
  24 #if !defined(CONFIG_SOFTMMU)
  25 #undef EAX
  26 #undef ECX
  27 #undef EDX
  28 #undef EBX
  29 #undef ESP
  30 #undef EBP
  31 #undef ESI
  32 #undef EDI
  33 #undef EIP
  34 #include <signal.h>
  35 #include <sys/ucontext.h>
  36 #endif
  37
  38 int tb_invalidated_flag;
  39
  40 //#define DEBUG_EXEC
  41 //#define DEBUG_SIGNAL
  42
  43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
  44 /* XXX: unify with i386 target */
  45 void cpu_loop_exit(void)
  46 {
  47     longjmp(env->jmp_env, 1);
  48 }
  49 #endif
  50
  51 /* exit the current TB from a signal handler. The host registers are
  52    restored in a state compatible with the CPU emulator
  53  */
  54 void cpu_resume_from_signal(CPUState *env1, void *puc)
  55 {
  56 #if !defined(CONFIG_SOFTMMU)
  57     struct ucontext *uc = puc;
  58 #endif
  59
  60     env = env1;
  61
  62     /* XXX: restore cpu registers saved in host registers */
  63
  64 #if !defined(CONFIG_SOFTMMU)
  65     if (puc) {
  66         /* XXX: use siglongjmp ? */
  67         sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
  68     }
  69 #endif
  70     longjmp(env->jmp_env, 1);
  71 }
  72
  73 /* main execution loop */
  74
  75 int cpu_exec(CPUState *env1)
  76 {
  77     int saved_T0, saved_T1, saved_T2;
  78     CPUState *saved_env;
  79 #ifdef reg_EAX
  80     int saved_EAX;
  81 #endif
  82 #ifdef reg_ECX
  83     int saved_ECX;
  84 #endif
  85 #ifdef reg_EDX
  86     int saved_EDX;
  87 #endif
  88 #ifdef reg_EBX
  89     int saved_EBX;
  90 #endif
  91 #ifdef reg_ESP
  92     int saved_ESP;
  93 #endif
  94 #ifdef reg_EBP
  95     int saved_EBP;
  96 #endif
  97 #ifdef reg_ESI
  98     int saved_ESI;
  99 #endif
 100 #ifdef reg_EDI
 101     int saved_EDI;
 102 #endif
 103 #ifdef __sparc__
 104     int saved_i7, tmp_T0;
 105 #endif
 106     int code_gen_size, ret, interrupt_request;
 107     void (*gen_func)(void);
 108     TranslationBlock *tb, **ptb;
 109     uint8_t *tc_ptr, *cs_base, *pc;
 110     unsigned int flags;
 111
 112     /* first we save global registers */
 113     saved_T0 = T0;
 114     saved_T1 = T1;
 115     saved_T2 = T2;
 116     saved_env = env;
 117     env = env1;
 118 #ifdef __sparc__
 119     /* we also save i7 because longjmp may not restore it */
 120     asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
 121 #endif
 122
 123 #if defined(TARGET_I386)
 124 #ifdef reg_EAX
 125     saved_EAX = EAX;
 126     EAX = env->regs[R_EAX];
 127 #endif
 128 #ifdef reg_ECX
 129     saved_ECX = ECX;
 130     ECX = env->regs[R_ECX];
 131 #endif
 132 #ifdef reg_EDX
 133     saved_EDX = EDX;
 134     EDX = env->regs[R_EDX];
 135 #endif
 136 #ifdef reg_EBX
 137     saved_EBX = EBX;
 138     EBX = env->regs[R_EBX];
 139 #endif
 140 #ifdef reg_ESP
 141     saved_ESP = ESP;
 142     ESP = env->regs[R_ESP];
 143 #endif
 144 #ifdef reg_EBP
 145     saved_EBP = EBP;
 146     EBP = env->regs[R_EBP];
 147 #endif
 148 #ifdef reg_ESI
 149     saved_ESI = ESI;
 150     ESI = env->regs[R_ESI];
 151 #endif
 152 #ifdef reg_EDI
 153     saved_EDI = EDI;
 154     EDI = env->regs[R_EDI];
 155 #endif
 156
 157     /* put eflags in CPU temporary format */
 158     CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 159     DF = 1 - (2 * ((env->eflags >> 10) & 1));
 160     CC_OP = CC_OP_EFLAGS;
 161     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 162 #elif defined(TARGET_ARM)
 163     {
 164         unsigned int psr;
 165         psr = env->cpsr;
 166         env->CF = (psr >> 29) & 1;
 167         env->NZF = (psr & 0xc0000000) ^ 0x40000000;
 168         env->VF = (psr << 3) & 0x80000000;
 169         env->cpsr = psr & ~0xf0000000;
 170     }
 171 #elif defined(TARGET_SPARC)
 172 #elif defined(TARGET_PPC)
 173 #else
 174 #error unsupported target CPU
 175 #endif
 176     env->exception_index = -1;
 177
 178     /* prepare setjmp context for exception handling */
 179     for(;;) {
 180         if (setjmp(env->jmp_env) == 0) {
 181             env->current_tb = NULL;
 182             /* if an exception is pending, we execute it here */
 183             if (env->exception_index >= 0) {
 184                 if (env->exception_index >= EXCP_INTERRUPT) {
 185                     /* exit request from the cpu execution loop */
 186                     ret = env->exception_index;
 187                     break;
 188                 } else if (env->user_mode_only) {
 189                     /* if user mode only, we simulate a fake exception
 190                        which will be hanlded outside the cpu execution
 191                        loop */
 192 #if defined(TARGET_I386)
 193                     do_interrupt_user(env->exception_index,
 194                                       env->exception_is_int,
 195                                       env->error_code,
 196                                       env->exception_next_eip);
 197 #endif
 198                     ret = env->exception_index;
 199                     break;
 200                 } else {
 201 #if defined(TARGET_I386)
 202                     /* simulate a real cpu exception. On i386, it can
 203                        trigger new exceptions, but we do not handle
 204                        double or triple faults yet. */
 205                     do_interrupt(env->exception_index,
 206                                  env->exception_is_int,
 207                                  env->error_code,
 208                                  env->exception_next_eip, 0);
 209 #elif defined(TARGET_PPC)
 210                     do_interrupt(env);
 211 #endif
 212                 }
 213                 env->exception_index = -1;
 214             }
 215             T0 = 0; /* force lookup of first TB */
 216             for(;;) {
 217 #ifdef __sparc__
 218                 /* g1 can be modified by some libc? functions */
 219                 tmp_T0 = T0;
 220 #endif
 221                 interrupt_request = env->interrupt_request;
 222                 if (__builtin_expect(interrupt_request, 0)) {
 223 #if defined(TARGET_I386)
 224                     /* if hardware interrupt pending, we execute it */
 225                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 226                         (env->eflags & IF_MASK) &&
 227                         !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
 228                         int intno;
 229                         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 230                         intno = cpu_get_pic_interrupt(env);
 231                         if (loglevel & CPU_LOG_TB_IN_ASM) {
 232                             fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
 233                         }
 234                         do_interrupt(intno, 0, 0, 0, 1);
 235                         /* ensure that no TB jump will be modified as
 236                            the program flow was changed */
 237 #ifdef __sparc__
 238                         tmp_T0 = 0;
 239 #else
 240                         T0 = 0;
 241 #endif
 242                     }
 243 #elif defined(TARGET_PPC)
 244 #if 0
 245                     if ((interrupt_request & CPU_INTERRUPT_RESET)) {
 246                         cpu_ppc_reset(env);
 247                     }
 248 #endif
 249                     if (msr_ee != 0) {
 250                     if ((interrupt_request & CPU_INTERRUPT_HARD)) {
 251                             /* Raise it */
 252                             env->exception_index = EXCP_EXTERNAL;
 253                             env->error_code = 0;
 254                             do_interrupt(env);
 255                         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 256                         } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
 257                             /* Raise it */
 258                             env->exception_index = EXCP_DECR;
 259                             env->error_code = 0;
 260                             do_interrupt(env);
 261                             env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
 262                         }
 263                     }
 264 #endif
 265                     if (interrupt_request & CPU_INTERRUPT_EXITTB) {
 266                         env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
 267                         /* ensure that no TB jump will be modified as
 268                            the program flow was changed */
 269 #ifdef __sparc__
 270                         tmp_T0 = 0;
 271 #else
 272                         T0 = 0;
 273 #endif
 274                     }
 275                     if (interrupt_request & CPU_INTERRUPT_EXIT) {
 276                         env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
 277                         env->exception_index = EXCP_INTERRUPT;
 278                         cpu_loop_exit();
 279                     }
 280                 }
 281 #ifdef DEBUG_EXEC
 282                 if (loglevel & CPU_LOG_EXEC) {
 283 #if defined(TARGET_I386)
 284                     /* restore flags in standard format */
 285                     env->regs[R_EAX] = EAX;
 286                     env->regs[R_EBX] = EBX;
 287                     env->regs[R_ECX] = ECX;
 288                     env->regs[R_EDX] = EDX;
 289                     env->regs[R_ESI] = ESI;
 290                     env->regs[R_EDI] = EDI;
 291                     env->regs[R_EBP] = EBP;
 292                     env->regs[R_ESP] = ESP;
 293                     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 294                     cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
 295                     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 296 #elif defined(TARGET_ARM)
 297                     env->cpsr = compute_cpsr();
 298                     cpu_arm_dump_state(env, logfile, 0);
 299                     env->cpsr &= ~0xf0000000;
 300 #elif defined(TARGET_SPARC)
 301                     cpu_sparc_dump_state (env, logfile, 0);
 302 #elif defined(TARGET_PPC)
 303                     cpu_ppc_dump_state(env, logfile, 0);
 304 #else
 305 #error unsupported target CPU
 306 #endif
 307                 }
 308 #endif
 309                 /* we record a subset of the CPU state. It will
 310                    always be the same before a given translated block
 311                    is executed. */
 312 #if defined(TARGET_I386)
 313                 flags = env->hflags;
 314                 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
 315                 cs_base = env->segs[R_CS].base;
 316                 pc = cs_base + env->eip;
 317 #elif defined(TARGET_ARM)
 318                 flags = 0;
 319                 cs_base = 0;
 320                 pc = (uint8_t *)env->regs[15];
 321 #elif defined(TARGET_SPARC)
 322                 flags = 0;
 323                 cs_base = (uint8_t *)env->npc;
 324                 pc = (uint8_t *) env->pc;
 325 #elif defined(TARGET_PPC)
 326                 flags = 0;
 327                 cs_base = 0;
 328                 pc = (uint8_t *)env->nip;
 329 #else
 330 #error unsupported CPU
 331 #endif
 332                 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
 333                              flags);
 334                 if (!tb) {
 335                     TranslationBlock **ptb1;
 336                     unsigned int h;
 337                     target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
 338
 339
 340                     spin_lock(&tb_lock);
 341
 342                     tb_invalidated_flag = 0;
 343
 344                     /* find translated block using physical mappings */
 345                     phys_pc = get_phys_addr_code(env, (unsigned long)pc);
 346                     phys_page1 = phys_pc & TARGET_PAGE_MASK;
 347                     phys_page2 = -1;
 348                     h = tb_phys_hash_func(phys_pc);
 349                     ptb1 = &tb_phys_hash[h];
 350                     for(;;) {
 351                         tb = *ptb1;
 352                         if (!tb)
 353                             goto not_found;
 354                         if (tb->pc == (unsigned long)pc &&
 355                             tb->page_addr[0] == phys_page1 &&
 356                             tb->cs_base == (unsigned long)cs_base &&
 357                             tb->flags == flags) {
 358                             /* check next page if needed */
 359                             if (tb->page_addr[1] != -1) {
 360                                 virt_page2 = ((unsigned long)pc & TARGET_PAGE_MASK) +
 361                                     TARGET_PAGE_SIZE;
 362                                 phys_page2 = get_phys_addr_code(env, virt_page2);
 363                                 if (tb->page_addr[1] == phys_page2)
 364                                     goto found;
 365                             } else {
 366                                 goto found;
 367                             }
 368                         }
 369                         ptb1 = &tb->phys_hash_next;
 370                     }
 371                 not_found:
 372                     /* if no translated code available, then translate it now */
 373                     tb = tb_alloc((unsigned long)pc);
 374                     if (!tb) {
 375                         /* flush must be done */
 376                         tb_flush(env);
 377                         /* cannot fail at this point */
 378                         tb = tb_alloc((unsigned long)pc);
 379                         /* don't forget to invalidate previous TB info */
 380                         ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
 381                         T0 = 0;
 382                     }
 383                     tc_ptr = code_gen_ptr;
 384                     tb->tc_ptr = tc_ptr;
 385                     tb->cs_base = (unsigned long)cs_base;
 386                     tb->flags = flags;
 387                     cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
 388                     code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
 389
 390                     /* check next page if needed */
 391                     virt_page2 = ((unsigned long)pc + tb->size - 1) & TARGET_PAGE_MASK;
 392                     phys_page2 = -1;
 393                     if (((unsigned long)pc & TARGET_PAGE_MASK) != virt_page2) {
 394                         phys_page2 = get_phys_addr_code(env, virt_page2);
 395                     }
 396                     tb_link_phys(tb, phys_pc, phys_page2);
 397
 398                 found:
 399                     if (tb_invalidated_flag) {
 400                         /* as some TB could have been invalidated because
 401                            of memory exceptions while generating the code, we
 402                            must recompute the hash index here */
 403                         ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
 404                         while (*ptb != NULL)
 405                             ptb = &(*ptb)->hash_next;
 406                         T0 = 0;
 407                     }
 408                     /* we add the TB in the virtual pc hash table */
 409                     *ptb = tb;
 410                     tb->hash_next = NULL;
 411                     tb_link(tb);
 412                     spin_unlock(&tb_lock);
 413                 }
 414 #ifdef DEBUG_EXEC
 415                 if (loglevel & CPU_LOG_EXEC) {
 416                     fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
 417                             (long)tb->tc_ptr, (long)tb->pc,
 418                             lookup_symbol((void *)tb->pc));
 419                 }
 420 #endif
 421 #ifdef __sparc__
 422                 T0 = tmp_T0;
 423 #endif
 424                 /* see if we can patch the calling TB. */
 425                 if (T0 != 0
 426 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
 427                     && (tb->cflags & CF_CODE_COPY) ==
 428                     (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
 429 #endif
 430                     ) {
 431                     spin_lock(&tb_lock);
 432                     tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
 433 #if defined(USE_CODE_COPY)
 434                     /* propagates the FP use info */
 435                     ((TranslationBlock *)(T0 & ~3))->cflags |=
 436                         (tb->cflags & CF_FP_USED);
 437 #endif
 438                     spin_unlock(&tb_lock);
 439                 }
 440                 tc_ptr = tb->tc_ptr;
 441                 env->current_tb = tb;
 442                 /* execute the generated code */
 443                 gen_func = (void *)tc_ptr;
 444 #if defined(__sparc__)
 445                 __asm__ __volatile__("call      %0\n\t"
 446                                      "mov       %%o7,%%i0"
 447                                      : /* no outputs */
 448                                      : "r" (gen_func)
 449                                      : "i0", "i1", "i2", "i3", "i4", "i5");
 450 #elif defined(__arm__)
 451                 asm volatile ("mov pc, %0\n\t"
 452                               ".global exec_loop\n\t"
 453                               "exec_loop:\n\t"
 454                               : /* no outputs */
 455                               : "r" (gen_func)
 456                               : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
 457 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
 458 {
 459     if (!(tb->cflags & CF_CODE_COPY)) {
 460         if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
 461             save_native_fp_state(env);
 462         }
 463         gen_func();
 464     } else {
 465         if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
 466             restore_native_fp_state(env);
 467         }
 468         /* we work with native eflags */
 469         CC_SRC = cc_table[CC_OP].compute_all();
 470         CC_OP = CC_OP_EFLAGS;
 471         asm(".globl exec_loop\n"
 472             "\n"
 473             "debug1:\n"
 474             "    pushl %%ebp\n"
 475             "    fs movl %10, %9\n"
 476             "    fs movl %11, %%eax\n"
 477             "    andl $0x400, %%eax\n"
 478             "    fs orl %8, %%eax\n"
 479             "    pushl %%eax\n"
 480             "    popf\n"
 481             "    fs movl %%esp, %12\n"
 482             "    fs movl %0, %%eax\n"
 483             "    fs movl %1, %%ecx\n"
 484             "    fs movl %2, %%edx\n"
 485             "    fs movl %3, %%ebx\n"
 486             "    fs movl %4, %%esp\n"
 487             "    fs movl %5, %%ebp\n"
 488             "    fs movl %6, %%esi\n"
 489             "    fs movl %7, %%edi\n"
 490             "    fs jmp *%9\n"
 491             "exec_loop:\n"
 492             "    fs movl %%esp, %4\n"
 493             "    fs movl %12, %%esp\n"
 494             "    fs movl %%eax, %0\n"
 495             "    fs movl %%ecx, %1\n"
 496             "    fs movl %%edx, %2\n"
 497             "    fs movl %%ebx, %3\n"
 498             "    fs movl %%ebp, %5\n"
 499             "    fs movl %%esi, %6\n"
 500             "    fs movl %%edi, %7\n"
 501             "    pushf\n"
 502             "    popl %%eax\n"
 503             "    movl %%eax, %%ecx\n"
 504             "    andl $0x400, %%ecx\n"
 505             "    shrl $9, %%ecx\n"
 506             "    andl $0x8d5, %%eax\n"
 507             "    fs movl %%eax, %8\n"
 508             "    movl $1, %%eax\n"
 509             "    subl %%ecx, %%eax\n"
 510             "    fs movl %%eax, %11\n"
 511             "    fs movl %9, %%ebx\n" /* get T0 value */
 512             "    popl %%ebp\n"
 513             :
 514             : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
 515             "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
 516             "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
 517             "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
 518             "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
 519             "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
 520             "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
 521             "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
 522             "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
 523             "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
 524             "a" (gen_func),
 525             "m" (*(uint8_t *)offsetof(CPUState, df)),
 526             "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
 527             : "%ecx", "%edx"
 528             );
 529     }
 530 }
 531 #else
 532                 gen_func();
 533 #endif
 534                 env->current_tb = NULL;
 535                 /* reset soft MMU for next block (it can currently
 536                    only be set by a memory fault) */
 537 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
 538                 if (env->hflags & HF_SOFTMMU_MASK) {
 539                     env->hflags &= ~HF_SOFTMMU_MASK;
 540                     /* do not allow linking to another block */
 541                     T0 = 0;
 542                 }
 543 #endif
 544             }
 545         } else {
 546         }
 547     } /* for(;;) */
 548
 549
 550 #if defined(TARGET_I386)
 551 #if defined(USE_CODE_COPY)
 552     if (env->native_fp_regs) {
 553         save_native_fp_state(env);
 554     }
 555 #endif
 556     /* restore flags in standard format */
 557     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 558
 559     /* restore global registers */
 560 #ifdef reg_EAX
 561     EAX = saved_EAX;
 562 #endif
 563 #ifdef reg_ECX
 564     ECX = saved_ECX;
 565 #endif
 566 #ifdef reg_EDX
 567     EDX = saved_EDX;
 568 #endif
 569 #ifdef reg_EBX
 570     EBX = saved_EBX;
 571 #endif
 572 #ifdef reg_ESP
 573     ESP = saved_ESP;
 574 #endif
 575 #ifdef reg_EBP
 576     EBP = saved_EBP;
 577 #endif
 578 #ifdef reg_ESI
 579     ESI = saved_ESI;
 580 #endif
 581 #ifdef reg_EDI
 582     EDI = saved_EDI;
 583 #endif
 584 #elif defined(TARGET_ARM)
 585     env->cpsr = compute_cpsr();
 586 #elif defined(TARGET_SPARC)
 587 #elif defined(TARGET_PPC)
 588 #else
 589 #error unsupported target CPU
 590 #endif
 591 #ifdef __sparc__
 592     asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
 593 #endif
 594     T0 = saved_T0;
 595     T1 = saved_T1;
 596     T2 = saved_T2;
 597     env = saved_env;
 598     return ret;
 599 }
 600
 601 /* must only be called from the generated code as an exception can be
 602    generated */
 603 void tb_invalidate_page_range(target_ulong start, target_ulong end)
 604 {
 605     target_ulong phys_addr;
 606     phys_addr = get_phys_addr_code(env, start);
 607     tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
 608 }
 609
 610 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
 611
 612 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
 613 {
 614     CPUX86State *saved_env;
 615
 616     saved_env = env;
 617     env = s;
 618     if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
 619         selector &= 0xffff;
 620         cpu_x86_load_seg_cache(env, seg_reg, selector,
 621                                (uint8_t *)(selector << 4), 0xffff, 0);
 622     } else {
 623         load_seg(seg_reg, selector);
 624     }
 625     env = saved_env;
 626 }
 627
 628 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
 629 {
 630     CPUX86State *saved_env;
 631
 632     saved_env = env;
 633     env = s;
 634
 635     helper_fsave(ptr, data32);
 636
 637     env = saved_env;
 638 }
 639
 640 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
 641 {
 642     CPUX86State *saved_env;
 643
 644     saved_env = env;
 645     env = s;
 646
 647     helper_frstor(ptr, data32);
 648
 649     env = saved_env;
 650 }
 651
 652 #endif /* TARGET_I386 */
 653
 654 #if !defined(CONFIG_SOFTMMU)
 655
 656 #if defined(TARGET_I386)
 657
 658 /* 'pc' is the host PC at which the exception was raised. 'address' is
 659    the effective address of the memory exception. 'is_write' is 1 if a
 660    write caused the exception and otherwise 0'. 'old_set' is the
 661    signal set which should be restored */
 662 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 663                                     int is_write, sigset_t *old_set,
 664                                     void *puc)
 665 {
 666     TranslationBlock *tb;
 667     int ret;
 668
 669     if (cpu_single_env)
 670         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 671 #if defined(DEBUG_SIGNAL)
 672     qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 673                 pc, address, is_write, *(unsigned long *)old_set);
 674 #endif
 675     /* XXX: locking issue */
 676     if (is_write && page_unprotect(address, pc, puc)) {
 677         return 1;
 678     }
 679
 680     /* see if it is an MMU fault */
 681     ret = cpu_x86_handle_mmu_fault(env, address, is_write,
 682                                    ((env->hflags & HF_CPL_MASK) == 3), 0);
 683     if (ret < 0)
 684         return 0; /* not an MMU fault */
 685     if (ret == 0)
 686         return 1; /* the MMU fault was handled without causing real CPU fault */
 687     /* now we have a real cpu fault */
 688     tb = tb_find_pc(pc);
 689     if (tb) {
 690         /* the PC is inside the translated code. It means that we have
 691            a virtual CPU fault */
 692         cpu_restore_state(tb, env, pc, puc);
 693     }
 694     if (ret == 1) {
 695 #if 0
 696         printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
 697                env->eip, env->cr[2], env->error_code);
 698 #endif
 699         /* we restore the process signal mask as the sigreturn should
 700            do it (XXX: use sigsetjmp) */
 701         sigprocmask(SIG_SETMASK, old_set, NULL);
 702         raise_exception_err(EXCP0E_PAGE, env->error_code);
 703     } else {
 704         /* activate soft MMU for this block */
 705         env->hflags |= HF_SOFTMMU_MASK;
 706         cpu_resume_from_signal(env, puc);
 707     }
 708     /* never comes here */
 709     return 1;
 710 }
 711
 712 #elif defined(TARGET_ARM)
 713 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 714                                     int is_write, sigset_t *old_set,
 715                                     void *puc)
 716 {
 717     /* XXX: do more */
 718     return 0;
 719 }
 720 #elif defined(TARGET_SPARC)
 721 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 722                                     int is_write, sigset_t *old_set,
 723                                     void *puc)
 724 {
 725     /* XXX: locking issue */
 726     if (is_write && page_unprotect(address, pc, puc)) {
 727         return 1;
 728     }
 729     return 0;
 730 }
 731 #elif defined (TARGET_PPC)
 732 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 733                                     int is_write, sigset_t *old_set,
 734                                     void *puc)
 735 {
 736     TranslationBlock *tb;
 737     int ret;
 738
 739 #if 1
 740     if (cpu_single_env)
 741         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 742 #endif
 743 #if defined(DEBUG_SIGNAL)
 744     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 745            pc, address, is_write, *(unsigned long *)old_set);
 746 #endif
 747     /* XXX: locking issue */
 748     if (is_write && page_unprotect(address, pc, puc)) {
 749         return 1;
 750     }
 751
 752     /* see if it is an MMU fault */
 753     ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
 754     if (ret < 0)
 755         return 0; /* not an MMU fault */
 756     if (ret == 0)
 757         return 1; /* the MMU fault was handled without causing real CPU fault */
 758
 759     /* now we have a real cpu fault */
 760     tb = tb_find_pc(pc);
 761     if (tb) {
 762         /* the PC is inside the translated code. It means that we have
 763            a virtual CPU fault */
 764         cpu_restore_state(tb, env, pc, puc);
 765     }
 766     if (ret == 1) {
 767 #if 0
 768         printf("PF exception: NIP=0x%08x error=0x%x %p\n",
 769                env->nip, env->error_code, tb);
 770 #endif
 771     /* we restore the process signal mask as the sigreturn should
 772        do it (XXX: use sigsetjmp) */
 773         sigprocmask(SIG_SETMASK, old_set, NULL);
 774         do_raise_exception_err(env->exception_index, env->error_code);
 775     } else {
 776         /* activate soft MMU for this block */
 777         cpu_resume_from_signal(env, puc);
 778     }
 779     /* never comes here */
 780     return 1;
 781 }
 782 #else
 783 #error unsupported target CPU
 784 #endif
 785
 786 #if defined(__i386__)
 787
 788 #if defined(USE_CODE_COPY)
 789 static void cpu_send_trap(unsigned long pc, int trap,
 790                           struct ucontext *uc)
 791 {
 792     TranslationBlock *tb;
 793
 794     if (cpu_single_env)
 795         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 796     /* now we have a real cpu fault */
 797     tb = tb_find_pc(pc);
 798     if (tb) {
 799         /* the PC is inside the translated code. It means that we have
 800            a virtual CPU fault */
 801         cpu_restore_state(tb, env, pc, uc);
 802     }
 803     sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
 804     raise_exception_err(trap, env->error_code);
 805 }
 806 #endif
 807
 808 int cpu_signal_handler(int host_signum, struct siginfo *info,
 809                        void *puc)
 810 {
 811     struct ucontext *uc = puc;
 812     unsigned long pc;
 813     int trapno;
 814
 815 #ifndef REG_EIP
 816 /* for glibc 2.1 */
 817 #define REG_EIP    EIP
 818 #define REG_ERR    ERR
 819 #define REG_TRAPNO TRAPNO
 820 #endif
 821     pc = uc->uc_mcontext.gregs[REG_EIP];
 822     trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
 823 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
 824     if (trapno == 0x00 || trapno == 0x05) {
 825         /* send division by zero or bound exception */
 826         cpu_send_trap(pc, trapno, uc);
 827         return 1;
 828     } else
 829 #endif
 830         return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 831                                  trapno == 0xe ?
 832                                  (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
 833                                  &uc->uc_sigmask, puc);
 834 }
 835
 836 #elif defined(__x86_64__)
 837
 838 int cpu_signal_handler(int host_signum, struct siginfo *info,
 839                        void *puc)
 840 {
 841     struct ucontext *uc = puc;
 842     unsigned long pc;
 843
 844     pc = uc->uc_mcontext.gregs[REG_RIP];
 845     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 846                              uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
 847                              (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
 848                              &uc->uc_sigmask, puc);
 849 }
 850
 851 #elif defined(__powerpc)
 852
 853 int cpu_signal_handler(int host_signum, struct siginfo *info,
 854                        void *puc)
 855 {
 856     struct ucontext *uc = puc;
 857     struct pt_regs *regs = uc->uc_mcontext.regs;
 858     unsigned long pc;
 859     int is_write;
 860
 861     pc = regs->nip;
 862     is_write = 0;
 863 #if 0
 864     /* ppc 4xx case */
 865     if (regs->dsisr & 0x00800000)
 866         is_write = 1;
 867 #else
 868     if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
 869         is_write = 1;
 870 #endif
 871     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 872                              is_write, &uc->uc_sigmask, puc);
 873 }
 874
 875 #elif defined(__alpha__)
 876
 877 int cpu_signal_handler(int host_signum, struct siginfo *info,
 878                            void *puc)
 879 {
 880     struct ucontext *uc = puc;
 881     uint32_t *pc = uc->uc_mcontext.sc_pc;
 882     uint32_t insn = *pc;
 883     int is_write = 0;
 884
 885     /* XXX: need kernel patch to get write flag faster */
 886     switch (insn >> 26) {
 887     case 0x0d: // stw
 888     case 0x0e: // stb
 889     case 0x0f: // stq_u
 890     case 0x24: // stf
 891     case 0x25: // stg
 892     case 0x26: // sts
 893     case 0x27: // stt
 894     case 0x2c: // stl
 895     case 0x2d: // stq
 896     case 0x2e: // stl_c
 897     case 0x2f: // stq_c
 898         is_write = 1;
 899     }
 900
 901     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 902                              is_write, &uc->uc_sigmask, puc);
 903 }
 904 #elif defined(__sparc__)
 905
 906 int cpu_signal_handler(int host_signum, struct siginfo *info,
 907                        void *puc)
 908 {
 909     uint32_t *regs = (uint32_t *)(info + 1);
 910     void *sigmask = (regs + 20);
 911     unsigned long pc;
 912     int is_write;
 913     uint32_t insn;
 914
 915     /* XXX: is there a standard glibc define ? */
 916     pc = regs[1];
 917     /* XXX: need kernel patch to get write flag faster */
 918     is_write = 0;
 919     insn = *(uint32_t *)pc;
 920     if ((insn >> 30) == 3) {
 921       switch((insn >> 19) & 0x3f) {
 922       case 0x05: // stb
 923       case 0x06: // sth
 924       case 0x04: // st
 925       case 0x07: // std
 926       case 0x24: // stf
 927       case 0x27: // stdf
 928       case 0x25: // stfsr
 929         is_write = 1;
 930         break;
 931       }
 932     }
 933     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 934                              is_write, sigmask, NULL);
 935 }
 936
 937 #elif defined(__arm__)
 938
 939 int cpu_signal_handler(int host_signum, struct siginfo *info,
 940                        void *puc)
 941 {
 942     struct ucontext *uc = puc;
 943     unsigned long pc;
 944     int is_write;
 945
 946     pc = uc->uc_mcontext.gregs[R15];
 947     /* XXX: compute is_write */
 948     is_write = 0;
 949     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 950                              is_write,
 951                              &uc->uc_sigmask);
 952 }
 953
 954 #elif defined(__mc68000)
 955
 956 int cpu_signal_handler(int host_signum, struct siginfo *info,
 957                        void *puc)
 958 {
 959     struct ucontext *uc = puc;
 960     unsigned long pc;
 961     int is_write;
 962
 963     pc = uc->uc_mcontext.gregs[16];
 964     /* XXX: compute is_write */
 965     is_write = 0;
 966     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 967                              is_write,
 968                              &uc->uc_sigmask, puc);
 969 }
 970
 971 #else
 972
 973 #error host CPU specific signal handler needed
 974
 975 #endif
 976
 977 #endif /* !defined(CONFIG_SOFTMMU) */