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target-arm: Detect tininess before rounding for FP operations
[qemu.git] / hw / cirrus_vga.c
blob2724f7b480af74844b14e483dfe2763ba4347bcb
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "hw.h"
30 #include "pc.h"
31 #include "pci.h"
32 #include "console.h"
33 #include "vga_int.h"
34 #include "loader.h"
35
36 /*
37 * TODO:
38 * - destination write mask support not complete (bits 5..7)
39 * - optimize linear mappings
40 * - optimize bitblt functions
41 */
42
43 //#define DEBUG_CIRRUS
44 //#define DEBUG_BITBLT
45
46 /***************************************
47 *
48 * definitions
49 *
50 ***************************************/
51
52 // ID
53 #define CIRRUS_ID_CLGD5422 (0x23<<2)
54 #define CIRRUS_ID_CLGD5426 (0x24<<2)
55 #define CIRRUS_ID_CLGD5424 (0x25<<2)
56 #define CIRRUS_ID_CLGD5428 (0x26<<2)
57 #define CIRRUS_ID_CLGD5430 (0x28<<2)
58 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
59 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
60 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
61
62 // sequencer 0x07
63 #define CIRRUS_SR7_BPP_VGA 0x00
64 #define CIRRUS_SR7_BPP_SVGA 0x01
65 #define CIRRUS_SR7_BPP_MASK 0x0e
66 #define CIRRUS_SR7_BPP_8 0x00
67 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
68 #define CIRRUS_SR7_BPP_24 0x04
69 #define CIRRUS_SR7_BPP_16 0x06
70 #define CIRRUS_SR7_BPP_32 0x08
71 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
72
73 // sequencer 0x0f
74 #define CIRRUS_MEMSIZE_512k 0x08
75 #define CIRRUS_MEMSIZE_1M 0x10
76 #define CIRRUS_MEMSIZE_2M 0x18
77 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
78
79 // sequencer 0x12
80 #define CIRRUS_CURSOR_SHOW 0x01
81 #define CIRRUS_CURSOR_HIDDENPEL 0x02
82 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
83
84 // sequencer 0x17
85 #define CIRRUS_BUSTYPE_VLBFAST 0x10
86 #define CIRRUS_BUSTYPE_PCI 0x20
87 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
88 #define CIRRUS_BUSTYPE_ISA 0x38
89 #define CIRRUS_MMIO_ENABLE 0x04
90 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
91 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
92
93 // control 0x0b
94 #define CIRRUS_BANKING_DUAL 0x01
95 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
96
97 // control 0x30
98 #define CIRRUS_BLTMODE_BACKWARDS 0x01
99 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
100 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
101 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
102 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
103 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
104 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
105 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
106 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
107 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
108 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
109
110 // control 0x31
111 #define CIRRUS_BLT_BUSY 0x01
112 #define CIRRUS_BLT_START 0x02
113 #define CIRRUS_BLT_RESET 0x04
114 #define CIRRUS_BLT_FIFOUSED 0x10
115 #define CIRRUS_BLT_AUTOSTART 0x80
116
117 // control 0x32
118 #define CIRRUS_ROP_0 0x00
119 #define CIRRUS_ROP_SRC_AND_DST 0x05
120 #define CIRRUS_ROP_NOP 0x06
121 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
122 #define CIRRUS_ROP_NOTDST 0x0b
123 #define CIRRUS_ROP_SRC 0x0d
124 #define CIRRUS_ROP_1 0x0e
125 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
126 #define CIRRUS_ROP_SRC_XOR_DST 0x59
127 #define CIRRUS_ROP_SRC_OR_DST 0x6d
128 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
129 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
130 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
131 #define CIRRUS_ROP_NOTSRC 0xd0
132 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
133 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
134
135 #define CIRRUS_ROP_NOP_INDEX 2
136 #define CIRRUS_ROP_SRC_INDEX 5
137
138 // control 0x33
139 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
140 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
141 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
142
143 // memory-mapped IO
144 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
145 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
146 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
147 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
148 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
149 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
150 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
151 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
152 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
153 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
154 #define CIRRUS_MMIO_BLTROP 0x1a // byte
155 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
156 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
157 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
158 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
159 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
160 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
161 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
162 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
163 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
164 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
166 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
167 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
168 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
169 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
170 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
171 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
172 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
173
174 #define CIRRUS_PNPMMIO_SIZE 0x1000
175
176 #define ABS(a) ((signed)(a) > 0 ? a : -a)
177
178 #define BLTUNSAFE(s) \
179 ( \
180 ( /* check dst is within bounds */ \
181 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
182 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
183 (s)->vga.vram_size \
184 ) || \
185 ( /* check src is within bounds */ \
186 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
187 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
188 (s)->vga.vram_size \
189 ) \
190 )
191
192 struct CirrusVGAState;
193 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
194 uint8_t * dst, const uint8_t * src,
195 int dstpitch, int srcpitch,
196 int bltwidth, int bltheight);
197 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
198 uint8_t *dst, int dst_pitch, int width, int height);
199
200 typedef struct CirrusVGAState {
201 VGACommonState vga;
202
203 int cirrus_linear_io_addr;
204 int cirrus_linear_bitblt_io_addr;
205 int cirrus_mmio_io_addr;
206 uint32_t cirrus_addr_mask;
207 uint32_t linear_mmio_mask;
208 uint8_t cirrus_shadow_gr0;
209 uint8_t cirrus_shadow_gr1;
210 uint8_t cirrus_hidden_dac_lockindex;
211 uint8_t cirrus_hidden_dac_data;
212 uint32_t cirrus_bank_base[2];
213 uint32_t cirrus_bank_limit[2];
214 uint8_t cirrus_hidden_palette[48];
215 uint32_t hw_cursor_x;
216 uint32_t hw_cursor_y;
217 int cirrus_blt_pixelwidth;
218 int cirrus_blt_width;
219 int cirrus_blt_height;
220 int cirrus_blt_dstpitch;
221 int cirrus_blt_srcpitch;
222 uint32_t cirrus_blt_fgcol;
223 uint32_t cirrus_blt_bgcol;
224 uint32_t cirrus_blt_dstaddr;
225 uint32_t cirrus_blt_srcaddr;
226 uint8_t cirrus_blt_mode;
227 uint8_t cirrus_blt_modeext;
228 cirrus_bitblt_rop_t cirrus_rop;
229 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
230 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
231 uint8_t *cirrus_srcptr;
232 uint8_t *cirrus_srcptr_end;
233 uint32_t cirrus_srccounter;
234 /* hwcursor display state */
235 int last_hw_cursor_size;
236 int last_hw_cursor_x;
237 int last_hw_cursor_y;
238 int last_hw_cursor_y_start;
239 int last_hw_cursor_y_end;
240 int real_vram_size; /* XXX: suppress that */
241 int device_id;
242 int bustype;
243 } CirrusVGAState;
244
245 typedef struct PCICirrusVGAState {
246 PCIDevice dev;
247 CirrusVGAState cirrus_vga;
248 } PCICirrusVGAState;
249
250 static uint8_t rop_to_index[256];
251
252 /***************************************
253 *
254 * prototypes.
255 *
256 ***************************************/
257
258
259 static void cirrus_bitblt_reset(CirrusVGAState *s);
260 static void cirrus_update_memory_access(CirrusVGAState *s);
261
262 /***************************************
263 *
264 * raster operations
265 *
266 ***************************************/
267
268 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
269 uint8_t *dst,const uint8_t *src,
270 int dstpitch,int srcpitch,
271 int bltwidth,int bltheight)
272 {
273 }
274
275 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
276 uint8_t *dst,
277 int dstpitch, int bltwidth,int bltheight)
278 {
279 }
280
281 #define ROP_NAME 0
282 #define ROP_FN(d, s) 0
283 #include "cirrus_vga_rop.h"
284
285 #define ROP_NAME src_and_dst
286 #define ROP_FN(d, s) (s) & (d)
287 #include "cirrus_vga_rop.h"
288
289 #define ROP_NAME src_and_notdst
290 #define ROP_FN(d, s) (s) & (~(d))
291 #include "cirrus_vga_rop.h"
292
293 #define ROP_NAME notdst
294 #define ROP_FN(d, s) ~(d)
295 #include "cirrus_vga_rop.h"
296
297 #define ROP_NAME src
298 #define ROP_FN(d, s) s
299 #include "cirrus_vga_rop.h"
300
301 #define ROP_NAME 1
302 #define ROP_FN(d, s) ~0
303 #include "cirrus_vga_rop.h"
304
305 #define ROP_NAME notsrc_and_dst
306 #define ROP_FN(d, s) (~(s)) & (d)
307 #include "cirrus_vga_rop.h"
308
309 #define ROP_NAME src_xor_dst
310 #define ROP_FN(d, s) (s) ^ (d)
311 #include "cirrus_vga_rop.h"
312
313 #define ROP_NAME src_or_dst
314 #define ROP_FN(d, s) (s) | (d)
315 #include "cirrus_vga_rop.h"
316
317 #define ROP_NAME notsrc_or_notdst
318 #define ROP_FN(d, s) (~(s)) | (~(d))
319 #include "cirrus_vga_rop.h"
320
321 #define ROP_NAME src_notxor_dst
322 #define ROP_FN(d, s) ~((s) ^ (d))
323 #include "cirrus_vga_rop.h"
324
325 #define ROP_NAME src_or_notdst
326 #define ROP_FN(d, s) (s) | (~(d))
327 #include "cirrus_vga_rop.h"
328
329 #define ROP_NAME notsrc
330 #define ROP_FN(d, s) (~(s))
331 #include "cirrus_vga_rop.h"
332
333 #define ROP_NAME notsrc_or_dst
334 #define ROP_FN(d, s) (~(s)) | (d)
335 #include "cirrus_vga_rop.h"
336
337 #define ROP_NAME notsrc_and_notdst
338 #define ROP_FN(d, s) (~(s)) & (~(d))
339 #include "cirrus_vga_rop.h"
340
341 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
342 cirrus_bitblt_rop_fwd_0,
343 cirrus_bitblt_rop_fwd_src_and_dst,
344 cirrus_bitblt_rop_nop,
345 cirrus_bitblt_rop_fwd_src_and_notdst,
346 cirrus_bitblt_rop_fwd_notdst,
347 cirrus_bitblt_rop_fwd_src,
348 cirrus_bitblt_rop_fwd_1,
349 cirrus_bitblt_rop_fwd_notsrc_and_dst,
350 cirrus_bitblt_rop_fwd_src_xor_dst,
351 cirrus_bitblt_rop_fwd_src_or_dst,
352 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
353 cirrus_bitblt_rop_fwd_src_notxor_dst,
354 cirrus_bitblt_rop_fwd_src_or_notdst,
355 cirrus_bitblt_rop_fwd_notsrc,
356 cirrus_bitblt_rop_fwd_notsrc_or_dst,
357 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
358 };
359
360 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
361 cirrus_bitblt_rop_bkwd_0,
362 cirrus_bitblt_rop_bkwd_src_and_dst,
363 cirrus_bitblt_rop_nop,
364 cirrus_bitblt_rop_bkwd_src_and_notdst,
365 cirrus_bitblt_rop_bkwd_notdst,
366 cirrus_bitblt_rop_bkwd_src,
367 cirrus_bitblt_rop_bkwd_1,
368 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
369 cirrus_bitblt_rop_bkwd_src_xor_dst,
370 cirrus_bitblt_rop_bkwd_src_or_dst,
371 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
372 cirrus_bitblt_rop_bkwd_src_notxor_dst,
373 cirrus_bitblt_rop_bkwd_src_or_notdst,
374 cirrus_bitblt_rop_bkwd_notsrc,
375 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
376 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
377 };
378
379 #define TRANSP_ROP(name) {\
380 name ## _8,\
381 name ## _16,\
382 }
383 #define TRANSP_NOP(func) {\
384 func,\
385 func,\
386 }
387
388 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
389 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
390 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
391 TRANSP_NOP(cirrus_bitblt_rop_nop),
392 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
393 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
394 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
395 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
396 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
397 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
398 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
399 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
400 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
401 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
402 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
403 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
404 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
405 };
406
407 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
408 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
409 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
410 TRANSP_NOP(cirrus_bitblt_rop_nop),
411 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
412 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
413 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
414 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
415 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
416 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
417 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
418 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
419 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
420 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
421 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
422 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
423 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
424 };
425
426 #define ROP2(name) {\
427 name ## _8,\
428 name ## _16,\
429 name ## _24,\
430 name ## _32,\
431 }
432
433 #define ROP_NOP2(func) {\
434 func,\
435 func,\
436 func,\
437 func,\
438 }
439
440 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
441 ROP2(cirrus_patternfill_0),
442 ROP2(cirrus_patternfill_src_and_dst),
443 ROP_NOP2(cirrus_bitblt_rop_nop),
444 ROP2(cirrus_patternfill_src_and_notdst),
445 ROP2(cirrus_patternfill_notdst),
446 ROP2(cirrus_patternfill_src),
447 ROP2(cirrus_patternfill_1),
448 ROP2(cirrus_patternfill_notsrc_and_dst),
449 ROP2(cirrus_patternfill_src_xor_dst),
450 ROP2(cirrus_patternfill_src_or_dst),
451 ROP2(cirrus_patternfill_notsrc_or_notdst),
452 ROP2(cirrus_patternfill_src_notxor_dst),
453 ROP2(cirrus_patternfill_src_or_notdst),
454 ROP2(cirrus_patternfill_notsrc),
455 ROP2(cirrus_patternfill_notsrc_or_dst),
456 ROP2(cirrus_patternfill_notsrc_and_notdst),
457 };
458
459 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
460 ROP2(cirrus_colorexpand_transp_0),
461 ROP2(cirrus_colorexpand_transp_src_and_dst),
462 ROP_NOP2(cirrus_bitblt_rop_nop),
463 ROP2(cirrus_colorexpand_transp_src_and_notdst),
464 ROP2(cirrus_colorexpand_transp_notdst),
465 ROP2(cirrus_colorexpand_transp_src),
466 ROP2(cirrus_colorexpand_transp_1),
467 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
468 ROP2(cirrus_colorexpand_transp_src_xor_dst),
469 ROP2(cirrus_colorexpand_transp_src_or_dst),
470 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
471 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
472 ROP2(cirrus_colorexpand_transp_src_or_notdst),
473 ROP2(cirrus_colorexpand_transp_notsrc),
474 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
475 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
476 };
477
478 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
479 ROP2(cirrus_colorexpand_0),
480 ROP2(cirrus_colorexpand_src_and_dst),
481 ROP_NOP2(cirrus_bitblt_rop_nop),
482 ROP2(cirrus_colorexpand_src_and_notdst),
483 ROP2(cirrus_colorexpand_notdst),
484 ROP2(cirrus_colorexpand_src),
485 ROP2(cirrus_colorexpand_1),
486 ROP2(cirrus_colorexpand_notsrc_and_dst),
487 ROP2(cirrus_colorexpand_src_xor_dst),
488 ROP2(cirrus_colorexpand_src_or_dst),
489 ROP2(cirrus_colorexpand_notsrc_or_notdst),
490 ROP2(cirrus_colorexpand_src_notxor_dst),
491 ROP2(cirrus_colorexpand_src_or_notdst),
492 ROP2(cirrus_colorexpand_notsrc),
493 ROP2(cirrus_colorexpand_notsrc_or_dst),
494 ROP2(cirrus_colorexpand_notsrc_and_notdst),
495 };
496
497 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
498 ROP2(cirrus_colorexpand_pattern_transp_0),
499 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
500 ROP_NOP2(cirrus_bitblt_rop_nop),
501 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
502 ROP2(cirrus_colorexpand_pattern_transp_notdst),
503 ROP2(cirrus_colorexpand_pattern_transp_src),
504 ROP2(cirrus_colorexpand_pattern_transp_1),
505 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
506 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
507 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
508 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
509 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
510 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
511 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
512 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
513 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
514 };
515
516 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
517 ROP2(cirrus_colorexpand_pattern_0),
518 ROP2(cirrus_colorexpand_pattern_src_and_dst),
519 ROP_NOP2(cirrus_bitblt_rop_nop),
520 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
521 ROP2(cirrus_colorexpand_pattern_notdst),
522 ROP2(cirrus_colorexpand_pattern_src),
523 ROP2(cirrus_colorexpand_pattern_1),
524 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
525 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
526 ROP2(cirrus_colorexpand_pattern_src_or_dst),
527 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
528 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
529 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
530 ROP2(cirrus_colorexpand_pattern_notsrc),
531 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
532 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
533 };
534
535 static const cirrus_fill_t cirrus_fill[16][4] = {
536 ROP2(cirrus_fill_0),
537 ROP2(cirrus_fill_src_and_dst),
538 ROP_NOP2(cirrus_bitblt_fill_nop),
539 ROP2(cirrus_fill_src_and_notdst),
540 ROP2(cirrus_fill_notdst),
541 ROP2(cirrus_fill_src),
542 ROP2(cirrus_fill_1),
543 ROP2(cirrus_fill_notsrc_and_dst),
544 ROP2(cirrus_fill_src_xor_dst),
545 ROP2(cirrus_fill_src_or_dst),
546 ROP2(cirrus_fill_notsrc_or_notdst),
547 ROP2(cirrus_fill_src_notxor_dst),
548 ROP2(cirrus_fill_src_or_notdst),
549 ROP2(cirrus_fill_notsrc),
550 ROP2(cirrus_fill_notsrc_or_dst),
551 ROP2(cirrus_fill_notsrc_and_notdst),
552 };
553
554 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
555 {
556 unsigned int color;
557 switch (s->cirrus_blt_pixelwidth) {
558 case 1:
559 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
560 break;
561 case 2:
562 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
563 s->cirrus_blt_fgcol = le16_to_cpu(color);
564 break;
565 case 3:
566 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
567 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
568 break;
569 default:
570 case 4:
571 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
572 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
573 s->cirrus_blt_fgcol = le32_to_cpu(color);
574 break;
575 }
576 }
577
578 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
579 {
580 unsigned int color;
581 switch (s->cirrus_blt_pixelwidth) {
582 case 1:
583 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
584 break;
585 case 2:
586 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
587 s->cirrus_blt_bgcol = le16_to_cpu(color);
588 break;
589 case 3:
590 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
591 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
592 break;
593 default:
594 case 4:
595 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
596 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
597 s->cirrus_blt_bgcol = le32_to_cpu(color);
598 break;
599 }
600 }
601
602 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
603 int off_pitch, int bytesperline,
604 int lines)
605 {
606 int y;
607 int off_cur;
608 int off_cur_end;
609
610 for (y = 0; y < lines; y++) {
611 off_cur = off_begin;
612 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
613 off_cur &= TARGET_PAGE_MASK;
614 while (off_cur < off_cur_end) {
615 cpu_physical_memory_set_dirty(s->vga.vram_offset + off_cur);
616 off_cur += TARGET_PAGE_SIZE;
617 }
618 off_begin += off_pitch;
619 }
620 }
621
622 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
623 const uint8_t * src)
624 {
625 uint8_t *dst;
626
627 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
628
629 if (BLTUNSAFE(s))
630 return 0;
631
632 (*s->cirrus_rop) (s, dst, src,
633 s->cirrus_blt_dstpitch, 0,
634 s->cirrus_blt_width, s->cirrus_blt_height);
635 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
636 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
637 s->cirrus_blt_height);
638 return 1;
639 }
640
641 /* fill */
642
643 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
644 {
645 cirrus_fill_t rop_func;
646
647 if (BLTUNSAFE(s))
648 return 0;
649 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
650 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
651 s->cirrus_blt_dstpitch,
652 s->cirrus_blt_width, s->cirrus_blt_height);
653 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
654 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
655 s->cirrus_blt_height);
656 cirrus_bitblt_reset(s);
657 return 1;
658 }
659
660 /***************************************
661 *
662 * bitblt (video-to-video)
663 *
664 ***************************************/
665
666 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
667 {
668 return cirrus_bitblt_common_patterncopy(s,
669 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
670 s->cirrus_addr_mask));
671 }
672
673 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
674 {
675 int sx = 0, sy = 0;
676 int dx = 0, dy = 0;
677 int depth = 0;
678 int notify = 0;
679
680 /* make sure to only copy if it's a plain copy ROP */
681 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
682 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
683
684 int width, height;
685
686 depth = s->vga.get_bpp(&s->vga) / 8;
687 s->vga.get_resolution(&s->vga, &width, &height);
688
689 /* extra x, y */
690 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
691 sy = (src / ABS(s->cirrus_blt_srcpitch));
692 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
693 dy = (dst / ABS(s->cirrus_blt_dstpitch));
694
695 /* normalize width */
696 w /= depth;
697
698 /* if we're doing a backward copy, we have to adjust
699 our x/y to be the upper left corner (instead of the lower
700 right corner) */
701 if (s->cirrus_blt_dstpitch < 0) {
702 sx -= (s->cirrus_blt_width / depth) - 1;
703 dx -= (s->cirrus_blt_width / depth) - 1;
704 sy -= s->cirrus_blt_height - 1;
705 dy -= s->cirrus_blt_height - 1;
706 }
707
708 /* are we in the visible portion of memory? */
709 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
710 (sx + w) <= width && (sy + h) <= height &&
711 (dx + w) <= width && (dy + h) <= height) {
712 notify = 1;
713 }
714 }
715
716 /* we have to flush all pending changes so that the copy
717 is generated at the appropriate moment in time */
718 if (notify)
719 vga_hw_update();
720
721 (*s->cirrus_rop) (s, s->vga.vram_ptr +
722 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
723 s->vga.vram_ptr +
724 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
725 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
726 s->cirrus_blt_width, s->cirrus_blt_height);
727
728 if (notify)
729 qemu_console_copy(s->vga.ds,
730 sx, sy, dx, dy,
731 s->cirrus_blt_width / depth,
732 s->cirrus_blt_height);
733
734 /* we don't have to notify the display that this portion has
735 changed since qemu_console_copy implies this */
736
737 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
738 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
739 s->cirrus_blt_height);
740 }
741
742 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
743 {
744 if (BLTUNSAFE(s))
745 return 0;
746
747 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
748 s->cirrus_blt_srcaddr - s->vga.start_addr,
749 s->cirrus_blt_width, s->cirrus_blt_height);
750
751 return 1;
752 }
753
754 /***************************************
755 *
756 * bitblt (cpu-to-video)
757 *
758 ***************************************/
759
760 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
761 {
762 int copy_count;
763 uint8_t *end_ptr;
764
765 if (s->cirrus_srccounter > 0) {
766 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
767 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
768 the_end:
769 s->cirrus_srccounter = 0;
770 cirrus_bitblt_reset(s);
771 } else {
772 /* at least one scan line */
773 do {
774 (*s->cirrus_rop)(s, s->vga.vram_ptr +
775 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
776 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
777 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
778 s->cirrus_blt_width, 1);
779 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
780 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
781 if (s->cirrus_srccounter <= 0)
782 goto the_end;
783 /* more bytes than needed can be transfered because of
784 word alignment, so we keep them for the next line */
785 /* XXX: keep alignment to speed up transfer */
786 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
787 copy_count = s->cirrus_srcptr_end - end_ptr;
788 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
789 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
790 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
791 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
792 }
793 }
794 }
795
796 /***************************************
797 *
798 * bitblt wrapper
799 *
800 ***************************************/
801
802 static void cirrus_bitblt_reset(CirrusVGAState * s)
803 {
804 int need_update;
805
806 s->vga.gr[0x31] &=
807 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
808 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
809 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
810 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
811 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
812 s->cirrus_srccounter = 0;
813 if (!need_update)
814 return;
815 cirrus_update_memory_access(s);
816 }
817
818 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
819 {
820 int w;
821
822 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
823 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
824 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
825
826 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
827 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
828 s->cirrus_blt_srcpitch = 8;
829 } else {
830 /* XXX: check for 24 bpp */
831 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
832 }
833 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
834 } else {
835 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
836 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
837 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
838 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
839 else
840 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
841 } else {
842 /* always align input size to 32 bits */
843 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
844 }
845 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
846 }
847 s->cirrus_srcptr = s->cirrus_bltbuf;
848 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
849 cirrus_update_memory_access(s);
850 return 1;
851 }
852
853 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
854 {
855 /* XXX */
856 #ifdef DEBUG_BITBLT
857 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
858 #endif
859 return 0;
860 }
861
862 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
863 {
864 int ret;
865
866 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
867 ret = cirrus_bitblt_videotovideo_patterncopy(s);
868 } else {
869 ret = cirrus_bitblt_videotovideo_copy(s);
870 }
871 if (ret)
872 cirrus_bitblt_reset(s);
873 return ret;
874 }
875
876 static void cirrus_bitblt_start(CirrusVGAState * s)
877 {
878 uint8_t blt_rop;
879
880 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
881
882 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
883 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
884 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
885 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
886 s->cirrus_blt_dstaddr =
887 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
888 s->cirrus_blt_srcaddr =
889 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
890 s->cirrus_blt_mode = s->vga.gr[0x30];
891 s->cirrus_blt_modeext = s->vga.gr[0x33];
892 blt_rop = s->vga.gr[0x32];
893
894 #ifdef DEBUG_BITBLT
895 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
896 blt_rop,
897 s->cirrus_blt_mode,
898 s->cirrus_blt_modeext,
899 s->cirrus_blt_width,
900 s->cirrus_blt_height,
901 s->cirrus_blt_dstpitch,
902 s->cirrus_blt_srcpitch,
903 s->cirrus_blt_dstaddr,
904 s->cirrus_blt_srcaddr,
905 s->vga.gr[0x2f]);
906 #endif
907
908 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
909 case CIRRUS_BLTMODE_PIXELWIDTH8:
910 s->cirrus_blt_pixelwidth = 1;
911 break;
912 case CIRRUS_BLTMODE_PIXELWIDTH16:
913 s->cirrus_blt_pixelwidth = 2;
914 break;
915 case CIRRUS_BLTMODE_PIXELWIDTH24:
916 s->cirrus_blt_pixelwidth = 3;
917 break;
918 case CIRRUS_BLTMODE_PIXELWIDTH32:
919 s->cirrus_blt_pixelwidth = 4;
920 break;
921 default:
922 #ifdef DEBUG_BITBLT
923 printf("cirrus: bitblt - pixel width is unknown\n");
924 #endif
925 goto bitblt_ignore;
926 }
927 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
928
929 if ((s->
930 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
931 CIRRUS_BLTMODE_MEMSYSDEST))
932 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
933 #ifdef DEBUG_BITBLT
934 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
935 #endif
936 goto bitblt_ignore;
937 }
938
939 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
940 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
941 CIRRUS_BLTMODE_TRANSPARENTCOMP |
942 CIRRUS_BLTMODE_PATTERNCOPY |
943 CIRRUS_BLTMODE_COLOREXPAND)) ==
944 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
945 cirrus_bitblt_fgcol(s);
946 cirrus_bitblt_solidfill(s, blt_rop);
947 } else {
948 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
949 CIRRUS_BLTMODE_PATTERNCOPY)) ==
950 CIRRUS_BLTMODE_COLOREXPAND) {
951
952 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
953 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
954 cirrus_bitblt_bgcol(s);
955 else
956 cirrus_bitblt_fgcol(s);
957 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
958 } else {
959 cirrus_bitblt_fgcol(s);
960 cirrus_bitblt_bgcol(s);
961 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
962 }
963 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
964 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
965 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
966 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
967 cirrus_bitblt_bgcol(s);
968 else
969 cirrus_bitblt_fgcol(s);
970 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
971 } else {
972 cirrus_bitblt_fgcol(s);
973 cirrus_bitblt_bgcol(s);
974 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
975 }
976 } else {
977 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
978 }
979 } else {
980 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
981 if (s->cirrus_blt_pixelwidth > 2) {
982 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
983 goto bitblt_ignore;
984 }
985 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
986 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
987 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
988 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
989 } else {
990 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
991 }
992 } else {
993 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
994 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
995 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
996 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
997 } else {
998 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
999 }
1000 }
1001 }
1002 // setup bitblt engine.
1003 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1004 if (!cirrus_bitblt_cputovideo(s))
1005 goto bitblt_ignore;
1006 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1007 if (!cirrus_bitblt_videotocpu(s))
1008 goto bitblt_ignore;
1009 } else {
1010 if (!cirrus_bitblt_videotovideo(s))
1011 goto bitblt_ignore;
1012 }
1013 }
1014 return;
1015 bitblt_ignore:;
1016 cirrus_bitblt_reset(s);
1017 }
1018
1019 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1020 {
1021 unsigned old_value;
1022
1023 old_value = s->vga.gr[0x31];
1024 s->vga.gr[0x31] = reg_value;
1025
1026 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1027 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1028 cirrus_bitblt_reset(s);
1029 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1030 ((reg_value & CIRRUS_BLT_START) != 0)) {
1031 cirrus_bitblt_start(s);
1032 }
1033 }
1034
1035
1036 /***************************************
1037 *
1038 * basic parameters
1039 *
1040 ***************************************/
1041
1042 static void cirrus_get_offsets(VGACommonState *s1,
1043 uint32_t *pline_offset,
1044 uint32_t *pstart_addr,
1045 uint32_t *pline_compare)
1046 {
1047 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1048 uint32_t start_addr, line_offset, line_compare;
1049
1050 line_offset = s->vga.cr[0x13]
1051 | ((s->vga.cr[0x1b] & 0x10) << 4);
1052 line_offset <<= 3;
1053 *pline_offset = line_offset;
1054
1055 start_addr = (s->vga.cr[0x0c] << 8)
1056 | s->vga.cr[0x0d]
1057 | ((s->vga.cr[0x1b] & 0x01) << 16)
1058 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1059 | ((s->vga.cr[0x1d] & 0x80) << 12);
1060 *pstart_addr = start_addr;
1061
1062 line_compare = s->vga.cr[0x18] |
1063 ((s->vga.cr[0x07] & 0x10) << 4) |
1064 ((s->vga.cr[0x09] & 0x40) << 3);
1065 *pline_compare = line_compare;
1066 }
1067
1068 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1069 {
1070 uint32_t ret = 16;
1071
1072 switch (s->cirrus_hidden_dac_data & 0xf) {
1073 case 0:
1074 ret = 15;
1075 break; /* Sierra HiColor */
1076 case 1:
1077 ret = 16;
1078 break; /* XGA HiColor */
1079 default:
1080 #ifdef DEBUG_CIRRUS
1081 printf("cirrus: invalid DAC value %x in 16bpp\n",
1082 (s->cirrus_hidden_dac_data & 0xf));
1083 #endif
1084 ret = 15; /* XXX */
1085 break;
1086 }
1087 return ret;
1088 }
1089
1090 static int cirrus_get_bpp(VGACommonState *s1)
1091 {
1092 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1093 uint32_t ret = 8;
1094
1095 if ((s->vga.sr[0x07] & 0x01) != 0) {
1096 /* Cirrus SVGA */
1097 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1098 case CIRRUS_SR7_BPP_8:
1099 ret = 8;
1100 break;
1101 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1102 ret = cirrus_get_bpp16_depth(s);
1103 break;
1104 case CIRRUS_SR7_BPP_24:
1105 ret = 24;
1106 break;
1107 case CIRRUS_SR7_BPP_16:
1108 ret = cirrus_get_bpp16_depth(s);
1109 break;
1110 case CIRRUS_SR7_BPP_32:
1111 ret = 32;
1112 break;
1113 default:
1114 #ifdef DEBUG_CIRRUS
1115 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
1116 #endif
1117 ret = 8;
1118 break;
1119 }
1120 } else {
1121 /* VGA */
1122 ret = 0;
1123 }
1124
1125 return ret;
1126 }
1127
1128 static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1129 {
1130 int width, height;
1131
1132 width = (s->cr[0x01] + 1) * 8;
1133 height = s->cr[0x12] |
1134 ((s->cr[0x07] & 0x02) << 7) |
1135 ((s->cr[0x07] & 0x40) << 3);
1136 height = (height + 1);
1137 /* interlace support */
1138 if (s->cr[0x1a] & 0x01)
1139 height = height * 2;
1140 *pwidth = width;
1141 *pheight = height;
1142 }
1143
1144 /***************************************
1145 *
1146 * bank memory
1147 *
1148 ***************************************/
1149
1150 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1151 {
1152 unsigned offset;
1153 unsigned limit;
1154
1155 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1156 offset = s->vga.gr[0x09 + bank_index];
1157 else /* single bank */
1158 offset = s->vga.gr[0x09];
1159
1160 if ((s->vga.gr[0x0b] & 0x20) != 0)
1161 offset <<= 14;
1162 else
1163 offset <<= 12;
1164
1165 if (s->real_vram_size <= offset)
1166 limit = 0;
1167 else
1168 limit = s->real_vram_size - offset;
1169
1170 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1171 if (limit > 0x8000) {
1172 offset += 0x8000;
1173 limit -= 0x8000;
1174 } else {
1175 limit = 0;
1176 }
1177 }
1178
1179 if (limit > 0) {
1180 /* Thinking about changing bank base? First, drop the dirty bitmap information
1181 * on the current location, otherwise we lose this pointer forever */
1182 if (s->vga.lfb_vram_mapped) {
1183 target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1184 cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1185 }
1186 s->cirrus_bank_base[bank_index] = offset;
1187 s->cirrus_bank_limit[bank_index] = limit;
1188 } else {
1189 s->cirrus_bank_base[bank_index] = 0;
1190 s->cirrus_bank_limit[bank_index] = 0;
1191 }
1192 }
1193
1194 /***************************************
1195 *
1196 * I/O access between 0x3c4-0x3c5
1197 *
1198 ***************************************/
1199
1200 static int cirrus_vga_read_sr(CirrusVGAState * s)
1201 {
1202 switch (s->vga.sr_index) {
1203 case 0x00: // Standard VGA
1204 case 0x01: // Standard VGA
1205 case 0x02: // Standard VGA
1206 case 0x03: // Standard VGA
1207 case 0x04: // Standard VGA
1208 return s->vga.sr[s->vga.sr_index];
1209 case 0x06: // Unlock Cirrus extensions
1210 return s->vga.sr[s->vga.sr_index];
1211 case 0x10:
1212 case 0x30:
1213 case 0x50:
1214 case 0x70: // Graphics Cursor X
1215 case 0x90:
1216 case 0xb0:
1217 case 0xd0:
1218 case 0xf0: // Graphics Cursor X
1219 return s->vga.sr[0x10];
1220 case 0x11:
1221 case 0x31:
1222 case 0x51:
1223 case 0x71: // Graphics Cursor Y
1224 case 0x91:
1225 case 0xb1:
1226 case 0xd1:
1227 case 0xf1: // Graphics Cursor Y
1228 return s->vga.sr[0x11];
1229 case 0x05: // ???
1230 case 0x07: // Extended Sequencer Mode
1231 case 0x08: // EEPROM Control
1232 case 0x09: // Scratch Register 0
1233 case 0x0a: // Scratch Register 1
1234 case 0x0b: // VCLK 0
1235 case 0x0c: // VCLK 1
1236 case 0x0d: // VCLK 2
1237 case 0x0e: // VCLK 3
1238 case 0x0f: // DRAM Control
1239 case 0x12: // Graphics Cursor Attribute
1240 case 0x13: // Graphics Cursor Pattern Address
1241 case 0x14: // Scratch Register 2
1242 case 0x15: // Scratch Register 3
1243 case 0x16: // Performance Tuning Register
1244 case 0x17: // Configuration Readback and Extended Control
1245 case 0x18: // Signature Generator Control
1246 case 0x19: // Signal Generator Result
1247 case 0x1a: // Signal Generator Result
1248 case 0x1b: // VCLK 0 Denominator & Post
1249 case 0x1c: // VCLK 1 Denominator & Post
1250 case 0x1d: // VCLK 2 Denominator & Post
1251 case 0x1e: // VCLK 3 Denominator & Post
1252 case 0x1f: // BIOS Write Enable and MCLK select
1253 #ifdef DEBUG_CIRRUS
1254 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
1255 #endif
1256 return s->vga.sr[s->vga.sr_index];
1257 default:
1258 #ifdef DEBUG_CIRRUS
1259 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
1260 #endif
1261 return 0xff;
1262 break;
1263 }
1264 }
1265
1266 static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
1267 {
1268 switch (s->vga.sr_index) {
1269 case 0x00: // Standard VGA
1270 case 0x01: // Standard VGA
1271 case 0x02: // Standard VGA
1272 case 0x03: // Standard VGA
1273 case 0x04: // Standard VGA
1274 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1275 if (s->vga.sr_index == 1)
1276 s->vga.update_retrace_info(&s->vga);
1277 break;
1278 case 0x06: // Unlock Cirrus extensions
1279 val &= 0x17;
1280 if (val == 0x12) {
1281 s->vga.sr[s->vga.sr_index] = 0x12;
1282 } else {
1283 s->vga.sr[s->vga.sr_index] = 0x0f;
1284 }
1285 break;
1286 case 0x10:
1287 case 0x30:
1288 case 0x50:
1289 case 0x70: // Graphics Cursor X
1290 case 0x90:
1291 case 0xb0:
1292 case 0xd0:
1293 case 0xf0: // Graphics Cursor X
1294 s->vga.sr[0x10] = val;
1295 s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
1296 break;
1297 case 0x11:
1298 case 0x31:
1299 case 0x51:
1300 case 0x71: // Graphics Cursor Y
1301 case 0x91:
1302 case 0xb1:
1303 case 0xd1:
1304 case 0xf1: // Graphics Cursor Y
1305 s->vga.sr[0x11] = val;
1306 s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
1307 break;
1308 case 0x07: // Extended Sequencer Mode
1309 cirrus_update_memory_access(s);
1310 case 0x08: // EEPROM Control
1311 case 0x09: // Scratch Register 0
1312 case 0x0a: // Scratch Register 1
1313 case 0x0b: // VCLK 0
1314 case 0x0c: // VCLK 1
1315 case 0x0d: // VCLK 2
1316 case 0x0e: // VCLK 3
1317 case 0x0f: // DRAM Control
1318 case 0x12: // Graphics Cursor Attribute
1319 case 0x13: // Graphics Cursor Pattern Address
1320 case 0x14: // Scratch Register 2
1321 case 0x15: // Scratch Register 3
1322 case 0x16: // Performance Tuning Register
1323 case 0x18: // Signature Generator Control
1324 case 0x19: // Signature Generator Result
1325 case 0x1a: // Signature Generator Result
1326 case 0x1b: // VCLK 0 Denominator & Post
1327 case 0x1c: // VCLK 1 Denominator & Post
1328 case 0x1d: // VCLK 2 Denominator & Post
1329 case 0x1e: // VCLK 3 Denominator & Post
1330 case 0x1f: // BIOS Write Enable and MCLK select
1331 s->vga.sr[s->vga.sr_index] = val;
1332 #ifdef DEBUG_CIRRUS
1333 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1334 s->vga.sr_index, val);
1335 #endif
1336 break;
1337 case 0x17: // Configuration Readback and Extended Control
1338 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1339 | (val & 0xc7);
1340 cirrus_update_memory_access(s);
1341 break;
1342 default:
1343 #ifdef DEBUG_CIRRUS
1344 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1345 s->vga.sr_index, val);
1346 #endif
1347 break;
1348 }
1349 }
1350
1351 /***************************************
1352 *
1353 * I/O access at 0x3c6
1354 *
1355 ***************************************/
1356
1357 static int cirrus_read_hidden_dac(CirrusVGAState * s)
1358 {
1359 if (++s->cirrus_hidden_dac_lockindex == 5) {
1360 s->cirrus_hidden_dac_lockindex = 0;
1361 return s->cirrus_hidden_dac_data;
1362 }
1363 return 0xff;
1364 }
1365
1366 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1367 {
1368 if (s->cirrus_hidden_dac_lockindex == 4) {
1369 s->cirrus_hidden_dac_data = reg_value;
1370 #if defined(DEBUG_CIRRUS)
1371 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1372 #endif
1373 }
1374 s->cirrus_hidden_dac_lockindex = 0;
1375 }
1376
1377 /***************************************
1378 *
1379 * I/O access at 0x3c9
1380 *
1381 ***************************************/
1382
1383 static int cirrus_vga_read_palette(CirrusVGAState * s)
1384 {
1385 int val;
1386
1387 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1388 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1389 s->vga.dac_sub_index];
1390 } else {
1391 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1392 }
1393 if (++s->vga.dac_sub_index == 3) {
1394 s->vga.dac_sub_index = 0;
1395 s->vga.dac_read_index++;
1396 }
1397 return val;
1398 }
1399
1400 static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
1401 {
1402 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1403 if (++s->vga.dac_sub_index == 3) {
1404 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1405 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1406 s->vga.dac_cache, 3);
1407 } else {
1408 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1409 }
1410 /* XXX update cursor */
1411 s->vga.dac_sub_index = 0;
1412 s->vga.dac_write_index++;
1413 }
1414 }
1415
1416 /***************************************
1417 *
1418 * I/O access between 0x3ce-0x3cf
1419 *
1420 ***************************************/
1421
1422 static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
1423 {
1424 switch (reg_index) {
1425 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1426 return s->cirrus_shadow_gr0;
1427 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1428 return s->cirrus_shadow_gr1;
1429 case 0x02: // Standard VGA
1430 case 0x03: // Standard VGA
1431 case 0x04: // Standard VGA
1432 case 0x06: // Standard VGA
1433 case 0x07: // Standard VGA
1434 case 0x08: // Standard VGA
1435 return s->vga.gr[s->vga.gr_index];
1436 case 0x05: // Standard VGA, Cirrus extended mode
1437 default:
1438 break;
1439 }
1440
1441 if (reg_index < 0x3a) {
1442 return s->vga.gr[reg_index];
1443 } else {
1444 #ifdef DEBUG_CIRRUS
1445 printf("cirrus: inport gr_index %02x\n", reg_index);
1446 #endif
1447 return 0xff;
1448 }
1449 }
1450
1451 static void
1452 cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1453 {
1454 #if defined(DEBUG_BITBLT) && 0
1455 printf("gr%02x: %02x\n", reg_index, reg_value);
1456 #endif
1457 switch (reg_index) {
1458 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1459 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1460 s->cirrus_shadow_gr0 = reg_value;
1461 break;
1462 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1463 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1464 s->cirrus_shadow_gr1 = reg_value;
1465 break;
1466 case 0x02: // Standard VGA
1467 case 0x03: // Standard VGA
1468 case 0x04: // Standard VGA
1469 case 0x06: // Standard VGA
1470 case 0x07: // Standard VGA
1471 case 0x08: // Standard VGA
1472 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1473 break;
1474 case 0x05: // Standard VGA, Cirrus extended mode
1475 s->vga.gr[reg_index] = reg_value & 0x7f;
1476 cirrus_update_memory_access(s);
1477 break;
1478 case 0x09: // bank offset #0
1479 case 0x0A: // bank offset #1
1480 s->vga.gr[reg_index] = reg_value;
1481 cirrus_update_bank_ptr(s, 0);
1482 cirrus_update_bank_ptr(s, 1);
1483 cirrus_update_memory_access(s);
1484 break;
1485 case 0x0B:
1486 s->vga.gr[reg_index] = reg_value;
1487 cirrus_update_bank_ptr(s, 0);
1488 cirrus_update_bank_ptr(s, 1);
1489 cirrus_update_memory_access(s);
1490 break;
1491 case 0x10: // BGCOLOR 0x0000ff00
1492 case 0x11: // FGCOLOR 0x0000ff00
1493 case 0x12: // BGCOLOR 0x00ff0000
1494 case 0x13: // FGCOLOR 0x00ff0000
1495 case 0x14: // BGCOLOR 0xff000000
1496 case 0x15: // FGCOLOR 0xff000000
1497 case 0x20: // BLT WIDTH 0x0000ff
1498 case 0x22: // BLT HEIGHT 0x0000ff
1499 case 0x24: // BLT DEST PITCH 0x0000ff
1500 case 0x26: // BLT SRC PITCH 0x0000ff
1501 case 0x28: // BLT DEST ADDR 0x0000ff
1502 case 0x29: // BLT DEST ADDR 0x00ff00
1503 case 0x2c: // BLT SRC ADDR 0x0000ff
1504 case 0x2d: // BLT SRC ADDR 0x00ff00
1505 case 0x2f: // BLT WRITEMASK
1506 case 0x30: // BLT MODE
1507 case 0x32: // RASTER OP
1508 case 0x33: // BLT MODEEXT
1509 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1510 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1511 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1512 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1513 s->vga.gr[reg_index] = reg_value;
1514 break;
1515 case 0x21: // BLT WIDTH 0x001f00
1516 case 0x23: // BLT HEIGHT 0x001f00
1517 case 0x25: // BLT DEST PITCH 0x001f00
1518 case 0x27: // BLT SRC PITCH 0x001f00
1519 s->vga.gr[reg_index] = reg_value & 0x1f;
1520 break;
1521 case 0x2a: // BLT DEST ADDR 0x3f0000
1522 s->vga.gr[reg_index] = reg_value & 0x3f;
1523 /* if auto start mode, starts bit blt now */
1524 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1525 cirrus_bitblt_start(s);
1526 }
1527 break;
1528 case 0x2e: // BLT SRC ADDR 0x3f0000
1529 s->vga.gr[reg_index] = reg_value & 0x3f;
1530 break;
1531 case 0x31: // BLT STATUS/START
1532 cirrus_write_bitblt(s, reg_value);
1533 break;
1534 default:
1535 #ifdef DEBUG_CIRRUS
1536 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1537 reg_value);
1538 #endif
1539 break;
1540 }
1541 }
1542
1543 /***************************************
1544 *
1545 * I/O access between 0x3d4-0x3d5
1546 *
1547 ***************************************/
1548
1549 static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
1550 {
1551 switch (reg_index) {
1552 case 0x00: // Standard VGA
1553 case 0x01: // Standard VGA
1554 case 0x02: // Standard VGA
1555 case 0x03: // Standard VGA
1556 case 0x04: // Standard VGA
1557 case 0x05: // Standard VGA
1558 case 0x06: // Standard VGA
1559 case 0x07: // Standard VGA
1560 case 0x08: // Standard VGA
1561 case 0x09: // Standard VGA
1562 case 0x0a: // Standard VGA
1563 case 0x0b: // Standard VGA
1564 case 0x0c: // Standard VGA
1565 case 0x0d: // Standard VGA
1566 case 0x0e: // Standard VGA
1567 case 0x0f: // Standard VGA
1568 case 0x10: // Standard VGA
1569 case 0x11: // Standard VGA
1570 case 0x12: // Standard VGA
1571 case 0x13: // Standard VGA
1572 case 0x14: // Standard VGA
1573 case 0x15: // Standard VGA
1574 case 0x16: // Standard VGA
1575 case 0x17: // Standard VGA
1576 case 0x18: // Standard VGA
1577 return s->vga.cr[s->vga.cr_index];
1578 case 0x24: // Attribute Controller Toggle Readback (R)
1579 return (s->vga.ar_flip_flop << 7);
1580 case 0x19: // Interlace End
1581 case 0x1a: // Miscellaneous Control
1582 case 0x1b: // Extended Display Control
1583 case 0x1c: // Sync Adjust and Genlock
1584 case 0x1d: // Overlay Extended Control
1585 case 0x22: // Graphics Data Latches Readback (R)
1586 case 0x25: // Part Status
1587 case 0x27: // Part ID (R)
1588 return s->vga.cr[s->vga.cr_index];
1589 case 0x26: // Attribute Controller Index Readback (R)
1590 return s->vga.ar_index & 0x3f;
1591 break;
1592 default:
1593 #ifdef DEBUG_CIRRUS
1594 printf("cirrus: inport cr_index %02x\n", reg_index);
1595 #endif
1596 return 0xff;
1597 }
1598 }
1599
1600 static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
1601 {
1602 switch (s->vga.cr_index) {
1603 case 0x00: // Standard VGA
1604 case 0x01: // Standard VGA
1605 case 0x02: // Standard VGA
1606 case 0x03: // Standard VGA
1607 case 0x04: // Standard VGA
1608 case 0x05: // Standard VGA
1609 case 0x06: // Standard VGA
1610 case 0x07: // Standard VGA
1611 case 0x08: // Standard VGA
1612 case 0x09: // Standard VGA
1613 case 0x0a: // Standard VGA
1614 case 0x0b: // Standard VGA
1615 case 0x0c: // Standard VGA
1616 case 0x0d: // Standard VGA
1617 case 0x0e: // Standard VGA
1618 case 0x0f: // Standard VGA
1619 case 0x10: // Standard VGA
1620 case 0x11: // Standard VGA
1621 case 0x12: // Standard VGA
1622 case 0x13: // Standard VGA
1623 case 0x14: // Standard VGA
1624 case 0x15: // Standard VGA
1625 case 0x16: // Standard VGA
1626 case 0x17: // Standard VGA
1627 case 0x18: // Standard VGA
1628 /* handle CR0-7 protection */
1629 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1630 /* can always write bit 4 of CR7 */
1631 if (s->vga.cr_index == 7)
1632 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1633 return;
1634 }
1635 s->vga.cr[s->vga.cr_index] = reg_value;
1636 switch(s->vga.cr_index) {
1637 case 0x00:
1638 case 0x04:
1639 case 0x05:
1640 case 0x06:
1641 case 0x07:
1642 case 0x11:
1643 case 0x17:
1644 s->vga.update_retrace_info(&s->vga);
1645 break;
1646 }
1647 break;
1648 case 0x19: // Interlace End
1649 case 0x1a: // Miscellaneous Control
1650 case 0x1b: // Extended Display Control
1651 case 0x1c: // Sync Adjust and Genlock
1652 case 0x1d: // Overlay Extended Control
1653 s->vga.cr[s->vga.cr_index] = reg_value;
1654 #ifdef DEBUG_CIRRUS
1655 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1656 s->vga.cr_index, reg_value);
1657 #endif
1658 break;
1659 case 0x22: // Graphics Data Latches Readback (R)
1660 case 0x24: // Attribute Controller Toggle Readback (R)
1661 case 0x26: // Attribute Controller Index Readback (R)
1662 case 0x27: // Part ID (R)
1663 break;
1664 case 0x25: // Part Status
1665 default:
1666 #ifdef DEBUG_CIRRUS
1667 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1668 s->vga.cr_index, reg_value);
1669 #endif
1670 break;
1671 }
1672 }
1673
1674 /***************************************
1675 *
1676 * memory-mapped I/O (bitblt)
1677 *
1678 ***************************************/
1679
1680 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1681 {
1682 int value = 0xff;
1683
1684 switch (address) {
1685 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1686 value = cirrus_vga_read_gr(s, 0x00);
1687 break;
1688 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1689 value = cirrus_vga_read_gr(s, 0x10);
1690 break;
1691 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1692 value = cirrus_vga_read_gr(s, 0x12);
1693 break;
1694 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1695 value = cirrus_vga_read_gr(s, 0x14);
1696 break;
1697 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1698 value = cirrus_vga_read_gr(s, 0x01);
1699 break;
1700 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1701 value = cirrus_vga_read_gr(s, 0x11);
1702 break;
1703 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1704 value = cirrus_vga_read_gr(s, 0x13);
1705 break;
1706 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1707 value = cirrus_vga_read_gr(s, 0x15);
1708 break;
1709 case (CIRRUS_MMIO_BLTWIDTH + 0):
1710 value = cirrus_vga_read_gr(s, 0x20);
1711 break;
1712 case (CIRRUS_MMIO_BLTWIDTH + 1):
1713 value = cirrus_vga_read_gr(s, 0x21);
1714 break;
1715 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1716 value = cirrus_vga_read_gr(s, 0x22);
1717 break;
1718 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1719 value = cirrus_vga_read_gr(s, 0x23);
1720 break;
1721 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1722 value = cirrus_vga_read_gr(s, 0x24);
1723 break;
1724 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1725 value = cirrus_vga_read_gr(s, 0x25);
1726 break;
1727 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1728 value = cirrus_vga_read_gr(s, 0x26);
1729 break;
1730 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1731 value = cirrus_vga_read_gr(s, 0x27);
1732 break;
1733 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1734 value = cirrus_vga_read_gr(s, 0x28);
1735 break;
1736 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1737 value = cirrus_vga_read_gr(s, 0x29);
1738 break;
1739 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1740 value = cirrus_vga_read_gr(s, 0x2a);
1741 break;
1742 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1743 value = cirrus_vga_read_gr(s, 0x2c);
1744 break;
1745 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1746 value = cirrus_vga_read_gr(s, 0x2d);
1747 break;
1748 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1749 value = cirrus_vga_read_gr(s, 0x2e);
1750 break;
1751 case CIRRUS_MMIO_BLTWRITEMASK:
1752 value = cirrus_vga_read_gr(s, 0x2f);
1753 break;
1754 case CIRRUS_MMIO_BLTMODE:
1755 value = cirrus_vga_read_gr(s, 0x30);
1756 break;
1757 case CIRRUS_MMIO_BLTROP:
1758 value = cirrus_vga_read_gr(s, 0x32);
1759 break;
1760 case CIRRUS_MMIO_BLTMODEEXT:
1761 value = cirrus_vga_read_gr(s, 0x33);
1762 break;
1763 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1764 value = cirrus_vga_read_gr(s, 0x34);
1765 break;
1766 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1767 value = cirrus_vga_read_gr(s, 0x35);
1768 break;
1769 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1770 value = cirrus_vga_read_gr(s, 0x38);
1771 break;
1772 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1773 value = cirrus_vga_read_gr(s, 0x39);
1774 break;
1775 case CIRRUS_MMIO_BLTSTATUS:
1776 value = cirrus_vga_read_gr(s, 0x31);
1777 break;
1778 default:
1779 #ifdef DEBUG_CIRRUS
1780 printf("cirrus: mmio read - address 0x%04x\n", address);
1781 #endif
1782 break;
1783 }
1784
1785 return (uint8_t) value;
1786 }
1787
1788 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1789 uint8_t value)
1790 {
1791 switch (address) {
1792 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1793 cirrus_vga_write_gr(s, 0x00, value);
1794 break;
1795 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1796 cirrus_vga_write_gr(s, 0x10, value);
1797 break;
1798 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1799 cirrus_vga_write_gr(s, 0x12, value);
1800 break;
1801 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1802 cirrus_vga_write_gr(s, 0x14, value);
1803 break;
1804 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1805 cirrus_vga_write_gr(s, 0x01, value);
1806 break;
1807 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1808 cirrus_vga_write_gr(s, 0x11, value);
1809 break;
1810 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1811 cirrus_vga_write_gr(s, 0x13, value);
1812 break;
1813 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1814 cirrus_vga_write_gr(s, 0x15, value);
1815 break;
1816 case (CIRRUS_MMIO_BLTWIDTH + 0):
1817 cirrus_vga_write_gr(s, 0x20, value);
1818 break;
1819 case (CIRRUS_MMIO_BLTWIDTH + 1):
1820 cirrus_vga_write_gr(s, 0x21, value);
1821 break;
1822 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1823 cirrus_vga_write_gr(s, 0x22, value);
1824 break;
1825 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1826 cirrus_vga_write_gr(s, 0x23, value);
1827 break;
1828 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1829 cirrus_vga_write_gr(s, 0x24, value);
1830 break;
1831 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1832 cirrus_vga_write_gr(s, 0x25, value);
1833 break;
1834 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1835 cirrus_vga_write_gr(s, 0x26, value);
1836 break;
1837 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1838 cirrus_vga_write_gr(s, 0x27, value);
1839 break;
1840 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1841 cirrus_vga_write_gr(s, 0x28, value);
1842 break;
1843 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1844 cirrus_vga_write_gr(s, 0x29, value);
1845 break;
1846 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1847 cirrus_vga_write_gr(s, 0x2a, value);
1848 break;
1849 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1850 /* ignored */
1851 break;
1852 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1853 cirrus_vga_write_gr(s, 0x2c, value);
1854 break;
1855 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1856 cirrus_vga_write_gr(s, 0x2d, value);
1857 break;
1858 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1859 cirrus_vga_write_gr(s, 0x2e, value);
1860 break;
1861 case CIRRUS_MMIO_BLTWRITEMASK:
1862 cirrus_vga_write_gr(s, 0x2f, value);
1863 break;
1864 case CIRRUS_MMIO_BLTMODE:
1865 cirrus_vga_write_gr(s, 0x30, value);
1866 break;
1867 case CIRRUS_MMIO_BLTROP:
1868 cirrus_vga_write_gr(s, 0x32, value);
1869 break;
1870 case CIRRUS_MMIO_BLTMODEEXT:
1871 cirrus_vga_write_gr(s, 0x33, value);
1872 break;
1873 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1874 cirrus_vga_write_gr(s, 0x34, value);
1875 break;
1876 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1877 cirrus_vga_write_gr(s, 0x35, value);
1878 break;
1879 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1880 cirrus_vga_write_gr(s, 0x38, value);
1881 break;
1882 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1883 cirrus_vga_write_gr(s, 0x39, value);
1884 break;
1885 case CIRRUS_MMIO_BLTSTATUS:
1886 cirrus_vga_write_gr(s, 0x31, value);
1887 break;
1888 default:
1889 #ifdef DEBUG_CIRRUS
1890 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1891 address, value);
1892 #endif
1893 break;
1894 }
1895 }
1896
1897 /***************************************
1898 *
1899 * write mode 4/5
1900 *
1901 * assume TARGET_PAGE_SIZE >= 16
1902 *
1903 ***************************************/
1904
1905 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1906 unsigned mode,
1907 unsigned offset,
1908 uint32_t mem_value)
1909 {
1910 int x;
1911 unsigned val = mem_value;
1912 uint8_t *dst;
1913
1914 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1915 for (x = 0; x < 8; x++) {
1916 if (val & 0x80) {
1917 *dst = s->cirrus_shadow_gr1;
1918 } else if (mode == 5) {
1919 *dst = s->cirrus_shadow_gr0;
1920 }
1921 val <<= 1;
1922 dst++;
1923 }
1924 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1925 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 7);
1926 }
1927
1928 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1929 unsigned mode,
1930 unsigned offset,
1931 uint32_t mem_value)
1932 {
1933 int x;
1934 unsigned val = mem_value;
1935 uint8_t *dst;
1936
1937 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1938 for (x = 0; x < 8; x++) {
1939 if (val & 0x80) {
1940 *dst = s->cirrus_shadow_gr1;
1941 *(dst + 1) = s->vga.gr[0x11];
1942 } else if (mode == 5) {
1943 *dst = s->cirrus_shadow_gr0;
1944 *(dst + 1) = s->vga.gr[0x10];
1945 }
1946 val <<= 1;
1947 dst += 2;
1948 }
1949 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1950 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 15);
1951 }
1952
1953 /***************************************
1954 *
1955 * memory access between 0xa0000-0xbffff
1956 *
1957 ***************************************/
1958
1959 static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1960 {
1961 CirrusVGAState *s = opaque;
1962 unsigned bank_index;
1963 unsigned bank_offset;
1964 uint32_t val;
1965
1966 if ((s->vga.sr[0x07] & 0x01) == 0) {
1967 return vga_mem_readb(s, addr);
1968 }
1969
1970 addr &= 0x1ffff;
1971
1972 if (addr < 0x10000) {
1973 /* XXX handle bitblt */
1974 /* video memory */
1975 bank_index = addr >> 15;
1976 bank_offset = addr & 0x7fff;
1977 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1978 bank_offset += s->cirrus_bank_base[bank_index];
1979 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
1980 bank_offset <<= 4;
1981 } else if (s->vga.gr[0x0B] & 0x02) {
1982 bank_offset <<= 3;
1983 }
1984 bank_offset &= s->cirrus_addr_mask;
1985 val = *(s->vga.vram_ptr + bank_offset);
1986 } else
1987 val = 0xff;
1988 } else if (addr >= 0x18000 && addr < 0x18100) {
1989 /* memory-mapped I/O */
1990 val = 0xff;
1991 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
1992 val = cirrus_mmio_blt_read(s, addr & 0xff);
1993 }
1994 } else {
1995 val = 0xff;
1996 #ifdef DEBUG_CIRRUS
1997 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
1998 #endif
1999 }
2000 return val;
2001 }
2002
2003 static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2004 {
2005 uint32_t v;
2006
2007 v = cirrus_vga_mem_readb(opaque, addr);
2008 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2009 return v;
2010 }
2011
2012 static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2013 {
2014 uint32_t v;
2015
2016 v = cirrus_vga_mem_readb(opaque, addr);
2017 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2018 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2019 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2020 return v;
2021 }
2022
2023 static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2024 uint32_t mem_value)
2025 {
2026 CirrusVGAState *s = opaque;
2027 unsigned bank_index;
2028 unsigned bank_offset;
2029 unsigned mode;
2030
2031 if ((s->vga.sr[0x07] & 0x01) == 0) {
2032 vga_mem_writeb(s, addr, mem_value);
2033 return;
2034 }
2035
2036 addr &= 0x1ffff;
2037
2038 if (addr < 0x10000) {
2039 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2040 /* bitblt */
2041 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2042 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2043 cirrus_bitblt_cputovideo_next(s);
2044 }
2045 } else {
2046 /* video memory */
2047 bank_index = addr >> 15;
2048 bank_offset = addr & 0x7fff;
2049 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2050 bank_offset += s->cirrus_bank_base[bank_index];
2051 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2052 bank_offset <<= 4;
2053 } else if (s->vga.gr[0x0B] & 0x02) {
2054 bank_offset <<= 3;
2055 }
2056 bank_offset &= s->cirrus_addr_mask;
2057 mode = s->vga.gr[0x05] & 0x7;
2058 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2059 *(s->vga.vram_ptr + bank_offset) = mem_value;
2060 cpu_physical_memory_set_dirty(s->vga.vram_offset +
2061 bank_offset);
2062 } else {
2063 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2064 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2065 bank_offset,
2066 mem_value);
2067 } else {
2068 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2069 bank_offset,
2070 mem_value);
2071 }
2072 }
2073 }
2074 }
2075 } else if (addr >= 0x18000 && addr < 0x18100) {
2076 /* memory-mapped I/O */
2077 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2078 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2079 }
2080 } else {
2081 #ifdef DEBUG_CIRRUS
2082 printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr,
2083 mem_value);
2084 #endif
2085 }
2086 }
2087
2088 static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2089 {
2090 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2091 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2092 }
2093
2094 static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2095 {
2096 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2097 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2098 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2099 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2100 }
2101
2102 static CPUReadMemoryFunc * const cirrus_vga_mem_read[3] = {
2103 cirrus_vga_mem_readb,
2104 cirrus_vga_mem_readw,
2105 cirrus_vga_mem_readl,
2106 };
2107
2108 static CPUWriteMemoryFunc * const cirrus_vga_mem_write[3] = {
2109 cirrus_vga_mem_writeb,
2110 cirrus_vga_mem_writew,
2111 cirrus_vga_mem_writel,
2112 };
2113
2114 /***************************************
2115 *
2116 * hardware cursor
2117 *
2118 ***************************************/
2119
2120 static inline void invalidate_cursor1(CirrusVGAState *s)
2121 {
2122 if (s->last_hw_cursor_size) {
2123 vga_invalidate_scanlines(&s->vga,
2124 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2125 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2126 }
2127 }
2128
2129 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2130 {
2131 const uint8_t *src;
2132 uint32_t content;
2133 int y, y_min, y_max;
2134
2135 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2136 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2137 src += (s->vga.sr[0x13] & 0x3c) * 256;
2138 y_min = 64;
2139 y_max = -1;
2140 for(y = 0; y < 64; y++) {
2141 content = ((uint32_t *)src)[0] |
2142 ((uint32_t *)src)[1] |
2143 ((uint32_t *)src)[2] |
2144 ((uint32_t *)src)[3];
2145 if (content) {
2146 if (y < y_min)
2147 y_min = y;
2148 if (y > y_max)
2149 y_max = y;
2150 }
2151 src += 16;
2152 }
2153 } else {
2154 src += (s->vga.sr[0x13] & 0x3f) * 256;
2155 y_min = 32;
2156 y_max = -1;
2157 for(y = 0; y < 32; y++) {
2158 content = ((uint32_t *)src)[0] |
2159 ((uint32_t *)(src + 128))[0];
2160 if (content) {
2161 if (y < y_min)
2162 y_min = y;
2163 if (y > y_max)
2164 y_max = y;
2165 }
2166 src += 4;
2167 }
2168 }
2169 if (y_min > y_max) {
2170 s->last_hw_cursor_y_start = 0;
2171 s->last_hw_cursor_y_end = 0;
2172 } else {
2173 s->last_hw_cursor_y_start = y_min;
2174 s->last_hw_cursor_y_end = y_max + 1;
2175 }
2176 }
2177
2178 /* NOTE: we do not currently handle the cursor bitmap change, so we
2179 update the cursor only if it moves. */
2180 static void cirrus_cursor_invalidate(VGACommonState *s1)
2181 {
2182 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2183 int size;
2184
2185 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2186 size = 0;
2187 } else {
2188 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
2189 size = 64;
2190 else
2191 size = 32;
2192 }
2193 /* invalidate last cursor and new cursor if any change */
2194 if (s->last_hw_cursor_size != size ||
2195 s->last_hw_cursor_x != s->hw_cursor_x ||
2196 s->last_hw_cursor_y != s->hw_cursor_y) {
2197
2198 invalidate_cursor1(s);
2199
2200 s->last_hw_cursor_size = size;
2201 s->last_hw_cursor_x = s->hw_cursor_x;
2202 s->last_hw_cursor_y = s->hw_cursor_y;
2203 /* compute the real cursor min and max y */
2204 cirrus_cursor_compute_yrange(s);
2205 invalidate_cursor1(s);
2206 }
2207 }
2208
2209 static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
2210 {
2211 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2212 int w, h, bpp, x1, x2, poffset;
2213 unsigned int color0, color1;
2214 const uint8_t *palette, *src;
2215 uint32_t content;
2216
2217 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
2218 return;
2219 /* fast test to see if the cursor intersects with the scan line */
2220 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2221 h = 64;
2222 } else {
2223 h = 32;
2224 }
2225 if (scr_y < s->hw_cursor_y ||
2226 scr_y >= (s->hw_cursor_y + h))
2227 return;
2228
2229 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2230 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2231 src += (s->vga.sr[0x13] & 0x3c) * 256;
2232 src += (scr_y - s->hw_cursor_y) * 16;
2233 poffset = 8;
2234 content = ((uint32_t *)src)[0] |
2235 ((uint32_t *)src)[1] |
2236 ((uint32_t *)src)[2] |
2237 ((uint32_t *)src)[3];
2238 } else {
2239 src += (s->vga.sr[0x13] & 0x3f) * 256;
2240 src += (scr_y - s->hw_cursor_y) * 4;
2241 poffset = 128;
2242 content = ((uint32_t *)src)[0] |
2243 ((uint32_t *)(src + 128))[0];
2244 }
2245 /* if nothing to draw, no need to continue */
2246 if (!content)
2247 return;
2248 w = h;
2249
2250 x1 = s->hw_cursor_x;
2251 if (x1 >= s->vga.last_scr_width)
2252 return;
2253 x2 = s->hw_cursor_x + w;
2254 if (x2 > s->vga.last_scr_width)
2255 x2 = s->vga.last_scr_width;
2256 w = x2 - x1;
2257 palette = s->cirrus_hidden_palette;
2258 color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2259 c6_to_8(palette[0x0 * 3 + 1]),
2260 c6_to_8(palette[0x0 * 3 + 2]));
2261 color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2262 c6_to_8(palette[0xf * 3 + 1]),
2263 c6_to_8(palette[0xf * 3 + 2]));
2264 bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
2265 d1 += x1 * bpp;
2266 switch(ds_get_bits_per_pixel(s->vga.ds)) {
2267 default:
2268 break;
2269 case 8:
2270 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2271 break;
2272 case 15:
2273 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2274 break;
2275 case 16:
2276 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2277 break;
2278 case 32:
2279 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2280 break;
2281 }
2282 }
2283
2284 /***************************************
2285 *
2286 * LFB memory access
2287 *
2288 ***************************************/
2289
2290 static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2291 {
2292 CirrusVGAState *s = opaque;
2293 uint32_t ret;
2294
2295 addr &= s->cirrus_addr_mask;
2296
2297 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2298 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2299 /* memory-mapped I/O */
2300 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2301 } else if (0) {
2302 /* XXX handle bitblt */
2303 ret = 0xff;
2304 } else {
2305 /* video memory */
2306 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2307 addr <<= 4;
2308 } else if (s->vga.gr[0x0B] & 0x02) {
2309 addr <<= 3;
2310 }
2311 addr &= s->cirrus_addr_mask;
2312 ret = *(s->vga.vram_ptr + addr);
2313 }
2314
2315 return ret;
2316 }
2317
2318 static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2319 {
2320 uint32_t v;
2321
2322 v = cirrus_linear_readb(opaque, addr);
2323 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2324 return v;
2325 }
2326
2327 static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2328 {
2329 uint32_t v;
2330
2331 v = cirrus_linear_readb(opaque, addr);
2332 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2333 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2334 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2335 return v;
2336 }
2337
2338 static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2339 uint32_t val)
2340 {
2341 CirrusVGAState *s = opaque;
2342 unsigned mode;
2343
2344 addr &= s->cirrus_addr_mask;
2345
2346 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2347 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2348 /* memory-mapped I/O */
2349 cirrus_mmio_blt_write(s, addr & 0xff, val);
2350 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2351 /* bitblt */
2352 *s->cirrus_srcptr++ = (uint8_t) val;
2353 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2354 cirrus_bitblt_cputovideo_next(s);
2355 }
2356 } else {
2357 /* video memory */
2358 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2359 addr <<= 4;
2360 } else if (s->vga.gr[0x0B] & 0x02) {
2361 addr <<= 3;
2362 }
2363 addr &= s->cirrus_addr_mask;
2364
2365 mode = s->vga.gr[0x05] & 0x7;
2366 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2367 *(s->vga.vram_ptr + addr) = (uint8_t) val;
2368 cpu_physical_memory_set_dirty(s->vga.vram_offset + addr);
2369 } else {
2370 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2371 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2372 } else {
2373 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2374 }
2375 }
2376 }
2377 }
2378
2379 static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2380 uint32_t val)
2381 {
2382 cirrus_linear_writeb(opaque, addr, val & 0xff);
2383 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2384 }
2385
2386 static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2387 uint32_t val)
2388 {
2389 cirrus_linear_writeb(opaque, addr, val & 0xff);
2390 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2391 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2392 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2393 }
2394
2395
2396 static CPUReadMemoryFunc * const cirrus_linear_read[3] = {
2397 cirrus_linear_readb,
2398 cirrus_linear_readw,
2399 cirrus_linear_readl,
2400 };
2401
2402 static CPUWriteMemoryFunc * const cirrus_linear_write[3] = {
2403 cirrus_linear_writeb,
2404 cirrus_linear_writew,
2405 cirrus_linear_writel,
2406 };
2407
2408 /***************************************
2409 *
2410 * system to screen memory access
2411 *
2412 ***************************************/
2413
2414
2415 static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2416 {
2417 uint32_t ret;
2418
2419 /* XXX handle bitblt */
2420 ret = 0xff;
2421 return ret;
2422 }
2423
2424 static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2425 {
2426 uint32_t v;
2427
2428 v = cirrus_linear_bitblt_readb(opaque, addr);
2429 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2430 return v;
2431 }
2432
2433 static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2434 {
2435 uint32_t v;
2436
2437 v = cirrus_linear_bitblt_readb(opaque, addr);
2438 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2439 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2440 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2441 return v;
2442 }
2443
2444 static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2445 uint32_t val)
2446 {
2447 CirrusVGAState *s = opaque;
2448
2449 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2450 /* bitblt */
2451 *s->cirrus_srcptr++ = (uint8_t) val;
2452 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2453 cirrus_bitblt_cputovideo_next(s);
2454 }
2455 }
2456 }
2457
2458 static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2459 uint32_t val)
2460 {
2461 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2462 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2463 }
2464
2465 static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2466 uint32_t val)
2467 {
2468 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2469 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2470 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2471 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2472 }
2473
2474
2475 static CPUReadMemoryFunc * const cirrus_linear_bitblt_read[3] = {
2476 cirrus_linear_bitblt_readb,
2477 cirrus_linear_bitblt_readw,
2478 cirrus_linear_bitblt_readl,
2479 };
2480
2481 static CPUWriteMemoryFunc * const cirrus_linear_bitblt_write[3] = {
2482 cirrus_linear_bitblt_writeb,
2483 cirrus_linear_bitblt_writew,
2484 cirrus_linear_bitblt_writel,
2485 };
2486
2487 static void map_linear_vram(CirrusVGAState *s)
2488 {
2489 if (!s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) {
2490 s->vga.map_addr = s->vga.lfb_addr;
2491 s->vga.map_end = s->vga.lfb_end;
2492 cpu_register_physical_memory(s->vga.map_addr, s->vga.map_end - s->vga.map_addr, s->vga.vram_offset);
2493 }
2494
2495 if (!s->vga.map_addr)
2496 return;
2497
2498 s->vga.lfb_vram_mapped = 0;
2499
2500 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
2501 && !((s->vga.sr[0x07] & 0x01) == 0)
2502 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2503 && !(s->vga.gr[0x0B] & 0x02)) {
2504
2505 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2506 (s->vga.vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2507 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2508 (s->vga.vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2509
2510 s->vga.lfb_vram_mapped = 1;
2511 }
2512 else {
2513 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2514 s->vga.vga_io_memory);
2515 }
2516
2517 vga_dirty_log_start(&s->vga);
2518 }
2519
2520 static void unmap_linear_vram(CirrusVGAState *s)
2521 {
2522 if (s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) {
2523 s->vga.map_addr = s->vga.map_end = 0;
2524 cpu_register_physical_memory(s->vga.lfb_addr, s->vga.vram_size,
2525 s->cirrus_linear_io_addr);
2526 }
2527 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2528 s->vga.vga_io_memory);
2529 }
2530
2531 /* Compute the memory access functions */
2532 static void cirrus_update_memory_access(CirrusVGAState *s)
2533 {
2534 unsigned mode;
2535
2536 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
2537 goto generic_io;
2538 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2539 goto generic_io;
2540 } else {
2541 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2542 goto generic_io;
2543 } else if (s->vga.gr[0x0B] & 0x02) {
2544 goto generic_io;
2545 }
2546
2547 mode = s->vga.gr[0x05] & 0x7;
2548 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2549 map_linear_vram(s);
2550 } else {
2551 generic_io:
2552 unmap_linear_vram(s);
2553 }
2554 }
2555 }
2556
2557
2558 /* I/O ports */
2559
2560 static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr)
2561 {
2562 CirrusVGAState *c = opaque;
2563 VGACommonState *s = &c->vga;
2564 int val, index;
2565
2566 if (vga_ioport_invalid(s, addr)) {
2567 val = 0xff;
2568 } else {
2569 switch (addr) {
2570 case 0x3c0:
2571 if (s->ar_flip_flop == 0) {
2572 val = s->ar_index;
2573 } else {
2574 val = 0;
2575 }
2576 break;
2577 case 0x3c1:
2578 index = s->ar_index & 0x1f;
2579 if (index < 21)
2580 val = s->ar[index];
2581 else
2582 val = 0;
2583 break;
2584 case 0x3c2:
2585 val = s->st00;
2586 break;
2587 case 0x3c4:
2588 val = s->sr_index;
2589 break;
2590 case 0x3c5:
2591 val = cirrus_vga_read_sr(c);
2592 break;
2593 #ifdef DEBUG_VGA_REG
2594 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2595 #endif
2596 break;
2597 case 0x3c6:
2598 val = cirrus_read_hidden_dac(c);
2599 break;
2600 case 0x3c7:
2601 val = s->dac_state;
2602 break;
2603 case 0x3c8:
2604 val = s->dac_write_index;
2605 c->cirrus_hidden_dac_lockindex = 0;
2606 break;
2607 case 0x3c9:
2608 val = cirrus_vga_read_palette(c);
2609 break;
2610 case 0x3ca:
2611 val = s->fcr;
2612 break;
2613 case 0x3cc:
2614 val = s->msr;
2615 break;
2616 case 0x3ce:
2617 val = s->gr_index;
2618 break;
2619 case 0x3cf:
2620 val = cirrus_vga_read_gr(c, s->gr_index);
2621 #ifdef DEBUG_VGA_REG
2622 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2623 #endif
2624 break;
2625 case 0x3b4:
2626 case 0x3d4:
2627 val = s->cr_index;
2628 break;
2629 case 0x3b5:
2630 case 0x3d5:
2631 val = cirrus_vga_read_cr(c, s->cr_index);
2632 #ifdef DEBUG_VGA_REG
2633 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2634 #endif
2635 break;
2636 case 0x3ba:
2637 case 0x3da:
2638 /* just toggle to fool polling */
2639 val = s->st01 = s->retrace(s);
2640 s->ar_flip_flop = 0;
2641 break;
2642 default:
2643 val = 0x00;
2644 break;
2645 }
2646 }
2647 #if defined(DEBUG_VGA)
2648 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2649 #endif
2650 return val;
2651 }
2652
2653 static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2654 {
2655 CirrusVGAState *c = opaque;
2656 VGACommonState *s = &c->vga;
2657 int index;
2658
2659 /* check port range access depending on color/monochrome mode */
2660 if (vga_ioport_invalid(s, addr)) {
2661 return;
2662 }
2663 #ifdef DEBUG_VGA
2664 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2665 #endif
2666
2667 switch (addr) {
2668 case 0x3c0:
2669 if (s->ar_flip_flop == 0) {
2670 val &= 0x3f;
2671 s->ar_index = val;
2672 } else {
2673 index = s->ar_index & 0x1f;
2674 switch (index) {
2675 case 0x00 ... 0x0f:
2676 s->ar[index] = val & 0x3f;
2677 break;
2678 case 0x10:
2679 s->ar[index] = val & ~0x10;
2680 break;
2681 case 0x11:
2682 s->ar[index] = val;
2683 break;
2684 case 0x12:
2685 s->ar[index] = val & ~0xc0;
2686 break;
2687 case 0x13:
2688 s->ar[index] = val & ~0xf0;
2689 break;
2690 case 0x14:
2691 s->ar[index] = val & ~0xf0;
2692 break;
2693 default:
2694 break;
2695 }
2696 }
2697 s->ar_flip_flop ^= 1;
2698 break;
2699 case 0x3c2:
2700 s->msr = val & ~0x10;
2701 s->update_retrace_info(s);
2702 break;
2703 case 0x3c4:
2704 s->sr_index = val;
2705 break;
2706 case 0x3c5:
2707 #ifdef DEBUG_VGA_REG
2708 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2709 #endif
2710 cirrus_vga_write_sr(c, val);
2711 break;
2712 break;
2713 case 0x3c6:
2714 cirrus_write_hidden_dac(c, val);
2715 break;
2716 case 0x3c7:
2717 s->dac_read_index = val;
2718 s->dac_sub_index = 0;
2719 s->dac_state = 3;
2720 break;
2721 case 0x3c8:
2722 s->dac_write_index = val;
2723 s->dac_sub_index = 0;
2724 s->dac_state = 0;
2725 break;
2726 case 0x3c9:
2727 cirrus_vga_write_palette(c, val);
2728 break;
2729 case 0x3ce:
2730 s->gr_index = val;
2731 break;
2732 case 0x3cf:
2733 #ifdef DEBUG_VGA_REG
2734 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2735 #endif
2736 cirrus_vga_write_gr(c, s->gr_index, val);
2737 break;
2738 case 0x3b4:
2739 case 0x3d4:
2740 s->cr_index = val;
2741 break;
2742 case 0x3b5:
2743 case 0x3d5:
2744 #ifdef DEBUG_VGA_REG
2745 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2746 #endif
2747 cirrus_vga_write_cr(c, val);
2748 break;
2749 case 0x3ba:
2750 case 0x3da:
2751 s->fcr = val & 0x10;
2752 break;
2753 }
2754 }
2755
2756 /***************************************
2757 *
2758 * memory-mapped I/O access
2759 *
2760 ***************************************/
2761
2762 static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2763 {
2764 CirrusVGAState *s = opaque;
2765
2766 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2767
2768 if (addr >= 0x100) {
2769 return cirrus_mmio_blt_read(s, addr - 0x100);
2770 } else {
2771 return cirrus_vga_ioport_read(s, addr + 0x3c0);
2772 }
2773 }
2774
2775 static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2776 {
2777 uint32_t v;
2778
2779 v = cirrus_mmio_readb(opaque, addr);
2780 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2781 return v;
2782 }
2783
2784 static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
2785 {
2786 uint32_t v;
2787
2788 v = cirrus_mmio_readb(opaque, addr);
2789 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2790 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
2791 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
2792 return v;
2793 }
2794
2795 static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
2796 uint32_t val)
2797 {
2798 CirrusVGAState *s = opaque;
2799
2800 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2801
2802 if (addr >= 0x100) {
2803 cirrus_mmio_blt_write(s, addr - 0x100, val);
2804 } else {
2805 cirrus_vga_ioport_write(s, addr + 0x3c0, val);
2806 }
2807 }
2808
2809 static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
2810 uint32_t val)
2811 {
2812 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2813 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2814 }
2815
2816 static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
2817 uint32_t val)
2818 {
2819 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2820 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2821 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2822 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2823 }
2824
2825
2826 static CPUReadMemoryFunc * const cirrus_mmio_read[3] = {
2827 cirrus_mmio_readb,
2828 cirrus_mmio_readw,
2829 cirrus_mmio_readl,
2830 };
2831
2832 static CPUWriteMemoryFunc * const cirrus_mmio_write[3] = {
2833 cirrus_mmio_writeb,
2834 cirrus_mmio_writew,
2835 cirrus_mmio_writel,
2836 };
2837
2838 /* load/save state */
2839
2840 static int cirrus_post_load(void *opaque, int version_id)
2841 {
2842 CirrusVGAState *s = opaque;
2843
2844 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2845 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2846
2847 cirrus_update_memory_access(s);
2848 /* force refresh */
2849 s->vga.graphic_mode = -1;
2850 cirrus_update_bank_ptr(s, 0);
2851 cirrus_update_bank_ptr(s, 1);
2852 return 0;
2853 }
2854
2855 static const VMStateDescription vmstate_cirrus_vga = {
2856 .name = "cirrus_vga",
2857 .version_id = 2,
2858 .minimum_version_id = 1,
2859 .minimum_version_id_old = 1,
2860 .post_load = cirrus_post_load,
2861 .fields = (VMStateField []) {
2862 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2863 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2864 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2865 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2866 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2867 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2868 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2869 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2870 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2871 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2872 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2873 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2874 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2875 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2876 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2877 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2878 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2879 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2880 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2881 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2882 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2883 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2884 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2885 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2886 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2887 VMSTATE_UINT32(hw_cursor_x, CirrusVGAState),
2888 VMSTATE_UINT32(hw_cursor_y, CirrusVGAState),
2889 /* XXX: we do not save the bitblt state - we assume we do not save
2890 the state when the blitter is active */
2891 VMSTATE_END_OF_LIST()
2892 }
2893 };
2894
2895 static const VMStateDescription vmstate_pci_cirrus_vga = {
2896 .name = "cirrus_vga",
2897 .version_id = 2,
2898 .minimum_version_id = 2,
2899 .minimum_version_id_old = 2,
2900 .fields = (VMStateField []) {
2901 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2902 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2903 vmstate_cirrus_vga, CirrusVGAState),
2904 VMSTATE_END_OF_LIST()
2905 }
2906 };
2907
2908 /***************************************
2909 *
2910 * initialize
2911 *
2912 ***************************************/
2913
2914 static void cirrus_reset(void *opaque)
2915 {
2916 CirrusVGAState *s = opaque;
2917
2918 vga_common_reset(&s->vga);
2919 unmap_linear_vram(s);
2920 s->vga.sr[0x06] = 0x0f;
2921 if (s->device_id == CIRRUS_ID_CLGD5446) {
2922 /* 4MB 64 bit memory config, always PCI */
2923 s->vga.sr[0x1F] = 0x2d; // MemClock
2924 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2925 s->vga.sr[0x0f] = 0x98;
2926 s->vga.sr[0x17] = 0x20;
2927 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
2928 } else {
2929 s->vga.sr[0x1F] = 0x22; // MemClock
2930 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2931 s->vga.sr[0x17] = s->bustype;
2932 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2933 }
2934 s->vga.cr[0x27] = s->device_id;
2935
2936 /* Win2K seems to assume that the pattern buffer is at 0xff
2937 initially ! */
2938 memset(s->vga.vram_ptr, 0xff, s->real_vram_size);
2939
2940 s->cirrus_hidden_dac_lockindex = 5;
2941 s->cirrus_hidden_dac_data = 0;
2942 }
2943
2944 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
2945 {
2946 int i;
2947 static int inited;
2948
2949 if (!inited) {
2950 inited = 1;
2951 for(i = 0;i < 256; i++)
2952 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2953 rop_to_index[CIRRUS_ROP_0] = 0;
2954 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2955 rop_to_index[CIRRUS_ROP_NOP] = 2;
2956 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2957 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2958 rop_to_index[CIRRUS_ROP_SRC] = 5;
2959 rop_to_index[CIRRUS_ROP_1] = 6;
2960 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2961 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2962 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2963 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2964 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2965 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2966 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2967 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2968 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2969 s->device_id = device_id;
2970 if (is_pci)
2971 s->bustype = CIRRUS_BUSTYPE_PCI;
2972 else
2973 s->bustype = CIRRUS_BUSTYPE_ISA;
2974 }
2975
2976 register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s);
2977
2978 register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s);
2979 register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s);
2980 register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s);
2981 register_ioport_write(0x3da, 1, 1, cirrus_vga_ioport_write, s);
2982
2983 register_ioport_read(0x3c0, 16, 1, cirrus_vga_ioport_read, s);
2984
2985 register_ioport_read(0x3b4, 2, 1, cirrus_vga_ioport_read, s);
2986 register_ioport_read(0x3d4, 2, 1, cirrus_vga_ioport_read, s);
2987 register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read, s);
2988 register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s);
2989
2990 s->vga.vga_io_memory = cpu_register_io_memory(cirrus_vga_mem_read,
2991 cirrus_vga_mem_write, s,
2992 DEVICE_LITTLE_ENDIAN);
2993 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
2994 s->vga.vga_io_memory);
2995 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
2996
2997 /* I/O handler for LFB */
2998 s->cirrus_linear_io_addr =
2999 cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s,
3000 DEVICE_LITTLE_ENDIAN);
3001
3002 /* I/O handler for LFB */
3003 s->cirrus_linear_bitblt_io_addr =
3004 cpu_register_io_memory(cirrus_linear_bitblt_read,
3005 cirrus_linear_bitblt_write, s,
3006 DEVICE_LITTLE_ENDIAN);
3007
3008 /* I/O handler for memory-mapped I/O */
3009 s->cirrus_mmio_io_addr =
3010 cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s,
3011 DEVICE_LITTLE_ENDIAN);
3012
3013 s->real_vram_size =
3014 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
3015
3016 /* XXX: s->vga.vram_size must be a power of two */
3017 s->cirrus_addr_mask = s->real_vram_size - 1;
3018 s->linear_mmio_mask = s->real_vram_size - 256;
3019
3020 s->vga.get_bpp = cirrus_get_bpp;
3021 s->vga.get_offsets = cirrus_get_offsets;
3022 s->vga.get_resolution = cirrus_get_resolution;
3023 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
3024 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
3025
3026 qemu_register_reset(cirrus_reset, s);
3027 cirrus_reset(s);
3028 }
3029
3030 /***************************************
3031 *
3032 * ISA bus support
3033 *
3034 ***************************************/
3035
3036 void isa_cirrus_vga_init(void)
3037 {
3038 CirrusVGAState *s;
3039
3040 s = qemu_mallocz(sizeof(CirrusVGAState));
3041
3042 vga_common_init(&s->vga, VGA_RAM_SIZE);
3043 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3044 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3045 s->vga.screen_dump, s->vga.text_update,
3046 &s->vga);
3047 vmstate_register(NULL, 0, &vmstate_cirrus_vga, s);
3048 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
3049 /* XXX ISA-LFB support */
3050 }
3051
3052 /***************************************
3053 *
3054 * PCI bus support
3055 *
3056 ***************************************/
3057
3058 static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3059 pcibus_t addr, pcibus_t size, int type)
3060 {
3061 CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;
3062
3063 /* XXX: add byte swapping apertures */
3064 cpu_register_physical_memory(addr, s->vga.vram_size,
3065 s->cirrus_linear_io_addr);
3066 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3067 s->cirrus_linear_bitblt_io_addr);
3068
3069 s->vga.map_addr = s->vga.map_end = 0;
3070 s->vga.lfb_addr = addr & TARGET_PAGE_MASK;
3071 s->vga.lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
3072 /* account for overflow */
3073 if (s->vga.lfb_end < addr + VGA_RAM_SIZE)
3074 s->vga.lfb_end = addr + VGA_RAM_SIZE;
3075
3076 vga_dirty_log_start(&s->vga);
3077 }
3078
3079 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3080 pcibus_t addr, pcibus_t size, int type)
3081 {
3082 CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;
3083
3084 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3085 s->cirrus_mmio_io_addr);
3086 }
3087
3088 static void pci_cirrus_write_config(PCIDevice *d,
3089 uint32_t address, uint32_t val, int len)
3090 {
3091 PCICirrusVGAState *pvs = DO_UPCAST(PCICirrusVGAState, dev, d);
3092 CirrusVGAState *s = &pvs->cirrus_vga;
3093
3094 pci_default_write_config(d, address, val, len);
3095 if (s->vga.map_addr && d->io_regions[0].addr == PCI_BAR_UNMAPPED)
3096 s->vga.map_addr = 0;
3097 cirrus_update_memory_access(s);
3098 }
3099
3100 static int pci_cirrus_vga_initfn(PCIDevice *dev)
3101 {
3102 PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
3103 CirrusVGAState *s = &d->cirrus_vga;
3104 uint8_t *pci_conf = d->dev.config;
3105 int device_id = CIRRUS_ID_CLGD5446;
3106
3107 /* setup VGA */
3108 vga_common_init(&s->vga, VGA_RAM_SIZE);
3109 cirrus_init_common(s, device_id, 1);
3110 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3111 s->vga.screen_dump, s->vga.text_update,
3112 &s->vga);
3113
3114 /* setup PCI */
3115 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
3116 pci_config_set_device_id(pci_conf, device_id);
3117 pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
3118
3119 /* setup memory space */
3120 /* memory #0 LFB */
3121 /* memory #1 memory-mapped I/O */
3122 /* XXX: s->vga.vram_size must be a power of two */
3123 pci_register_bar(&d->dev, 0, 0x2000000,
3124 PCI_BASE_ADDRESS_MEM_PREFETCH, cirrus_pci_lfb_map);
3125 if (device_id == CIRRUS_ID_CLGD5446) {
3126 pci_register_bar(&d->dev, 1, CIRRUS_PNPMMIO_SIZE,
3127 PCI_BASE_ADDRESS_SPACE_MEMORY, cirrus_pci_mmio_map);
3128 }
3129 return 0;
3130 }
3131
3132 void pci_cirrus_vga_init(PCIBus *bus)
3133 {
3134 pci_create_simple(bus, -1, "cirrus-vga");
3135 }
3136
3137 static PCIDeviceInfo cirrus_vga_info = {
3138 .qdev.name = "cirrus-vga",
3139 .qdev.desc = "Cirrus CLGD 54xx VGA",
3140 .qdev.size = sizeof(PCICirrusVGAState),
3141 .qdev.vmsd = &vmstate_pci_cirrus_vga,
3142 .no_hotplug = 1,
3143 .init = pci_cirrus_vga_initfn,
3144 .romfile = VGABIOS_CIRRUS_FILENAME,
3145 .config_write = pci_cirrus_write_config,
3146 };
3147
3148 static void cirrus_vga_register(void)
3149 {
3150 pci_qdev_register(&cirrus_vga_info);
3151 }
3152 device_init(cirrus_vga_register);
QEmu