hw/misc/exynos4210_rng.c

   1 /*
   2  *  Exynos4210 Pseudo Random Nubmer Generator Emulation
   3  *
   4  *  Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License as published by the
   8  *  Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14  *  for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License along
  17  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "crypto/random.h"
  22 #include "hw/sysbus.h"
  23 #include "qemu/log.h"
  24
  25 #define DEBUG_EXYNOS_RNG 0
  26
  27 #define DPRINTF(fmt, ...) \
  28     do { \
  29         if (DEBUG_EXYNOS_RNG) { \
  30             printf("exynos4210_rng: " fmt, ## __VA_ARGS__); \
  31         } \
  32     } while (0)
  33
  34 #define TYPE_EXYNOS4210_RNG             "exynos4210.rng"
  35 #define EXYNOS4210_RNG(obj) \
  36     OBJECT_CHECK(Exynos4210RngState, (obj), TYPE_EXYNOS4210_RNG)
  37
  38 /*
  39  * Exynos4220, PRNG, only polling mode is supported.
  40  */
  41
  42 /* RNG_CONTROL_1 register bitfields, reset value: 0x0 */
  43 #define EXYNOS4210_RNG_CONTROL_1_PRNG           0x8
  44 #define EXYNOS4210_RNG_CONTROL_1_START_INIT     BIT(4)
  45 /* RNG_STATUS register bitfields, reset value: 0x1 */
  46 #define EXYNOS4210_RNG_STATUS_PRNG_ERROR        BIT(7)
  47 #define EXYNOS4210_RNG_STATUS_PRNG_DONE         BIT(5)
  48 #define EXYNOS4210_RNG_STATUS_MSG_DONE          BIT(4)
  49 #define EXYNOS4210_RNG_STATUS_PARTIAL_DONE      BIT(3)
  50 #define EXYNOS4210_RNG_STATUS_PRNG_BUSY         BIT(2)
  51 #define EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE BIT(1)
  52 #define EXYNOS4210_RNG_STATUS_BUFFER_READY      BIT(0)
  53 #define EXYNOS4210_RNG_STATUS_WRITE_MASK   (EXYNOS4210_RNG_STATUS_PRNG_DONE \
  54                                            | EXYNOS4210_RNG_STATUS_MSG_DONE \
  55                                            | EXYNOS4210_RNG_STATUS_PARTIAL_DONE)
  56
  57 #define EXYNOS4210_RNG_CONTROL_1                  0x0
  58 #define EXYNOS4210_RNG_STATUS                    0x10
  59 #define EXYNOS4210_RNG_SEED_IN                  0x140
  60 #define EXYNOS4210_RNG_SEED_IN_OFFSET(n)   (EXYNOS4210_RNG_SEED_IN + (n * 0x4))
  61 #define EXYNOS4210_RNG_PRNG                     0x160
  62 #define EXYNOS4210_RNG_PRNG_OFFSET(n)      (EXYNOS4210_RNG_PRNG + (n * 0x4))
  63
  64 #define EXYNOS4210_RNG_PRNG_NUM                 5
  65
  66 #define EXYNOS4210_RNG_REGS_MEM_SIZE            0x200
  67
  68 typedef struct Exynos4210RngState {
  69     SysBusDevice parent_obj;
  70     MemoryRegion iomem;
  71
  72     int32_t randr_value[EXYNOS4210_RNG_PRNG_NUM];
  73     /* bits from 0 to EXYNOS4210_RNG_PRNG_NUM if given seed register was set */
  74     uint32_t seed_set;
  75
  76     /* Register values */
  77     uint32_t reg_control;
  78     uint32_t reg_status;
  79 } Exynos4210RngState;
  80
  81 static bool exynos4210_rng_seed_ready(const Exynos4210RngState *s)
  82 {
  83     uint32_t mask = MAKE_64BIT_MASK(0, EXYNOS4210_RNG_PRNG_NUM);
  84
  85     /* Return true if all the seed-set bits are set. */
  86     return (s->seed_set & mask) == mask;
  87 }
  88
  89 static void exynos4210_rng_set_seed(Exynos4210RngState *s, unsigned int i,
  90                                     uint64_t val)
  91 {
  92     /*
  93      * We actually ignore the seed and always generate true random numbers.
  94      * Theoretically this should not match the device as Exynos has
  95      * a Pseudo Random Number Generator but testing shown that it always
  96      * generates random numbers regardless of the seed value.
  97      */
  98     s->seed_set |= BIT(i);
  99
 100     /* If all seeds were written, update the status to reflect it */
 101     if (exynos4210_rng_seed_ready(s)) {
 102         s->reg_status |= EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE;
 103     } else {
 104         s->reg_status &= ~EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE;
 105     }
 106 }
 107
 108 static void exynos4210_rng_run_engine(Exynos4210RngState *s)
 109 {
 110     Error *err = NULL;
 111     int ret;
 112
 113     /* Seed set? */
 114     if ((s->reg_status & EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE) == 0) {
 115         goto out;
 116     }
 117
 118     /* PRNG engine chosen? */
 119     if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_PRNG) == 0) {
 120         goto out;
 121     }
 122
 123     /* PRNG engine started? */
 124     if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_START_INIT) == 0) {
 125         goto out;
 126     }
 127
 128     /* Get randoms */
 129     ret = qcrypto_random_bytes((uint8_t *)s->randr_value,
 130                                sizeof(s->randr_value), &err);
 131     if (!ret) {
 132         /* Notify that PRNG is ready */
 133         s->reg_status |= EXYNOS4210_RNG_STATUS_PRNG_DONE;
 134     } else {
 135         error_report_err(err);
 136     }
 137
 138 out:
 139     /* Always clear start engine bit */
 140     s->reg_control &= ~EXYNOS4210_RNG_CONTROL_1_START_INIT;
 141 }
 142
 143 static uint64_t exynos4210_rng_read(void *opaque, hwaddr offset,
 144                                     unsigned size)
 145 {
 146     Exynos4210RngState *s = (Exynos4210RngState *)opaque;
 147     uint32_t val = 0;
 148
 149     assert(size == 4);
 150
 151     switch (offset) {
 152     case EXYNOS4210_RNG_CONTROL_1:
 153         val = s->reg_control;
 154         break;
 155
 156     case EXYNOS4210_RNG_STATUS:
 157         val = s->reg_status;
 158         break;
 159
 160     case EXYNOS4210_RNG_PRNG_OFFSET(0):
 161     case EXYNOS4210_RNG_PRNG_OFFSET(1):
 162     case EXYNOS4210_RNG_PRNG_OFFSET(2):
 163     case EXYNOS4210_RNG_PRNG_OFFSET(3):
 164     case EXYNOS4210_RNG_PRNG_OFFSET(4):
 165         val = s->randr_value[(offset - EXYNOS4210_RNG_PRNG_OFFSET(0)) / 4];
 166         DPRINTF("returning random @0x%" HWADDR_PRIx ": 0x%" PRIx32 "\n",
 167                 offset, val);
 168         break;
 169
 170     default:
 171         qemu_log_mask(LOG_GUEST_ERROR,
 172                       "%s: bad read offset 0x%" HWADDR_PRIx "\n",
 173                       __func__, offset);
 174     }
 175
 176     return val;
 177 }
 178
 179 static void exynos4210_rng_write(void *opaque, hwaddr offset,
 180                                  uint64_t val, unsigned size)
 181 {
 182     Exynos4210RngState *s = (Exynos4210RngState *)opaque;
 183
 184     assert(size == 4);
 185
 186     switch (offset) {
 187     case EXYNOS4210_RNG_CONTROL_1:
 188         DPRINTF("RNG_CONTROL_1 = 0x%" PRIx64 "\n", val);
 189         s->reg_control = val;
 190         exynos4210_rng_run_engine(s);
 191         break;
 192
 193     case EXYNOS4210_RNG_STATUS:
 194         /* For clearing status fields */
 195         s->reg_status &= ~EXYNOS4210_RNG_STATUS_WRITE_MASK;
 196         s->reg_status |= val & EXYNOS4210_RNG_STATUS_WRITE_MASK;
 197         break;
 198
 199     case EXYNOS4210_RNG_SEED_IN_OFFSET(0):
 200     case EXYNOS4210_RNG_SEED_IN_OFFSET(1):
 201     case EXYNOS4210_RNG_SEED_IN_OFFSET(2):
 202     case EXYNOS4210_RNG_SEED_IN_OFFSET(3):
 203     case EXYNOS4210_RNG_SEED_IN_OFFSET(4):
 204         exynos4210_rng_set_seed(s,
 205                                 (offset - EXYNOS4210_RNG_SEED_IN_OFFSET(0)) / 4,
 206                                 val);
 207         break;
 208
 209     default:
 210         qemu_log_mask(LOG_GUEST_ERROR,
 211                       "%s: bad write offset 0x%" HWADDR_PRIx "\n",
 212                       __func__, offset);
 213     }
 214 }
 215
 216 static const MemoryRegionOps exynos4210_rng_ops = {
 217     .read = exynos4210_rng_read,
 218     .write = exynos4210_rng_write,
 219     .endianness = DEVICE_NATIVE_ENDIAN,
 220 };
 221
 222 static void exynos4210_rng_reset(DeviceState *dev)
 223 {
 224     Exynos4210RngState *s = EXYNOS4210_RNG(dev);
 225
 226     s->reg_control = 0;
 227     s->reg_status = EXYNOS4210_RNG_STATUS_BUFFER_READY;
 228     memset(s->randr_value, 0, sizeof(s->randr_value));
 229     s->seed_set = 0;
 230 }
 231
 232 static void exynos4210_rng_init(Object *obj)
 233 {
 234     Exynos4210RngState *s = EXYNOS4210_RNG(obj);
 235     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 236
 237     memory_region_init_io(&s->iomem, obj, &exynos4210_rng_ops, s,
 238                           TYPE_EXYNOS4210_RNG, EXYNOS4210_RNG_REGS_MEM_SIZE);
 239     sysbus_init_mmio(dev, &s->iomem);
 240 }
 241
 242 static const VMStateDescription exynos4210_rng_vmstate = {
 243     .name = TYPE_EXYNOS4210_RNG,
 244     .version_id = 1,
 245     .minimum_version_id = 1,
 246     .fields = (VMStateField[]) {
 247         VMSTATE_INT32_ARRAY(randr_value, Exynos4210RngState,
 248                             EXYNOS4210_RNG_PRNG_NUM),
 249         VMSTATE_UINT32(seed_set, Exynos4210RngState),
 250         VMSTATE_UINT32(reg_status, Exynos4210RngState),
 251         VMSTATE_UINT32(reg_control, Exynos4210RngState),
 252         VMSTATE_END_OF_LIST()
 253     }
 254 };
 255
 256 static void exynos4210_rng_class_init(ObjectClass *klass, void *data)
 257 {
 258     DeviceClass *dc = DEVICE_CLASS(klass);
 259
 260     dc->reset = exynos4210_rng_reset;
 261     dc->vmsd = &exynos4210_rng_vmstate;
 262 }
 263
 264 static const TypeInfo exynos4210_rng_info = {
 265     .name          = TYPE_EXYNOS4210_RNG,
 266     .parent        = TYPE_SYS_BUS_DEVICE,
 267     .instance_size = sizeof(Exynos4210RngState),
 268     .instance_init = exynos4210_rng_init,
 269     .class_init    = exynos4210_rng_class_init,
 270 };
 271
 272 static void exynos4210_rng_register(void)
 273 {
 274     type_register_static(&exynos4210_rng_info);
 275 }
 276
 277 type_init(exynos4210_rng_register)