hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "hw.h"
  20 #include "apic.h"
  21 #include "ioapic.h"
  22 #include "qemu-timer.h"
  23 #include "host-utils.h"
  24 #include "sysbus.h"
  25 #include "trace.h"
  26
  27 /* APIC Local Vector Table */
  28 #define APIC_LVT_TIMER   0
  29 #define APIC_LVT_THERMAL 1
  30 #define APIC_LVT_PERFORM 2
  31 #define APIC_LVT_LINT0   3
  32 #define APIC_LVT_LINT1   4
  33 #define APIC_LVT_ERROR   5
  34 #define APIC_LVT_NB      6
  35
  36 /* APIC delivery modes */
  37 #define APIC_DM_FIXED   0
  38 #define APIC_DM_LOWPRI  1
  39 #define APIC_DM_SMI     2
  40 #define APIC_DM_NMI     4
  41 #define APIC_DM_INIT    5
  42 #define APIC_DM_SIPI    6
  43 #define APIC_DM_EXTINT  7
  44
  45 /* APIC destination mode */
  46 #define APIC_DESTMODE_FLAT      0xf
  47 #define APIC_DESTMODE_CLUSTER   1
  48
  49 #define APIC_TRIGGER_EDGE  0
  50 #define APIC_TRIGGER_LEVEL 1
  51
  52 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  53 #define APIC_LVT_MASKED                 (1<<16)
  54 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  55 #define APIC_LVT_REMOTE_IRR             (1<<14)
  56 #define APIC_INPUT_POLARITY             (1<<13)
  57 #define APIC_SEND_PENDING               (1<<12)
  58
  59 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  60
  61 #define APIC_SV_DIRECTED_IO             (1<<12)
  62 #define APIC_SV_ENABLE                  (1<<8)
  63
  64 #define MAX_APICS 255
  65 #define MAX_APIC_WORDS 8
  66
  67 /* Intel APIC constants: from include/asm/msidef.h */
  68 #define MSI_DATA_VECTOR_SHIFT           0
  69 #define MSI_DATA_VECTOR_MASK            0x000000ff
  70 #define MSI_DATA_DELIVERY_MODE_SHIFT    8
  71 #define MSI_DATA_TRIGGER_SHIFT          15
  72 #define MSI_DATA_LEVEL_SHIFT            14
  73 #define MSI_ADDR_DEST_MODE_SHIFT        2
  74 #define MSI_ADDR_DEST_ID_SHIFT          12
  75 #define MSI_ADDR_DEST_ID_MASK           0x00ffff0
  76
  77 #define MSI_ADDR_SIZE                   0x100000
  78
  79 typedef struct APICState APICState;
  80
  81 struct APICState {
  82     SysBusDevice busdev;
  83     void *cpu_env;
  84     uint32_t apicbase;
  85     uint8_t id;
  86     uint8_t arb_id;
  87     uint8_t tpr;
  88     uint32_t spurious_vec;
  89     uint8_t log_dest;
  90     uint8_t dest_mode;
  91     uint32_t isr[8];  /* in service register */
  92     uint32_t tmr[8];  /* trigger mode register */
  93     uint32_t irr[8]; /* interrupt request register */
  94     uint32_t lvt[APIC_LVT_NB];
  95     uint32_t esr; /* error register */
  96     uint32_t icr[2];
  97
  98     uint32_t divide_conf;
  99     int count_shift;
 100     uint32_t initial_count;
 101     int64_t initial_count_load_time, next_time;
 102     uint32_t idx;
 103     QEMUTimer *timer;
 104     int sipi_vector;
 105     int wait_for_sipi;
 106 };
 107
 108 static APICState *local_apics[MAX_APICS + 1];
 109 static int apic_irq_delivered;
 110
 111 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 112 static void apic_update_irq(APICState *s);
 113 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 114                                       uint8_t dest, uint8_t dest_mode);
 115
 116 /* Find first bit starting from msb */
 117 static int fls_bit(uint32_t value)
 118 {
 119     return 31 - clz32(value);
 120 }
 121
 122 /* Find first bit starting from lsb */
 123 static int ffs_bit(uint32_t value)
 124 {
 125     return ctz32(value);
 126 }
 127
 128 static inline void set_bit(uint32_t *tab, int index)
 129 {
 130     int i, mask;
 131     i = index >> 5;
 132     mask = 1 << (index & 0x1f);
 133     tab[i] |= mask;
 134 }
 135
 136 static inline void reset_bit(uint32_t *tab, int index)
 137 {
 138     int i, mask;
 139     i = index >> 5;
 140     mask = 1 << (index & 0x1f);
 141     tab[i] &= ~mask;
 142 }
 143
 144 static inline int get_bit(uint32_t *tab, int index)
 145 {
 146     int i, mask;
 147     i = index >> 5;
 148     mask = 1 << (index & 0x1f);
 149     return !!(tab[i] & mask);
 150 }
 151
 152 static void apic_local_deliver(APICState *s, int vector)
 153 {
 154     uint32_t lvt = s->lvt[vector];
 155     int trigger_mode;
 156
 157     trace_apic_local_deliver(vector, (lvt >> 8) & 7);
 158
 159     if (lvt & APIC_LVT_MASKED)
 160         return;
 161
 162     switch ((lvt >> 8) & 7) {
 163     case APIC_DM_SMI:
 164         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
 165         break;
 166
 167     case APIC_DM_NMI:
 168         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
 169         break;
 170
 171     case APIC_DM_EXTINT:
 172         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 173         break;
 174
 175     case APIC_DM_FIXED:
 176         trigger_mode = APIC_TRIGGER_EDGE;
 177         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 178             (lvt & APIC_LVT_LEVEL_TRIGGER))
 179             trigger_mode = APIC_TRIGGER_LEVEL;
 180         apic_set_irq(s, lvt & 0xff, trigger_mode);
 181     }
 182 }
 183
 184 void apic_deliver_pic_intr(DeviceState *d, int level)
 185 {
 186     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 187
 188     if (level) {
 189         apic_local_deliver(s, APIC_LVT_LINT0);
 190     } else {
 191         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 192
 193         switch ((lvt >> 8) & 7) {
 194         case APIC_DM_FIXED:
 195             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 196                 break;
 197             reset_bit(s->irr, lvt & 0xff);
 198             /* fall through */
 199         case APIC_DM_EXTINT:
 200             cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 201             break;
 202         }
 203     }
 204 }
 205
 206 #define foreach_apic(apic, deliver_bitmask, code) \
 207 {\
 208     int __i, __j, __mask;\
 209     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 210         __mask = deliver_bitmask[__i];\
 211         if (__mask) {\
 212             for(__j = 0; __j < 32; __j++) {\
 213                 if (__mask & (1 << __j)) {\
 214                     apic = local_apics[__i * 32 + __j];\
 215                     if (apic) {\
 216                         code;\
 217                     }\
 218                 }\
 219             }\
 220         }\
 221     }\
 222 }
 223
 224 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 225                              uint8_t delivery_mode,
 226                              uint8_t vector_num, uint8_t polarity,
 227                              uint8_t trigger_mode)
 228 {
 229     APICState *apic_iter;
 230
 231     switch (delivery_mode) {
 232         case APIC_DM_LOWPRI:
 233             /* XXX: search for focus processor, arbitration */
 234             {
 235                 int i, d;
 236                 d = -1;
 237                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 238                     if (deliver_bitmask[i]) {
 239                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 240                         break;
 241                     }
 242                 }
 243                 if (d >= 0) {
 244                     apic_iter = local_apics[d];
 245                     if (apic_iter) {
 246                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 247                     }
 248                 }
 249             }
 250             return;
 251
 252         case APIC_DM_FIXED:
 253             break;
 254
 255         case APIC_DM_SMI:
 256             foreach_apic(apic_iter, deliver_bitmask,
 257                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 258             return;
 259
 260         case APIC_DM_NMI:
 261             foreach_apic(apic_iter, deliver_bitmask,
 262                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 263             return;
 264
 265         case APIC_DM_INIT:
 266             /* normal INIT IPI sent to processors */
 267             foreach_apic(apic_iter, deliver_bitmask,
 268                          cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
 269             return;
 270
 271         case APIC_DM_EXTINT:
 272             /* handled in I/O APIC code */
 273             break;
 274
 275         default:
 276             return;
 277     }
 278
 279     foreach_apic(apic_iter, deliver_bitmask,
 280                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 281 }
 282
 283 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
 284                       uint8_t delivery_mode, uint8_t vector_num,
 285                       uint8_t polarity, uint8_t trigger_mode)
 286 {
 287     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 288
 289     trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
 290                            polarity, trigger_mode);
 291
 292     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 293     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 294                      trigger_mode);
 295 }
 296
 297 void cpu_set_apic_base(DeviceState *d, uint64_t val)
 298 {
 299     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 300
 301     trace_cpu_set_apic_base(val);
 302
 303     if (!s)
 304         return;
 305     s->apicbase = (val & 0xfffff000) |
 306         (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 307     /* if disabled, cannot be enabled again */
 308     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 309         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 310         cpu_clear_apic_feature(s->cpu_env);
 311         s->spurious_vec &= ~APIC_SV_ENABLE;
 312     }
 313 }
 314
 315 uint64_t cpu_get_apic_base(DeviceState *d)
 316 {
 317     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 318
 319     trace_cpu_get_apic_base(s ? (uint64_t)s->apicbase: 0);
 320
 321     return s ? s->apicbase : 0;
 322 }
 323
 324 void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
 325 {
 326     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 327
 328     if (!s)
 329         return;
 330     s->tpr = (val & 0x0f) << 4;
 331     apic_update_irq(s);
 332 }
 333
 334 uint8_t cpu_get_apic_tpr(DeviceState *d)
 335 {
 336     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 337
 338     return s ? s->tpr >> 4 : 0;
 339 }
 340
 341 /* return -1 if no bit is set */
 342 static int get_highest_priority_int(uint32_t *tab)
 343 {
 344     int i;
 345     for(i = 7; i >= 0; i--) {
 346         if (tab[i] != 0) {
 347             return i * 32 + fls_bit(tab[i]);
 348         }
 349     }
 350     return -1;
 351 }
 352
 353 static int apic_get_ppr(APICState *s)
 354 {
 355     int tpr, isrv, ppr;
 356
 357     tpr = (s->tpr >> 4);
 358     isrv = get_highest_priority_int(s->isr);
 359     if (isrv < 0)
 360         isrv = 0;
 361     isrv >>= 4;
 362     if (tpr >= isrv)
 363         ppr = s->tpr;
 364     else
 365         ppr = isrv << 4;
 366     return ppr;
 367 }
 368
 369 static int apic_get_arb_pri(APICState *s)
 370 {
 371     /* XXX: arbitration */
 372     return 0;
 373 }
 374
 375 /* signal the CPU if an irq is pending */
 376 static void apic_update_irq(APICState *s)
 377 {
 378     int irrv, ppr;
 379     if (!(s->spurious_vec & APIC_SV_ENABLE))
 380         return;
 381     irrv = get_highest_priority_int(s->irr);
 382     if (irrv < 0)
 383         return;
 384     ppr = apic_get_ppr(s);
 385     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 386         return;
 387     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 388 }
 389
 390 void apic_reset_irq_delivered(void)
 391 {
 392     trace_apic_reset_irq_delivered(apic_irq_delivered);
 393
 394     apic_irq_delivered = 0;
 395 }
 396
 397 int apic_get_irq_delivered(void)
 398 {
 399     trace_apic_get_irq_delivered(apic_irq_delivered);
 400
 401     return apic_irq_delivered;
 402 }
 403
 404 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 405 {
 406     apic_irq_delivered += !get_bit(s->irr, vector_num);
 407
 408     trace_apic_set_irq(apic_irq_delivered);
 409
 410     set_bit(s->irr, vector_num);
 411     if (trigger_mode)
 412         set_bit(s->tmr, vector_num);
 413     else
 414         reset_bit(s->tmr, vector_num);
 415     apic_update_irq(s);
 416 }
 417
 418 static void apic_eoi(APICState *s)
 419 {
 420     int isrv;
 421     isrv = get_highest_priority_int(s->isr);
 422     if (isrv < 0)
 423         return;
 424     reset_bit(s->isr, isrv);
 425     if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, isrv)) {
 426         ioapic_eoi_broadcast(isrv);
 427     }
 428     apic_update_irq(s);
 429 }
 430
 431 static int apic_find_dest(uint8_t dest)
 432 {
 433     APICState *apic = local_apics[dest];
 434     int i;
 435
 436     if (apic && apic->id == dest)
 437         return dest;  /* shortcut in case apic->id == apic->idx */
 438
 439     for (i = 0; i < MAX_APICS; i++) {
 440         apic = local_apics[i];
 441         if (apic && apic->id == dest)
 442             return i;
 443         if (!apic)
 444             break;
 445     }
 446
 447     return -1;
 448 }
 449
 450 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 451                                       uint8_t dest, uint8_t dest_mode)
 452 {
 453     APICState *apic_iter;
 454     int i;
 455
 456     if (dest_mode == 0) {
 457         if (dest == 0xff) {
 458             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 459         } else {
 460             int idx = apic_find_dest(dest);
 461             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 462             if (idx >= 0)
 463                 set_bit(deliver_bitmask, idx);
 464         }
 465     } else {
 466         /* XXX: cluster mode */
 467         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 468         for(i = 0; i < MAX_APICS; i++) {
 469             apic_iter = local_apics[i];
 470             if (apic_iter) {
 471                 if (apic_iter->dest_mode == 0xf) {
 472                     if (dest & apic_iter->log_dest)
 473                         set_bit(deliver_bitmask, i);
 474                 } else if (apic_iter->dest_mode == 0x0) {
 475                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 476                         (dest & apic_iter->log_dest & 0x0f)) {
 477                         set_bit(deliver_bitmask, i);
 478                     }
 479                 }
 480             } else {
 481                 break;
 482             }
 483         }
 484     }
 485 }
 486
 487 void apic_init_reset(DeviceState *d)
 488 {
 489     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 490     int i;
 491
 492     if (!s)
 493         return;
 494
 495     s->tpr = 0;
 496     s->spurious_vec = 0xff;
 497     s->log_dest = 0;
 498     s->dest_mode = 0xf;
 499     memset(s->isr, 0, sizeof(s->isr));
 500     memset(s->tmr, 0, sizeof(s->tmr));
 501     memset(s->irr, 0, sizeof(s->irr));
 502     for(i = 0; i < APIC_LVT_NB; i++)
 503         s->lvt[i] = 1 << 16; /* mask LVT */
 504     s->esr = 0;
 505     memset(s->icr, 0, sizeof(s->icr));
 506     s->divide_conf = 0;
 507     s->count_shift = 0;
 508     s->initial_count = 0;
 509     s->initial_count_load_time = 0;
 510     s->next_time = 0;
 511     s->wait_for_sipi = 1;
 512 }
 513
 514 static void apic_startup(APICState *s, int vector_num)
 515 {
 516     s->sipi_vector = vector_num;
 517     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 518 }
 519
 520 void apic_sipi(DeviceState *d)
 521 {
 522     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 523
 524     cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 525
 526     if (!s->wait_for_sipi)
 527         return;
 528     cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
 529     s->wait_for_sipi = 0;
 530 }
 531
 532 static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
 533                          uint8_t delivery_mode, uint8_t vector_num,
 534                          uint8_t polarity, uint8_t trigger_mode)
 535 {
 536     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 537     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 538     int dest_shorthand = (s->icr[0] >> 18) & 3;
 539     APICState *apic_iter;
 540
 541     switch (dest_shorthand) {
 542     case 0:
 543         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 544         break;
 545     case 1:
 546         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 547         set_bit(deliver_bitmask, s->idx);
 548         break;
 549     case 2:
 550         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 551         break;
 552     case 3:
 553         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 554         reset_bit(deliver_bitmask, s->idx);
 555         break;
 556     }
 557
 558     switch (delivery_mode) {
 559         case APIC_DM_INIT:
 560             {
 561                 int trig_mode = (s->icr[0] >> 15) & 1;
 562                 int level = (s->icr[0] >> 14) & 1;
 563                 if (level == 0 && trig_mode == 1) {
 564                     foreach_apic(apic_iter, deliver_bitmask,
 565                                  apic_iter->arb_id = apic_iter->id );
 566                     return;
 567                 }
 568             }
 569             break;
 570
 571         case APIC_DM_SIPI:
 572             foreach_apic(apic_iter, deliver_bitmask,
 573                          apic_startup(apic_iter, vector_num) );
 574             return;
 575     }
 576
 577     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 578                      trigger_mode);
 579 }
 580
 581 int apic_get_interrupt(DeviceState *d)
 582 {
 583     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 584     int intno;
 585
 586     /* if the APIC is installed or enabled, we let the 8259 handle the
 587        IRQs */
 588     if (!s)
 589         return -1;
 590     if (!(s->spurious_vec & APIC_SV_ENABLE))
 591         return -1;
 592
 593     /* XXX: spurious IRQ handling */
 594     intno = get_highest_priority_int(s->irr);
 595     if (intno < 0)
 596         return -1;
 597     if (s->tpr && intno <= s->tpr)
 598         return s->spurious_vec & 0xff;
 599     reset_bit(s->irr, intno);
 600     set_bit(s->isr, intno);
 601     apic_update_irq(s);
 602     return intno;
 603 }
 604
 605 int apic_accept_pic_intr(DeviceState *d)
 606 {
 607     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 608     uint32_t lvt0;
 609
 610     if (!s)
 611         return -1;
 612
 613     lvt0 = s->lvt[APIC_LVT_LINT0];
 614
 615     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 616         (lvt0 & APIC_LVT_MASKED) == 0)
 617         return 1;
 618
 619     return 0;
 620 }
 621
 622 static uint32_t apic_get_current_count(APICState *s)
 623 {
 624     int64_t d;
 625     uint32_t val;
 626     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 627         s->count_shift;
 628     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 629         /* periodic */
 630         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 631     } else {
 632         if (d >= s->initial_count)
 633             val = 0;
 634         else
 635             val = s->initial_count - d;
 636     }
 637     return val;
 638 }
 639
 640 static void apic_timer_update(APICState *s, int64_t current_time)
 641 {
 642     int64_t next_time, d;
 643
 644     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 645         d = (current_time - s->initial_count_load_time) >>
 646             s->count_shift;
 647         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 648             if (!s->initial_count)
 649                 goto no_timer;
 650             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 651         } else {
 652             if (d >= s->initial_count)
 653                 goto no_timer;
 654             d = (uint64_t)s->initial_count + 1;
 655         }
 656         next_time = s->initial_count_load_time + (d << s->count_shift);
 657         qemu_mod_timer(s->timer, next_time);
 658         s->next_time = next_time;
 659     } else {
 660     no_timer:
 661         qemu_del_timer(s->timer);
 662     }
 663 }
 664
 665 static void apic_timer(void *opaque)
 666 {
 667     APICState *s = opaque;
 668
 669     apic_local_deliver(s, APIC_LVT_TIMER);
 670     apic_timer_update(s, s->next_time);
 671 }
 672
 673 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 674 {
 675     return 0;
 676 }
 677
 678 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 679 {
 680     return 0;
 681 }
 682
 683 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 684 {
 685 }
 686
 687 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 688 {
 689 }
 690
 691 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 692 {
 693     DeviceState *d;
 694     APICState *s;
 695     uint32_t val;
 696     int index;
 697
 698     d = cpu_get_current_apic();
 699     if (!d) {
 700         return 0;
 701     }
 702     s = DO_UPCAST(APICState, busdev.qdev, d);
 703
 704     index = (addr >> 4) & 0xff;
 705     switch(index) {
 706     case 0x02: /* id */
 707         val = s->id << 24;
 708         break;
 709     case 0x03: /* version */
 710         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 711         break;
 712     case 0x08:
 713         val = s->tpr;
 714         break;
 715     case 0x09:
 716         val = apic_get_arb_pri(s);
 717         break;
 718     case 0x0a:
 719         /* ppr */
 720         val = apic_get_ppr(s);
 721         break;
 722     case 0x0b:
 723         val = 0;
 724         break;
 725     case 0x0d:
 726         val = s->log_dest << 24;
 727         break;
 728     case 0x0e:
 729         val = s->dest_mode << 28;
 730         break;
 731     case 0x0f:
 732         val = s->spurious_vec;
 733         break;
 734     case 0x10 ... 0x17:
 735         val = s->isr[index & 7];
 736         break;
 737     case 0x18 ... 0x1f:
 738         val = s->tmr[index & 7];
 739         break;
 740     case 0x20 ... 0x27:
 741         val = s->irr[index & 7];
 742         break;
 743     case 0x28:
 744         val = s->esr;
 745         break;
 746     case 0x30:
 747     case 0x31:
 748         val = s->icr[index & 1];
 749         break;
 750     case 0x32 ... 0x37:
 751         val = s->lvt[index - 0x32];
 752         break;
 753     case 0x38:
 754         val = s->initial_count;
 755         break;
 756     case 0x39:
 757         val = apic_get_current_count(s);
 758         break;
 759     case 0x3e:
 760         val = s->divide_conf;
 761         break;
 762     default:
 763         s->esr |= ESR_ILLEGAL_ADDRESS;
 764         val = 0;
 765         break;
 766     }
 767     trace_apic_mem_readl(addr, val);
 768     return val;
 769 }
 770
 771 static void apic_send_msi(target_phys_addr_t addr, uint32_t data)
 772 {
 773     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 774     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 775     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 776     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 777     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 778     /* XXX: Ignore redirection hint. */
 779     apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
 780 }
 781
 782 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 783 {
 784     DeviceState *d;
 785     APICState *s;
 786     int index = (addr >> 4) & 0xff;
 787     if (addr > 0xfff || !index) {
 788         /* MSI and MMIO APIC are at the same memory location,
 789          * but actually not on the global bus: MSI is on PCI bus
 790          * APIC is connected directly to the CPU.
 791          * Mapping them on the global bus happens to work because
 792          * MSI registers are reserved in APIC MMIO and vice versa. */
 793         apic_send_msi(addr, val);
 794         return;
 795     }
 796
 797     d = cpu_get_current_apic();
 798     if (!d) {
 799         return;
 800     }
 801     s = DO_UPCAST(APICState, busdev.qdev, d);
 802
 803     trace_apic_mem_writel(addr, val);
 804
 805     switch(index) {
 806     case 0x02:
 807         s->id = (val >> 24);
 808         break;
 809     case 0x03:
 810         break;
 811     case 0x08:
 812         s->tpr = val;
 813         apic_update_irq(s);
 814         break;
 815     case 0x09:
 816     case 0x0a:
 817         break;
 818     case 0x0b: /* EOI */
 819         apic_eoi(s);
 820         break;
 821     case 0x0d:
 822         s->log_dest = val >> 24;
 823         break;
 824     case 0x0e:
 825         s->dest_mode = val >> 28;
 826         break;
 827     case 0x0f:
 828         s->spurious_vec = val & 0x1ff;
 829         apic_update_irq(s);
 830         break;
 831     case 0x10 ... 0x17:
 832     case 0x18 ... 0x1f:
 833     case 0x20 ... 0x27:
 834     case 0x28:
 835         break;
 836     case 0x30:
 837         s->icr[0] = val;
 838         apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 839                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 840                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 841         break;
 842     case 0x31:
 843         s->icr[1] = val;
 844         break;
 845     case 0x32 ... 0x37:
 846         {
 847             int n = index - 0x32;
 848             s->lvt[n] = val;
 849             if (n == APIC_LVT_TIMER)
 850                 apic_timer_update(s, qemu_get_clock(vm_clock));
 851         }
 852         break;
 853     case 0x38:
 854         s->initial_count = val;
 855         s->initial_count_load_time = qemu_get_clock(vm_clock);
 856         apic_timer_update(s, s->initial_count_load_time);
 857         break;
 858     case 0x39:
 859         break;
 860     case 0x3e:
 861         {
 862             int v;
 863             s->divide_conf = val & 0xb;
 864             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 865             s->count_shift = (v + 1) & 7;
 866         }
 867         break;
 868     default:
 869         s->esr |= ESR_ILLEGAL_ADDRESS;
 870         break;
 871     }
 872 }
 873
 874 /* This function is only used for old state version 1 and 2 */
 875 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 876 {
 877     APICState *s = opaque;
 878     int i;
 879
 880     if (version_id > 2)
 881         return -EINVAL;
 882
 883     /* XXX: what if the base changes? (registered memory regions) */
 884     qemu_get_be32s(f, &s->apicbase);
 885     qemu_get_8s(f, &s->id);
 886     qemu_get_8s(f, &s->arb_id);
 887     qemu_get_8s(f, &s->tpr);
 888     qemu_get_be32s(f, &s->spurious_vec);
 889     qemu_get_8s(f, &s->log_dest);
 890     qemu_get_8s(f, &s->dest_mode);
 891     for (i = 0; i < 8; i++) {
 892         qemu_get_be32s(f, &s->isr[i]);
 893         qemu_get_be32s(f, &s->tmr[i]);
 894         qemu_get_be32s(f, &s->irr[i]);
 895     }
 896     for (i = 0; i < APIC_LVT_NB; i++) {
 897         qemu_get_be32s(f, &s->lvt[i]);
 898     }
 899     qemu_get_be32s(f, &s->esr);
 900     qemu_get_be32s(f, &s->icr[0]);
 901     qemu_get_be32s(f, &s->icr[1]);
 902     qemu_get_be32s(f, &s->divide_conf);
 903     s->count_shift=qemu_get_be32(f);
 904     qemu_get_be32s(f, &s->initial_count);
 905     s->initial_count_load_time=qemu_get_be64(f);
 906     s->next_time=qemu_get_be64(f);
 907
 908     if (version_id >= 2)
 909         qemu_get_timer(f, s->timer);
 910     return 0;
 911 }
 912
 913 static const VMStateDescription vmstate_apic = {
 914     .name = "apic",
 915     .version_id = 3,
 916     .minimum_version_id = 3,
 917     .minimum_version_id_old = 1,
 918     .load_state_old = apic_load_old,
 919     .fields      = (VMStateField []) {
 920         VMSTATE_UINT32(apicbase, APICState),
 921         VMSTATE_UINT8(id, APICState),
 922         VMSTATE_UINT8(arb_id, APICState),
 923         VMSTATE_UINT8(tpr, APICState),
 924         VMSTATE_UINT32(spurious_vec, APICState),
 925         VMSTATE_UINT8(log_dest, APICState),
 926         VMSTATE_UINT8(dest_mode, APICState),
 927         VMSTATE_UINT32_ARRAY(isr, APICState, 8),
 928         VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
 929         VMSTATE_UINT32_ARRAY(irr, APICState, 8),
 930         VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB),
 931         VMSTATE_UINT32(esr, APICState),
 932         VMSTATE_UINT32_ARRAY(icr, APICState, 2),
 933         VMSTATE_UINT32(divide_conf, APICState),
 934         VMSTATE_INT32(count_shift, APICState),
 935         VMSTATE_UINT32(initial_count, APICState),
 936         VMSTATE_INT64(initial_count_load_time, APICState),
 937         VMSTATE_INT64(next_time, APICState),
 938         VMSTATE_TIMER(timer, APICState),
 939         VMSTATE_END_OF_LIST()
 940     }
 941 };
 942
 943 static void apic_reset(DeviceState *d)
 944 {
 945     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 946     int bsp;
 947
 948     bsp = cpu_is_bsp(s->cpu_env);
 949     s->apicbase = 0xfee00000 |
 950         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
 951
 952     apic_init_reset(d);
 953
 954     if (bsp) {
 955         /*
 956          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
 957          * time typically by BIOS, so PIC interrupt can be delivered to the
 958          * processor when local APIC is enabled.
 959          */
 960         s->lvt[APIC_LVT_LINT0] = 0x700;
 961     }
 962 }
 963
 964 static CPUReadMemoryFunc * const apic_mem_read[3] = {
 965     apic_mem_readb,
 966     apic_mem_readw,
 967     apic_mem_readl,
 968 };
 969
 970 static CPUWriteMemoryFunc * const apic_mem_write[3] = {
 971     apic_mem_writeb,
 972     apic_mem_writew,
 973     apic_mem_writel,
 974 };
 975
 976 static int apic_init1(SysBusDevice *dev)
 977 {
 978     APICState *s = FROM_SYSBUS(APICState, dev);
 979     int apic_io_memory;
 980     static int last_apic_idx;
 981
 982     if (last_apic_idx >= MAX_APICS) {
 983         return -1;
 984     }
 985     apic_io_memory = cpu_register_io_memory(apic_mem_read,
 986                                             apic_mem_write, NULL,
 987                                             DEVICE_NATIVE_ENDIAN);
 988     sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory);
 989
 990     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
 991     s->idx = last_apic_idx++;
 992     local_apics[s->idx] = s;
 993     return 0;
 994 }
 995
 996 static SysBusDeviceInfo apic_info = {
 997     .init = apic_init1,
 998     .qdev.name = "apic",
 999     .qdev.size = sizeof(APICState),
1000     .qdev.vmsd = &vmstate_apic,
1001     .qdev.reset = apic_reset,
1002     .qdev.no_user = 1,
1003     .qdev.props = (Property[]) {
1004         DEFINE_PROP_UINT8("id", APICState, id, -1),
1005         DEFINE_PROP_PTR("cpu_env", APICState, cpu_env),
1006         DEFINE_PROP_END_OF_LIST(),
1007     }
1008 };
1009
1010 static void apic_register_devices(void)
1011 {
1012     sysbus_register_withprop(&apic_info);
1013 }
1014
1015 device_init(apic_register_devices)