2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 * o Isochronous transfers
22 * o Allocate bandwidth in frames properly
23 * o Disable timers when nothing needs to be done, or remove timer usage
25 * o Handle unrecoverable errors properly
26 * o BIOS work to boot from USB storage
30 #include "qemu-timer.h"
35 #include "qdev-addr.h"
38 /* Dump packet contents. */
39 //#define DEBUG_PACKET
41 /* This causes frames to occur 1000x slower */
42 //#define OHCI_TIME_WARP 1
45 #define DPRINTF printf
50 /* Number of Downstream Ports on the root hub. */
52 #define OHCI_MAX_PORTS 15
54 static int64_t usb_frame_time
;
55 static int64_t usb_bit_time
;
57 typedef struct OHCIPort
{
73 /* Control partition */
78 /* memory pointer partition */
80 uint32_t ctrl_head
, ctrl_cur
;
81 uint32_t bulk_head
, bulk_cur
;
86 /* Frame counter partition */
91 uint16_t frame_number
;
96 /* Root Hub partition */
97 uint32_t rhdesc_a
, rhdesc_b
;
99 OHCIPort rhport
[OHCI_MAX_PORTS
];
101 /* PXA27x Non-OHCI events */
107 /* SM501 local memory offset */
108 target_phys_addr_t localmem_base
;
110 /* Active packets. */
112 USBPacket usb_packet
;
113 uint8_t usb_buf
[8192];
119 /* Host Controller Communications Area */
126 static void ohci_bus_stop(OHCIState
*ohci
);
127 static void ohci_async_cancel_device(OHCIState
*ohci
, USBDevice
*dev
);
129 /* Bitfields for the first word of an Endpoint Desciptor. */
130 #define OHCI_ED_FA_SHIFT 0
131 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
132 #define OHCI_ED_EN_SHIFT 7
133 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
134 #define OHCI_ED_D_SHIFT 11
135 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
136 #define OHCI_ED_S (1<<13)
137 #define OHCI_ED_K (1<<14)
138 #define OHCI_ED_F (1<<15)
139 #define OHCI_ED_MPS_SHIFT 16
140 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
142 /* Flags in the head field of an Endpoint Desciptor. */
146 /* Bitfields for the first word of a Transfer Desciptor. */
147 #define OHCI_TD_R (1<<18)
148 #define OHCI_TD_DP_SHIFT 19
149 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
150 #define OHCI_TD_DI_SHIFT 21
151 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
152 #define OHCI_TD_T0 (1<<24)
153 #define OHCI_TD_T1 (1<<24)
154 #define OHCI_TD_EC_SHIFT 26
155 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
156 #define OHCI_TD_CC_SHIFT 28
157 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
159 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */
160 /* CC & DI - same as in the General Transfer Desciptor */
161 #define OHCI_TD_SF_SHIFT 0
162 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
163 #define OHCI_TD_FC_SHIFT 24
164 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
166 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
167 #define OHCI_TD_PSW_CC_SHIFT 12
168 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
169 #define OHCI_TD_PSW_SIZE_SHIFT 0
170 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
172 #define OHCI_PAGE_MASK 0xfffff000
173 #define OHCI_OFFSET_MASK 0xfff
175 #define OHCI_DPTR_MASK 0xfffffff0
177 #define OHCI_BM(val, field) \
178 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
180 #define OHCI_SET_BM(val, field, newval) do { \
181 val &= ~OHCI_##field##_MASK; \
182 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
185 /* endpoint descriptor */
193 /* General transfer descriptor */
201 /* Isochronous transfer descriptor */
210 #define USB_HZ 12000000
212 /* OHCI Local stuff */
213 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
214 #define OHCI_CTL_PLE (1<<2)
215 #define OHCI_CTL_IE (1<<3)
216 #define OHCI_CTL_CLE (1<<4)
217 #define OHCI_CTL_BLE (1<<5)
218 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
219 #define OHCI_USB_RESET 0x00
220 #define OHCI_USB_RESUME 0x40
221 #define OHCI_USB_OPERATIONAL 0x80
222 #define OHCI_USB_SUSPEND 0xc0
223 #define OHCI_CTL_IR (1<<8)
224 #define OHCI_CTL_RWC (1<<9)
225 #define OHCI_CTL_RWE (1<<10)
227 #define OHCI_STATUS_HCR (1<<0)
228 #define OHCI_STATUS_CLF (1<<1)
229 #define OHCI_STATUS_BLF (1<<2)
230 #define OHCI_STATUS_OCR (1<<3)
231 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
233 #define OHCI_INTR_SO (1<<0) /* Scheduling overrun */
234 #define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */
235 #define OHCI_INTR_SF (1<<2) /* Start of frame */
236 #define OHCI_INTR_RD (1<<3) /* Resume detect */
237 #define OHCI_INTR_UE (1<<4) /* Unrecoverable error */
238 #define OHCI_INTR_FNO (1<<5) /* Frame number overflow */
239 #define OHCI_INTR_RHSC (1<<6) /* Root hub status change */
240 #define OHCI_INTR_OC (1<<30) /* Ownership change */
241 #define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */
243 #define OHCI_HCCA_SIZE 0x100
244 #define OHCI_HCCA_MASK 0xffffff00
246 #define OHCI_EDPTR_MASK 0xfffffff0
248 #define OHCI_FMI_FI 0x00003fff
249 #define OHCI_FMI_FSMPS 0xffff0000
250 #define OHCI_FMI_FIT 0x80000000
252 #define OHCI_FR_RT (1<<31)
254 #define OHCI_LS_THRESH 0x628
256 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
257 #define OHCI_RHA_PSM (1<<8)
258 #define OHCI_RHA_NPS (1<<9)
259 #define OHCI_RHA_DT (1<<10)
260 #define OHCI_RHA_OCPM (1<<11)
261 #define OHCI_RHA_NOCP (1<<12)
262 #define OHCI_RHA_POTPGT_MASK 0xff000000
264 #define OHCI_RHS_LPS (1<<0)
265 #define OHCI_RHS_OCI (1<<1)
266 #define OHCI_RHS_DRWE (1<<15)
267 #define OHCI_RHS_LPSC (1<<16)
268 #define OHCI_RHS_OCIC (1<<17)
269 #define OHCI_RHS_CRWE (1<<31)
271 #define OHCI_PORT_CCS (1<<0)
272 #define OHCI_PORT_PES (1<<1)
273 #define OHCI_PORT_PSS (1<<2)
274 #define OHCI_PORT_POCI (1<<3)
275 #define OHCI_PORT_PRS (1<<4)
276 #define OHCI_PORT_PPS (1<<8)
277 #define OHCI_PORT_LSDA (1<<9)
278 #define OHCI_PORT_CSC (1<<16)
279 #define OHCI_PORT_PESC (1<<17)
280 #define OHCI_PORT_PSSC (1<<18)
281 #define OHCI_PORT_OCIC (1<<19)
282 #define OHCI_PORT_PRSC (1<<20)
283 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
284 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
286 #define OHCI_TD_DIR_SETUP 0x0
287 #define OHCI_TD_DIR_OUT 0x1
288 #define OHCI_TD_DIR_IN 0x2
289 #define OHCI_TD_DIR_RESERVED 0x3
291 #define OHCI_CC_NOERROR 0x0
292 #define OHCI_CC_CRC 0x1
293 #define OHCI_CC_BITSTUFFING 0x2
294 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
295 #define OHCI_CC_STALL 0x4
296 #define OHCI_CC_DEVICENOTRESPONDING 0x5
297 #define OHCI_CC_PIDCHECKFAILURE 0x6
298 #define OHCI_CC_UNDEXPETEDPID 0x7
299 #define OHCI_CC_DATAOVERRUN 0x8
300 #define OHCI_CC_DATAUNDERRUN 0x9
301 #define OHCI_CC_BUFFEROVERRUN 0xc
302 #define OHCI_CC_BUFFERUNDERRUN 0xd
304 #define OHCI_HRESET_FSBIR (1 << 0)
306 /* Update IRQ levels */
307 static inline void ohci_intr_update(OHCIState
*ohci
)
311 if ((ohci
->intr
& OHCI_INTR_MIE
) &&
312 (ohci
->intr_status
& ohci
->intr
))
315 qemu_set_irq(ohci
->irq
, level
);
318 /* Set an interrupt */
319 static inline void ohci_set_interrupt(OHCIState
*ohci
, uint32_t intr
)
321 ohci
->intr_status
|= intr
;
322 ohci_intr_update(ohci
);
325 /* Attach or detach a device on a root hub port. */
326 static void ohci_attach(USBPort
*port1
)
328 OHCIState
*s
= port1
->opaque
;
329 OHCIPort
*port
= &s
->rhport
[port1
->index
];
331 /* set connect status */
332 port
->ctrl
|= OHCI_PORT_CCS
| OHCI_PORT_CSC
;
335 if (port
->port
.dev
->speed
== USB_SPEED_LOW
) {
336 port
->ctrl
|= OHCI_PORT_LSDA
;
338 port
->ctrl
&= ~OHCI_PORT_LSDA
;
341 /* notify of remote-wakeup */
342 if ((s
->ctl
& OHCI_CTL_HCFS
) == OHCI_USB_SUSPEND
) {
343 ohci_set_interrupt(s
, OHCI_INTR_RD
);
346 DPRINTF("usb-ohci: Attached port %d\n", port1
->index
);
349 static void ohci_detach(USBPort
*port1
)
351 OHCIState
*s
= port1
->opaque
;
352 OHCIPort
*port
= &s
->rhport
[port1
->index
];
353 uint32_t old_state
= port
->ctrl
;
355 ohci_async_cancel_device(s
, port1
->dev
);
357 /* set connect status */
358 if (port
->ctrl
& OHCI_PORT_CCS
) {
359 port
->ctrl
&= ~OHCI_PORT_CCS
;
360 port
->ctrl
|= OHCI_PORT_CSC
;
363 if (port
->ctrl
& OHCI_PORT_PES
) {
364 port
->ctrl
&= ~OHCI_PORT_PES
;
365 port
->ctrl
|= OHCI_PORT_PESC
;
367 DPRINTF("usb-ohci: Detached port %d\n", port1
->index
);
369 if (old_state
!= port
->ctrl
)
370 ohci_set_interrupt(s
, OHCI_INTR_RHSC
);
373 static void ohci_wakeup(USBPort
*port1
)
375 OHCIState
*s
= port1
->opaque
;
376 OHCIPort
*port
= &s
->rhport
[port1
->index
];
378 if (port
->ctrl
& OHCI_PORT_PSS
) {
379 DPRINTF("usb-ohci: port %d: wakeup\n", port1
->index
);
380 port
->ctrl
|= OHCI_PORT_PSSC
;
381 port
->ctrl
&= ~OHCI_PORT_PSS
;
382 intr
= OHCI_INTR_RHSC
;
384 /* Note that the controller can be suspended even if this port is not */
385 if ((s
->ctl
& OHCI_CTL_HCFS
) == OHCI_USB_SUSPEND
) {
386 DPRINTF("usb-ohci: remote-wakeup: SUSPEND->RESUME\n");
387 /* This is the one state transition the controller can do by itself */
388 s
->ctl
&= ~OHCI_CTL_HCFS
;
389 s
->ctl
|= OHCI_USB_RESUME
;
390 /* In suspend mode only ResumeDetected is possible, not RHSC:
391 * see the OHCI spec 5.1.2.3.
395 ohci_set_interrupt(s
, intr
);
398 static void ohci_child_detach(USBPort
*port1
, USBDevice
*child
)
400 OHCIState
*s
= port1
->opaque
;
402 ohci_async_cancel_device(s
, child
);
405 /* Reset the controller */
406 static void ohci_reset(void *opaque
)
408 OHCIState
*ohci
= opaque
;
416 ohci
->intr_status
= 0;
417 ohci
->intr
= OHCI_INTR_MIE
;
420 ohci
->ctrl_head
= ohci
->ctrl_cur
= 0;
421 ohci
->bulk_head
= ohci
->bulk_cur
= 0;
424 ohci
->done_count
= 7;
426 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
427 * I took the value linux sets ...
429 ohci
->fsmps
= 0x2778;
433 ohci
->frame_number
= 0;
435 ohci
->lst
= OHCI_LS_THRESH
;
437 ohci
->rhdesc_a
= OHCI_RHA_NPS
| ohci
->num_ports
;
438 ohci
->rhdesc_b
= 0x0; /* Impl. specific */
441 for (i
= 0; i
< ohci
->num_ports
; i
++)
443 port
= &ohci
->rhport
[i
];
445 if (port
->port
.dev
) {
446 usb_attach(&port
->port
, port
->port
.dev
);
449 if (ohci
->async_td
) {
450 usb_cancel_packet(&ohci
->usb_packet
);
453 DPRINTF("usb-ohci: Reset %s\n", ohci
->name
);
456 /* Get an array of dwords from main memory */
457 static inline int get_dwords(OHCIState
*ohci
,
458 uint32_t addr
, uint32_t *buf
, int num
)
462 addr
+= ohci
->localmem_base
;
464 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
465 cpu_physical_memory_read(addr
, buf
, sizeof(*buf
));
466 *buf
= le32_to_cpu(*buf
);
472 /* Put an array of dwords in to main memory */
473 static inline int put_dwords(OHCIState
*ohci
,
474 uint32_t addr
, uint32_t *buf
, int num
)
478 addr
+= ohci
->localmem_base
;
480 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
481 uint32_t tmp
= cpu_to_le32(*buf
);
482 cpu_physical_memory_write(addr
, &tmp
, sizeof(tmp
));
488 /* Get an array of words from main memory */
489 static inline int get_words(OHCIState
*ohci
,
490 uint32_t addr
, uint16_t *buf
, int num
)
494 addr
+= ohci
->localmem_base
;
496 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
497 cpu_physical_memory_read(addr
, buf
, sizeof(*buf
));
498 *buf
= le16_to_cpu(*buf
);
504 /* Put an array of words in to main memory */
505 static inline int put_words(OHCIState
*ohci
,
506 uint32_t addr
, uint16_t *buf
, int num
)
510 addr
+= ohci
->localmem_base
;
512 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
513 uint16_t tmp
= cpu_to_le16(*buf
);
514 cpu_physical_memory_write(addr
, &tmp
, sizeof(tmp
));
520 static inline int ohci_read_ed(OHCIState
*ohci
,
521 uint32_t addr
, struct ohci_ed
*ed
)
523 return get_dwords(ohci
, addr
, (uint32_t *)ed
, sizeof(*ed
) >> 2);
526 static inline int ohci_read_td(OHCIState
*ohci
,
527 uint32_t addr
, struct ohci_td
*td
)
529 return get_dwords(ohci
, addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
532 static inline int ohci_read_iso_td(OHCIState
*ohci
,
533 uint32_t addr
, struct ohci_iso_td
*td
)
535 return (get_dwords(ohci
, addr
, (uint32_t *)td
, 4) &&
536 get_words(ohci
, addr
+ 16, td
->offset
, 8));
539 static inline int ohci_read_hcca(OHCIState
*ohci
,
540 uint32_t addr
, struct ohci_hcca
*hcca
)
542 cpu_physical_memory_read(addr
+ ohci
->localmem_base
, hcca
, sizeof(*hcca
));
546 static inline int ohci_put_ed(OHCIState
*ohci
,
547 uint32_t addr
, struct ohci_ed
*ed
)
549 return put_dwords(ohci
, addr
, (uint32_t *)ed
, sizeof(*ed
) >> 2);
552 static inline int ohci_put_td(OHCIState
*ohci
,
553 uint32_t addr
, struct ohci_td
*td
)
555 return put_dwords(ohci
, addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
558 static inline int ohci_put_iso_td(OHCIState
*ohci
,
559 uint32_t addr
, struct ohci_iso_td
*td
)
561 return (put_dwords(ohci
, addr
, (uint32_t *)td
, 4) &&
562 put_words(ohci
, addr
+ 16, td
->offset
, 8));
565 static inline int ohci_put_hcca(OHCIState
*ohci
,
566 uint32_t addr
, struct ohci_hcca
*hcca
)
568 cpu_physical_memory_write(addr
+ ohci
->localmem_base
, hcca
, sizeof(*hcca
));
572 /* Read/Write the contents of a TD from/to main memory. */
573 static void ohci_copy_td(OHCIState
*ohci
, struct ohci_td
*td
,
574 uint8_t *buf
, int len
, int write
)
580 n
= 0x1000 - (ptr
& 0xfff);
583 cpu_physical_memory_rw(ptr
+ ohci
->localmem_base
, buf
, n
, write
);
586 ptr
= td
->be
& ~0xfffu
;
588 cpu_physical_memory_rw(ptr
+ ohci
->localmem_base
, buf
, len
- n
, write
);
591 /* Read/Write the contents of an ISO TD from/to main memory. */
592 static void ohci_copy_iso_td(OHCIState
*ohci
,
593 uint32_t start_addr
, uint32_t end_addr
,
594 uint8_t *buf
, int len
, int write
)
600 n
= 0x1000 - (ptr
& 0xfff);
603 cpu_physical_memory_rw(ptr
+ ohci
->localmem_base
, buf
, n
, write
);
606 ptr
= end_addr
& ~0xfffu
;
608 cpu_physical_memory_rw(ptr
+ ohci
->localmem_base
, buf
, len
- n
, write
);
611 static void ohci_process_lists(OHCIState
*ohci
, int completion
);
613 static void ohci_async_complete_packet(USBPort
*port
, USBPacket
*packet
)
615 OHCIState
*ohci
= container_of(packet
, OHCIState
, usb_packet
);
617 DPRINTF("Async packet complete\n");
619 ohci
->async_complete
= 1;
620 ohci_process_lists(ohci
, 1);
623 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
625 static int ohci_service_iso_td(OHCIState
*ohci
, struct ohci_ed
*ed
,
631 const char *str
= NULL
;
637 struct ohci_iso_td iso_td
;
639 uint16_t starting_frame
;
640 int16_t relative_frame_number
;
642 uint32_t start_offset
, next_offset
, end_offset
= 0;
643 uint32_t start_addr
, end_addr
;
645 addr
= ed
->head
& OHCI_DPTR_MASK
;
647 if (!ohci_read_iso_td(ohci
, addr
, &iso_td
)) {
648 printf("usb-ohci: ISO_TD read error at %x\n", addr
);
652 starting_frame
= OHCI_BM(iso_td
.flags
, TD_SF
);
653 frame_count
= OHCI_BM(iso_td
.flags
, TD_FC
);
654 relative_frame_number
= USUB(ohci
->frame_number
, starting_frame
);
657 printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
658 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
659 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
660 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
661 "frame_number 0x%.8x starting_frame 0x%.8x\n"
662 "frame_count 0x%.8x relative %d\n"
663 "di 0x%.8x cc 0x%.8x\n",
664 ed
->head
& OHCI_DPTR_MASK
, ed
->tail
& OHCI_DPTR_MASK
,
665 iso_td
.flags
, iso_td
.bp
, iso_td
.next
, iso_td
.be
,
666 iso_td
.offset
[0], iso_td
.offset
[1], iso_td
.offset
[2], iso_td
.offset
[3],
667 iso_td
.offset
[4], iso_td
.offset
[5], iso_td
.offset
[6], iso_td
.offset
[7],
668 ohci
->frame_number
, starting_frame
,
669 frame_count
, relative_frame_number
,
670 OHCI_BM(iso_td
.flags
, TD_DI
), OHCI_BM(iso_td
.flags
, TD_CC
));
673 if (relative_frame_number
< 0) {
674 DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number
);
676 } else if (relative_frame_number
> frame_count
) {
677 /* ISO TD expired - retire the TD to the Done Queue and continue with
678 the next ISO TD of the same ED */
679 DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number
,
681 OHCI_SET_BM(iso_td
.flags
, TD_CC
, OHCI_CC_DATAOVERRUN
);
682 ed
->head
&= ~OHCI_DPTR_MASK
;
683 ed
->head
|= (iso_td
.next
& OHCI_DPTR_MASK
);
684 iso_td
.next
= ohci
->done
;
686 i
= OHCI_BM(iso_td
.flags
, TD_DI
);
687 if (i
< ohci
->done_count
)
688 ohci
->done_count
= i
;
689 ohci_put_iso_td(ohci
, addr
, &iso_td
);
693 dir
= OHCI_BM(ed
->flags
, ED_D
);
701 case OHCI_TD_DIR_OUT
:
707 case OHCI_TD_DIR_SETUP
:
711 pid
= USB_TOKEN_SETUP
;
714 printf("usb-ohci: Bad direction %d\n", dir
);
718 if (!iso_td
.bp
|| !iso_td
.be
) {
719 printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td
.bp
, iso_td
.be
);
723 start_offset
= iso_td
.offset
[relative_frame_number
];
724 next_offset
= iso_td
.offset
[relative_frame_number
+ 1];
726 if (!(OHCI_BM(start_offset
, TD_PSW_CC
) & 0xe) ||
727 ((relative_frame_number
< frame_count
) &&
728 !(OHCI_BM(next_offset
, TD_PSW_CC
) & 0xe))) {
729 printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
730 start_offset
, next_offset
);
734 if ((relative_frame_number
< frame_count
) && (start_offset
> next_offset
)) {
735 printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
736 start_offset
, next_offset
);
740 if ((start_offset
& 0x1000) == 0) {
741 start_addr
= (iso_td
.bp
& OHCI_PAGE_MASK
) |
742 (start_offset
& OHCI_OFFSET_MASK
);
744 start_addr
= (iso_td
.be
& OHCI_PAGE_MASK
) |
745 (start_offset
& OHCI_OFFSET_MASK
);
748 if (relative_frame_number
< frame_count
) {
749 end_offset
= next_offset
- 1;
750 if ((end_offset
& 0x1000) == 0) {
751 end_addr
= (iso_td
.bp
& OHCI_PAGE_MASK
) |
752 (end_offset
& OHCI_OFFSET_MASK
);
754 end_addr
= (iso_td
.be
& OHCI_PAGE_MASK
) |
755 (end_offset
& OHCI_OFFSET_MASK
);
758 /* Last packet in the ISO TD */
759 end_addr
= iso_td
.be
;
762 if ((start_addr
& OHCI_PAGE_MASK
) != (end_addr
& OHCI_PAGE_MASK
)) {
763 len
= (end_addr
& OHCI_OFFSET_MASK
) + 0x1001
764 - (start_addr
& OHCI_OFFSET_MASK
);
766 len
= end_addr
- start_addr
+ 1;
769 if (len
&& dir
!= OHCI_TD_DIR_IN
) {
770 ohci_copy_iso_td(ohci
, start_addr
, end_addr
, ohci
->usb_buf
, len
, 0);
774 ret
= ohci
->usb_packet
.len
;
777 for (i
= 0; i
< ohci
->num_ports
; i
++) {
778 dev
= ohci
->rhport
[i
].port
.dev
;
779 if ((ohci
->rhport
[i
].ctrl
& OHCI_PORT_PES
) == 0)
781 ohci
->usb_packet
.pid
= pid
;
782 ohci
->usb_packet
.devaddr
= OHCI_BM(ed
->flags
, ED_FA
);
783 ohci
->usb_packet
.devep
= OHCI_BM(ed
->flags
, ED_EN
);
784 ohci
->usb_packet
.data
= ohci
->usb_buf
;
785 ohci
->usb_packet
.len
= len
;
786 ret
= usb_handle_packet(dev
, &ohci
->usb_packet
);
787 if (ret
!= USB_RET_NODEV
)
791 if (ret
== USB_RET_ASYNC
) {
797 printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
798 start_offset
, end_offset
, start_addr
, end_addr
, str
, len
, ret
);
802 if (dir
== OHCI_TD_DIR_IN
&& ret
>= 0 && ret
<= len
) {
803 /* IN transfer succeeded */
804 ohci_copy_iso_td(ohci
, start_addr
, end_addr
, ohci
->usb_buf
, ret
, 1);
805 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
807 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
, ret
);
808 } else if (dir
== OHCI_TD_DIR_OUT
&& ret
== len
) {
809 /* OUT transfer succeeded */
810 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
812 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
, 0);
814 if (ret
> (ssize_t
) len
) {
815 printf("usb-ohci: DataOverrun %d > %zu\n", ret
, len
);
816 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
817 OHCI_CC_DATAOVERRUN
);
818 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
,
820 } else if (ret
>= 0) {
821 printf("usb-ohci: DataUnderrun %d\n", ret
);
822 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
823 OHCI_CC_DATAUNDERRUN
);
827 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
828 OHCI_CC_DEVICENOTRESPONDING
);
829 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
,
834 printf("usb-ohci: got NAK/STALL %d\n", ret
);
835 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
837 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
,
841 printf("usb-ohci: Bad device response %d\n", ret
);
842 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
843 OHCI_CC_UNDEXPETEDPID
);
849 if (relative_frame_number
== frame_count
) {
850 /* Last data packet of ISO TD - retire the TD to the Done Queue */
851 OHCI_SET_BM(iso_td
.flags
, TD_CC
, OHCI_CC_NOERROR
);
852 ed
->head
&= ~OHCI_DPTR_MASK
;
853 ed
->head
|= (iso_td
.next
& OHCI_DPTR_MASK
);
854 iso_td
.next
= ohci
->done
;
856 i
= OHCI_BM(iso_td
.flags
, TD_DI
);
857 if (i
< ohci
->done_count
)
858 ohci
->done_count
= i
;
860 ohci_put_iso_td(ohci
, addr
, &iso_td
);
864 /* Service a transport descriptor.
865 Returns nonzero to terminate processing of this endpoint. */
867 static int ohci_service_td(OHCIState
*ohci
, struct ohci_ed
*ed
)
872 const char *str
= NULL
;
883 addr
= ed
->head
& OHCI_DPTR_MASK
;
884 /* See if this TD has already been submitted to the device. */
885 completion
= (addr
== ohci
->async_td
);
886 if (completion
&& !ohci
->async_complete
) {
888 DPRINTF("Skipping async TD\n");
892 if (!ohci_read_td(ohci
, addr
, &td
)) {
893 fprintf(stderr
, "usb-ohci: TD read error at %x\n", addr
);
897 dir
= OHCI_BM(ed
->flags
, ED_D
);
899 case OHCI_TD_DIR_OUT
:
904 dir
= OHCI_BM(td
.flags
, TD_DP
);
915 case OHCI_TD_DIR_OUT
:
921 case OHCI_TD_DIR_SETUP
:
925 pid
= USB_TOKEN_SETUP
;
928 fprintf(stderr
, "usb-ohci: Bad direction\n");
931 if (td
.cbp
&& td
.be
) {
932 if ((td
.cbp
& 0xfffff000) != (td
.be
& 0xfffff000)) {
933 len
= (td
.be
& 0xfff) + 0x1001 - (td
.cbp
& 0xfff);
935 len
= (td
.be
- td
.cbp
) + 1;
938 if (len
&& dir
!= OHCI_TD_DIR_IN
&& !completion
) {
939 ohci_copy_td(ohci
, &td
, ohci
->usb_buf
, len
, 0);
943 flag_r
= (td
.flags
& OHCI_TD_R
) != 0;
945 DPRINTF(" TD @ 0x%.8x %" PRId64
" bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
946 addr
, (int64_t)len
, str
, flag_r
, td
.cbp
, td
.be
);
948 if (len
> 0 && dir
!= OHCI_TD_DIR_IN
) {
950 for (i
= 0; i
< len
; i
++)
951 printf(" %.2x", ohci
->usb_buf
[i
]);
956 ret
= ohci
->usb_packet
.len
;
958 ohci
->async_complete
= 0;
961 for (i
= 0; i
< ohci
->num_ports
; i
++) {
962 dev
= ohci
->rhport
[i
].port
.dev
;
963 if ((ohci
->rhport
[i
].ctrl
& OHCI_PORT_PES
) == 0)
966 if (ohci
->async_td
) {
967 /* ??? The hardware should allow one active packet per
968 endpoint. We only allow one active packet per controller.
969 This should be sufficient as long as devices respond in a
973 DPRINTF("Too many pending packets\n");
977 ohci
->usb_packet
.pid
= pid
;
978 ohci
->usb_packet
.devaddr
= OHCI_BM(ed
->flags
, ED_FA
);
979 ohci
->usb_packet
.devep
= OHCI_BM(ed
->flags
, ED_EN
);
980 ohci
->usb_packet
.data
= ohci
->usb_buf
;
981 ohci
->usb_packet
.len
= len
;
982 ret
= usb_handle_packet(dev
, &ohci
->usb_packet
);
983 if (ret
!= USB_RET_NODEV
)
987 DPRINTF("ret=%d\n", ret
);
989 if (ret
== USB_RET_ASYNC
) {
990 ohci
->async_td
= addr
;
995 if (dir
== OHCI_TD_DIR_IN
) {
996 ohci_copy_td(ohci
, &td
, ohci
->usb_buf
, ret
, 1);
999 for (i
= 0; i
< ret
; i
++)
1000 printf(" %.2x", ohci
->usb_buf
[i
]);
1009 if (ret
== len
|| (dir
== OHCI_TD_DIR_IN
&& ret
>= 0 && flag_r
)) {
1010 /* Transmission succeeded. */
1015 if ((td
.cbp
& 0xfff) + ret
> 0xfff) {
1017 td
.cbp
|= td
.be
& ~0xfff;
1020 td
.flags
|= OHCI_TD_T1
;
1021 td
.flags
^= OHCI_TD_T0
;
1022 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_NOERROR
);
1023 OHCI_SET_BM(td
.flags
, TD_EC
, 0);
1025 ed
->head
&= ~OHCI_ED_C
;
1026 if (td
.flags
& OHCI_TD_T0
)
1027 ed
->head
|= OHCI_ED_C
;
1030 DPRINTF("usb-ohci: Underrun\n");
1031 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAUNDERRUN
);
1035 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DEVICENOTRESPONDING
);
1037 DPRINTF("usb-ohci: got NAK\n");
1040 DPRINTF("usb-ohci: got STALL\n");
1041 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_STALL
);
1043 case USB_RET_BABBLE
:
1044 DPRINTF("usb-ohci: got BABBLE\n");
1045 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAOVERRUN
);
1048 fprintf(stderr
, "usb-ohci: Bad device response %d\n", ret
);
1049 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_UNDEXPETEDPID
);
1050 OHCI_SET_BM(td
.flags
, TD_EC
, 3);
1054 ed
->head
|= OHCI_ED_H
;
1057 /* Retire this TD */
1058 ed
->head
&= ~OHCI_DPTR_MASK
;
1059 ed
->head
|= td
.next
& OHCI_DPTR_MASK
;
1060 td
.next
= ohci
->done
;
1062 i
= OHCI_BM(td
.flags
, TD_DI
);
1063 if (i
< ohci
->done_count
)
1064 ohci
->done_count
= i
;
1065 ohci_put_td(ohci
, addr
, &td
);
1066 return OHCI_BM(td
.flags
, TD_CC
) != OHCI_CC_NOERROR
;
1069 /* Service an endpoint list. Returns nonzero if active TD were found. */
1070 static int ohci_service_ed_list(OHCIState
*ohci
, uint32_t head
, int completion
)
1082 for (cur
= head
; cur
; cur
= next_ed
) {
1083 if (!ohci_read_ed(ohci
, cur
, &ed
)) {
1084 fprintf(stderr
, "usb-ohci: ED read error at %x\n", cur
);
1088 next_ed
= ed
.next
& OHCI_DPTR_MASK
;
1090 if ((ed
.head
& OHCI_ED_H
) || (ed
.flags
& OHCI_ED_K
)) {
1092 /* Cancel pending packets for ED that have been paused. */
1093 addr
= ed
.head
& OHCI_DPTR_MASK
;
1094 if (ohci
->async_td
&& addr
== ohci
->async_td
) {
1095 usb_cancel_packet(&ohci
->usb_packet
);
1101 while ((ed
.head
& OHCI_DPTR_MASK
) != ed
.tail
) {
1103 DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
1104 "h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur
,
1105 OHCI_BM(ed
.flags
, ED_FA
), OHCI_BM(ed
.flags
, ED_EN
),
1106 OHCI_BM(ed
.flags
, ED_D
), (ed
.flags
& OHCI_ED_S
)!= 0,
1107 (ed
.flags
& OHCI_ED_K
) != 0, (ed
.flags
& OHCI_ED_F
) != 0,
1108 OHCI_BM(ed
.flags
, ED_MPS
), (ed
.head
& OHCI_ED_H
) != 0,
1109 (ed
.head
& OHCI_ED_C
) != 0, ed
.head
& OHCI_DPTR_MASK
,
1110 ed
.tail
& OHCI_DPTR_MASK
, ed
.next
& OHCI_DPTR_MASK
);
1114 if ((ed
.flags
& OHCI_ED_F
) == 0) {
1115 if (ohci_service_td(ohci
, &ed
))
1118 /* Handle isochronous endpoints */
1119 if (ohci_service_iso_td(ohci
, &ed
, completion
))
1124 ohci_put_ed(ohci
, cur
, &ed
);
1130 /* Generate a SOF event, and set a timer for EOF */
1131 static void ohci_sof(OHCIState
*ohci
)
1133 ohci
->sof_time
= qemu_get_clock_ns(vm_clock
);
1134 qemu_mod_timer(ohci
->eof_timer
, ohci
->sof_time
+ usb_frame_time
);
1135 ohci_set_interrupt(ohci
, OHCI_INTR_SF
);
1138 /* Process Control and Bulk lists. */
1139 static void ohci_process_lists(OHCIState
*ohci
, int completion
)
1141 if ((ohci
->ctl
& OHCI_CTL_CLE
) && (ohci
->status
& OHCI_STATUS_CLF
)) {
1142 if (ohci
->ctrl_cur
&& ohci
->ctrl_cur
!= ohci
->ctrl_head
) {
1143 DPRINTF("usb-ohci: head %x, cur %x\n",
1144 ohci
->ctrl_head
, ohci
->ctrl_cur
);
1146 if (!ohci_service_ed_list(ohci
, ohci
->ctrl_head
, completion
)) {
1148 ohci
->status
&= ~OHCI_STATUS_CLF
;
1152 if ((ohci
->ctl
& OHCI_CTL_BLE
) && (ohci
->status
& OHCI_STATUS_BLF
)) {
1153 if (!ohci_service_ed_list(ohci
, ohci
->bulk_head
, completion
)) {
1155 ohci
->status
&= ~OHCI_STATUS_BLF
;
1160 /* Do frame processing on frame boundary */
1161 static void ohci_frame_boundary(void *opaque
)
1163 OHCIState
*ohci
= opaque
;
1164 struct ohci_hcca hcca
;
1166 ohci_read_hcca(ohci
, ohci
->hcca
, &hcca
);
1168 /* Process all the lists at the end of the frame */
1169 if (ohci
->ctl
& OHCI_CTL_PLE
) {
1172 n
= ohci
->frame_number
& 0x1f;
1173 ohci_service_ed_list(ohci
, le32_to_cpu(hcca
.intr
[n
]), 0);
1176 /* Cancel all pending packets if either of the lists has been disabled. */
1177 if (ohci
->async_td
&&
1178 ohci
->old_ctl
& (~ohci
->ctl
) & (OHCI_CTL_BLE
| OHCI_CTL_CLE
)) {
1179 usb_cancel_packet(&ohci
->usb_packet
);
1182 ohci
->old_ctl
= ohci
->ctl
;
1183 ohci_process_lists(ohci
, 0);
1185 /* Frame boundary, so do EOF stuf here */
1186 ohci
->frt
= ohci
->fit
;
1188 /* Increment frame number and take care of endianness. */
1189 ohci
->frame_number
= (ohci
->frame_number
+ 1) & 0xffff;
1190 hcca
.frame
= cpu_to_le16(ohci
->frame_number
);
1192 if (ohci
->done_count
== 0 && !(ohci
->intr_status
& OHCI_INTR_WD
)) {
1195 if (ohci
->intr
& ohci
->intr_status
)
1197 hcca
.done
= cpu_to_le32(ohci
->done
);
1199 ohci
->done_count
= 7;
1200 ohci_set_interrupt(ohci
, OHCI_INTR_WD
);
1203 if (ohci
->done_count
!= 7 && ohci
->done_count
!= 0)
1206 /* Do SOF stuff here */
1209 /* Writeback HCCA */
1210 ohci_put_hcca(ohci
, ohci
->hcca
, &hcca
);
1213 /* Start sending SOF tokens across the USB bus, lists are processed in
1216 static int ohci_bus_start(OHCIState
*ohci
)
1218 ohci
->eof_timer
= qemu_new_timer_ns(vm_clock
,
1219 ohci_frame_boundary
,
1222 if (ohci
->eof_timer
== NULL
) {
1223 fprintf(stderr
, "usb-ohci: %s: qemu_new_timer_ns failed\n", ohci
->name
);
1224 /* TODO: Signal unrecoverable error */
1228 DPRINTF("usb-ohci: %s: USB Operational\n", ohci
->name
);
1235 /* Stop sending SOF tokens on the bus */
1236 static void ohci_bus_stop(OHCIState
*ohci
)
1238 if (ohci
->eof_timer
)
1239 qemu_del_timer(ohci
->eof_timer
);
1240 ohci
->eof_timer
= NULL
;
1243 /* Sets a flag in a port status register but only set it if the port is
1244 * connected, if not set ConnectStatusChange flag. If flag is enabled
1247 static int ohci_port_set_if_connected(OHCIState
*ohci
, int i
, uint32_t val
)
1251 /* writing a 0 has no effect */
1255 /* If CurrentConnectStatus is cleared we set
1256 * ConnectStatusChange
1258 if (!(ohci
->rhport
[i
].ctrl
& OHCI_PORT_CCS
)) {
1259 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_CSC
;
1260 if (ohci
->rhstatus
& OHCI_RHS_DRWE
) {
1261 /* TODO: CSC is a wakeup event */
1266 if (ohci
->rhport
[i
].ctrl
& val
)
1270 ohci
->rhport
[i
].ctrl
|= val
;
1275 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1276 static void ohci_set_frame_interval(OHCIState
*ohci
, uint16_t val
)
1280 if (val
!= ohci
->fi
) {
1281 DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
1282 ohci
->name
, ohci
->fi
, ohci
->fi
);
1288 static void ohci_port_power(OHCIState
*ohci
, int i
, int p
)
1291 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_PPS
;
1293 ohci
->rhport
[i
].ctrl
&= ~(OHCI_PORT_PPS
|
1300 /* Set HcControlRegister */
1301 static void ohci_set_ctl(OHCIState
*ohci
, uint32_t val
)
1306 old_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
1308 new_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
1310 /* no state change */
1311 if (old_state
== new_state
)
1314 switch (new_state
) {
1315 case OHCI_USB_OPERATIONAL
:
1316 ohci_bus_start(ohci
);
1318 case OHCI_USB_SUSPEND
:
1319 ohci_bus_stop(ohci
);
1320 DPRINTF("usb-ohci: %s: USB Suspended\n", ohci
->name
);
1322 case OHCI_USB_RESUME
:
1323 DPRINTF("usb-ohci: %s: USB Resume\n", ohci
->name
);
1325 case OHCI_USB_RESET
:
1327 DPRINTF("usb-ohci: %s: USB Reset\n", ohci
->name
);
1332 static uint32_t ohci_get_frame_remaining(OHCIState
*ohci
)
1337 if ((ohci
->ctl
& OHCI_CTL_HCFS
) != OHCI_USB_OPERATIONAL
)
1338 return (ohci
->frt
<< 31);
1340 /* Being in USB operational state guarnatees sof_time was
1343 tks
= qemu_get_clock_ns(vm_clock
) - ohci
->sof_time
;
1345 /* avoid muldiv if possible */
1346 if (tks
>= usb_frame_time
)
1347 return (ohci
->frt
<< 31);
1349 tks
= muldiv64(1, tks
, usb_bit_time
);
1350 fr
= (uint16_t)(ohci
->fi
- tks
);
1352 return (ohci
->frt
<< 31) | fr
;
1356 /* Set root hub status */
1357 static void ohci_set_hub_status(OHCIState
*ohci
, uint32_t val
)
1361 old_state
= ohci
->rhstatus
;
1363 /* write 1 to clear OCIC */
1364 if (val
& OHCI_RHS_OCIC
)
1365 ohci
->rhstatus
&= ~OHCI_RHS_OCIC
;
1367 if (val
& OHCI_RHS_LPS
) {
1370 for (i
= 0; i
< ohci
->num_ports
; i
++)
1371 ohci_port_power(ohci
, i
, 0);
1372 DPRINTF("usb-ohci: powered down all ports\n");
1375 if (val
& OHCI_RHS_LPSC
) {
1378 for (i
= 0; i
< ohci
->num_ports
; i
++)
1379 ohci_port_power(ohci
, i
, 1);
1380 DPRINTF("usb-ohci: powered up all ports\n");
1383 if (val
& OHCI_RHS_DRWE
)
1384 ohci
->rhstatus
|= OHCI_RHS_DRWE
;
1386 if (val
& OHCI_RHS_CRWE
)
1387 ohci
->rhstatus
&= ~OHCI_RHS_DRWE
;
1389 if (old_state
!= ohci
->rhstatus
)
1390 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
1393 /* Set root hub port status */
1394 static void ohci_port_set_status(OHCIState
*ohci
, int portnum
, uint32_t val
)
1399 port
= &ohci
->rhport
[portnum
];
1400 old_state
= port
->ctrl
;
1402 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1403 if (val
& OHCI_PORT_WTC
)
1404 port
->ctrl
&= ~(val
& OHCI_PORT_WTC
);
1406 if (val
& OHCI_PORT_CCS
)
1407 port
->ctrl
&= ~OHCI_PORT_PES
;
1409 ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PES
);
1411 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PSS
)) {
1412 DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum
);
1415 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PRS
)) {
1416 DPRINTF("usb-ohci: port %d: RESET\n", portnum
);
1417 usb_send_msg(port
->port
.dev
, USB_MSG_RESET
);
1418 port
->ctrl
&= ~OHCI_PORT_PRS
;
1419 /* ??? Should this also set OHCI_PORT_PESC. */
1420 port
->ctrl
|= OHCI_PORT_PES
| OHCI_PORT_PRSC
;
1423 /* Invert order here to ensure in ambiguous case, device is
1426 if (val
& OHCI_PORT_LSDA
)
1427 ohci_port_power(ohci
, portnum
, 0);
1428 if (val
& OHCI_PORT_PPS
)
1429 ohci_port_power(ohci
, portnum
, 1);
1431 if (old_state
!= port
->ctrl
)
1432 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
1437 static uint32_t ohci_mem_read(void *ptr
, target_phys_addr_t addr
)
1439 OHCIState
*ohci
= ptr
;
1444 /* Only aligned reads are allowed on OHCI */
1446 fprintf(stderr
, "usb-ohci: Mis-aligned read\n");
1448 } else if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
1449 /* HcRhPortStatus */
1450 retval
= ohci
->rhport
[(addr
- 0x54) >> 2].ctrl
| OHCI_PORT_PPS
;
1452 switch (addr
>> 2) {
1453 case 0: /* HcRevision */
1457 case 1: /* HcControl */
1461 case 2: /* HcCommandStatus */
1462 retval
= ohci
->status
;
1465 case 3: /* HcInterruptStatus */
1466 retval
= ohci
->intr_status
;
1469 case 4: /* HcInterruptEnable */
1470 case 5: /* HcInterruptDisable */
1471 retval
= ohci
->intr
;
1474 case 6: /* HcHCCA */
1475 retval
= ohci
->hcca
;
1478 case 7: /* HcPeriodCurrentED */
1479 retval
= ohci
->per_cur
;
1482 case 8: /* HcControlHeadED */
1483 retval
= ohci
->ctrl_head
;
1486 case 9: /* HcControlCurrentED */
1487 retval
= ohci
->ctrl_cur
;
1490 case 10: /* HcBulkHeadED */
1491 retval
= ohci
->bulk_head
;
1494 case 11: /* HcBulkCurrentED */
1495 retval
= ohci
->bulk_cur
;
1498 case 12: /* HcDoneHead */
1499 retval
= ohci
->done
;
1502 case 13: /* HcFmInterretval */
1503 retval
= (ohci
->fit
<< 31) | (ohci
->fsmps
<< 16) | (ohci
->fi
);
1506 case 14: /* HcFmRemaining */
1507 retval
= ohci_get_frame_remaining(ohci
);
1510 case 15: /* HcFmNumber */
1511 retval
= ohci
->frame_number
;
1514 case 16: /* HcPeriodicStart */
1515 retval
= ohci
->pstart
;
1518 case 17: /* HcLSThreshold */
1522 case 18: /* HcRhDescriptorA */
1523 retval
= ohci
->rhdesc_a
;
1526 case 19: /* HcRhDescriptorB */
1527 retval
= ohci
->rhdesc_b
;
1530 case 20: /* HcRhStatus */
1531 retval
= ohci
->rhstatus
;
1534 /* PXA27x specific registers */
1535 case 24: /* HcStatus */
1536 retval
= ohci
->hstatus
& ohci
->hmask
;
1539 case 25: /* HcHReset */
1540 retval
= ohci
->hreset
;
1543 case 26: /* HcHInterruptEnable */
1544 retval
= ohci
->hmask
;
1547 case 27: /* HcHInterruptTest */
1548 retval
= ohci
->htest
;
1552 fprintf(stderr
, "ohci_read: Bad offset %x\n", (int)addr
);
1553 retval
= 0xffffffff;
1560 static void ohci_mem_write(void *ptr
, target_phys_addr_t addr
, uint32_t val
)
1562 OHCIState
*ohci
= ptr
;
1566 /* Only aligned reads are allowed on OHCI */
1568 fprintf(stderr
, "usb-ohci: Mis-aligned write\n");
1572 if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
1573 /* HcRhPortStatus */
1574 ohci_port_set_status(ohci
, (addr
- 0x54) >> 2, val
);
1578 switch (addr
>> 2) {
1579 case 1: /* HcControl */
1580 ohci_set_ctl(ohci
, val
);
1583 case 2: /* HcCommandStatus */
1584 /* SOC is read-only */
1585 val
= (val
& ~OHCI_STATUS_SOC
);
1587 /* Bits written as '0' remain unchanged in the register */
1588 ohci
->status
|= val
;
1590 if (ohci
->status
& OHCI_STATUS_HCR
)
1594 case 3: /* HcInterruptStatus */
1595 ohci
->intr_status
&= ~val
;
1596 ohci_intr_update(ohci
);
1599 case 4: /* HcInterruptEnable */
1601 ohci_intr_update(ohci
);
1604 case 5: /* HcInterruptDisable */
1606 ohci_intr_update(ohci
);
1609 case 6: /* HcHCCA */
1610 ohci
->hcca
= val
& OHCI_HCCA_MASK
;
1613 case 7: /* HcPeriodCurrentED */
1614 /* Ignore writes to this read-only register, Linux does them */
1617 case 8: /* HcControlHeadED */
1618 ohci
->ctrl_head
= val
& OHCI_EDPTR_MASK
;
1621 case 9: /* HcControlCurrentED */
1622 ohci
->ctrl_cur
= val
& OHCI_EDPTR_MASK
;
1625 case 10: /* HcBulkHeadED */
1626 ohci
->bulk_head
= val
& OHCI_EDPTR_MASK
;
1629 case 11: /* HcBulkCurrentED */
1630 ohci
->bulk_cur
= val
& OHCI_EDPTR_MASK
;
1633 case 13: /* HcFmInterval */
1634 ohci
->fsmps
= (val
& OHCI_FMI_FSMPS
) >> 16;
1635 ohci
->fit
= (val
& OHCI_FMI_FIT
) >> 31;
1636 ohci_set_frame_interval(ohci
, val
);
1639 case 15: /* HcFmNumber */
1642 case 16: /* HcPeriodicStart */
1643 ohci
->pstart
= val
& 0xffff;
1646 case 17: /* HcLSThreshold */
1647 ohci
->lst
= val
& 0xffff;
1650 case 18: /* HcRhDescriptorA */
1651 ohci
->rhdesc_a
&= ~OHCI_RHA_RW_MASK
;
1652 ohci
->rhdesc_a
|= val
& OHCI_RHA_RW_MASK
;
1655 case 19: /* HcRhDescriptorB */
1658 case 20: /* HcRhStatus */
1659 ohci_set_hub_status(ohci
, val
);
1662 /* PXA27x specific registers */
1663 case 24: /* HcStatus */
1664 ohci
->hstatus
&= ~(val
& ohci
->hmask
);
1666 case 25: /* HcHReset */
1667 ohci
->hreset
= val
& ~OHCI_HRESET_FSBIR
;
1668 if (val
& OHCI_HRESET_FSBIR
)
1672 case 26: /* HcHInterruptEnable */
1676 case 27: /* HcHInterruptTest */
1681 fprintf(stderr
, "ohci_write: Bad offset %x\n", (int)addr
);
1686 static void ohci_async_cancel_device(OHCIState
*ohci
, USBDevice
*dev
)
1688 if (ohci
->async_td
&& ohci
->usb_packet
.owner
== dev
) {
1689 usb_cancel_packet(&ohci
->usb_packet
);
1694 /* Only dword reads are defined on OHCI register space */
1695 static CPUReadMemoryFunc
* const ohci_readfn
[3]={
1701 /* Only dword writes are defined on OHCI register space */
1702 static CPUWriteMemoryFunc
* const ohci_writefn
[3]={
1708 static USBPortOps ohci_port_ops
= {
1709 .attach
= ohci_attach
,
1710 .detach
= ohci_detach
,
1711 .child_detach
= ohci_child_detach
,
1712 .wakeup
= ohci_wakeup
,
1713 .complete
= ohci_async_complete_packet
,
1716 static USBBusOps ohci_bus_ops
= {
1719 static int usb_ohci_init(OHCIState
*ohci
, DeviceState
*dev
,
1720 int num_ports
, uint32_t localmem_base
,
1721 char *masterbus
, uint32_t firstport
)
1725 if (usb_frame_time
== 0) {
1726 #ifdef OHCI_TIME_WARP
1727 usb_frame_time
= get_ticks_per_sec();
1728 usb_bit_time
= muldiv64(1, get_ticks_per_sec(), USB_HZ
/1000);
1730 usb_frame_time
= muldiv64(1, get_ticks_per_sec(), 1000);
1731 if (get_ticks_per_sec() >= USB_HZ
) {
1732 usb_bit_time
= muldiv64(1, get_ticks_per_sec(), USB_HZ
);
1737 DPRINTF("usb-ohci: usb_bit_time=%" PRId64
" usb_frame_time=%" PRId64
"\n",
1738 usb_frame_time
, usb_bit_time
);
1741 ohci
->num_ports
= num_ports
;
1743 USBPort
*ports
[OHCI_MAX_PORTS
];
1744 for(i
= 0; i
< num_ports
; i
++) {
1745 ports
[i
] = &ohci
->rhport
[i
].port
;
1747 if (usb_register_companion(masterbus
, ports
, num_ports
,
1748 firstport
, ohci
, &ohci_port_ops
,
1749 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
) != 0) {
1753 usb_bus_new(&ohci
->bus
, &ohci_bus_ops
, dev
);
1754 for (i
= 0; i
< num_ports
; i
++) {
1755 usb_register_port(&ohci
->bus
, &ohci
->rhport
[i
].port
,
1756 ohci
, i
, &ohci_port_ops
,
1757 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
);
1761 ohci
->mem
= cpu_register_io_memory(ohci_readfn
, ohci_writefn
, ohci
,
1762 DEVICE_LITTLE_ENDIAN
);
1763 ohci
->localmem_base
= localmem_base
;
1765 ohci
->name
= dev
->info
->name
;
1768 qemu_register_reset(ohci_reset
, ohci
);
1781 static int usb_ohci_initfn_pci(struct PCIDevice
*dev
)
1783 OHCIPCIState
*ohci
= DO_UPCAST(OHCIPCIState
, pci_dev
, dev
);
1785 ohci
->pci_dev
.config
[PCI_CLASS_PROG
] = 0x10; /* OHCI */
1786 /* TODO: RST# value should be 0. */
1787 ohci
->pci_dev
.config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin 1 */
1789 if (usb_ohci_init(&ohci
->state
, &dev
->qdev
, ohci
->num_ports
, 0,
1790 ohci
->masterbus
, ohci
->firstport
) != 0) {
1793 ohci
->state
.irq
= ohci
->pci_dev
.irq
[0];
1795 /* TODO: avoid cast below by using dev */
1796 pci_register_bar_simple(&ohci
->pci_dev
, 0, 256, 0, ohci
->state
.mem
);
1800 void usb_ohci_init_pci(struct PCIBus
*bus
, int devfn
)
1802 pci_create_simple(bus
, devfn
, "pci-ohci");
1806 SysBusDevice busdev
;
1809 target_phys_addr_t dma_offset
;
1812 static int ohci_init_pxa(SysBusDevice
*dev
)
1814 OHCISysBusState
*s
= FROM_SYSBUS(OHCISysBusState
, dev
);
1816 /* Cannot fail as we pass NULL for masterbus */
1817 usb_ohci_init(&s
->ohci
, &dev
->qdev
, s
->num_ports
, s
->dma_offset
, NULL
, 0);
1818 sysbus_init_irq(dev
, &s
->ohci
.irq
);
1819 sysbus_init_mmio(dev
, 0x1000, s
->ohci
.mem
);
1824 static PCIDeviceInfo ohci_pci_info
= {
1825 .qdev
.name
= "pci-ohci",
1826 .qdev
.desc
= "Apple USB Controller",
1827 .qdev
.size
= sizeof(OHCIPCIState
),
1828 .init
= usb_ohci_initfn_pci
,
1829 .vendor_id
= PCI_VENDOR_ID_APPLE
,
1830 .device_id
= PCI_DEVICE_ID_APPLE_IPID_USB
,
1831 .class_id
= PCI_CLASS_SERIAL_USB
,
1832 .qdev
.props
= (Property
[]) {
1833 DEFINE_PROP_STRING("masterbus", OHCIPCIState
, masterbus
),
1834 DEFINE_PROP_UINT32("num-ports", OHCIPCIState
, num_ports
, 3),
1835 DEFINE_PROP_UINT32("firstport", OHCIPCIState
, firstport
, 0),
1836 DEFINE_PROP_END_OF_LIST(),
1840 static SysBusDeviceInfo ohci_sysbus_info
= {
1841 .init
= ohci_init_pxa
,
1842 .qdev
.name
= "sysbus-ohci",
1843 .qdev
.desc
= "OHCI USB Controller",
1844 .qdev
.size
= sizeof(OHCISysBusState
),
1845 .qdev
.props
= (Property
[]) {
1846 DEFINE_PROP_UINT32("num-ports", OHCISysBusState
, num_ports
, 3),
1847 DEFINE_PROP_TADDR("dma-offset", OHCISysBusState
, dma_offset
, 3),
1848 DEFINE_PROP_END_OF_LIST(),
1852 static void ohci_register(void)
1854 pci_qdev_register(&ohci_pci_info
);
1855 sysbus_register_withprop(&ohci_sysbus_info
);
1857 device_init(ohci_register
);