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virtio-9p: Add P9_TFLUSH support
[qemu.git] / hw / eepro100.c
bloba74d8348111290f8d3fc1df2df791523425cfd98
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2010 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * non-i386 platforms
28 * Windows networking
29 *
30 * References:
31 *
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
34 *
35 * TODO:
36 * * PHY emulation should be separated from nic emulation.
37 * Most nic emulations could share the same phy code.
38 * * i82550 is untested. It is programmed like the i82559.
39 * * i82562 is untested. It is programmed like the i82559.
40 * * Power management (i82558 and later) is not implemented.
41 * * Wake-on-LAN is not implemented.
42 */
43
44 #include <stdbool.h> /* bool */
45 #include <stddef.h> /* offsetof */
46 #include "hw.h"
47 #include "pci.h"
48 #include "net.h"
49 #include "eeprom93xx.h"
50
51 #define KiB 1024
52
53 /* Debug EEPRO100 card. */
54 #if 0
55 # define DEBUG_EEPRO100
56 #endif
57
58 #ifdef DEBUG_EEPRO100
59 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
60 #else
61 #define logout(fmt, ...) ((void)0)
62 #endif
63
64 /* Set flags to 0 to disable debug output. */
65 #define INT 1 /* interrupt related actions */
66 #define MDI 1 /* mdi related actions */
67 #define OTHER 1
68 #define RXTX 1
69 #define EEPROM 1 /* eeprom related actions */
70
71 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
72
73 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
74
75 #define MAX_ETH_FRAME_SIZE 1514
76
77 /* This driver supports several different devices which are declared here. */
78 #define i82550 0x82550
79 #define i82551 0x82551
80 #define i82557A 0x82557a
81 #define i82557B 0x82557b
82 #define i82557C 0x82557c
83 #define i82558A 0x82558a
84 #define i82558B 0x82558b
85 #define i82559A 0x82559a
86 #define i82559B 0x82559b
87 #define i82559C 0x82559c
88 #define i82559ER 0x82559e
89 #define i82562 0x82562
90 #define i82801 0x82801
91
92 /* Use 64 word EEPROM. TODO: could be a runtime option. */
93 #define EEPROM_SIZE 64
94
95 #define PCI_MEM_SIZE (4 * KiB)
96 #define PCI_IO_SIZE 64
97 #define PCI_FLASH_SIZE (128 * KiB)
98
99 #define BIT(n) (1 << (n))
100 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
101
102 /* The SCB accepts the following controls for the Tx and Rx units: */
103 #define CU_NOP 0x0000 /* No operation. */
104 #define CU_START 0x0010 /* CU start. */
105 #define CU_RESUME 0x0020 /* CU resume. */
106 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
107 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
108 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
109 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
110 #define CU_SRESUME 0x00a0 /* CU static resume. */
111
112 #define RU_NOP 0x0000
113 #define RX_START 0x0001
114 #define RX_RESUME 0x0002
115 #define RU_ABORT 0x0004
116 #define RX_ADDR_LOAD 0x0006
117 #define RX_RESUMENR 0x0007
118 #define INT_MASK 0x0100
119 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
120
121 typedef struct {
122 PCIDeviceInfo pci;
123 uint32_t device;
124 uint16_t device_id;
125 uint8_t revision;
126 uint8_t stats_size;
127 bool has_extended_tcb_support;
128 bool power_management;
129 } E100PCIDeviceInfo;
130
131 /* Offsets to the various registers.
132 All accesses need not be longword aligned. */
133 enum speedo_offsets {
134 SCBStatus = 0, /* Status Word. */
135 SCBAck = 1,
136 SCBCmd = 2, /* Rx/Command Unit command and status. */
137 SCBIntmask = 3,
138 SCBPointer = 4, /* General purpose pointer. */
139 SCBPort = 8, /* Misc. commands and operands. */
140 SCBflash = 12, /* Flash memory control. */
141 SCBeeprom = 14, /* EEPROM control. */
142 SCBCtrlMDI = 16, /* MDI interface control. */
143 SCBEarlyRx = 20, /* Early receive byte count. */
144 SCBFlow = 24, /* Flow Control. */
145 SCBpmdr = 27, /* Power Management Driver. */
146 SCBgctrl = 28, /* General Control. */
147 SCBgstat = 29, /* General Status. */
148 };
149
150 /* A speedo3 transmit buffer descriptor with two buffers... */
151 typedef struct {
152 uint16_t status;
153 uint16_t command;
154 uint32_t link; /* void * */
155 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
156 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
157 uint8_t tx_threshold; /* transmit threshold */
158 uint8_t tbd_count; /* TBD number */
159 #if 0
160 /* This constitutes two "TBD" entries: hdr and data */
161 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
162 int32_t tx_buf_size0; /* Length of Tx hdr. */
163 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
164 int32_t tx_buf_size1; /* Length of Tx data. */
165 #endif
166 } eepro100_tx_t;
167
168 /* Receive frame descriptor. */
169 typedef struct {
170 int16_t status;
171 uint16_t command;
172 uint32_t link; /* struct RxFD * */
173 uint32_t rx_buf_addr; /* void * */
174 uint16_t count;
175 uint16_t size;
176 char packet[MAX_ETH_FRAME_SIZE + 4];
177 } eepro100_rx_t;
178
179 typedef enum {
180 COMMAND_EL = BIT(15),
181 COMMAND_S = BIT(14),
182 COMMAND_I = BIT(13),
183 COMMAND_NC = BIT(4),
184 COMMAND_SF = BIT(3),
185 COMMAND_CMD = BITS(2, 0),
186 } scb_command_bit;
187
188 typedef enum {
189 STATUS_C = BIT(15),
190 STATUS_OK = BIT(13),
191 } scb_status_bit;
192
193 typedef struct {
194 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
195 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
196 tx_multiple_collisions, tx_total_collisions;
197 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
198 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
199 rx_short_frame_errors;
200 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
201 uint16_t xmt_tco_frames, rcv_tco_frames;
202 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
203 uint32_t reserved[4];
204 } eepro100_stats_t;
205
206 typedef enum {
207 cu_idle = 0,
208 cu_suspended = 1,
209 cu_active = 2,
210 cu_lpq_active = 2,
211 cu_hqp_active = 3
212 } cu_state_t;
213
214 typedef enum {
215 ru_idle = 0,
216 ru_suspended = 1,
217 ru_no_resources = 2,
218 ru_ready = 4
219 } ru_state_t;
220
221 typedef struct {
222 PCIDevice dev;
223 uint8_t mult[8]; /* multicast mask array */
224 int mmio_index;
225 NICState *nic;
226 NICConf conf;
227 uint8_t scb_stat; /* SCB stat/ack byte */
228 uint8_t int_stat; /* PCI interrupt status */
229 /* region must not be saved by nic_save. */
230 uint32_t region[3]; /* PCI region addresses */
231 uint16_t mdimem[32];
232 eeprom_t *eeprom;
233 uint32_t device; /* device variant */
234 uint32_t pointer;
235 /* (cu_base + cu_offset) address the next command block in the command block list. */
236 uint32_t cu_base; /* CU base address */
237 uint32_t cu_offset; /* CU address offset */
238 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
239 uint32_t ru_base; /* RU base address */
240 uint32_t ru_offset; /* RU address offset */
241 uint32_t statsaddr; /* pointer to eepro100_stats_t */
242
243 /* Temporary status information (no need to save these values),
244 * used while processing CU commands. */
245 eepro100_tx_t tx; /* transmit buffer descriptor */
246 uint32_t cb_address; /* = cu_base + cu_offset */
247
248 /* Statistical counters. Also used for wake-up packet (i82559). */
249 eepro100_stats_t statistics;
250
251 /* Configuration bytes. */
252 uint8_t configuration[22];
253
254 /* Data in mem is always in the byte order of the controller (le). */
255 uint8_t mem[PCI_MEM_SIZE];
256 /* vmstate for each particular nic */
257 VMStateDescription *vmstate;
258
259 /* Quasi static device properties (no need to save them). */
260 uint16_t stats_size;
261 bool has_extended_tcb_support;
262 } EEPRO100State;
263
264 /* Word indices in EEPROM. */
265 typedef enum {
266 EEPROM_CNFG_MDIX = 0x03,
267 EEPROM_ID = 0x05,
268 EEPROM_PHY_ID = 0x06,
269 EEPROM_VENDOR_ID = 0x0c,
270 EEPROM_CONFIG_ASF = 0x0d,
271 EEPROM_DEVICE_ID = 0x23,
272 EEPROM_SMBUS_ADDR = 0x90,
273 } EEPROMOffset;
274
275 /* Bit values for EEPROM ID word. */
276 typedef enum {
277 EEPROM_ID_MDM = BIT(0), /* Modem */
278 EEPROM_ID_STB = BIT(1), /* Standby Enable */
279 EEPROM_ID_WMR = BIT(2), /* ??? */
280 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
281 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
282 EEPROM_ID_ALT = BIT(7), /* */
283 /* BITS(10, 8) device revision */
284 EEPROM_ID_BD = BIT(11), /* boot disable */
285 EEPROM_ID_ID = BIT(13), /* id bit */
286 /* BITS(15, 14) signature */
287 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
288 } eeprom_id_bit;
289
290 /* Default values for MDI (PHY) registers */
291 static const uint16_t eepro100_mdi_default[] = {
292 /* MDI Registers 0 - 6, 7 */
293 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
294 /* MDI Registers 8 - 15 */
295 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
296 /* MDI Registers 16 - 31 */
297 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
298 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
299 };
300
301 /* Readonly mask for MDI (PHY) registers */
302 static const uint16_t eepro100_mdi_mask[] = {
303 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
304 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
305 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
306 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
307 };
308
309 /* XXX: optimize */
310 static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
311 {
312 val = cpu_to_le32(val);
313 cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
314 }
315
316 #define POLYNOMIAL 0x04c11db6
317
318 /* From FreeBSD */
319 /* XXX: optimize */
320 static unsigned compute_mcast_idx(const uint8_t * ep)
321 {
322 uint32_t crc;
323 int carry, i, j;
324 uint8_t b;
325
326 crc = 0xffffffff;
327 for (i = 0; i < 6; i++) {
328 b = *ep++;
329 for (j = 0; j < 8; j++) {
330 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
331 crc <<= 1;
332 b >>= 1;
333 if (carry) {
334 crc = ((crc ^ POLYNOMIAL) | carry);
335 }
336 }
337 }
338 return (crc & BITS(7, 2)) >> 2;
339 }
340
341 #if defined(DEBUG_EEPRO100)
342 static const char *nic_dump(const uint8_t * buf, unsigned size)
343 {
344 static char dump[3 * 16 + 1];
345 char *p = &dump[0];
346 if (size > 16) {
347 size = 16;
348 }
349 while (size-- > 0) {
350 p += sprintf(p, " %02x", *buf++);
351 }
352 return dump;
353 }
354 #endif /* DEBUG_EEPRO100 */
355
356 enum scb_stat_ack {
357 stat_ack_not_ours = 0x00,
358 stat_ack_sw_gen = 0x04,
359 stat_ack_rnr = 0x10,
360 stat_ack_cu_idle = 0x20,
361 stat_ack_frame_rx = 0x40,
362 stat_ack_cu_cmd_done = 0x80,
363 stat_ack_not_present = 0xFF,
364 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
365 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
366 };
367
368 static void disable_interrupt(EEPRO100State * s)
369 {
370 if (s->int_stat) {
371 TRACE(INT, logout("interrupt disabled\n"));
372 qemu_irq_lower(s->dev.irq[0]);
373 s->int_stat = 0;
374 }
375 }
376
377 static void enable_interrupt(EEPRO100State * s)
378 {
379 if (!s->int_stat) {
380 TRACE(INT, logout("interrupt enabled\n"));
381 qemu_irq_raise(s->dev.irq[0]);
382 s->int_stat = 1;
383 }
384 }
385
386 static void eepro100_acknowledge(EEPRO100State * s)
387 {
388 s->scb_stat &= ~s->mem[SCBAck];
389 s->mem[SCBAck] = s->scb_stat;
390 if (s->scb_stat == 0) {
391 disable_interrupt(s);
392 }
393 }
394
395 static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
396 {
397 uint8_t mask = ~s->mem[SCBIntmask];
398 s->mem[SCBAck] |= status;
399 status = s->scb_stat = s->mem[SCBAck];
400 status &= (mask | 0x0f);
401 #if 0
402 status &= (~s->mem[SCBIntmask] | 0x0xf);
403 #endif
404 if (status && (mask & 0x01)) {
405 /* SCB mask and SCB Bit M do not disable interrupt. */
406 enable_interrupt(s);
407 } else if (s->int_stat) {
408 disable_interrupt(s);
409 }
410 }
411
412 static void eepro100_cx_interrupt(EEPRO100State * s)
413 {
414 /* CU completed action command. */
415 /* Transmit not ok (82557 only, not in emulation). */
416 eepro100_interrupt(s, 0x80);
417 }
418
419 static void eepro100_cna_interrupt(EEPRO100State * s)
420 {
421 /* CU left the active state. */
422 eepro100_interrupt(s, 0x20);
423 }
424
425 static void eepro100_fr_interrupt(EEPRO100State * s)
426 {
427 /* RU received a complete frame. */
428 eepro100_interrupt(s, 0x40);
429 }
430
431 static void eepro100_rnr_interrupt(EEPRO100State * s)
432 {
433 /* RU is not ready. */
434 eepro100_interrupt(s, 0x10);
435 }
436
437 static void eepro100_mdi_interrupt(EEPRO100State * s)
438 {
439 /* MDI completed read or write cycle. */
440 eepro100_interrupt(s, 0x08);
441 }
442
443 static void eepro100_swi_interrupt(EEPRO100State * s)
444 {
445 /* Software has requested an interrupt. */
446 eepro100_interrupt(s, 0x04);
447 }
448
449 #if 0
450 static void eepro100_fcp_interrupt(EEPRO100State * s)
451 {
452 /* Flow control pause interrupt (82558 and later). */
453 eepro100_interrupt(s, 0x01);
454 }
455 #endif
456
457 static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device)
458 {
459 uint32_t device = s->device;
460 uint8_t *pci_conf = s->dev.config;
461
462 TRACE(OTHER, logout("%p\n", s));
463
464 /* PCI Vendor ID */
465 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
466 /* PCI Device ID */
467 pci_config_set_device_id(pci_conf, e100_device->device_id);
468 /* PCI Status */
469 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
470 PCI_STATUS_FAST_BACK);
471 /* PCI Revision ID */
472 pci_config_set_revision(pci_conf, e100_device->revision);
473 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
474 /* PCI Latency Timer */
475 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
476 /* Capability Pointer is set by PCI framework. */
477 /* Interrupt Line */
478 /* Interrupt Pin */
479 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */
480 /* Minimum Grant */
481 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
482 /* Maximum Latency */
483 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
484
485 s->stats_size = e100_device->stats_size;
486 s->has_extended_tcb_support = e100_device->has_extended_tcb_support;
487
488 switch (device) {
489 case i82550:
490 case i82551:
491 case i82557A:
492 case i82557B:
493 case i82557C:
494 case i82558A:
495 case i82558B:
496 case i82559A:
497 case i82559B:
498 case i82559ER:
499 case i82562:
500 case i82801:
501 break;
502 case i82559C:
503 #if EEPROM_SIZE > 0
504 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_INTEL);
505 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040);
506 #endif
507 break;
508 default:
509 logout("Device %X is undefined!\n", device);
510 }
511
512 /* Standard TxCB. */
513 s->configuration[6] |= BIT(4);
514
515 /* Standard statistical counters. */
516 s->configuration[6] |= BIT(5);
517
518 if (s->stats_size == 80) {
519 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
520 if (s->configuration[6] & BIT(2)) {
521 /* TCO statistical counters. */
522 assert(s->configuration[6] & BIT(5));
523 } else {
524 if (s->configuration[6] & BIT(5)) {
525 /* No extended statistical counters, i82557 compatible. */
526 s->stats_size = 64;
527 } else {
528 /* i82558 compatible. */
529 s->stats_size = 76;
530 }
531 }
532 } else {
533 if (s->configuration[6] & BIT(5)) {
534 /* No extended statistical counters. */
535 s->stats_size = 64;
536 }
537 }
538 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
539
540 if (e100_device->power_management) {
541 /* Power Management Capabilities */
542 int cfg_offset = 0xdc;
543 int r = pci_add_capability_at_offset(&s->dev, PCI_CAP_ID_PM,
544 cfg_offset, PCI_PM_SIZEOF);
545 assert(r >= 0);
546 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
547 #if 0 /* TODO: replace dummy code for power management emulation. */
548 /* TODO: Power Management Control / Status. */
549 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
550 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
551 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
552 #endif
553 }
554
555 #if EEPROM_SIZE > 0
556 if (device == i82557C || device == i82558B || device == i82559C) {
557 /*
558 TODO: get vendor id from EEPROM for i82557C or later.
559 TODO: get device id from EEPROM for i82557C or later.
560 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
561 TODO: header type is determined by EEPROM for i82559.
562 TODO: get subsystem id from EEPROM for i82557C or later.
563 TODO: get subsystem vendor id from EEPROM for i82557C or later.
564 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
565 TODO: capability pointer depends on EEPROM for i82558.
566 */
567 logout("Get device id and revision from EEPROM!!!\n");
568 }
569 #endif /* EEPROM_SIZE > 0 */
570 }
571
572 static void nic_selective_reset(EEPRO100State * s)
573 {
574 size_t i;
575 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
576 #if 0
577 eeprom93xx_reset(s->eeprom);
578 #endif
579 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
580 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
581 if (s->device == i82557B || s->device == i82557C)
582 eeprom_contents[5] = 0x0100;
583 eeprom_contents[EEPROM_PHY_ID] = 1;
584 uint16_t sum = 0;
585 for (i = 0; i < EEPROM_SIZE - 1; i++) {
586 sum += eeprom_contents[i];
587 }
588 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
589 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
590
591 memset(s->mem, 0, sizeof(s->mem));
592 uint32_t val = BIT(21);
593 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
594
595 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
596 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
597 }
598
599 static void nic_reset(void *opaque)
600 {
601 EEPRO100State *s = opaque;
602 TRACE(OTHER, logout("%p\n", s));
603 /* TODO: Clearing of multicast table for selective reset, too? */
604 memset(&s->mult[0], 0, sizeof(s->mult));
605 nic_selective_reset(s);
606 }
607
608 #if defined(DEBUG_EEPRO100)
609 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
610 "Command/Status",
611 "General Pointer",
612 "Port",
613 "EEPROM/Flash Control",
614 "MDI Control",
615 "Receive DMA Byte Count",
616 "Flow Control",
617 "General Status/Control"
618 };
619
620 static char *regname(uint32_t addr)
621 {
622 static char buf[32];
623 if (addr < PCI_IO_SIZE) {
624 const char *r = e100_reg[addr / 4];
625 if (r != 0) {
626 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
627 } else {
628 snprintf(buf, sizeof(buf), "0x%02x", addr);
629 }
630 } else {
631 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
632 }
633 return buf;
634 }
635 #endif /* DEBUG_EEPRO100 */
636
637 /*****************************************************************************
638 *
639 * Command emulation.
640 *
641 ****************************************************************************/
642
643 #if 0
644 static uint16_t eepro100_read_command(EEPRO100State * s)
645 {
646 uint16_t val = 0xffff;
647 TRACE(OTHER, logout("val=0x%04x\n", val));
648 return val;
649 }
650 #endif
651
652 /* Commands that can be put in a command list entry. */
653 enum commands {
654 CmdNOp = 0,
655 CmdIASetup = 1,
656 CmdConfigure = 2,
657 CmdMulticastList = 3,
658 CmdTx = 4,
659 CmdTDR = 5, /* load microcode */
660 CmdDump = 6,
661 CmdDiagnose = 7,
662
663 /* And some extra flags: */
664 CmdSuspend = 0x4000, /* Suspend after completion. */
665 CmdIntr = 0x2000, /* Interrupt after completion. */
666 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
667 };
668
669 static cu_state_t get_cu_state(EEPRO100State * s)
670 {
671 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
672 }
673
674 static void set_cu_state(EEPRO100State * s, cu_state_t state)
675 {
676 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
677 }
678
679 static ru_state_t get_ru_state(EEPRO100State * s)
680 {
681 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
682 }
683
684 static void set_ru_state(EEPRO100State * s, ru_state_t state)
685 {
686 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
687 }
688
689 static void dump_statistics(EEPRO100State * s)
690 {
691 /* Dump statistical data. Most data is never changed by the emulation
692 * and always 0, so we first just copy the whole block and then those
693 * values which really matter.
694 * Number of data should check configuration!!!
695 */
696 cpu_physical_memory_write(s->statsaddr,
697 (uint8_t *) & s->statistics, s->stats_size);
698 stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
699 stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
700 stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
701 stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
702 #if 0
703 stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
704 stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
705 missing("CU dump statistical counters");
706 #endif
707 }
708
709 static void read_cb(EEPRO100State *s)
710 {
711 cpu_physical_memory_read(s->cb_address, (uint8_t *) &s->tx, sizeof(s->tx));
712 s->tx.status = le16_to_cpu(s->tx.status);
713 s->tx.command = le16_to_cpu(s->tx.command);
714 s->tx.link = le32_to_cpu(s->tx.link);
715 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
716 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
717 }
718
719 static void tx_command(EEPRO100State *s)
720 {
721 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
722 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
723 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
724 uint8_t buf[2600];
725 uint16_t size = 0;
726 uint32_t tbd_address = s->cb_address + 0x10;
727 TRACE(RXTX, logout
728 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
729 tbd_array, tcb_bytes, s->tx.tbd_count));
730
731 if (tcb_bytes > 2600) {
732 logout("TCB byte count too large, using 2600\n");
733 tcb_bytes = 2600;
734 }
735 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
736 logout
737 ("illegal values of TBD array address and TCB byte count!\n");
738 }
739 assert(tcb_bytes <= sizeof(buf));
740 while (size < tcb_bytes) {
741 uint32_t tx_buffer_address = ldl_phys(tbd_address);
742 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
743 #if 0
744 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
745 #endif
746 tbd_address += 8;
747 TRACE(RXTX, logout
748 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
749 tx_buffer_address, tx_buffer_size));
750 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
751 cpu_physical_memory_read(tx_buffer_address, &buf[size],
752 tx_buffer_size);
753 size += tx_buffer_size;
754 }
755 if (tbd_array == 0xffffffff) {
756 /* Simplified mode. Was already handled by code above. */
757 } else {
758 /* Flexible mode. */
759 uint8_t tbd_count = 0;
760 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
761 /* Extended Flexible TCB. */
762 for (; tbd_count < 2; tbd_count++) {
763 uint32_t tx_buffer_address = ldl_phys(tbd_address);
764 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
765 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
766 tbd_address += 8;
767 TRACE(RXTX, logout
768 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
769 tx_buffer_address, tx_buffer_size));
770 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
771 cpu_physical_memory_read(tx_buffer_address, &buf[size],
772 tx_buffer_size);
773 size += tx_buffer_size;
774 if (tx_buffer_el & 1) {
775 break;
776 }
777 }
778 }
779 tbd_address = tbd_array;
780 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
781 uint32_t tx_buffer_address = ldl_phys(tbd_address);
782 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
783 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
784 tbd_address += 8;
785 TRACE(RXTX, logout
786 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
787 tx_buffer_address, tx_buffer_size));
788 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
789 cpu_physical_memory_read(tx_buffer_address, &buf[size],
790 tx_buffer_size);
791 size += tx_buffer_size;
792 if (tx_buffer_el & 1) {
793 break;
794 }
795 }
796 }
797 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
798 qemu_send_packet(&s->nic->nc, buf, size);
799 s->statistics.tx_good_frames++;
800 /* Transmit with bad status would raise an CX/TNO interrupt.
801 * (82557 only). Emulation never has bad status. */
802 #if 0
803 eepro100_cx_interrupt(s);
804 #endif
805 }
806
807 static void set_multicast_list(EEPRO100State *s)
808 {
809 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
810 uint16_t i;
811 memset(&s->mult[0], 0, sizeof(s->mult));
812 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
813 for (i = 0; i < multicast_count; i += 6) {
814 uint8_t multicast_addr[6];
815 cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
816 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
817 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
818 assert(mcast_idx < 64);
819 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
820 }
821 }
822
823 static void action_command(EEPRO100State *s)
824 {
825 for (;;) {
826 bool bit_el;
827 bool bit_s;
828 bool bit_i;
829 bool bit_nc;
830 uint16_t ok_status = STATUS_OK;
831 s->cb_address = s->cu_base + s->cu_offset;
832 read_cb(s);
833 bit_el = ((s->tx.command & COMMAND_EL) != 0);
834 bit_s = ((s->tx.command & COMMAND_S) != 0);
835 bit_i = ((s->tx.command & COMMAND_I) != 0);
836 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
837 #if 0
838 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
839 #endif
840 s->cu_offset = s->tx.link;
841 TRACE(OTHER,
842 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
843 s->tx.status, s->tx.command, s->tx.link));
844 switch (s->tx.command & COMMAND_CMD) {
845 case CmdNOp:
846 /* Do nothing. */
847 break;
848 case CmdIASetup:
849 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
850 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
851 break;
852 case CmdConfigure:
853 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
854 sizeof(s->configuration));
855 TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
856 break;
857 case CmdMulticastList:
858 set_multicast_list(s);
859 break;
860 case CmdTx:
861 if (bit_nc) {
862 missing("CmdTx: NC = 0");
863 ok_status = 0;
864 break;
865 }
866 tx_command(s);
867 break;
868 case CmdTDR:
869 TRACE(OTHER, logout("load microcode\n"));
870 /* Starting with offset 8, the command contains
871 * 64 dwords microcode which we just ignore here. */
872 break;
873 case CmdDiagnose:
874 TRACE(OTHER, logout("diagnose\n"));
875 /* Make sure error flag is not set. */
876 s->tx.status = 0;
877 break;
878 default:
879 missing("undefined command");
880 ok_status = 0;
881 break;
882 }
883 /* Write new status. */
884 stw_phys(s->cb_address, s->tx.status | ok_status | STATUS_C);
885 if (bit_i) {
886 /* CU completed action. */
887 eepro100_cx_interrupt(s);
888 }
889 if (bit_el) {
890 /* CU becomes idle. Terminate command loop. */
891 set_cu_state(s, cu_idle);
892 eepro100_cna_interrupt(s);
893 break;
894 } else if (bit_s) {
895 /* CU becomes suspended. Terminate command loop. */
896 set_cu_state(s, cu_suspended);
897 eepro100_cna_interrupt(s);
898 break;
899 } else {
900 /* More entries in list. */
901 TRACE(OTHER, logout("CU list with at least one more entry\n"));
902 }
903 }
904 TRACE(OTHER, logout("CU list empty\n"));
905 /* List is empty. Now CU is idle or suspended. */
906 }
907
908 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
909 {
910 cu_state_t cu_state;
911 switch (val) {
912 case CU_NOP:
913 /* No operation. */
914 break;
915 case CU_START:
916 cu_state = get_cu_state(s);
917 if (cu_state != cu_idle && cu_state != cu_suspended) {
918 /* Intel documentation says that CU must be idle or suspended
919 * for the CU start command. */
920 logout("unexpected CU state is %u\n", cu_state);
921 }
922 set_cu_state(s, cu_active);
923 s->cu_offset = s->pointer;
924 action_command(s);
925 break;
926 case CU_RESUME:
927 if (get_cu_state(s) != cu_suspended) {
928 logout("bad CU resume from CU state %u\n", get_cu_state(s));
929 /* Workaround for bad Linux eepro100 driver which resumes
930 * from idle state. */
931 #if 0
932 missing("cu resume");
933 #endif
934 set_cu_state(s, cu_suspended);
935 }
936 if (get_cu_state(s) == cu_suspended) {
937 TRACE(OTHER, logout("CU resuming\n"));
938 set_cu_state(s, cu_active);
939 action_command(s);
940 }
941 break;
942 case CU_STATSADDR:
943 /* Load dump counters address. */
944 s->statsaddr = s->pointer;
945 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
946 break;
947 case CU_SHOWSTATS:
948 /* Dump statistical counters. */
949 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
950 dump_statistics(s);
951 stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
952 break;
953 case CU_CMD_BASE:
954 /* Load CU base. */
955 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
956 s->cu_base = s->pointer;
957 break;
958 case CU_DUMPSTATS:
959 /* Dump and reset statistical counters. */
960 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
961 dump_statistics(s);
962 stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
963 memset(&s->statistics, 0, sizeof(s->statistics));
964 break;
965 case CU_SRESUME:
966 /* CU static resume. */
967 missing("CU static resume");
968 break;
969 default:
970 missing("Undefined CU command");
971 }
972 }
973
974 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
975 {
976 switch (val) {
977 case RU_NOP:
978 /* No operation. */
979 break;
980 case RX_START:
981 /* RU start. */
982 if (get_ru_state(s) != ru_idle) {
983 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
984 #if 0
985 assert(!"wrong RU state");
986 #endif
987 }
988 set_ru_state(s, ru_ready);
989 s->ru_offset = s->pointer;
990 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
991 break;
992 case RX_RESUME:
993 /* Restart RU. */
994 if (get_ru_state(s) != ru_suspended) {
995 logout("RU state is %u, should be %u\n", get_ru_state(s),
996 ru_suspended);
997 #if 0
998 assert(!"wrong RU state");
999 #endif
1000 }
1001 set_ru_state(s, ru_ready);
1002 break;
1003 case RU_ABORT:
1004 /* RU abort. */
1005 if (get_ru_state(s) == ru_ready) {
1006 eepro100_rnr_interrupt(s);
1007 }
1008 set_ru_state(s, ru_idle);
1009 break;
1010 case RX_ADDR_LOAD:
1011 /* Load RU base. */
1012 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1013 s->ru_base = s->pointer;
1014 break;
1015 default:
1016 logout("val=0x%02x (undefined RU command)\n", val);
1017 missing("Undefined SU command");
1018 }
1019 }
1020
1021 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1022 {
1023 eepro100_ru_command(s, val & 0x0f);
1024 eepro100_cu_command(s, val & 0xf0);
1025 if ((val) == 0) {
1026 TRACE(OTHER, logout("val=0x%02x\n", val));
1027 }
1028 /* Clear command byte after command was accepted. */
1029 s->mem[SCBCmd] = 0;
1030 }
1031
1032 /*****************************************************************************
1033 *
1034 * EEPROM emulation.
1035 *
1036 ****************************************************************************/
1037
1038 #define EEPROM_CS 0x02
1039 #define EEPROM_SK 0x01
1040 #define EEPROM_DI 0x04
1041 #define EEPROM_DO 0x08
1042
1043 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1044 {
1045 uint16_t val;
1046 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1047 if (eeprom93xx_read(s->eeprom)) {
1048 val |= EEPROM_DO;
1049 } else {
1050 val &= ~EEPROM_DO;
1051 }
1052 TRACE(EEPROM, logout("val=0x%04x\n", val));
1053 return val;
1054 }
1055
1056 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1057 {
1058 TRACE(EEPROM, logout("val=0x%02x\n", val));
1059
1060 /* mask unwriteable bits */
1061 #if 0
1062 val = SET_MASKED(val, 0x31, eeprom->value);
1063 #endif
1064
1065 int eecs = ((val & EEPROM_CS) != 0);
1066 int eesk = ((val & EEPROM_SK) != 0);
1067 int eedi = ((val & EEPROM_DI) != 0);
1068 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1069 }
1070
1071 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1072 {
1073 s->pointer = le32_to_cpu(val);
1074 TRACE(OTHER, logout("val=0x%08x\n", val));
1075 }
1076
1077 /*****************************************************************************
1078 *
1079 * MDI emulation.
1080 *
1081 ****************************************************************************/
1082
1083 #if defined(DEBUG_EEPRO100)
1084 static const char * const mdi_op_name[] = {
1085 "opcode 0",
1086 "write",
1087 "read",
1088 "opcode 3"
1089 };
1090
1091 static const char * const mdi_reg_name[] = {
1092 "Control",
1093 "Status",
1094 "PHY Identification (Word 1)",
1095 "PHY Identification (Word 2)",
1096 "Auto-Negotiation Advertisement",
1097 "Auto-Negotiation Link Partner Ability",
1098 "Auto-Negotiation Expansion"
1099 };
1100
1101 static const char *reg2name(uint8_t reg)
1102 {
1103 static char buffer[10];
1104 const char *p = buffer;
1105 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1106 p = mdi_reg_name[reg];
1107 } else {
1108 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1109 }
1110 return p;
1111 }
1112 #endif /* DEBUG_EEPRO100 */
1113
1114 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1115 {
1116 uint32_t val;
1117 memcpy(&val, &s->mem[0x10], sizeof(val));
1118
1119 #ifdef DEBUG_EEPRO100
1120 uint8_t raiseint = (val & BIT(29)) >> 29;
1121 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1122 uint8_t phy = (val & BITS(25, 21)) >> 21;
1123 uint8_t reg = (val & BITS(20, 16)) >> 16;
1124 uint16_t data = (val & BITS(15, 0));
1125 #endif
1126 /* Emulation takes no time to finish MDI transaction. */
1127 val |= BIT(28);
1128 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1129 val, raiseint, mdi_op_name[opcode], phy,
1130 reg2name(reg), data));
1131 return val;
1132 }
1133
1134 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1135 {
1136 uint8_t raiseint = (val & BIT(29)) >> 29;
1137 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1138 uint8_t phy = (val & BITS(25, 21)) >> 21;
1139 uint8_t reg = (val & BITS(20, 16)) >> 16;
1140 uint16_t data = (val & BITS(15, 0));
1141 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1142 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1143 if (phy != 1) {
1144 /* Unsupported PHY address. */
1145 #if 0
1146 logout("phy must be 1 but is %u\n", phy);
1147 #endif
1148 data = 0;
1149 } else if (opcode != 1 && opcode != 2) {
1150 /* Unsupported opcode. */
1151 logout("opcode must be 1 or 2 but is %u\n", opcode);
1152 data = 0;
1153 } else if (reg > 6) {
1154 /* Unsupported register. */
1155 logout("register must be 0...6 but is %u\n", reg);
1156 data = 0;
1157 } else {
1158 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1159 val, raiseint, mdi_op_name[opcode], phy,
1160 reg2name(reg), data));
1161 if (opcode == 1) {
1162 /* MDI write */
1163 switch (reg) {
1164 case 0: /* Control Register */
1165 if (data & 0x8000) {
1166 /* Reset status and control registers to default. */
1167 s->mdimem[0] = eepro100_mdi_default[0];
1168 s->mdimem[1] = eepro100_mdi_default[1];
1169 data = s->mdimem[reg];
1170 } else {
1171 /* Restart Auto Configuration = Normal Operation */
1172 data &= ~0x0200;
1173 }
1174 break;
1175 case 1: /* Status Register */
1176 missing("not writable");
1177 data = s->mdimem[reg];
1178 break;
1179 case 2: /* PHY Identification Register (Word 1) */
1180 case 3: /* PHY Identification Register (Word 2) */
1181 missing("not implemented");
1182 break;
1183 case 4: /* Auto-Negotiation Advertisement Register */
1184 case 5: /* Auto-Negotiation Link Partner Ability Register */
1185 break;
1186 case 6: /* Auto-Negotiation Expansion Register */
1187 default:
1188 missing("not implemented");
1189 }
1190 s->mdimem[reg] = data;
1191 } else if (opcode == 2) {
1192 /* MDI read */
1193 switch (reg) {
1194 case 0: /* Control Register */
1195 if (data & 0x8000) {
1196 /* Reset status and control registers to default. */
1197 s->mdimem[0] = eepro100_mdi_default[0];
1198 s->mdimem[1] = eepro100_mdi_default[1];
1199 }
1200 break;
1201 case 1: /* Status Register */
1202 s->mdimem[reg] |= 0x0020;
1203 break;
1204 case 2: /* PHY Identification Register (Word 1) */
1205 case 3: /* PHY Identification Register (Word 2) */
1206 case 4: /* Auto-Negotiation Advertisement Register */
1207 break;
1208 case 5: /* Auto-Negotiation Link Partner Ability Register */
1209 s->mdimem[reg] = 0x41fe;
1210 break;
1211 case 6: /* Auto-Negotiation Expansion Register */
1212 s->mdimem[reg] = 0x0001;
1213 break;
1214 }
1215 data = s->mdimem[reg];
1216 }
1217 /* Emulation takes no time to finish MDI transaction.
1218 * Set MDI bit in SCB status register. */
1219 s->mem[SCBAck] |= 0x08;
1220 val |= BIT(28);
1221 if (raiseint) {
1222 eepro100_mdi_interrupt(s);
1223 }
1224 }
1225 val = (val & 0xffff0000) + data;
1226 memcpy(&s->mem[0x10], &val, sizeof(val));
1227 }
1228
1229 /*****************************************************************************
1230 *
1231 * Port emulation.
1232 *
1233 ****************************************************************************/
1234
1235 #define PORT_SOFTWARE_RESET 0
1236 #define PORT_SELFTEST 1
1237 #define PORT_SELECTIVE_RESET 2
1238 #define PORT_DUMP 3
1239 #define PORT_SELECTION_MASK 3
1240
1241 typedef struct {
1242 uint32_t st_sign; /* Self Test Signature */
1243 uint32_t st_result; /* Self Test Results */
1244 } eepro100_selftest_t;
1245
1246 static uint32_t eepro100_read_port(EEPRO100State * s)
1247 {
1248 return 0;
1249 }
1250
1251 static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1252 {
1253 val = le32_to_cpu(val);
1254 uint32_t address = (val & ~PORT_SELECTION_MASK);
1255 uint8_t selection = (val & PORT_SELECTION_MASK);
1256 switch (selection) {
1257 case PORT_SOFTWARE_RESET:
1258 nic_reset(s);
1259 break;
1260 case PORT_SELFTEST:
1261 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1262 eepro100_selftest_t data;
1263 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1264 data.st_sign = 0xffffffff;
1265 data.st_result = 0;
1266 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1267 break;
1268 case PORT_SELECTIVE_RESET:
1269 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1270 nic_selective_reset(s);
1271 break;
1272 default:
1273 logout("val=0x%08x\n", val);
1274 missing("unknown port selection");
1275 }
1276 }
1277
1278 /*****************************************************************************
1279 *
1280 * General hardware emulation.
1281 *
1282 ****************************************************************************/
1283
1284 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1285 {
1286 uint8_t val;
1287 if (addr <= sizeof(s->mem) - sizeof(val)) {
1288 memcpy(&val, &s->mem[addr], sizeof(val));
1289 }
1290
1291 switch (addr) {
1292 case SCBStatus:
1293 case SCBAck:
1294 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1295 break;
1296 case SCBCmd:
1297 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1298 #if 0
1299 val = eepro100_read_command(s);
1300 #endif
1301 break;
1302 case SCBIntmask:
1303 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1304 break;
1305 case SCBPort + 3:
1306 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1307 break;
1308 case SCBeeprom:
1309 val = eepro100_read_eeprom(s);
1310 break;
1311 case SCBpmdr: /* Power Management Driver Register */
1312 val = 0;
1313 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1314 break;
1315 case SCBgstat: /* General Status Register */
1316 /* 100 Mbps full duplex, valid link */
1317 val = 0x07;
1318 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1319 break;
1320 default:
1321 logout("addr=%s val=0x%02x\n", regname(addr), val);
1322 missing("unknown byte read");
1323 }
1324 return val;
1325 }
1326
1327 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1328 {
1329 uint16_t val;
1330 if (addr <= sizeof(s->mem) - sizeof(val)) {
1331 memcpy(&val, &s->mem[addr], sizeof(val));
1332 }
1333
1334 switch (addr) {
1335 case SCBStatus:
1336 case SCBCmd:
1337 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1338 break;
1339 case SCBeeprom:
1340 val = eepro100_read_eeprom(s);
1341 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1342 break;
1343 default:
1344 logout("addr=%s val=0x%04x\n", regname(addr), val);
1345 missing("unknown word read");
1346 }
1347 return val;
1348 }
1349
1350 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1351 {
1352 uint32_t val;
1353 if (addr <= sizeof(s->mem) - sizeof(val)) {
1354 memcpy(&val, &s->mem[addr], sizeof(val));
1355 }
1356
1357 switch (addr) {
1358 case SCBStatus:
1359 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1360 break;
1361 case SCBPointer:
1362 #if 0
1363 val = eepro100_read_pointer(s);
1364 #endif
1365 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1366 break;
1367 case SCBPort:
1368 val = eepro100_read_port(s);
1369 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1370 break;
1371 case SCBCtrlMDI:
1372 val = eepro100_read_mdi(s);
1373 break;
1374 default:
1375 logout("addr=%s val=0x%08x\n", regname(addr), val);
1376 missing("unknown longword read");
1377 }
1378 return val;
1379 }
1380
1381 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1382 {
1383 /* SCBStatus is readonly. */
1384 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1385 memcpy(&s->mem[addr], &val, sizeof(val));
1386 }
1387
1388 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1389
1390 switch (addr) {
1391 case SCBStatus:
1392 break;
1393 case SCBAck:
1394 eepro100_acknowledge(s);
1395 break;
1396 case SCBCmd:
1397 eepro100_write_command(s, val);
1398 break;
1399 case SCBIntmask:
1400 if (val & BIT(1)) {
1401 eepro100_swi_interrupt(s);
1402 }
1403 eepro100_interrupt(s, 0);
1404 break;
1405 case SCBPort + 3:
1406 case SCBFlow: /* does not exist on 82557 */
1407 case SCBFlow + 1:
1408 case SCBFlow + 2:
1409 case SCBpmdr: /* does not exist on 82557 */
1410 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1411 break;
1412 case SCBeeprom:
1413 eepro100_write_eeprom(s->eeprom, val);
1414 break;
1415 default:
1416 logout("addr=%s val=0x%02x\n", regname(addr), val);
1417 missing("unknown byte write");
1418 }
1419 }
1420
1421 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1422 {
1423 /* SCBStatus is readonly. */
1424 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1425 memcpy(&s->mem[addr], &val, sizeof(val));
1426 }
1427
1428 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1429
1430 switch (addr) {
1431 case SCBStatus:
1432 s->mem[SCBAck] = (val >> 8);
1433 eepro100_acknowledge(s);
1434 break;
1435 case SCBCmd:
1436 eepro100_write_command(s, val);
1437 eepro100_write1(s, SCBIntmask, val >> 8);
1438 break;
1439 case SCBeeprom:
1440 eepro100_write_eeprom(s->eeprom, val);
1441 break;
1442 default:
1443 logout("addr=%s val=0x%04x\n", regname(addr), val);
1444 missing("unknown word write");
1445 }
1446 }
1447
1448 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1449 {
1450 if (addr <= sizeof(s->mem) - sizeof(val)) {
1451 memcpy(&s->mem[addr], &val, sizeof(val));
1452 }
1453
1454 switch (addr) {
1455 case SCBPointer:
1456 eepro100_write_pointer(s, val);
1457 break;
1458 case SCBPort:
1459 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1460 eepro100_write_port(s, val);
1461 break;
1462 case SCBCtrlMDI:
1463 eepro100_write_mdi(s, val);
1464 break;
1465 default:
1466 logout("addr=%s val=0x%08x\n", regname(addr), val);
1467 missing("unknown longword write");
1468 }
1469 }
1470
1471 /*****************************************************************************
1472 *
1473 * Port mapped I/O.
1474 *
1475 ****************************************************************************/
1476
1477 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1478 {
1479 EEPRO100State *s = opaque;
1480 #if 0
1481 logout("addr=%s\n", regname(addr));
1482 #endif
1483 return eepro100_read1(s, addr - s->region[1]);
1484 }
1485
1486 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1487 {
1488 EEPRO100State *s = opaque;
1489 return eepro100_read2(s, addr - s->region[1]);
1490 }
1491
1492 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1493 {
1494 EEPRO100State *s = opaque;
1495 return eepro100_read4(s, addr - s->region[1]);
1496 }
1497
1498 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1499 {
1500 EEPRO100State *s = opaque;
1501 #if 0
1502 logout("addr=%s val=0x%02x\n", regname(addr), val);
1503 #endif
1504 eepro100_write1(s, addr - s->region[1], val);
1505 }
1506
1507 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1508 {
1509 EEPRO100State *s = opaque;
1510 eepro100_write2(s, addr - s->region[1], val);
1511 }
1512
1513 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1514 {
1515 EEPRO100State *s = opaque;
1516 eepro100_write4(s, addr - s->region[1], val);
1517 }
1518
1519 /***********************************************************/
1520 /* PCI EEPRO100 definitions */
1521
1522 static void pci_map(PCIDevice * pci_dev, int region_num,
1523 pcibus_t addr, pcibus_t size, int type)
1524 {
1525 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1526
1527 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1528 "size=0x%08"FMT_PCIBUS", type=%d\n",
1529 region_num, addr, size, type));
1530
1531 assert(region_num == 1);
1532 register_ioport_write(addr, size, 1, ioport_write1, s);
1533 register_ioport_read(addr, size, 1, ioport_read1, s);
1534 register_ioport_write(addr, size, 2, ioport_write2, s);
1535 register_ioport_read(addr, size, 2, ioport_read2, s);
1536 register_ioport_write(addr, size, 4, ioport_write4, s);
1537 register_ioport_read(addr, size, 4, ioport_read4, s);
1538
1539 s->region[region_num] = addr;
1540 }
1541
1542 /*****************************************************************************
1543 *
1544 * Memory mapped I/O.
1545 *
1546 ****************************************************************************/
1547
1548 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1549 {
1550 EEPRO100State *s = opaque;
1551 #if 0
1552 logout("addr=%s val=0x%02x\n", regname(addr), val);
1553 #endif
1554 eepro100_write1(s, addr, val);
1555 }
1556
1557 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1558 {
1559 EEPRO100State *s = opaque;
1560 #if 0
1561 logout("addr=%s val=0x%02x\n", regname(addr), val);
1562 #endif
1563 eepro100_write2(s, addr, val);
1564 }
1565
1566 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1567 {
1568 EEPRO100State *s = opaque;
1569 #if 0
1570 logout("addr=%s val=0x%02x\n", regname(addr), val);
1571 #endif
1572 eepro100_write4(s, addr, val);
1573 }
1574
1575 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1576 {
1577 EEPRO100State *s = opaque;
1578 #if 0
1579 logout("addr=%s\n", regname(addr));
1580 #endif
1581 return eepro100_read1(s, addr);
1582 }
1583
1584 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1585 {
1586 EEPRO100State *s = opaque;
1587 #if 0
1588 logout("addr=%s\n", regname(addr));
1589 #endif
1590 return eepro100_read2(s, addr);
1591 }
1592
1593 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1594 {
1595 EEPRO100State *s = opaque;
1596 #if 0
1597 logout("addr=%s\n", regname(addr));
1598 #endif
1599 return eepro100_read4(s, addr);
1600 }
1601
1602 static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1603 pci_mmio_writeb,
1604 pci_mmio_writew,
1605 pci_mmio_writel
1606 };
1607
1608 static CPUReadMemoryFunc * const pci_mmio_read[] = {
1609 pci_mmio_readb,
1610 pci_mmio_readw,
1611 pci_mmio_readl
1612 };
1613
1614 static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1615 pcibus_t addr, pcibus_t size, int type)
1616 {
1617 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1618
1619 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1620 "size=0x%08"FMT_PCIBUS", type=%d\n",
1621 region_num, addr, size, type));
1622
1623 assert(region_num == 0 || region_num == 2);
1624
1625 /* Map control / status registers and flash. */
1626 cpu_register_physical_memory(addr, size, s->mmio_index);
1627 s->region[region_num] = addr;
1628 }
1629
1630 static int nic_can_receive(VLANClientState *nc)
1631 {
1632 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1633 TRACE(RXTX, logout("%p\n", s));
1634 return get_ru_state(s) == ru_ready;
1635 #if 0
1636 return !eepro100_buffer_full(s);
1637 #endif
1638 }
1639
1640 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1641 {
1642 /* TODO:
1643 * - Magic packets should set bit 30 in power management driver register.
1644 * - Interesting packets should set bit 29 in power management driver register.
1645 */
1646 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1647 uint16_t rfd_status = 0xa000;
1648 static const uint8_t broadcast_macaddr[6] =
1649 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1650
1651 /* TODO: check multiple IA bit. */
1652 if (s->configuration[20] & BIT(6)) {
1653 missing("Multiple IA bit");
1654 return -1;
1655 }
1656
1657 if (s->configuration[8] & 0x80) {
1658 /* CSMA is disabled. */
1659 logout("%p received while CSMA is disabled\n", s);
1660 return -1;
1661 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1662 /* Short frame and configuration byte 7/0 (discard short receive) set:
1663 * Short frame is discarded */
1664 logout("%p received short frame (%zu byte)\n", s, size);
1665 s->statistics.rx_short_frame_errors++;
1666 #if 0
1667 return -1;
1668 #endif
1669 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1670 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1671 * Long frames are discarded. */
1672 logout("%p received long frame (%zu byte), ignored\n", s, size);
1673 return -1;
1674 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
1675 /* Frame matches individual address. */
1676 /* TODO: check configuration byte 15/4 (ignore U/L). */
1677 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1678 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1679 /* Broadcast frame. */
1680 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1681 rfd_status |= 0x0002;
1682 } else if (buf[0] & 0x01) {
1683 /* Multicast frame. */
1684 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1685 if (s->configuration[21] & BIT(3)) {
1686 /* Multicast all bit is set, receive all multicast frames. */
1687 } else {
1688 unsigned mcast_idx = compute_mcast_idx(buf);
1689 assert(mcast_idx < 64);
1690 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1691 /* Multicast frame is allowed in hash table. */
1692 } else if (s->configuration[15] & BIT(0)) {
1693 /* Promiscuous: receive all. */
1694 rfd_status |= 0x0004;
1695 } else {
1696 TRACE(RXTX, logout("%p multicast ignored\n", s));
1697 return -1;
1698 }
1699 }
1700 /* TODO: Next not for promiscuous mode? */
1701 rfd_status |= 0x0002;
1702 } else if (s->configuration[15] & BIT(0)) {
1703 /* Promiscuous: receive all. */
1704 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1705 rfd_status |= 0x0004;
1706 } else {
1707 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1708 nic_dump(buf, size)));
1709 return size;
1710 }
1711
1712 if (get_ru_state(s) != ru_ready) {
1713 /* No resources available. */
1714 logout("no resources, state=%u\n", get_ru_state(s));
1715 /* TODO: RNR interrupt only at first failed frame? */
1716 eepro100_rnr_interrupt(s);
1717 s->statistics.rx_resource_errors++;
1718 #if 0
1719 assert(!"no resources");
1720 #endif
1721 return -1;
1722 }
1723 /* !!! */
1724 eepro100_rx_t rx;
1725 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
1726 offsetof(eepro100_rx_t, packet));
1727 uint16_t rfd_command = le16_to_cpu(rx.command);
1728 uint16_t rfd_size = le16_to_cpu(rx.size);
1729
1730 if (size > rfd_size) {
1731 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1732 "(%zu bytes); data truncated\n", rfd_size, size);
1733 size = rfd_size;
1734 }
1735 if (size < 64) {
1736 rfd_status |= 0x0080;
1737 }
1738 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1739 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1740 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1741 rfd_status);
1742 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1743 /* Early receive interrupt not supported. */
1744 #if 0
1745 eepro100_er_interrupt(s);
1746 #endif
1747 /* Receive CRC Transfer not supported. */
1748 if (s->configuration[18] & BIT(2)) {
1749 missing("Receive CRC Transfer");
1750 return -1;
1751 }
1752 /* TODO: check stripping enable bit. */
1753 #if 0
1754 assert(!(s->configuration[17] & BIT(0)));
1755 #endif
1756 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1757 offsetof(eepro100_rx_t, packet), buf, size);
1758 s->statistics.rx_good_frames++;
1759 eepro100_fr_interrupt(s);
1760 s->ru_offset = le32_to_cpu(rx.link);
1761 if (rfd_command & COMMAND_EL) {
1762 /* EL bit is set, so this was the last frame. */
1763 logout("receive: Running out of frames\n");
1764 set_ru_state(s, ru_suspended);
1765 }
1766 if (rfd_command & COMMAND_S) {
1767 /* S bit is set. */
1768 set_ru_state(s, ru_suspended);
1769 }
1770 return size;
1771 }
1772
1773 static const VMStateDescription vmstate_eepro100 = {
1774 .version_id = 3,
1775 .minimum_version_id = 2,
1776 .minimum_version_id_old = 2,
1777 .fields = (VMStateField []) {
1778 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1779 VMSTATE_UNUSED(32),
1780 VMSTATE_BUFFER(mult, EEPRO100State),
1781 VMSTATE_BUFFER(mem, EEPRO100State),
1782 /* Save all members of struct between scb_stat and mem. */
1783 VMSTATE_UINT8(scb_stat, EEPRO100State),
1784 VMSTATE_UINT8(int_stat, EEPRO100State),
1785 VMSTATE_UNUSED(3*4),
1786 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1787 VMSTATE_UNUSED(19*4),
1788 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1789 /* The eeprom should be saved and restored by its own routines. */
1790 VMSTATE_UINT32(device, EEPRO100State),
1791 /* TODO check device. */
1792 VMSTATE_UINT32(pointer, EEPRO100State),
1793 VMSTATE_UINT32(cu_base, EEPRO100State),
1794 VMSTATE_UINT32(cu_offset, EEPRO100State),
1795 VMSTATE_UINT32(ru_base, EEPRO100State),
1796 VMSTATE_UINT32(ru_offset, EEPRO100State),
1797 VMSTATE_UINT32(statsaddr, EEPRO100State),
1798 /* Save eepro100_stats_t statistics. */
1799 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1800 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1801 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1802 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1803 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1804 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1805 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1806 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1807 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1808 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1809 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1810 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1811 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1812 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1813 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1814 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1815 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1816 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1817 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1818 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1819 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1820 /* Configuration bytes. */
1821 VMSTATE_BUFFER(configuration, EEPRO100State),
1822 VMSTATE_END_OF_LIST()
1823 }
1824 };
1825
1826 static void nic_cleanup(VLANClientState *nc)
1827 {
1828 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1829
1830 s->nic = NULL;
1831 }
1832
1833 static int pci_nic_uninit(PCIDevice *pci_dev)
1834 {
1835 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1836
1837 cpu_unregister_io_memory(s->mmio_index);
1838 vmstate_unregister(s->vmstate, s);
1839 eeprom93xx_free(s->eeprom);
1840 qemu_del_vlan_client(&s->nic->nc);
1841 return 0;
1842 }
1843
1844 static NetClientInfo net_eepro100_info = {
1845 .type = NET_CLIENT_TYPE_NIC,
1846 .size = sizeof(NICState),
1847 .can_receive = nic_can_receive,
1848 .receive = nic_receive,
1849 .cleanup = nic_cleanup,
1850 };
1851
1852 static int e100_nic_init(PCIDevice *pci_dev)
1853 {
1854 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1855 E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev,
1856 pci_dev->qdev.info);
1857
1858 TRACE(OTHER, logout("\n"));
1859
1860 s->device = e100_device->device;
1861
1862 e100_pci_reset(s, e100_device);
1863
1864 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1865 * i82559 and later support 64 or 256 word EEPROM. */
1866 s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1867
1868 /* Handler for memory-mapped I/O */
1869 s->mmio_index =
1870 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
1871
1872 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
1873 PCI_BASE_ADDRESS_SPACE_MEMORY |
1874 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
1875 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
1876 pci_map);
1877 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
1878 pci_mmio_map);
1879
1880 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1881 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1882 assert(s->region[1] == 0);
1883
1884 nic_reset(s);
1885
1886 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1887 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1888
1889 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1890 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1891
1892 qemu_register_reset(nic_reset, s);
1893
1894 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1895 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1896 s->vmstate->name = s->nic->nc.model;
1897 vmstate_register(-1, s->vmstate, s);
1898
1899 return 0;
1900 }
1901
1902 static E100PCIDeviceInfo e100_devices[] = {
1903 {
1904 .pci.qdev.name = "i82550",
1905 .pci.qdev.desc = "Intel i82550 Ethernet",
1906 .device = i82550,
1907 /* TODO: check device id. */
1908 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1909 /* Revision ID: 0x0c, 0x0d, 0x0e. */
1910 .revision = 0x0e,
1911 /* TODO: check size of statistical counters. */
1912 .stats_size = 80,
1913 /* TODO: check extended tcb support. */
1914 .has_extended_tcb_support = true,
1915 .power_management = true,
1916 },{
1917 .pci.qdev.name = "i82551",
1918 .pci.qdev.desc = "Intel i82551 Ethernet",
1919 .device = i82551,
1920 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1921 /* Revision ID: 0x0f, 0x10. */
1922 .revision = 0x0f,
1923 /* TODO: check size of statistical counters. */
1924 .stats_size = 80,
1925 .has_extended_tcb_support = true,
1926 .power_management = true,
1927 },{
1928 .pci.qdev.name = "i82557a",
1929 .pci.qdev.desc = "Intel i82557A Ethernet",
1930 .device = i82557A,
1931 .device_id = PCI_DEVICE_ID_INTEL_82557,
1932 .revision = 0x01,
1933 .power_management = false,
1934 },{
1935 .pci.qdev.name = "i82557b",
1936 .pci.qdev.desc = "Intel i82557B Ethernet",
1937 .device = i82557B,
1938 .device_id = PCI_DEVICE_ID_INTEL_82557,
1939 .revision = 0x02,
1940 .power_management = false,
1941 },{
1942 .pci.qdev.name = "i82557c",
1943 .pci.qdev.desc = "Intel i82557C Ethernet",
1944 .device = i82557C,
1945 .device_id = PCI_DEVICE_ID_INTEL_82557,
1946 .revision = 0x03,
1947 .power_management = false,
1948 },{
1949 .pci.qdev.name = "i82558a",
1950 .pci.qdev.desc = "Intel i82558A Ethernet",
1951 .device = i82558A,
1952 .device_id = PCI_DEVICE_ID_INTEL_82557,
1953 .revision = 0x04,
1954 .stats_size = 76,
1955 .has_extended_tcb_support = true,
1956 .power_management = true,
1957 },{
1958 .pci.qdev.name = "i82558b",
1959 .pci.qdev.desc = "Intel i82558B Ethernet",
1960 .device = i82558B,
1961 .device_id = PCI_DEVICE_ID_INTEL_82557,
1962 .revision = 0x05,
1963 .stats_size = 76,
1964 .has_extended_tcb_support = true,
1965 .power_management = true,
1966 },{
1967 .pci.qdev.name = "i82559a",
1968 .pci.qdev.desc = "Intel i82559A Ethernet",
1969 .device = i82559A,
1970 .device_id = PCI_DEVICE_ID_INTEL_82557,
1971 .revision = 0x06,
1972 .stats_size = 80,
1973 .has_extended_tcb_support = true,
1974 .power_management = true,
1975 },{
1976 .pci.qdev.name = "i82559b",
1977 .pci.qdev.desc = "Intel i82559B Ethernet",
1978 .device = i82559B,
1979 .device_id = PCI_DEVICE_ID_INTEL_82557,
1980 .revision = 0x07,
1981 .stats_size = 80,
1982 .has_extended_tcb_support = true,
1983 .power_management = true,
1984 },{
1985 .pci.qdev.name = "i82559c",
1986 .pci.qdev.desc = "Intel i82559C Ethernet",
1987 .device = i82559C,
1988 .device_id = PCI_DEVICE_ID_INTEL_82557,
1989 #if 0
1990 .revision = 0x08,
1991 #endif
1992 /* TODO: Windows wants revision id 0x0c. */
1993 .revision = 0x0c,
1994 .stats_size = 80,
1995 .has_extended_tcb_support = true,
1996 .power_management = true,
1997 },{
1998 .pci.qdev.name = "i82559er",
1999 .pci.qdev.desc = "Intel i82559ER Ethernet",
2000 .device = i82559ER,
2001 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2002 .revision = 0x09,
2003 .stats_size = 80,
2004 .has_extended_tcb_support = true,
2005 .power_management = true,
2006 },{
2007 .pci.qdev.name = "i82562",
2008 .pci.qdev.desc = "Intel i82562 Ethernet",
2009 .device = i82562,
2010 /* TODO: check device id. */
2011 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2012 /* TODO: wrong revision id. */
2013 .revision = 0x0e,
2014 .stats_size = 80,
2015 .has_extended_tcb_support = true,
2016 .power_management = true,
2017 },{
2018 /* Toshiba Tecra 8200. */
2019 .pci.qdev.name = "i82801",
2020 .pci.qdev.desc = "Intel i82801 Ethernet",
2021 .device = i82801,
2022 .device_id = 0x2449,
2023 .revision = 0x03,
2024 .stats_size = 80,
2025 .has_extended_tcb_support = true,
2026 .power_management = true,
2027 }
2028 };
2029
2030 static Property e100_properties[] = {
2031 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2032 DEFINE_PROP_END_OF_LIST(),
2033 };
2034
2035 static void eepro100_register_devices(void)
2036 {
2037 size_t i;
2038 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
2039 PCIDeviceInfo *pci_dev = &e100_devices[i].pci;
2040 switch (e100_devices[i].device_id) {
2041 case PCI_DEVICE_ID_INTEL_82551IT:
2042 pci_dev->romfile = "gpxe-eepro100-80861209.rom";
2043 break;
2044 case PCI_DEVICE_ID_INTEL_82557:
2045 pci_dev->romfile = "gpxe-eepro100-80861229.rom";
2046 break;
2047 case 0x2449:
2048 pci_dev->romfile = "gpxe-eepro100-80862449.rom";
2049 break;
2050 }
2051 pci_dev->init = e100_nic_init;
2052 pci_dev->exit = pci_nic_uninit;
2053 pci_dev->qdev.props = e100_properties;
2054 pci_dev->qdev.size = sizeof(EEPRO100State);
2055 pci_qdev_register(pci_dev);
2056 }
2057 }
2058
2059 device_init(eepro100_register_devices)
QEmu