9 #include "qemu-common.h"
10 #include "host-utils.h"
11 #if !defined(CONFIG_USER_ONLY)
12 #include "hw/loader.h"
15 static uint32_t cortexa9_cp15_c0_c1
[8] =
16 { 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
18 static uint32_t cortexa9_cp15_c0_c2
[8] =
19 { 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
21 static uint32_t cortexa8_cp15_c0_c1
[8] =
22 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
24 static uint32_t cortexa8_cp15_c0_c2
[8] =
25 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
27 static uint32_t mpcore_cp15_c0_c1
[8] =
28 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
30 static uint32_t mpcore_cp15_c0_c2
[8] =
31 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
33 static uint32_t arm1136_cp15_c0_c1
[8] =
34 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
36 static uint32_t arm1136_cp15_c0_c2
[8] =
37 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
39 static uint32_t cpu_arm_find_by_name(const char *name
);
41 static inline void set_feature(CPUARMState
*env
, int feature
)
43 env
->features
|= 1u << feature
;
46 static void cpu_reset_model_id(CPUARMState
*env
, uint32_t id
)
48 env
->cp15
.c0_cpuid
= id
;
50 case ARM_CPUID_ARM926
:
51 set_feature(env
, ARM_FEATURE_VFP
);
52 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41011090;
53 env
->cp15
.c0_cachetype
= 0x1dd20d2;
54 env
->cp15
.c1_sys
= 0x00090078;
56 case ARM_CPUID_ARM946
:
57 set_feature(env
, ARM_FEATURE_MPU
);
58 env
->cp15
.c0_cachetype
= 0x0f004006;
59 env
->cp15
.c1_sys
= 0x00000078;
61 case ARM_CPUID_ARM1026
:
62 set_feature(env
, ARM_FEATURE_VFP
);
63 set_feature(env
, ARM_FEATURE_AUXCR
);
64 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410110a0;
65 env
->cp15
.c0_cachetype
= 0x1dd20d2;
66 env
->cp15
.c1_sys
= 0x00090078;
68 case ARM_CPUID_ARM1136_R2
:
69 case ARM_CPUID_ARM1136
:
70 set_feature(env
, ARM_FEATURE_V6
);
71 set_feature(env
, ARM_FEATURE_VFP
);
72 set_feature(env
, ARM_FEATURE_AUXCR
);
73 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
74 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
75 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
76 memcpy(env
->cp15
.c0_c1
, arm1136_cp15_c0_c1
, 8 * sizeof(uint32_t));
77 memcpy(env
->cp15
.c0_c2
, arm1136_cp15_c0_c2
, 8 * sizeof(uint32_t));
78 env
->cp15
.c0_cachetype
= 0x1dd20d2;
80 case ARM_CPUID_ARM11MPCORE
:
81 set_feature(env
, ARM_FEATURE_V6
);
82 set_feature(env
, ARM_FEATURE_V6K
);
83 set_feature(env
, ARM_FEATURE_VFP
);
84 set_feature(env
, ARM_FEATURE_AUXCR
);
85 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
86 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
87 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
88 memcpy(env
->cp15
.c0_c1
, mpcore_cp15_c0_c1
, 8 * sizeof(uint32_t));
89 memcpy(env
->cp15
.c0_c2
, mpcore_cp15_c0_c2
, 8 * sizeof(uint32_t));
90 env
->cp15
.c0_cachetype
= 0x1dd20d2;
92 case ARM_CPUID_CORTEXA8
:
93 set_feature(env
, ARM_FEATURE_V6
);
94 set_feature(env
, ARM_FEATURE_V6K
);
95 set_feature(env
, ARM_FEATURE_V7
);
96 set_feature(env
, ARM_FEATURE_AUXCR
);
97 set_feature(env
, ARM_FEATURE_THUMB2
);
98 set_feature(env
, ARM_FEATURE_VFP
);
99 set_feature(env
, ARM_FEATURE_VFP3
);
100 set_feature(env
, ARM_FEATURE_NEON
);
101 set_feature(env
, ARM_FEATURE_THUMB2EE
);
102 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410330c0;
103 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
104 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00011100;
105 memcpy(env
->cp15
.c0_c1
, cortexa8_cp15_c0_c1
, 8 * sizeof(uint32_t));
106 memcpy(env
->cp15
.c0_c2
, cortexa8_cp15_c0_c2
, 8 * sizeof(uint32_t));
107 env
->cp15
.c0_cachetype
= 0x82048004;
108 env
->cp15
.c0_clid
= (1 << 27) | (2 << 24) | 3;
109 env
->cp15
.c0_ccsid
[0] = 0xe007e01a; /* 16k L1 dcache. */
110 env
->cp15
.c0_ccsid
[1] = 0x2007e01a; /* 16k L1 icache. */
111 env
->cp15
.c0_ccsid
[2] = 0xf0000000; /* No L2 icache. */
112 env
->cp15
.c1_sys
= 0x00c50078;
114 case ARM_CPUID_CORTEXA9
:
115 set_feature(env
, ARM_FEATURE_V6
);
116 set_feature(env
, ARM_FEATURE_V6K
);
117 set_feature(env
, ARM_FEATURE_V7
);
118 set_feature(env
, ARM_FEATURE_AUXCR
);
119 set_feature(env
, ARM_FEATURE_THUMB2
);
120 set_feature(env
, ARM_FEATURE_VFP
);
121 set_feature(env
, ARM_FEATURE_VFP3
);
122 set_feature(env
, ARM_FEATURE_VFP_FP16
);
123 set_feature(env
, ARM_FEATURE_NEON
);
124 set_feature(env
, ARM_FEATURE_THUMB2EE
);
125 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41034000; /* Guess */
126 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
127 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x01111111;
128 memcpy(env
->cp15
.c0_c1
, cortexa9_cp15_c0_c1
, 8 * sizeof(uint32_t));
129 memcpy(env
->cp15
.c0_c2
, cortexa9_cp15_c0_c2
, 8 * sizeof(uint32_t));
130 env
->cp15
.c0_cachetype
= 0x80038003;
131 env
->cp15
.c0_clid
= (1 << 27) | (1 << 24) | 3;
132 env
->cp15
.c0_ccsid
[0] = 0xe00fe015; /* 16k L1 dcache. */
133 env
->cp15
.c0_ccsid
[1] = 0x200fe015; /* 16k L1 icache. */
135 case ARM_CPUID_CORTEXM3
:
136 set_feature(env
, ARM_FEATURE_V6
);
137 set_feature(env
, ARM_FEATURE_THUMB2
);
138 set_feature(env
, ARM_FEATURE_V7
);
139 set_feature(env
, ARM_FEATURE_M
);
140 set_feature(env
, ARM_FEATURE_DIV
);
142 case ARM_CPUID_ANY
: /* For userspace emulation. */
143 set_feature(env
, ARM_FEATURE_V6
);
144 set_feature(env
, ARM_FEATURE_V6K
);
145 set_feature(env
, ARM_FEATURE_V7
);
146 set_feature(env
, ARM_FEATURE_THUMB2
);
147 set_feature(env
, ARM_FEATURE_VFP
);
148 set_feature(env
, ARM_FEATURE_VFP3
);
149 set_feature(env
, ARM_FEATURE_VFP_FP16
);
150 set_feature(env
, ARM_FEATURE_NEON
);
151 set_feature(env
, ARM_FEATURE_THUMB2EE
);
152 set_feature(env
, ARM_FEATURE_DIV
);
154 case ARM_CPUID_TI915T
:
155 case ARM_CPUID_TI925T
:
156 set_feature(env
, ARM_FEATURE_OMAPCP
);
157 env
->cp15
.c0_cpuid
= ARM_CPUID_TI925T
; /* Depends on wiring. */
158 env
->cp15
.c0_cachetype
= 0x5109149;
159 env
->cp15
.c1_sys
= 0x00000070;
160 env
->cp15
.c15_i_max
= 0x000;
161 env
->cp15
.c15_i_min
= 0xff0;
163 case ARM_CPUID_PXA250
:
164 case ARM_CPUID_PXA255
:
165 case ARM_CPUID_PXA260
:
166 case ARM_CPUID_PXA261
:
167 case ARM_CPUID_PXA262
:
168 set_feature(env
, ARM_FEATURE_XSCALE
);
169 /* JTAG_ID is ((id << 28) | 0x09265013) */
170 env
->cp15
.c0_cachetype
= 0xd172172;
171 env
->cp15
.c1_sys
= 0x00000078;
173 case ARM_CPUID_PXA270_A0
:
174 case ARM_CPUID_PXA270_A1
:
175 case ARM_CPUID_PXA270_B0
:
176 case ARM_CPUID_PXA270_B1
:
177 case ARM_CPUID_PXA270_C0
:
178 case ARM_CPUID_PXA270_C5
:
179 set_feature(env
, ARM_FEATURE_XSCALE
);
180 /* JTAG_ID is ((id << 28) | 0x09265013) */
181 set_feature(env
, ARM_FEATURE_IWMMXT
);
182 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
183 env
->cp15
.c0_cachetype
= 0xd172172;
184 env
->cp15
.c1_sys
= 0x00000078;
187 cpu_abort(env
, "Bad CPU ID: %x\n", id
);
192 void cpu_reset(CPUARMState
*env
)
196 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
197 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
198 log_cpu_state(env
, 0);
201 id
= env
->cp15
.c0_cpuid
;
202 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
204 cpu_reset_model_id(env
, id
);
205 #if defined (CONFIG_USER_ONLY)
206 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
207 /* For user mode we must enable access to coprocessors */
208 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
209 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
210 env
->cp15
.c15_cpar
= 3;
211 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
212 env
->cp15
.c15_cpar
= 1;
215 /* SVC mode with interrupts disabled. */
216 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
217 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
218 clear at reset. Initial SP and PC are loaded from ROM. */
222 env
->uncached_cpsr
&= ~CPSR_I
;
225 /* We should really use ldl_phys here, in case the guest
226 modified flash and reset itself. However images
227 loaded via -kenrel have not been copied yet, so load the
228 values directly from there. */
229 env
->regs
[13] = ldl_p(rom
);
232 env
->regs
[15] = pc
& ~1;
235 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
236 env
->cp15
.c2_base_mask
= 0xffffc000u
;
241 static int vfp_gdb_get_reg(CPUState
*env
, uint8_t *buf
, int reg
)
245 /* VFP data registers are always little-endian. */
246 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
248 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
251 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
252 /* Aliases for Q regs. */
255 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
256 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
260 switch (reg
- nregs
) {
261 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
262 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
263 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
268 static int vfp_gdb_set_reg(CPUState
*env
, uint8_t *buf
, int reg
)
272 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
274 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
277 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
280 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
281 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
285 switch (reg
- nregs
) {
286 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
287 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
288 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
293 CPUARMState
*cpu_arm_init(const char *cpu_model
)
297 static int inited
= 0;
299 id
= cpu_arm_find_by_name(cpu_model
);
302 env
= qemu_mallocz(sizeof(CPUARMState
));
306 arm_translate_init();
309 env
->cpu_model_str
= cpu_model
;
310 env
->cp15
.c0_cpuid
= id
;
312 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
313 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
314 51, "arm-neon.xml", 0);
315 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
316 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
317 35, "arm-vfp3.xml", 0);
318 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
319 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
320 19, "arm-vfp.xml", 0);
331 static const struct arm_cpu_t arm_cpu_names
[] = {
332 { ARM_CPUID_ARM926
, "arm926"},
333 { ARM_CPUID_ARM946
, "arm946"},
334 { ARM_CPUID_ARM1026
, "arm1026"},
335 { ARM_CPUID_ARM1136
, "arm1136"},
336 { ARM_CPUID_ARM1136_R2
, "arm1136-r2"},
337 { ARM_CPUID_ARM11MPCORE
, "arm11mpcore"},
338 { ARM_CPUID_CORTEXM3
, "cortex-m3"},
339 { ARM_CPUID_CORTEXA8
, "cortex-a8"},
340 { ARM_CPUID_CORTEXA9
, "cortex-a9"},
341 { ARM_CPUID_TI925T
, "ti925t" },
342 { ARM_CPUID_PXA250
, "pxa250" },
343 { ARM_CPUID_PXA255
, "pxa255" },
344 { ARM_CPUID_PXA260
, "pxa260" },
345 { ARM_CPUID_PXA261
, "pxa261" },
346 { ARM_CPUID_PXA262
, "pxa262" },
347 { ARM_CPUID_PXA270
, "pxa270" },
348 { ARM_CPUID_PXA270_A0
, "pxa270-a0" },
349 { ARM_CPUID_PXA270_A1
, "pxa270-a1" },
350 { ARM_CPUID_PXA270_B0
, "pxa270-b0" },
351 { ARM_CPUID_PXA270_B1
, "pxa270-b1" },
352 { ARM_CPUID_PXA270_C0
, "pxa270-c0" },
353 { ARM_CPUID_PXA270_C5
, "pxa270-c5" },
354 { ARM_CPUID_ANY
, "any"},
358 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
362 (*cpu_fprintf
)(f
, "Available CPUs:\n");
363 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
364 (*cpu_fprintf
)(f
, " %s\n", arm_cpu_names
[i
].name
);
368 /* return 0 if not found */
369 static uint32_t cpu_arm_find_by_name(const char *name
)
375 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
376 if (strcmp(name
, arm_cpu_names
[i
].name
) == 0) {
377 id
= arm_cpu_names
[i
].id
;
384 void cpu_arm_close(CPUARMState
*env
)
389 uint32_t cpsr_read(CPUARMState
*env
)
393 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
394 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
395 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
396 | ((env
->condexec_bits
& 0xfc) << 8)
400 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
402 if (mask
& CPSR_NZCV
) {
403 env
->ZF
= (~val
) & CPSR_Z
;
405 env
->CF
= (val
>> 29) & 1;
406 env
->VF
= (val
<< 3) & 0x80000000;
409 env
->QF
= ((val
& CPSR_Q
) != 0);
411 env
->thumb
= ((val
& CPSR_T
) != 0);
412 if (mask
& CPSR_IT_0_1
) {
413 env
->condexec_bits
&= ~3;
414 env
->condexec_bits
|= (val
>> 25) & 3;
416 if (mask
& CPSR_IT_2_7
) {
417 env
->condexec_bits
&= 3;
418 env
->condexec_bits
|= (val
>> 8) & 0xfc;
420 if (mask
& CPSR_GE
) {
421 env
->GE
= (val
>> 16) & 0xf;
424 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
425 switch_mode(env
, val
& CPSR_M
);
427 mask
&= ~CACHED_CPSR_BITS
;
428 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
431 /* Sign/zero extend */
432 uint32_t HELPER(sxtb16
)(uint32_t x
)
435 res
= (uint16_t)(int8_t)x
;
436 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
440 uint32_t HELPER(uxtb16
)(uint32_t x
)
443 res
= (uint16_t)(uint8_t)x
;
444 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
448 uint32_t HELPER(clz
)(uint32_t x
)
453 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
457 if (num
== INT_MIN
&& den
== -1)
462 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
469 uint32_t HELPER(rbit
)(uint32_t x
)
471 x
= ((x
& 0xff000000) >> 24)
472 | ((x
& 0x00ff0000) >> 8)
473 | ((x
& 0x0000ff00) << 8)
474 | ((x
& 0x000000ff) << 24);
475 x
= ((x
& 0xf0f0f0f0) >> 4)
476 | ((x
& 0x0f0f0f0f) << 4);
477 x
= ((x
& 0x88888888) >> 3)
478 | ((x
& 0x44444444) >> 1)
479 | ((x
& 0x22222222) << 1)
480 | ((x
& 0x11111111) << 3);
484 uint32_t HELPER(abs
)(uint32_t x
)
486 return ((int32_t)x
< 0) ? -x
: x
;
489 #if defined(CONFIG_USER_ONLY)
491 void do_interrupt (CPUState
*env
)
493 env
->exception_index
= -1;
496 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
497 int mmu_idx
, int is_softmmu
)
500 env
->exception_index
= EXCP_PREFETCH_ABORT
;
501 env
->cp15
.c6_insn
= address
;
503 env
->exception_index
= EXCP_DATA_ABORT
;
504 env
->cp15
.c6_data
= address
;
509 /* These should probably raise undefined insn exceptions. */
510 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
512 int op1
= (insn
>> 8) & 0xf;
513 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
517 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
519 int op1
= (insn
>> 8) & 0xf;
520 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
524 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
526 cpu_abort(env
, "cp15 insn %08x\n", insn
);
529 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
531 cpu_abort(env
, "cp15 insn %08x\n", insn
);
534 /* These should probably raise undefined insn exceptions. */
535 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
537 cpu_abort(env
, "v7m_mrs %d\n", reg
);
540 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
542 cpu_abort(env
, "v7m_mrs %d\n", reg
);
546 void switch_mode(CPUState
*env
, int mode
)
548 if (mode
!= ARM_CPU_MODE_USR
)
549 cpu_abort(env
, "Tried to switch out of user mode\n");
552 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
554 cpu_abort(env
, "banked r13 write\n");
557 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
559 cpu_abort(env
, "banked r13 read\n");
565 extern int semihosting_enabled
;
567 /* Map CPU modes onto saved register banks. */
568 static inline int bank_number (int mode
)
571 case ARM_CPU_MODE_USR
:
572 case ARM_CPU_MODE_SYS
:
574 case ARM_CPU_MODE_SVC
:
576 case ARM_CPU_MODE_ABT
:
578 case ARM_CPU_MODE_UND
:
580 case ARM_CPU_MODE_IRQ
:
582 case ARM_CPU_MODE_FIQ
:
585 cpu_abort(cpu_single_env
, "Bad mode %x\n", mode
);
589 void switch_mode(CPUState
*env
, int mode
)
594 old_mode
= env
->uncached_cpsr
& CPSR_M
;
595 if (mode
== old_mode
)
598 if (old_mode
== ARM_CPU_MODE_FIQ
) {
599 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
600 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
601 } else if (mode
== ARM_CPU_MODE_FIQ
) {
602 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
603 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
606 i
= bank_number(old_mode
);
607 env
->banked_r13
[i
] = env
->regs
[13];
608 env
->banked_r14
[i
] = env
->regs
[14];
609 env
->banked_spsr
[i
] = env
->spsr
;
611 i
= bank_number(mode
);
612 env
->regs
[13] = env
->banked_r13
[i
];
613 env
->regs
[14] = env
->banked_r14
[i
];
614 env
->spsr
= env
->banked_spsr
[i
];
617 static void v7m_push(CPUARMState
*env
, uint32_t val
)
620 stl_phys(env
->regs
[13], val
);
623 static uint32_t v7m_pop(CPUARMState
*env
)
626 val
= ldl_phys(env
->regs
[13]);
631 /* Switch to V7M main or process stack pointer. */
632 static void switch_v7m_sp(CPUARMState
*env
, int process
)
635 if (env
->v7m
.current_sp
!= process
) {
636 tmp
= env
->v7m
.other_sp
;
637 env
->v7m
.other_sp
= env
->regs
[13];
639 env
->v7m
.current_sp
= process
;
643 static void do_v7m_exception_exit(CPUARMState
*env
)
648 type
= env
->regs
[15];
649 if (env
->v7m
.exception
!= 0)
650 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
652 /* Switch to the target stack. */
653 switch_v7m_sp(env
, (type
& 4) != 0);
655 env
->regs
[0] = v7m_pop(env
);
656 env
->regs
[1] = v7m_pop(env
);
657 env
->regs
[2] = v7m_pop(env
);
658 env
->regs
[3] = v7m_pop(env
);
659 env
->regs
[12] = v7m_pop(env
);
660 env
->regs
[14] = v7m_pop(env
);
661 env
->regs
[15] = v7m_pop(env
);
663 xpsr_write(env
, xpsr
, 0xfffffdff);
664 /* Undo stack alignment. */
667 /* ??? The exception return type specifies Thread/Handler mode. However
668 this is also implied by the xPSR value. Not sure what to do
669 if there is a mismatch. */
670 /* ??? Likewise for mismatches between the CONTROL register and the stack
674 static void do_interrupt_v7m(CPUARMState
*env
)
676 uint32_t xpsr
= xpsr_read(env
);
681 if (env
->v7m
.current_sp
)
683 if (env
->v7m
.exception
== 0)
686 /* For exceptions we just mark as pending on the NVIC, and let that
688 /* TODO: Need to escalate if the current priority is higher than the
689 one we're raising. */
690 switch (env
->exception_index
) {
692 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
696 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
698 case EXCP_PREFETCH_ABORT
:
699 case EXCP_DATA_ABORT
:
700 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
703 if (semihosting_enabled
) {
705 nr
= lduw_code(env
->regs
[15]) & 0xff;
708 env
->regs
[0] = do_arm_semihosting(env
);
712 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
715 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
717 case EXCP_EXCEPTION_EXIT
:
718 do_v7m_exception_exit(env
);
721 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
722 return; /* Never happens. Keep compiler happy. */
725 /* Align stack pointer. */
726 /* ??? Should only do this if Configuration Control Register
727 STACKALIGN bit is set. */
728 if (env
->regs
[13] & 4) {
732 /* Switch to the handler mode. */
734 v7m_push(env
, env
->regs
[15]);
735 v7m_push(env
, env
->regs
[14]);
736 v7m_push(env
, env
->regs
[12]);
737 v7m_push(env
, env
->regs
[3]);
738 v7m_push(env
, env
->regs
[2]);
739 v7m_push(env
, env
->regs
[1]);
740 v7m_push(env
, env
->regs
[0]);
741 switch_v7m_sp(env
, 0);
742 env
->uncached_cpsr
&= ~CPSR_IT
;
744 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
745 env
->regs
[15] = addr
& 0xfffffffe;
746 env
->thumb
= addr
& 1;
749 /* Handle a CPU exception. */
750 void do_interrupt(CPUARMState
*env
)
758 do_interrupt_v7m(env
);
761 /* TODO: Vectored interrupt controller. */
762 switch (env
->exception_index
) {
764 new_mode
= ARM_CPU_MODE_UND
;
773 if (semihosting_enabled
) {
774 /* Check for semihosting interrupt. */
776 mask
= lduw_code(env
->regs
[15] - 2) & 0xff;
778 mask
= ldl_code(env
->regs
[15] - 4) & 0xffffff;
780 /* Only intercept calls from privileged modes, to provide some
781 semblance of security. */
782 if (((mask
== 0x123456 && !env
->thumb
)
783 || (mask
== 0xab && env
->thumb
))
784 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
785 env
->regs
[0] = do_arm_semihosting(env
);
789 new_mode
= ARM_CPU_MODE_SVC
;
792 /* The PC already points to the next instruction. */
796 /* See if this is a semihosting syscall. */
797 if (env
->thumb
&& semihosting_enabled
) {
798 mask
= lduw_code(env
->regs
[15]) & 0xff;
800 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
802 env
->regs
[0] = do_arm_semihosting(env
);
806 /* Fall through to prefetch abort. */
807 case EXCP_PREFETCH_ABORT
:
808 new_mode
= ARM_CPU_MODE_ABT
;
810 mask
= CPSR_A
| CPSR_I
;
813 case EXCP_DATA_ABORT
:
814 new_mode
= ARM_CPU_MODE_ABT
;
816 mask
= CPSR_A
| CPSR_I
;
820 new_mode
= ARM_CPU_MODE_IRQ
;
822 /* Disable IRQ and imprecise data aborts. */
823 mask
= CPSR_A
| CPSR_I
;
827 new_mode
= ARM_CPU_MODE_FIQ
;
829 /* Disable FIQ, IRQ and imprecise data aborts. */
830 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
834 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
835 return; /* Never happens. Keep compiler happy. */
838 if (env
->cp15
.c1_sys
& (1 << 13)) {
841 switch_mode (env
, new_mode
);
842 env
->spsr
= cpsr_read(env
);
844 env
->condexec_bits
= 0;
845 /* Switch to the new mode, and to the correct instruction set. */
846 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
847 env
->uncached_cpsr
|= mask
;
848 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
849 env
->regs
[14] = env
->regs
[15] + offset
;
850 env
->regs
[15] = addr
;
851 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
854 /* Check section/page access permissions.
855 Returns the page protection flags, or zero if the access is not
857 static inline int check_ap(CPUState
*env
, int ap
, int domain
, int access_type
,
863 return PAGE_READ
| PAGE_WRITE
;
865 if (access_type
== 1)
872 if (access_type
== 1)
874 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
876 return is_user
? 0 : PAGE_READ
;
883 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
888 return PAGE_READ
| PAGE_WRITE
;
890 return PAGE_READ
| PAGE_WRITE
;
891 case 4: /* Reserved. */
894 return is_user
? 0 : prot_ro
;
898 if (!arm_feature (env
, ARM_FEATURE_V7
))
906 static uint32_t get_level1_table_address(CPUState
*env
, uint32_t address
)
910 if (address
& env
->cp15
.c2_mask
)
911 table
= env
->cp15
.c2_base1
& 0xffffc000;
913 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
915 table
|= (address
>> 18) & 0x3ffc;
919 static int get_phys_addr_v5(CPUState
*env
, uint32_t address
, int access_type
,
920 int is_user
, uint32_t *phys_ptr
, int *prot
,
921 target_ulong
*page_size
)
931 /* Pagetable walk. */
932 /* Lookup l1 descriptor. */
933 table
= get_level1_table_address(env
, address
);
934 desc
= ldl_phys(table
);
936 domain
= (env
->cp15
.c3
>> ((desc
>> 4) & 0x1e)) & 3;
938 /* Section translation fault. */
942 if (domain
== 0 || domain
== 2) {
944 code
= 9; /* Section domain fault. */
946 code
= 11; /* Page domain fault. */
951 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
952 ap
= (desc
>> 10) & 3;
954 *page_size
= 1024 * 1024;
956 /* Lookup l2 entry. */
958 /* Coarse pagetable. */
959 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
961 /* Fine pagetable. */
962 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
964 desc
= ldl_phys(table
);
966 case 0: /* Page translation fault. */
969 case 1: /* 64k page. */
970 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
971 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
972 *page_size
= 0x10000;
974 case 2: /* 4k page. */
975 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
976 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
979 case 3: /* 1k page. */
981 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
982 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
984 /* Page translation fault. */
989 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
991 ap
= (desc
>> 4) & 3;
995 /* Never happens, but compiler isn't smart enough to tell. */
1000 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
1002 /* Access permission fault. */
1006 *phys_ptr
= phys_addr
;
1009 return code
| (domain
<< 4);
1012 static int get_phys_addr_v6(CPUState
*env
, uint32_t address
, int access_type
,
1013 int is_user
, uint32_t *phys_ptr
, int *prot
,
1014 target_ulong
*page_size
)
1025 /* Pagetable walk. */
1026 /* Lookup l1 descriptor. */
1027 table
= get_level1_table_address(env
, address
);
1028 desc
= ldl_phys(table
);
1031 /* Section translation fault. */
1035 } else if (type
== 2 && (desc
& (1 << 18))) {
1039 /* Section or page. */
1040 domain
= (desc
>> 4) & 0x1e;
1042 domain
= (env
->cp15
.c3
>> domain
) & 3;
1043 if (domain
== 0 || domain
== 2) {
1045 code
= 9; /* Section domain fault. */
1047 code
= 11; /* Page domain fault. */
1051 if (desc
& (1 << 18)) {
1053 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1054 *page_size
= 0x1000000;
1057 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1058 *page_size
= 0x100000;
1060 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1061 xn
= desc
& (1 << 4);
1064 /* Lookup l2 entry. */
1065 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1066 desc
= ldl_phys(table
);
1067 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1069 case 0: /* Page translation fault. */
1072 case 1: /* 64k page. */
1073 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1074 xn
= desc
& (1 << 15);
1075 *page_size
= 0x10000;
1077 case 2: case 3: /* 4k page. */
1078 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1080 *page_size
= 0x1000;
1083 /* Never happens, but compiler isn't smart enough to tell. */
1089 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1091 if (xn
&& access_type
== 2)
1094 /* The simplified model uses AP[0] as an access control bit. */
1095 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
1096 /* Access flag fault. */
1097 code
= (code
== 15) ? 6 : 3;
1100 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
1102 /* Access permission fault. */
1109 *phys_ptr
= phys_addr
;
1112 return code
| (domain
<< 4);
1115 static int get_phys_addr_mpu(CPUState
*env
, uint32_t address
, int access_type
,
1116 int is_user
, uint32_t *phys_ptr
, int *prot
)
1122 *phys_ptr
= address
;
1123 for (n
= 7; n
>= 0; n
--) {
1124 base
= env
->cp15
.c6_region
[n
];
1125 if ((base
& 1) == 0)
1127 mask
= 1 << ((base
>> 1) & 0x1f);
1128 /* Keep this shift separate from the above to avoid an
1129 (undefined) << 32. */
1130 mask
= (mask
<< 1) - 1;
1131 if (((base
^ address
) & ~mask
) == 0)
1137 if (access_type
== 2) {
1138 mask
= env
->cp15
.c5_insn
;
1140 mask
= env
->cp15
.c5_data
;
1142 mask
= (mask
>> (n
* 4)) & 0xf;
1149 *prot
= PAGE_READ
| PAGE_WRITE
;
1154 *prot
|= PAGE_WRITE
;
1157 *prot
= PAGE_READ
| PAGE_WRITE
;
1168 /* Bad permission. */
1175 static inline int get_phys_addr(CPUState
*env
, uint32_t address
,
1176 int access_type
, int is_user
,
1177 uint32_t *phys_ptr
, int *prot
,
1178 target_ulong
*page_size
)
1180 /* Fast Context Switch Extension. */
1181 if (address
< 0x02000000)
1182 address
+= env
->cp15
.c13_fcse
;
1184 if ((env
->cp15
.c1_sys
& 1) == 0) {
1185 /* MMU/MPU disabled. */
1186 *phys_ptr
= address
;
1187 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1188 *page_size
= TARGET_PAGE_SIZE
;
1190 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1191 *page_size
= TARGET_PAGE_SIZE
;
1192 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1194 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1195 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1198 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1203 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
,
1204 int access_type
, int mmu_idx
, int is_softmmu
)
1207 target_ulong page_size
;
1211 is_user
= mmu_idx
== MMU_USER_IDX
;
1212 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
1215 /* Map a single [sub]page. */
1216 phys_addr
&= ~(uint32_t)0x3ff;
1217 address
&= ~(uint32_t)0x3ff;
1218 tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
1222 if (access_type
== 2) {
1223 env
->cp15
.c5_insn
= ret
;
1224 env
->cp15
.c6_insn
= address
;
1225 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1227 env
->cp15
.c5_data
= ret
;
1228 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1229 env
->cp15
.c5_data
|= (1 << 11);
1230 env
->cp15
.c6_data
= address
;
1231 env
->exception_index
= EXCP_DATA_ABORT
;
1236 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
1239 target_ulong page_size
;
1243 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
1251 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1253 int cp_num
= (insn
>> 8) & 0xf;
1254 int cp_info
= (insn
>> 5) & 7;
1255 int src
= (insn
>> 16) & 0xf;
1256 int operand
= insn
& 0xf;
1258 if (env
->cp
[cp_num
].cp_write
)
1259 env
->cp
[cp_num
].cp_write(env
->cp
[cp_num
].opaque
,
1260 cp_info
, src
, operand
, val
);
1263 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
1265 int cp_num
= (insn
>> 8) & 0xf;
1266 int cp_info
= (insn
>> 5) & 7;
1267 int dest
= (insn
>> 16) & 0xf;
1268 int operand
= insn
& 0xf;
1270 if (env
->cp
[cp_num
].cp_read
)
1271 return env
->cp
[cp_num
].cp_read(env
->cp
[cp_num
].opaque
,
1272 cp_info
, dest
, operand
);
1276 /* Return basic MPU access permission bits. */
1277 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1284 for (i
= 0; i
< 16; i
+= 2) {
1285 ret
|= (val
>> i
) & mask
;
1291 /* Pad basic MPU access permission bits to extended format. */
1292 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1299 for (i
= 0; i
< 16; i
+= 2) {
1300 ret
|= (val
& mask
) << i
;
1306 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1312 op1
= (insn
>> 21) & 7;
1313 op2
= (insn
>> 5) & 7;
1315 switch ((insn
>> 16) & 0xf) {
1318 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1320 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1322 if (arm_feature(env
, ARM_FEATURE_V7
)
1323 && op1
== 2 && crm
== 0 && op2
== 0) {
1324 env
->cp15
.c0_cssel
= val
& 0xf;
1328 case 1: /* System configuration. */
1329 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1333 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1334 env
->cp15
.c1_sys
= val
;
1335 /* ??? Lots of these bits are not implemented. */
1336 /* This may enable/disable the MMU, so do a TLB flush. */
1339 case 1: /* Auxiliary cotrol register. */
1340 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1341 env
->cp15
.c1_xscaleauxcr
= val
;
1344 /* Not implemented. */
1347 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1349 if (env
->cp15
.c1_coproc
!= val
) {
1350 env
->cp15
.c1_coproc
= val
;
1351 /* ??? Is this safe when called from within a TB? */
1359 case 2: /* MMU Page table control / MPU cache control. */
1360 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1363 env
->cp15
.c2_data
= val
;
1366 env
->cp15
.c2_insn
= val
;
1374 env
->cp15
.c2_base0
= val
;
1377 env
->cp15
.c2_base1
= val
;
1381 env
->cp15
.c2_control
= val
;
1382 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> val
);
1383 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> val
);
1390 case 3: /* MMU Domain access control / MPU write buffer control. */
1392 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
1394 case 4: /* Reserved. */
1396 case 5: /* MMU Fault status / MPU access permission. */
1397 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1401 if (arm_feature(env
, ARM_FEATURE_MPU
))
1402 val
= extended_mpu_ap_bits(val
);
1403 env
->cp15
.c5_data
= val
;
1406 if (arm_feature(env
, ARM_FEATURE_MPU
))
1407 val
= extended_mpu_ap_bits(val
);
1408 env
->cp15
.c5_insn
= val
;
1411 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1413 env
->cp15
.c5_data
= val
;
1416 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1418 env
->cp15
.c5_insn
= val
;
1424 case 6: /* MMU Fault address / MPU base/size. */
1425 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1428 env
->cp15
.c6_region
[crm
] = val
;
1430 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1434 env
->cp15
.c6_data
= val
;
1436 case 1: /* ??? This is WFAR on armv6 */
1438 env
->cp15
.c6_insn
= val
;
1445 case 7: /* Cache control. */
1446 env
->cp15
.c15_i_max
= 0x000;
1447 env
->cp15
.c15_i_min
= 0xff0;
1448 /* No cache, so nothing to do. */
1449 /* ??? MPCore has VA to PA translation functions. */
1451 case 8: /* MMU TLB control. */
1453 case 0: /* Invalidate all. */
1456 case 1: /* Invalidate single TLB entry. */
1457 tlb_flush_page(env
, val
& TARGET_PAGE_MASK
);
1459 case 2: /* Invalidate on ASID. */
1460 tlb_flush(env
, val
== 0);
1462 case 3: /* Invalidate single entry on MVA. */
1463 /* ??? This is like case 1, but ignores ASID. */
1471 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1474 case 0: /* Cache lockdown. */
1476 case 0: /* L1 cache. */
1479 env
->cp15
.c9_data
= val
;
1482 env
->cp15
.c9_insn
= val
;
1488 case 1: /* L2 cache. */
1489 /* Ignore writes to L2 lockdown/auxiliary registers. */
1495 case 1: /* TCM memory region registers. */
1496 /* Not implemented. */
1502 case 10: /* MMU TLB lockdown. */
1503 /* ??? TLB lockdown not implemented. */
1505 case 12: /* Reserved. */
1507 case 13: /* Process ID. */
1510 /* Unlike real hardware the qemu TLB uses virtual addresses,
1511 not modified virtual addresses, so this causes a TLB flush.
1513 if (env
->cp15
.c13_fcse
!= val
)
1515 env
->cp15
.c13_fcse
= val
;
1518 /* This changes the ASID, so do a TLB flush. */
1519 if (env
->cp15
.c13_context
!= val
1520 && !arm_feature(env
, ARM_FEATURE_MPU
))
1522 env
->cp15
.c13_context
= val
;
1528 case 14: /* Reserved. */
1530 case 15: /* Implementation specific. */
1531 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1532 if (op2
== 0 && crm
== 1) {
1533 if (env
->cp15
.c15_cpar
!= (val
& 0x3fff)) {
1534 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1536 env
->cp15
.c15_cpar
= val
& 0x3fff;
1542 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1546 case 1: /* Set TI925T configuration. */
1547 env
->cp15
.c15_ticonfig
= val
& 0xe7;
1548 env
->cp15
.c0_cpuid
= (val
& (1 << 5)) ? /* OS_TYPE bit */
1549 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1551 case 2: /* Set I_max. */
1552 env
->cp15
.c15_i_max
= val
;
1554 case 3: /* Set I_min. */
1555 env
->cp15
.c15_i_min
= val
;
1557 case 4: /* Set thread-ID. */
1558 env
->cp15
.c15_threadid
= val
& 0xffff;
1560 case 8: /* Wait-for-interrupt (deprecated). */
1561 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
1571 /* ??? For debugging only. Should raise illegal instruction exception. */
1572 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1573 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1576 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
1582 op1
= (insn
>> 21) & 7;
1583 op2
= (insn
>> 5) & 7;
1585 switch ((insn
>> 16) & 0xf) {
1586 case 0: /* ID codes. */
1592 case 0: /* Device ID. */
1593 return env
->cp15
.c0_cpuid
;
1594 case 1: /* Cache Type. */
1595 return env
->cp15
.c0_cachetype
;
1596 case 2: /* TCM status. */
1598 case 3: /* TLB type register. */
1599 return 0; /* No lockable TLB entries. */
1600 case 5: /* CPU ID */
1601 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA9
) {
1602 return env
->cpu_index
| 0x80000900;
1604 return env
->cpu_index
;
1610 if (!arm_feature(env
, ARM_FEATURE_V6
))
1612 return env
->cp15
.c0_c1
[op2
];
1614 if (!arm_feature(env
, ARM_FEATURE_V6
))
1616 return env
->cp15
.c0_c2
[op2
];
1617 case 3: case 4: case 5: case 6: case 7:
1623 /* These registers aren't documented on arm11 cores. However
1624 Linux looks at them anyway. */
1625 if (!arm_feature(env
, ARM_FEATURE_V6
))
1629 if (!arm_feature(env
, ARM_FEATURE_V7
))
1634 return env
->cp15
.c0_ccsid
[env
->cp15
.c0_cssel
];
1636 return env
->cp15
.c0_clid
;
1642 if (op2
!= 0 || crm
!= 0)
1644 return env
->cp15
.c0_cssel
;
1648 case 1: /* System configuration. */
1649 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1652 case 0: /* Control register. */
1653 return env
->cp15
.c1_sys
;
1654 case 1: /* Auxiliary control register. */
1655 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1656 return env
->cp15
.c1_xscaleauxcr
;
1657 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
1659 switch (ARM_CPUID(env
)) {
1660 case ARM_CPUID_ARM1026
:
1662 case ARM_CPUID_ARM1136
:
1663 case ARM_CPUID_ARM1136_R2
:
1665 case ARM_CPUID_ARM11MPCORE
:
1667 case ARM_CPUID_CORTEXA8
:
1669 case ARM_CPUID_CORTEXA9
:
1674 case 2: /* Coprocessor access register. */
1675 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1677 return env
->cp15
.c1_coproc
;
1681 case 2: /* MMU Page table control / MPU cache control. */
1682 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1685 return env
->cp15
.c2_data
;
1688 return env
->cp15
.c2_insn
;
1696 return env
->cp15
.c2_base0
;
1698 return env
->cp15
.c2_base1
;
1700 return env
->cp15
.c2_control
;
1705 case 3: /* MMU Domain access control / MPU write buffer control. */
1706 return env
->cp15
.c3
;
1707 case 4: /* Reserved. */
1709 case 5: /* MMU Fault status / MPU access permission. */
1710 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1714 if (arm_feature(env
, ARM_FEATURE_MPU
))
1715 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1716 return env
->cp15
.c5_data
;
1718 if (arm_feature(env
, ARM_FEATURE_MPU
))
1719 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1720 return env
->cp15
.c5_insn
;
1722 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1724 return env
->cp15
.c5_data
;
1726 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1728 return env
->cp15
.c5_insn
;
1732 case 6: /* MMU Fault address. */
1733 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1736 return env
->cp15
.c6_region
[crm
];
1738 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1742 return env
->cp15
.c6_data
;
1744 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1745 /* Watchpoint Fault Adrress. */
1746 return 0; /* Not implemented. */
1748 /* Instruction Fault Adrress. */
1749 /* Arm9 doesn't have an IFAR, but implementing it anyway
1750 shouldn't do any harm. */
1751 return env
->cp15
.c6_insn
;
1754 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1755 /* Instruction Fault Adrress. */
1756 return env
->cp15
.c6_insn
;
1764 case 7: /* Cache control. */
1765 /* FIXME: Should only clear Z flag if destination is r15. */
1768 case 8: /* MMU TLB control. */
1770 case 9: /* Cache lockdown. */
1772 case 0: /* L1 cache. */
1773 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1777 return env
->cp15
.c9_data
;
1779 return env
->cp15
.c9_insn
;
1783 case 1: /* L2 cache */
1786 /* L2 Lockdown and Auxiliary control. */
1791 case 10: /* MMU TLB lockdown. */
1792 /* ??? TLB lockdown not implemented. */
1794 case 11: /* TCM DMA control. */
1795 case 12: /* Reserved. */
1797 case 13: /* Process ID. */
1800 return env
->cp15
.c13_fcse
;
1802 return env
->cp15
.c13_context
;
1806 case 14: /* Reserved. */
1808 case 15: /* Implementation specific. */
1809 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1810 if (op2
== 0 && crm
== 1)
1811 return env
->cp15
.c15_cpar
;
1815 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1819 case 1: /* Read TI925T configuration. */
1820 return env
->cp15
.c15_ticonfig
;
1821 case 2: /* Read I_max. */
1822 return env
->cp15
.c15_i_max
;
1823 case 3: /* Read I_min. */
1824 return env
->cp15
.c15_i_min
;
1825 case 4: /* Read thread-ID. */
1826 return env
->cp15
.c15_threadid
;
1827 case 8: /* TI925T_status */
1830 /* TODO: Peripheral port remap register:
1831 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1832 * controller base address at $rn & ~0xfff and map size of
1833 * 0x200 << ($rn & 0xfff), when MMU is off. */
1839 /* ??? For debugging only. Should raise illegal instruction exception. */
1840 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1841 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1845 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
1847 env
->banked_r13
[bank_number(mode
)] = val
;
1850 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
1852 return env
->banked_r13
[bank_number(mode
)];
1855 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
1859 return xpsr_read(env
) & 0xf8000000;
1861 return xpsr_read(env
) & 0xf80001ff;
1863 return xpsr_read(env
) & 0xff00fc00;
1865 return xpsr_read(env
) & 0xff00fdff;
1867 return xpsr_read(env
) & 0x000001ff;
1869 return xpsr_read(env
) & 0x0700fc00;
1871 return xpsr_read(env
) & 0x0700edff;
1873 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
1875 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
1876 case 16: /* PRIMASK */
1877 return (env
->uncached_cpsr
& CPSR_I
) != 0;
1878 case 17: /* FAULTMASK */
1879 return (env
->uncached_cpsr
& CPSR_F
) != 0;
1880 case 18: /* BASEPRI */
1881 case 19: /* BASEPRI_MAX */
1882 return env
->v7m
.basepri
;
1883 case 20: /* CONTROL */
1884 return env
->v7m
.control
;
1886 /* ??? For debugging only. */
1887 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
1892 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
1896 xpsr_write(env
, val
, 0xf8000000);
1899 xpsr_write(env
, val
, 0xf8000000);
1902 xpsr_write(env
, val
, 0xfe00fc00);
1905 xpsr_write(env
, val
, 0xfe00fc00);
1908 /* IPSR bits are readonly. */
1911 xpsr_write(env
, val
, 0x0600fc00);
1914 xpsr_write(env
, val
, 0x0600fc00);
1917 if (env
->v7m
.current_sp
)
1918 env
->v7m
.other_sp
= val
;
1920 env
->regs
[13] = val
;
1923 if (env
->v7m
.current_sp
)
1924 env
->regs
[13] = val
;
1926 env
->v7m
.other_sp
= val
;
1928 case 16: /* PRIMASK */
1930 env
->uncached_cpsr
|= CPSR_I
;
1932 env
->uncached_cpsr
&= ~CPSR_I
;
1934 case 17: /* FAULTMASK */
1936 env
->uncached_cpsr
|= CPSR_F
;
1938 env
->uncached_cpsr
&= ~CPSR_F
;
1940 case 18: /* BASEPRI */
1941 env
->v7m
.basepri
= val
& 0xff;
1943 case 19: /* BASEPRI_MAX */
1945 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
1946 env
->v7m
.basepri
= val
;
1948 case 20: /* CONTROL */
1949 env
->v7m
.control
= val
& 3;
1950 switch_v7m_sp(env
, (val
& 2) != 0);
1953 /* ??? For debugging only. */
1954 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
1959 void cpu_arm_set_cp_io(CPUARMState
*env
, int cpnum
,
1960 ARMReadCPFunc
*cp_read
, ARMWriteCPFunc
*cp_write
,
1963 if (cpnum
< 0 || cpnum
> 14) {
1964 cpu_abort(env
, "Bad coprocessor number: %i\n", cpnum
);
1968 env
->cp
[cpnum
].cp_read
= cp_read
;
1969 env
->cp
[cpnum
].cp_write
= cp_write
;
1970 env
->cp
[cpnum
].opaque
= opaque
;
1975 /* Note that signed overflow is undefined in C. The following routines are
1976 careful to use unsigned types where modulo arithmetic is required.
1977 Failure to do so _will_ break on newer gcc. */
1979 /* Signed saturating arithmetic. */
1981 /* Perform 16-bit signed saturating addition. */
1982 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
1987 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
1996 /* Perform 8-bit signed saturating addition. */
1997 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2002 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2011 /* Perform 16-bit signed saturating subtraction. */
2012 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2017 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2026 /* Perform 8-bit signed saturating subtraction. */
2027 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2032 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2041 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2042 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2043 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2044 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2047 #include "op_addsub.h"
2049 /* Unsigned saturating arithmetic. */
2050 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2059 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2067 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2076 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2084 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2085 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2086 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2087 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2090 #include "op_addsub.h"
2092 /* Signed modulo arithmetic. */
2093 #define SARITH16(a, b, n, op) do { \
2095 sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
2096 RESULT(sum, n, 16); \
2098 ge |= 3 << (n * 2); \
2101 #define SARITH8(a, b, n, op) do { \
2103 sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
2104 RESULT(sum, n, 8); \
2110 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2111 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2112 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2113 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2117 #include "op_addsub.h"
2119 /* Unsigned modulo arithmetic. */
2120 #define ADD16(a, b, n) do { \
2122 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2123 RESULT(sum, n, 16); \
2124 if ((sum >> 16) == 1) \
2125 ge |= 3 << (n * 2); \
2128 #define ADD8(a, b, n) do { \
2130 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2131 RESULT(sum, n, 8); \
2132 if ((sum >> 8) == 1) \
2136 #define SUB16(a, b, n) do { \
2138 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2139 RESULT(sum, n, 16); \
2140 if ((sum >> 16) == 0) \
2141 ge |= 3 << (n * 2); \
2144 #define SUB8(a, b, n) do { \
2146 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2147 RESULT(sum, n, 8); \
2148 if ((sum >> 8) == 0) \
2155 #include "op_addsub.h"
2157 /* Halved signed arithmetic. */
2158 #define ADD16(a, b, n) \
2159 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2160 #define SUB16(a, b, n) \
2161 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2162 #define ADD8(a, b, n) \
2163 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2164 #define SUB8(a, b, n) \
2165 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2168 #include "op_addsub.h"
2170 /* Halved unsigned arithmetic. */
2171 #define ADD16(a, b, n) \
2172 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2173 #define SUB16(a, b, n) \
2174 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2175 #define ADD8(a, b, n) \
2176 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2177 #define SUB8(a, b, n) \
2178 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2181 #include "op_addsub.h"
2183 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2191 /* Unsigned sum of absolute byte differences. */
2192 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2195 sum
= do_usad(a
, b
);
2196 sum
+= do_usad(a
>> 8, b
>> 8);
2197 sum
+= do_usad(a
>> 16, b
>>16);
2198 sum
+= do_usad(a
>> 24, b
>> 24);
2202 /* For ARMv6 SEL instruction. */
2203 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2216 return (a
& mask
) | (b
& ~mask
);
2219 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2221 return (val
>> 32) | (val
!= 0);
2224 /* VFP support. We follow the convention used for VFP instrunctions:
2225 Single precition routines have a "s" suffix, double precision a
2228 /* Convert host exception flags to vfp form. */
2229 static inline int vfp_exceptbits_from_host(int host_bits
)
2231 int target_bits
= 0;
2233 if (host_bits
& float_flag_invalid
)
2235 if (host_bits
& float_flag_divbyzero
)
2237 if (host_bits
& float_flag_overflow
)
2239 if (host_bits
& float_flag_underflow
)
2241 if (host_bits
& float_flag_inexact
)
2242 target_bits
|= 0x10;
2246 uint32_t HELPER(vfp_get_fpscr
)(CPUState
*env
)
2251 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2252 | (env
->vfp
.vec_len
<< 16)
2253 | (env
->vfp
.vec_stride
<< 20);
2254 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2255 fpscr
|= vfp_exceptbits_from_host(i
);
2259 uint32_t vfp_get_fpscr(CPUState
*env
)
2261 return HELPER(vfp_get_fpscr
)(env
);
2264 /* Convert vfp exception flags to target form. */
2265 static inline int vfp_exceptbits_to_host(int target_bits
)
2269 if (target_bits
& 1)
2270 host_bits
|= float_flag_invalid
;
2271 if (target_bits
& 2)
2272 host_bits
|= float_flag_divbyzero
;
2273 if (target_bits
& 4)
2274 host_bits
|= float_flag_overflow
;
2275 if (target_bits
& 8)
2276 host_bits
|= float_flag_underflow
;
2277 if (target_bits
& 0x10)
2278 host_bits
|= float_flag_inexact
;
2282 void HELPER(vfp_set_fpscr
)(CPUState
*env
, uint32_t val
)
2287 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2288 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2289 env
->vfp
.vec_len
= (val
>> 16) & 7;
2290 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2293 if (changed
& (3 << 22)) {
2294 i
= (val
>> 22) & 3;
2297 i
= float_round_nearest_even
;
2303 i
= float_round_down
;
2306 i
= float_round_to_zero
;
2309 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2311 if (changed
& (1 << 24))
2312 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2313 if (changed
& (1 << 25))
2314 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
2316 i
= vfp_exceptbits_to_host((val
>> 8) & 0x1f);
2317 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2320 void vfp_set_fpscr(CPUState
*env
, uint32_t val
)
2322 HELPER(vfp_set_fpscr
)(env
, val
);
2325 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2327 #define VFP_BINOP(name) \
2328 float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2330 return float32_ ## name (a, b, &env->vfp.fp_status); \
2332 float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2334 return float64_ ## name (a, b, &env->vfp.fp_status); \
2342 float32
VFP_HELPER(neg
, s
)(float32 a
)
2344 return float32_chs(a
);
2347 float64
VFP_HELPER(neg
, d
)(float64 a
)
2349 return float64_chs(a
);
2352 float32
VFP_HELPER(abs
, s
)(float32 a
)
2354 return float32_abs(a
);
2357 float64
VFP_HELPER(abs
, d
)(float64 a
)
2359 return float64_abs(a
);
2362 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUState
*env
)
2364 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2367 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUState
*env
)
2369 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2372 /* XXX: check quiet/signaling case */
2373 #define DO_VFP_cmp(p, type) \
2374 void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2377 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2378 case 0: flags = 0x6; break; \
2379 case -1: flags = 0x8; break; \
2380 case 1: flags = 0x2; break; \
2381 default: case 2: flags = 0x3; break; \
2383 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2384 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2386 void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2389 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2390 case 0: flags = 0x6; break; \
2391 case -1: flags = 0x8; break; \
2392 case 1: flags = 0x2; break; \
2393 default: case 2: flags = 0x3; break; \
2395 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2396 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2398 DO_VFP_cmp(s
, float32
)
2399 DO_VFP_cmp(d
, float64
)
2402 /* Helper routines to perform bitwise copies between float and int. */
2403 static inline float32
vfp_itos(uint32_t i
)
2414 static inline uint32_t vfp_stoi(float32 s
)
2425 static inline float64
vfp_itod(uint64_t i
)
2436 static inline uint64_t vfp_dtoi(float64 d
)
2447 /* Integer to float conversion. */
2448 float32
VFP_HELPER(uito
, s
)(float32 x
, CPUState
*env
)
2450 return uint32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2453 float64
VFP_HELPER(uito
, d
)(float32 x
, CPUState
*env
)
2455 return uint32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2458 float32
VFP_HELPER(sito
, s
)(float32 x
, CPUState
*env
)
2460 return int32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2463 float64
VFP_HELPER(sito
, d
)(float32 x
, CPUState
*env
)
2465 return int32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2468 /* Float to integer conversion. */
2469 float32
VFP_HELPER(toui
, s
)(float32 x
, CPUState
*env
)
2471 if (float32_is_any_nan(x
)) {
2472 return float32_zero
;
2474 return vfp_itos(float32_to_uint32(x
, &env
->vfp
.fp_status
));
2477 float32
VFP_HELPER(toui
, d
)(float64 x
, CPUState
*env
)
2479 if (float64_is_any_nan(x
)) {
2480 return float32_zero
;
2482 return vfp_itos(float64_to_uint32(x
, &env
->vfp
.fp_status
));
2485 float32
VFP_HELPER(tosi
, s
)(float32 x
, CPUState
*env
)
2487 if (float32_is_any_nan(x
)) {
2488 return float32_zero
;
2490 return vfp_itos(float32_to_int32(x
, &env
->vfp
.fp_status
));
2493 float32
VFP_HELPER(tosi
, d
)(float64 x
, CPUState
*env
)
2495 if (float64_is_any_nan(x
)) {
2496 return float32_zero
;
2498 return vfp_itos(float64_to_int32(x
, &env
->vfp
.fp_status
));
2501 float32
VFP_HELPER(touiz
, s
)(float32 x
, CPUState
*env
)
2503 if (float32_is_any_nan(x
)) {
2504 return float32_zero
;
2506 return vfp_itos(float32_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2509 float32
VFP_HELPER(touiz
, d
)(float64 x
, CPUState
*env
)
2511 if (float64_is_any_nan(x
)) {
2512 return float32_zero
;
2514 return vfp_itos(float64_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2517 float32
VFP_HELPER(tosiz
, s
)(float32 x
, CPUState
*env
)
2519 if (float32_is_any_nan(x
)) {
2520 return float32_zero
;
2522 return vfp_itos(float32_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2525 float32
VFP_HELPER(tosiz
, d
)(float64 x
, CPUState
*env
)
2527 if (float64_is_any_nan(x
)) {
2528 return float32_zero
;
2530 return vfp_itos(float64_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2533 /* floating point conversion */
2534 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUState
*env
)
2536 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
2537 /* ARM requires that S<->D conversion of any kind of NaN generates
2538 * a quiet NaN by forcing the most significant frac bit to 1.
2540 return float64_maybe_silence_nan(r
);
2543 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUState
*env
)
2545 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
2546 /* ARM requires that S<->D conversion of any kind of NaN generates
2547 * a quiet NaN by forcing the most significant frac bit to 1.
2549 return float32_maybe_silence_nan(r
);
2552 /* VFP3 fixed point conversion. */
2553 #define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2554 ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2557 tmp = sign##int32_to_##ftype ((itype##_t)vfp_##p##toi(x), \
2558 &env->vfp.fp_status); \
2559 return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \
2561 ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2564 if (ftype##_is_any_nan(x)) { \
2565 return ftype##_zero; \
2567 tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
2568 return vfp_ito##p(ftype##_to_##itype##_round_to_zero(tmp, \
2569 &env->vfp.fp_status)); \
2572 VFP_CONV_FIX(sh
, d
, float64
, int16
, )
2573 VFP_CONV_FIX(sl
, d
, float64
, int32
, )
2574 VFP_CONV_FIX(uh
, d
, float64
, uint16
, u
)
2575 VFP_CONV_FIX(ul
, d
, float64
, uint32
, u
)
2576 VFP_CONV_FIX(sh
, s
, float32
, int16
, )
2577 VFP_CONV_FIX(sl
, s
, float32
, int32
, )
2578 VFP_CONV_FIX(uh
, s
, float32
, uint16
, u
)
2579 VFP_CONV_FIX(ul
, s
, float32
, uint32
, u
)
2582 /* Half precision conversions. */
2583 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUState
*env
)
2585 float_status
*s
= &env
->vfp
.fp_status
;
2586 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2587 return float16_to_float32(a
, ieee
, s
);
2590 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUState
*env
)
2592 float_status
*s
= &env
->vfp
.fp_status
;
2593 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2594 return float32_to_float16(a
, ieee
, s
);
2597 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUState
*env
)
2599 float_status
*s
= &env
->vfp
.fp_status
;
2600 float32 two
= int32_to_float32(2, s
);
2601 return float32_sub(two
, float32_mul(a
, b
, s
), s
);
2604 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUState
*env
)
2606 float_status
*s
= &env
->vfp
.fp_status
;
2607 float32 three
= int32_to_float32(3, s
);
2608 return float32_sub(three
, float32_mul(a
, b
, s
), s
);
2613 /* TODO: The architecture specifies the value that the estimate functions
2614 should return. We return the exact reciprocal/root instead. */
2615 float32
HELPER(recpe_f32
)(float32 a
, CPUState
*env
)
2617 float_status
*s
= &env
->vfp
.fp_status
;
2618 float32 one
= int32_to_float32(1, s
);
2619 return float32_div(one
, a
, s
);
2622 float32
HELPER(rsqrte_f32
)(float32 a
, CPUState
*env
)
2624 float_status
*s
= &env
->vfp
.fp_status
;
2625 float32 one
= int32_to_float32(1, s
);
2626 return float32_div(one
, float32_sqrt(a
, s
), s
);
2629 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUState
*env
)
2631 float_status
*s
= &env
->vfp
.fp_status
;
2633 tmp
= int32_to_float32(a
, s
);
2634 tmp
= float32_scalbn(tmp
, -32, s
);
2635 tmp
= helper_recpe_f32(tmp
, env
);
2636 tmp
= float32_scalbn(tmp
, 31, s
);
2637 return float32_to_int32(tmp
, s
);
2640 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUState
*env
)
2642 float_status
*s
= &env
->vfp
.fp_status
;
2644 tmp
= int32_to_float32(a
, s
);
2645 tmp
= float32_scalbn(tmp
, -32, s
);
2646 tmp
= helper_rsqrte_f32(tmp
, env
);
2647 tmp
= float32_scalbn(tmp
, 31, s
);
2648 return float32_to_int32(tmp
, s
);
2651 void HELPER(set_teecr
)(CPUState
*env
, uint32_t val
)
2654 if (env
->teecr
!= val
) {