2 * QEMU VMWARE VMXNET3 paravirtual NIC
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
19 #include "hw/pci/pci.h"
22 #include "net/checksum.h"
23 #include "sysemu/sysemu.h"
24 #include "qemu-common.h"
25 #include "qemu/bswap.h"
26 #include "hw/pci/msix.h"
27 #include "hw/pci/msi.h"
30 #include "vmxnet_debug.h"
31 #include "vmware_utils.h"
32 #include "vmxnet_tx_pkt.h"
33 #include "vmxnet_rx_pkt.h"
35 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
36 #define VMXNET3_MSIX_BAR_SIZE 0x2000
37 #define MIN_BUF_SIZE 60
39 /* Compatability flags for migration */
40 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0
41 #define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \
42 (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT)
44 #define VMXNET3_MSI_OFFSET(s) \
45 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84)
46 #define VMXNET3_MSIX_OFFSET(s) \
47 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c)
49 #define VMXNET3_BAR0_IDX (0)
50 #define VMXNET3_BAR1_IDX (1)
51 #define VMXNET3_MSIX_BAR_IDX (2)
53 #define VMXNET3_OFF_MSIX_TABLE (0x000)
54 #define VMXNET3_OFF_MSIX_PBA(s) \
55 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000)
57 /* Link speed in Mbps should be shifted by 16 */
58 #define VMXNET3_LINK_SPEED (1000 << 16)
60 /* Link status: 1 - up, 0 - down. */
61 #define VMXNET3_LINK_STATUS_UP 0x1
63 /* Least significant bit should be set for revision and version */
64 #define VMXNET3_UPT_REVISION 0x1
65 #define VMXNET3_DEVICE_REVISION 0x1
67 /* Number of interrupt vectors for non-MSIx modes */
68 #define VMXNET3_MAX_NMSIX_INTRS (1)
70 /* Macros for rings descriptors access */
71 #define VMXNET3_READ_TX_QUEUE_DESCR8(dpa, field) \
72 (vmw_shmem_ld8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
74 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(dpa, field, value) \
75 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
77 #define VMXNET3_READ_TX_QUEUE_DESCR32(dpa, field) \
78 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
80 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(dpa, field, value) \
81 (vmw_shmem_st32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
83 #define VMXNET3_READ_TX_QUEUE_DESCR64(dpa, field) \
84 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
86 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(dpa, field, value) \
87 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
89 #define VMXNET3_READ_RX_QUEUE_DESCR64(dpa, field) \
90 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
92 #define VMXNET3_READ_RX_QUEUE_DESCR32(dpa, field) \
93 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
95 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(dpa, field, value) \
96 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
98 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(dpa, field, value) \
99 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
101 /* Macros for guest driver shared area access */
102 #define VMXNET3_READ_DRV_SHARED64(shpa, field) \
103 (vmw_shmem_ld64(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
105 #define VMXNET3_READ_DRV_SHARED32(shpa, field) \
106 (vmw_shmem_ld32(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
108 #define VMXNET3_WRITE_DRV_SHARED32(shpa, field, val) \
109 (vmw_shmem_st32(shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
111 #define VMXNET3_READ_DRV_SHARED16(shpa, field) \
112 (vmw_shmem_ld16(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
114 #define VMXNET3_READ_DRV_SHARED8(shpa, field) \
115 (vmw_shmem_ld8(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
117 #define VMXNET3_READ_DRV_SHARED(shpa, field, b, l) \
118 (vmw_shmem_read(shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
120 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
122 #define TYPE_VMXNET3 "vmxnet3"
123 #define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3)
125 /* Cyclic ring abstraction */
134 static inline void vmxnet3_ring_init(Vmxnet3Ring
*ring
,
142 ring
->cell_size
= cell_size
;
143 ring
->gen
= VMXNET3_INIT_GEN
;
147 vmw_shmem_set(pa
, 0, size
* cell_size
);
151 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
152 macro("%s#%d: base %" PRIx64 " size %zu cell_size %zu gen %d next %zu", \
153 (ring_name), (ridx), \
154 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
156 static inline void vmxnet3_ring_inc(Vmxnet3Ring
*ring
)
158 if (++ring
->next
>= ring
->size
) {
164 static inline void vmxnet3_ring_dec(Vmxnet3Ring
*ring
)
166 if (ring
->next
-- == 0) {
167 ring
->next
= ring
->size
- 1;
172 static inline hwaddr
vmxnet3_ring_curr_cell_pa(Vmxnet3Ring
*ring
)
174 return ring
->pa
+ ring
->next
* ring
->cell_size
;
177 static inline void vmxnet3_ring_read_curr_cell(Vmxnet3Ring
*ring
, void *buff
)
179 vmw_shmem_read(vmxnet3_ring_curr_cell_pa(ring
), buff
, ring
->cell_size
);
182 static inline void vmxnet3_ring_write_curr_cell(Vmxnet3Ring
*ring
, void *buff
)
184 vmw_shmem_write(vmxnet3_ring_curr_cell_pa(ring
), buff
, ring
->cell_size
);
187 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring
*ring
)
192 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring
*ring
)
197 /* Debug trace-related functions */
199 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc
*descr
)
201 VMW_PKPRN("TX DESCR: "
202 "addr %" PRIx64
", len: %d, gen: %d, rsvd: %d, "
203 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
204 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
205 le64_to_cpu(descr
->addr
), descr
->len
, descr
->gen
, descr
->rsvd
,
206 descr
->dtype
, descr
->ext1
, descr
->msscof
, descr
->hlen
, descr
->om
,
207 descr
->eop
, descr
->cq
, descr
->ext2
, descr
->ti
, descr
->tci
);
211 vmxnet3_dump_virt_hdr(struct virtio_net_hdr
*vhdr
)
213 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
214 "csum_start: %d, csum_offset: %d",
215 vhdr
->flags
, vhdr
->gso_type
, vhdr
->hdr_len
, vhdr
->gso_size
,
216 vhdr
->csum_start
, vhdr
->csum_offset
);
220 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc
*descr
)
222 VMW_PKPRN("RX DESCR: addr %" PRIx64
", len: %d, gen: %d, rsvd: %d, "
223 "dtype: %d, ext1: %d, btype: %d",
224 le64_to_cpu(descr
->addr
), descr
->len
, descr
->gen
,
225 descr
->rsvd
, descr
->dtype
, descr
->ext1
, descr
->btype
);
228 /* Device state and helper functions */
229 #define VMXNET3_RX_RINGS_PER_QUEUE (2)
233 Vmxnet3Ring comp_ring
;
237 struct UPT1_TxStats txq_stats
;
241 Vmxnet3Ring rx_ring
[VMXNET3_RX_RINGS_PER_QUEUE
];
242 Vmxnet3Ring comp_ring
;
245 struct UPT1_RxStats rxq_stats
;
255 PCIDevice parent_obj
;
260 MemoryRegion msix_bar
;
262 Vmxnet3RxqDescr rxq_descr
[VMXNET3_DEVICE_MAX_RX_QUEUES
];
263 Vmxnet3TxqDescr txq_descr
[VMXNET3_DEVICE_MAX_TX_QUEUES
];
265 /* Whether MSI-X support was installed successfully */
267 /* Whether MSI support was installed successfully */
270 hwaddr temp_shared_guest_driver_memory
;
274 /* This boolean tells whether RX packet being indicated has to */
275 /* be split into head and body chunks from different RX rings */
276 bool rx_packets_compound
;
278 bool rx_vlan_stripping
;
286 /* Maximum number of fragments for indicated TX packets */
287 uint32_t max_tx_frags
;
289 /* Maximum number of fragments for indicated RX packets */
290 uint16_t max_rx_frags
;
292 /* Index for events interrupt */
293 uint8_t event_int_idx
;
295 /* Whether automatic interrupts masking enabled */
296 bool auto_int_masking
;
300 /* TX packets to QEMU interface */
301 struct VmxnetTxPkt
*tx_pkt
;
302 uint32_t offload_mode
;
303 uint32_t cso_or_gso_size
;
307 struct VmxnetRxPkt
*rx_pkt
;
310 bool skip_current_tx_pkt
;
312 uint32_t device_active
;
313 uint32_t last_command
;
315 uint32_t link_status_and_speed
;
317 Vmxnet3IntState interrupt_states
[VMXNET3_MAX_INTRS
];
319 uint32_t temp_mac
; /* To store the low part first */
322 uint32_t vlan_table
[VMXNET3_VFT_SIZE
];
325 uint32_t mcast_list_len
;
326 uint32_t mcast_list_buff_size
; /* needed for live migration. */
328 /* Compatability flags for migration */
329 uint32_t compat_flags
;
332 /* Interrupt management */
335 *This function returns sign whether interrupt line is in asserted state
336 * This depends on the type of interrupt used. For INTX interrupt line will
337 * be asserted until explicit deassertion, for MSI(X) interrupt line will
338 * be deasserted automatically due to notification semantics of the MSI(X)
341 static bool _vmxnet3_assert_interrupt_line(VMXNET3State
*s
, uint32_t int_idx
)
343 PCIDevice
*d
= PCI_DEVICE(s
);
345 if (s
->msix_used
&& msix_enabled(d
)) {
346 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx
);
347 msix_notify(d
, int_idx
);
350 if (s
->msi_used
&& msi_enabled(d
)) {
351 VMW_IRPRN("Sending MSI notification for vector %u", int_idx
);
352 msi_notify(d
, int_idx
);
356 VMW_IRPRN("Asserting line for interrupt %u", int_idx
);
361 static void _vmxnet3_deassert_interrupt_line(VMXNET3State
*s
, int lidx
)
363 PCIDevice
*d
= PCI_DEVICE(s
);
366 * This function should never be called for MSI(X) interrupts
367 * because deassertion never required for message interrupts
369 assert(!s
->msix_used
|| !msix_enabled(d
));
371 * This function should never be called for MSI(X) interrupts
372 * because deassertion never required for message interrupts
374 assert(!s
->msi_used
|| !msi_enabled(d
));
376 VMW_IRPRN("Deasserting line for interrupt %u", lidx
);
380 static void vmxnet3_update_interrupt_line_state(VMXNET3State
*s
, int lidx
)
382 if (!s
->interrupt_states
[lidx
].is_pending
&&
383 s
->interrupt_states
[lidx
].is_asserted
) {
384 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx
);
385 _vmxnet3_deassert_interrupt_line(s
, lidx
);
386 s
->interrupt_states
[lidx
].is_asserted
= false;
390 if (s
->interrupt_states
[lidx
].is_pending
&&
391 !s
->interrupt_states
[lidx
].is_masked
&&
392 !s
->interrupt_states
[lidx
].is_asserted
) {
393 VMW_IRPRN("New interrupt line state for index %d is UP", lidx
);
394 s
->interrupt_states
[lidx
].is_asserted
=
395 _vmxnet3_assert_interrupt_line(s
, lidx
);
396 s
->interrupt_states
[lidx
].is_pending
= false;
401 static void vmxnet3_trigger_interrupt(VMXNET3State
*s
, int lidx
)
403 PCIDevice
*d
= PCI_DEVICE(s
);
404 s
->interrupt_states
[lidx
].is_pending
= true;
405 vmxnet3_update_interrupt_line_state(s
, lidx
);
407 if (s
->msix_used
&& msix_enabled(d
) && s
->auto_int_masking
) {
411 if (s
->msi_used
&& msi_enabled(d
) && s
->auto_int_masking
) {
418 s
->interrupt_states
[lidx
].is_masked
= true;
419 vmxnet3_update_interrupt_line_state(s
, lidx
);
422 static bool vmxnet3_interrupt_asserted(VMXNET3State
*s
, int lidx
)
424 return s
->interrupt_states
[lidx
].is_asserted
;
427 static void vmxnet3_clear_interrupt(VMXNET3State
*s
, int int_idx
)
429 s
->interrupt_states
[int_idx
].is_pending
= false;
430 if (s
->auto_int_masking
) {
431 s
->interrupt_states
[int_idx
].is_masked
= true;
433 vmxnet3_update_interrupt_line_state(s
, int_idx
);
437 vmxnet3_on_interrupt_mask_changed(VMXNET3State
*s
, int lidx
, bool is_masked
)
439 s
->interrupt_states
[lidx
].is_masked
= is_masked
;
440 vmxnet3_update_interrupt_line_state(s
, lidx
);
443 static bool vmxnet3_verify_driver_magic(hwaddr dshmem
)
445 return (VMXNET3_READ_DRV_SHARED32(dshmem
, magic
) == VMXNET3_REV1_MAGIC
);
448 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
449 #define VMXNET3_MAKE_BYTE(byte_num, val) \
450 (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
452 static void vmxnet3_set_variable_mac(VMXNET3State
*s
, uint32_t h
, uint32_t l
)
454 s
->conf
.macaddr
.a
[0] = VMXNET3_GET_BYTE(l
, 0);
455 s
->conf
.macaddr
.a
[1] = VMXNET3_GET_BYTE(l
, 1);
456 s
->conf
.macaddr
.a
[2] = VMXNET3_GET_BYTE(l
, 2);
457 s
->conf
.macaddr
.a
[3] = VMXNET3_GET_BYTE(l
, 3);
458 s
->conf
.macaddr
.a
[4] = VMXNET3_GET_BYTE(h
, 0);
459 s
->conf
.macaddr
.a
[5] = VMXNET3_GET_BYTE(h
, 1);
461 VMW_CFPRN("Variable MAC: " VMXNET_MF
, VMXNET_MA(s
->conf
.macaddr
.a
));
463 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
466 static uint64_t vmxnet3_get_mac_low(MACAddr
*addr
)
468 return VMXNET3_MAKE_BYTE(0, addr
->a
[0]) |
469 VMXNET3_MAKE_BYTE(1, addr
->a
[1]) |
470 VMXNET3_MAKE_BYTE(2, addr
->a
[2]) |
471 VMXNET3_MAKE_BYTE(3, addr
->a
[3]);
474 static uint64_t vmxnet3_get_mac_high(MACAddr
*addr
)
476 return VMXNET3_MAKE_BYTE(0, addr
->a
[4]) |
477 VMXNET3_MAKE_BYTE(1, addr
->a
[5]);
481 vmxnet3_inc_tx_consumption_counter(VMXNET3State
*s
, int qidx
)
483 vmxnet3_ring_inc(&s
->txq_descr
[qidx
].tx_ring
);
487 vmxnet3_inc_rx_consumption_counter(VMXNET3State
*s
, int qidx
, int ridx
)
489 vmxnet3_ring_inc(&s
->rxq_descr
[qidx
].rx_ring
[ridx
]);
493 vmxnet3_inc_tx_completion_counter(VMXNET3State
*s
, int qidx
)
495 vmxnet3_ring_inc(&s
->txq_descr
[qidx
].comp_ring
);
499 vmxnet3_inc_rx_completion_counter(VMXNET3State
*s
, int qidx
)
501 vmxnet3_ring_inc(&s
->rxq_descr
[qidx
].comp_ring
);
505 vmxnet3_dec_rx_completion_counter(VMXNET3State
*s
, int qidx
)
507 vmxnet3_ring_dec(&s
->rxq_descr
[qidx
].comp_ring
);
510 static void vmxnet3_complete_packet(VMXNET3State
*s
, int qidx
, uint32 tx_ridx
)
512 struct Vmxnet3_TxCompDesc txcq_descr
;
514 VMXNET3_RING_DUMP(VMW_RIPRN
, "TXC", qidx
, &s
->txq_descr
[qidx
].comp_ring
);
516 txcq_descr
.txdIdx
= tx_ridx
;
517 txcq_descr
.gen
= vmxnet3_ring_curr_gen(&s
->txq_descr
[qidx
].comp_ring
);
519 vmxnet3_ring_write_curr_cell(&s
->txq_descr
[qidx
].comp_ring
, &txcq_descr
);
521 /* Flush changes in TX descriptor before changing the counter value */
524 vmxnet3_inc_tx_completion_counter(s
, qidx
);
525 vmxnet3_trigger_interrupt(s
, s
->txq_descr
[qidx
].intr_idx
);
529 vmxnet3_setup_tx_offloads(VMXNET3State
*s
)
531 switch (s
->offload_mode
) {
532 case VMXNET3_OM_NONE
:
533 vmxnet_tx_pkt_build_vheader(s
->tx_pkt
, false, false, 0);
536 case VMXNET3_OM_CSUM
:
537 vmxnet_tx_pkt_build_vheader(s
->tx_pkt
, false, true, 0);
538 VMW_PKPRN("L4 CSO requested\n");
542 vmxnet_tx_pkt_build_vheader(s
->tx_pkt
, true, true,
544 vmxnet_tx_pkt_update_ip_checksums(s
->tx_pkt
);
545 VMW_PKPRN("GSO offload requested.");
549 g_assert_not_reached();
557 vmxnet3_tx_retrieve_metadata(VMXNET3State
*s
,
558 const struct Vmxnet3_TxDesc
*txd
)
560 s
->offload_mode
= txd
->om
;
561 s
->cso_or_gso_size
= txd
->msscof
;
563 s
->needs_vlan
= txd
->ti
;
567 VMXNET3_PKT_STATUS_OK
,
568 VMXNET3_PKT_STATUS_ERROR
,
569 VMXNET3_PKT_STATUS_DISCARD
,/* only for tx */
570 VMXNET3_PKT_STATUS_OUT_OF_BUF
/* only for rx */
574 vmxnet3_on_tx_done_update_stats(VMXNET3State
*s
, int qidx
,
575 Vmxnet3PktStatus status
)
577 size_t tot_len
= vmxnet_tx_pkt_get_total_len(s
->tx_pkt
);
578 struct UPT1_TxStats
*stats
= &s
->txq_descr
[qidx
].txq_stats
;
581 case VMXNET3_PKT_STATUS_OK
:
582 switch (vmxnet_tx_pkt_get_packet_type(s
->tx_pkt
)) {
584 stats
->bcastPktsTxOK
++;
585 stats
->bcastBytesTxOK
+= tot_len
;
588 stats
->mcastPktsTxOK
++;
589 stats
->mcastBytesTxOK
+= tot_len
;
592 stats
->ucastPktsTxOK
++;
593 stats
->ucastBytesTxOK
+= tot_len
;
596 g_assert_not_reached();
599 if (s
->offload_mode
== VMXNET3_OM_TSO
) {
601 * According to VMWARE headers this statistic is a number
602 * of packets after segmentation but since we don't have
603 * this information in QEMU model, the best we can do is to
604 * provide number of non-segmented packets
606 stats
->TSOPktsTxOK
++;
607 stats
->TSOBytesTxOK
+= tot_len
;
611 case VMXNET3_PKT_STATUS_DISCARD
:
612 stats
->pktsTxDiscard
++;
615 case VMXNET3_PKT_STATUS_ERROR
:
616 stats
->pktsTxError
++;
620 g_assert_not_reached();
625 vmxnet3_on_rx_done_update_stats(VMXNET3State
*s
,
627 Vmxnet3PktStatus status
)
629 struct UPT1_RxStats
*stats
= &s
->rxq_descr
[qidx
].rxq_stats
;
630 size_t tot_len
= vmxnet_rx_pkt_get_total_len(s
->rx_pkt
);
633 case VMXNET3_PKT_STATUS_OUT_OF_BUF
:
634 stats
->pktsRxOutOfBuf
++;
637 case VMXNET3_PKT_STATUS_ERROR
:
638 stats
->pktsRxError
++;
640 case VMXNET3_PKT_STATUS_OK
:
641 switch (vmxnet_rx_pkt_get_packet_type(s
->rx_pkt
)) {
643 stats
->bcastPktsRxOK
++;
644 stats
->bcastBytesRxOK
+= tot_len
;
647 stats
->mcastPktsRxOK
++;
648 stats
->mcastBytesRxOK
+= tot_len
;
651 stats
->ucastPktsRxOK
++;
652 stats
->ucastBytesRxOK
+= tot_len
;
655 g_assert_not_reached();
658 if (tot_len
> s
->mtu
) {
659 stats
->LROPktsRxOK
++;
660 stats
->LROBytesRxOK
+= tot_len
;
664 g_assert_not_reached();
669 vmxnet3_pop_next_tx_descr(VMXNET3State
*s
,
671 struct Vmxnet3_TxDesc
*txd
,
674 Vmxnet3Ring
*ring
= &s
->txq_descr
[qidx
].tx_ring
;
676 vmxnet3_ring_read_curr_cell(ring
, txd
);
677 if (txd
->gen
== vmxnet3_ring_curr_gen(ring
)) {
678 /* Only read after generation field verification */
680 /* Re-read to be sure we got the latest version */
681 vmxnet3_ring_read_curr_cell(ring
, txd
);
682 VMXNET3_RING_DUMP(VMW_RIPRN
, "TX", qidx
, ring
);
683 *descr_idx
= vmxnet3_ring_curr_cell_idx(ring
);
684 vmxnet3_inc_tx_consumption_counter(s
, qidx
);
692 vmxnet3_send_packet(VMXNET3State
*s
, uint32_t qidx
)
694 Vmxnet3PktStatus status
= VMXNET3_PKT_STATUS_OK
;
696 if (!vmxnet3_setup_tx_offloads(s
)) {
697 status
= VMXNET3_PKT_STATUS_ERROR
;
702 vmxnet3_dump_virt_hdr(vmxnet_tx_pkt_get_vhdr(s
->tx_pkt
));
703 vmxnet_tx_pkt_dump(s
->tx_pkt
);
705 if (!vmxnet_tx_pkt_send(s
->tx_pkt
, qemu_get_queue(s
->nic
))) {
706 status
= VMXNET3_PKT_STATUS_DISCARD
;
711 vmxnet3_on_tx_done_update_stats(s
, qidx
, status
);
712 return (status
== VMXNET3_PKT_STATUS_OK
);
715 static void vmxnet3_process_tx_queue(VMXNET3State
*s
, int qidx
)
717 struct Vmxnet3_TxDesc txd
;
723 if (!vmxnet3_pop_next_tx_descr(s
, qidx
, &txd
, &txd_idx
)) {
727 vmxnet3_dump_tx_descr(&txd
);
729 if (!s
->skip_current_tx_pkt
) {
730 data_len
= (txd
.len
> 0) ? txd
.len
: VMXNET3_MAX_TX_BUF_SIZE
;
731 data_pa
= le64_to_cpu(txd
.addr
);
733 if (!vmxnet_tx_pkt_add_raw_fragment(s
->tx_pkt
,
736 s
->skip_current_tx_pkt
= true;
741 vmxnet3_tx_retrieve_metadata(s
, &txd
);
746 if (!s
->skip_current_tx_pkt
&& vmxnet_tx_pkt_parse(s
->tx_pkt
)) {
748 vmxnet_tx_pkt_setup_vlan_header(s
->tx_pkt
, s
->tci
);
751 vmxnet3_send_packet(s
, qidx
);
753 vmxnet3_on_tx_done_update_stats(s
, qidx
,
754 VMXNET3_PKT_STATUS_ERROR
);
757 vmxnet3_complete_packet(s
, qidx
, txd_idx
);
759 s
->skip_current_tx_pkt
= false;
760 vmxnet_tx_pkt_reset(s
->tx_pkt
);
766 vmxnet3_read_next_rx_descr(VMXNET3State
*s
, int qidx
, int ridx
,
767 struct Vmxnet3_RxDesc
*dbuf
, uint32_t *didx
)
769 Vmxnet3Ring
*ring
= &s
->rxq_descr
[qidx
].rx_ring
[ridx
];
770 *didx
= vmxnet3_ring_curr_cell_idx(ring
);
771 vmxnet3_ring_read_curr_cell(ring
, dbuf
);
774 static inline uint8_t
775 vmxnet3_get_rx_ring_gen(VMXNET3State
*s
, int qidx
, int ridx
)
777 return s
->rxq_descr
[qidx
].rx_ring
[ridx
].gen
;
781 vmxnet3_pop_rxc_descr(VMXNET3State
*s
, int qidx
, uint32_t *descr_gen
)
784 struct Vmxnet3_RxCompDesc rxcd
;
787 vmxnet3_ring_curr_cell_pa(&s
->rxq_descr
[qidx
].comp_ring
);
789 cpu_physical_memory_read(daddr
, &rxcd
, sizeof(struct Vmxnet3_RxCompDesc
));
790 ring_gen
= vmxnet3_ring_curr_gen(&s
->rxq_descr
[qidx
].comp_ring
);
792 if (rxcd
.gen
!= ring_gen
) {
793 *descr_gen
= ring_gen
;
794 vmxnet3_inc_rx_completion_counter(s
, qidx
);
802 vmxnet3_revert_rxc_descr(VMXNET3State
*s
, int qidx
)
804 vmxnet3_dec_rx_completion_counter(s
, qidx
);
808 #define RX_HEAD_BODY_RING (0)
809 #define RX_BODY_ONLY_RING (1)
812 vmxnet3_get_next_head_rx_descr(VMXNET3State
*s
,
813 struct Vmxnet3_RxDesc
*descr_buf
,
819 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
,
820 descr_buf
, descr_idx
);
822 /* If no more free descriptors - return */
823 ring_gen
= vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
824 if (descr_buf
->gen
!= ring_gen
) {
828 /* Only read after generation field verification */
830 /* Re-read to be sure we got the latest version */
831 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
,
832 descr_buf
, descr_idx
);
834 /* Mark current descriptor as used/skipped */
835 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
837 /* If this is what we are looking for - return */
838 if (descr_buf
->btype
== VMXNET3_RXD_BTYPE_HEAD
) {
839 *ridx
= RX_HEAD_BODY_RING
;
846 vmxnet3_get_next_body_rx_descr(VMXNET3State
*s
,
847 struct Vmxnet3_RxDesc
*d
,
851 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
, d
, didx
);
853 /* Try to find corresponding descriptor in head/body ring */
854 if (d
->gen
== vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_HEAD_BODY_RING
)) {
855 /* Only read after generation field verification */
857 /* Re-read to be sure we got the latest version */
858 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_HEAD_BODY_RING
, d
, didx
);
859 if (d
->btype
== VMXNET3_RXD_BTYPE_BODY
) {
860 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_HEAD_BODY_RING
);
861 *ridx
= RX_HEAD_BODY_RING
;
867 * If there is no free descriptors on head/body ring or next free
868 * descriptor is a head descriptor switch to body only ring
870 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_BODY_ONLY_RING
, d
, didx
);
872 /* If no more free descriptors - return */
873 if (d
->gen
== vmxnet3_get_rx_ring_gen(s
, RXQ_IDX
, RX_BODY_ONLY_RING
)) {
874 /* Only read after generation field verification */
876 /* Re-read to be sure we got the latest version */
877 vmxnet3_read_next_rx_descr(s
, RXQ_IDX
, RX_BODY_ONLY_RING
, d
, didx
);
878 assert(d
->btype
== VMXNET3_RXD_BTYPE_BODY
);
879 *ridx
= RX_BODY_ONLY_RING
;
880 vmxnet3_inc_rx_consumption_counter(s
, RXQ_IDX
, RX_BODY_ONLY_RING
);
888 vmxnet3_get_next_rx_descr(VMXNET3State
*s
, bool is_head
,
889 struct Vmxnet3_RxDesc
*descr_buf
,
893 if (is_head
|| !s
->rx_packets_compound
) {
894 return vmxnet3_get_next_head_rx_descr(s
, descr_buf
, descr_idx
, ridx
);
896 return vmxnet3_get_next_body_rx_descr(s
, descr_buf
, descr_idx
, ridx
);
900 /* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID),
901 * the implementation always passes an RxCompDesc with a "Checksum
902 * calculated and found correct" to the OS (cnc=0 and tuc=1, see
903 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior.
905 * Therefore, if packet has the NEEDS_CSUM set, we must calculate
906 * and place a fully computed checksum into the tcp/udp header.
907 * Otherwise, the OS driver will receive a checksum-correct indication
908 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field
909 * having just the pseudo header csum value.
911 * While this is not a problem if packet is destined for local delivery,
912 * in the case the host OS performs forwarding, it will forward an
913 * incorrectly checksummed packet.
915 static void vmxnet3_rx_need_csum_calculate(struct VmxnetRxPkt
*pkt
,
916 const void *pkt_data
,
919 struct virtio_net_hdr
*vhdr
;
920 bool isip4
, isip6
, istcp
, isudp
;
924 if (!vmxnet_rx_pkt_has_virt_hdr(pkt
)) {
928 vhdr
= vmxnet_rx_pkt_get_vhdr(pkt
);
929 if (!VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_NEEDS_CSUM
)) {
933 vmxnet_rx_pkt_get_protocols(pkt
, &isip4
, &isip6
, &isudp
, &istcp
);
934 if (!(isip4
|| isip6
) || !(istcp
|| isudp
)) {
938 vmxnet3_dump_virt_hdr(vhdr
);
940 /* Validate packet len: csum_start + scum_offset + length of csum field */
941 if (pkt_len
< (vhdr
->csum_start
+ vhdr
->csum_offset
+ 2)) {
942 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, "
943 "cannot calculate checksum",
944 pkt_len
, vhdr
->csum_start
, vhdr
->csum_offset
);
948 data
= (uint8_t *)pkt_data
+ vhdr
->csum_start
;
949 len
= pkt_len
- vhdr
->csum_start
;
950 /* Put the checksum obtained into the packet */
951 stw_be_p(data
+ vhdr
->csum_offset
, net_raw_checksum(data
, len
));
953 vhdr
->flags
&= ~VIRTIO_NET_HDR_F_NEEDS_CSUM
;
954 vhdr
->flags
|= VIRTIO_NET_HDR_F_DATA_VALID
;
957 static void vmxnet3_rx_update_descr(struct VmxnetRxPkt
*pkt
,
958 struct Vmxnet3_RxCompDesc
*rxcd
)
961 bool isip4
, isip6
, istcp
, isudp
;
962 struct virtio_net_hdr
*vhdr
;
963 uint8_t offload_type
;
965 if (vmxnet_rx_pkt_is_vlan_stripped(pkt
)) {
967 rxcd
->tci
= vmxnet_rx_pkt_get_vlan_tag(pkt
);
970 if (!vmxnet_rx_pkt_has_virt_hdr(pkt
)) {
974 vhdr
= vmxnet_rx_pkt_get_vhdr(pkt
);
976 * Checksum is valid when lower level tell so or when lower level
977 * requires checksum offload telling that packet produced/bridged
978 * locally and did travel over network after last checksum calculation
981 csum_ok
= VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_DATA_VALID
) ||
982 VMXNET_FLAG_IS_SET(vhdr
->flags
, VIRTIO_NET_HDR_F_NEEDS_CSUM
);
984 offload_type
= vhdr
->gso_type
& ~VIRTIO_NET_HDR_GSO_ECN
;
985 is_gso
= (offload_type
!= VIRTIO_NET_HDR_GSO_NONE
) ? 1 : 0;
987 if (!csum_ok
&& !is_gso
) {
991 vmxnet_rx_pkt_get_protocols(pkt
, &isip4
, &isip6
, &isudp
, &istcp
);
992 if ((!istcp
&& !isudp
) || (!isip4
&& !isip6
)) {
997 rxcd
->v4
= isip4
? 1 : 0;
998 rxcd
->v6
= isip6
? 1 : 0;
999 rxcd
->tcp
= istcp
? 1 : 0;
1000 rxcd
->udp
= isudp
? 1 : 0;
1001 rxcd
->fcs
= rxcd
->tuc
= rxcd
->ipc
= 1;
1010 vmxnet3_physical_memory_writev(const struct iovec
*iov
,
1011 size_t start_iov_off
,
1013 size_t bytes_to_copy
)
1015 size_t curr_off
= 0;
1018 while (bytes_to_copy
) {
1019 if (start_iov_off
< (curr_off
+ iov
->iov_len
)) {
1021 MIN((curr_off
+ iov
->iov_len
) - start_iov_off
, bytes_to_copy
);
1023 cpu_physical_memory_write(target_addr
+ copied
,
1024 iov
->iov_base
+ start_iov_off
- curr_off
,
1027 copied
+= chunk_len
;
1028 start_iov_off
+= chunk_len
;
1029 curr_off
= start_iov_off
;
1030 bytes_to_copy
-= chunk_len
;
1032 curr_off
+= iov
->iov_len
;
1039 vmxnet3_indicate_packet(VMXNET3State
*s
)
1041 struct Vmxnet3_RxDesc rxd
;
1042 bool is_head
= true;
1044 uint32_t rx_ridx
= 0;
1046 struct Vmxnet3_RxCompDesc rxcd
;
1047 uint32_t new_rxcd_gen
= VMXNET3_INIT_GEN
;
1048 hwaddr new_rxcd_pa
= 0;
1049 hwaddr ready_rxcd_pa
= 0;
1050 struct iovec
*data
= vmxnet_rx_pkt_get_iovec(s
->rx_pkt
);
1051 size_t bytes_copied
= 0;
1052 size_t bytes_left
= vmxnet_rx_pkt_get_total_len(s
->rx_pkt
);
1053 uint16_t num_frags
= 0;
1056 vmxnet_rx_pkt_dump(s
->rx_pkt
);
1058 while (bytes_left
> 0) {
1060 /* cannot add more frags to packet */
1061 if (num_frags
== s
->max_rx_frags
) {
1065 new_rxcd_pa
= vmxnet3_pop_rxc_descr(s
, RXQ_IDX
, &new_rxcd_gen
);
1070 if (!vmxnet3_get_next_rx_descr(s
, is_head
, &rxd
, &rxd_idx
, &rx_ridx
)) {
1074 chunk_size
= MIN(bytes_left
, rxd
.len
);
1075 vmxnet3_physical_memory_writev(data
, bytes_copied
,
1076 le64_to_cpu(rxd
.addr
), chunk_size
);
1077 bytes_copied
+= chunk_size
;
1078 bytes_left
-= chunk_size
;
1080 vmxnet3_dump_rx_descr(&rxd
);
1082 if (ready_rxcd_pa
!= 0) {
1083 cpu_physical_memory_write(ready_rxcd_pa
, &rxcd
, sizeof(rxcd
));
1086 memset(&rxcd
, 0, sizeof(struct Vmxnet3_RxCompDesc
));
1087 rxcd
.rxdIdx
= rxd_idx
;
1088 rxcd
.len
= chunk_size
;
1090 rxcd
.gen
= new_rxcd_gen
;
1091 rxcd
.rqID
= RXQ_IDX
+ rx_ridx
* s
->rxq_num
;
1093 if (bytes_left
== 0) {
1094 vmxnet3_rx_update_descr(s
->rx_pkt
, &rxcd
);
1097 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
1098 "sop %d csum_correct %lu",
1099 (unsigned long) rx_ridx
,
1100 (unsigned long) rxcd
.rxdIdx
,
1101 (unsigned long) rxcd
.len
,
1103 (unsigned long) rxcd
.tuc
);
1106 ready_rxcd_pa
= new_rxcd_pa
;
1111 if (ready_rxcd_pa
!= 0) {
1113 rxcd
.err
= (bytes_left
!= 0);
1114 cpu_physical_memory_write(ready_rxcd_pa
, &rxcd
, sizeof(rxcd
));
1116 /* Flush RX descriptor changes */
1120 if (new_rxcd_pa
!= 0) {
1121 vmxnet3_revert_rxc_descr(s
, RXQ_IDX
);
1124 vmxnet3_trigger_interrupt(s
, s
->rxq_descr
[RXQ_IDX
].intr_idx
);
1126 if (bytes_left
== 0) {
1127 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
, VMXNET3_PKT_STATUS_OK
);
1129 } else if (num_frags
== s
->max_rx_frags
) {
1130 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
, VMXNET3_PKT_STATUS_ERROR
);
1133 vmxnet3_on_rx_done_update_stats(s
, RXQ_IDX
,
1134 VMXNET3_PKT_STATUS_OUT_OF_BUF
);
1140 vmxnet3_io_bar0_write(void *opaque
, hwaddr addr
,
1141 uint64_t val
, unsigned size
)
1143 VMXNET3State
*s
= opaque
;
1145 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_TXPROD
,
1146 VMXNET3_DEVICE_MAX_TX_QUEUES
, VMXNET3_REG_ALIGN
)) {
1148 VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_TXPROD
,
1150 assert(tx_queue_idx
<= s
->txq_num
);
1151 vmxnet3_process_tx_queue(s
, tx_queue_idx
);
1155 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_IMR
,
1156 VMXNET3_MAX_INTRS
, VMXNET3_REG_ALIGN
)) {
1157 int l
= VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_IMR
,
1160 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64
, l
, val
);
1162 vmxnet3_on_interrupt_mask_changed(s
, l
, val
);
1166 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_RXPROD
,
1167 VMXNET3_DEVICE_MAX_RX_QUEUES
, VMXNET3_REG_ALIGN
) ||
1168 VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_RXPROD2
,
1169 VMXNET3_DEVICE_MAX_RX_QUEUES
, VMXNET3_REG_ALIGN
)) {
1173 VMW_WRPRN("BAR0 unknown write [%" PRIx64
"] = %" PRIx64
", size %d",
1174 (uint64_t) addr
, val
, size
);
1178 vmxnet3_io_bar0_read(void *opaque
, hwaddr addr
, unsigned size
)
1180 VMXNET3State
*s
= opaque
;
1182 if (VMW_IS_MULTIREG_ADDR(addr
, VMXNET3_REG_IMR
,
1183 VMXNET3_MAX_INTRS
, VMXNET3_REG_ALIGN
)) {
1184 int l
= VMW_MULTIREG_IDX_BY_ADDR(addr
, VMXNET3_REG_IMR
,
1186 return s
->interrupt_states
[l
].is_masked
;
1189 VMW_CBPRN("BAR0 unknown read [%" PRIx64
"], size %d", addr
, size
);
1193 static void vmxnet3_reset_interrupt_states(VMXNET3State
*s
)
1196 for (i
= 0; i
< ARRAY_SIZE(s
->interrupt_states
); i
++) {
1197 s
->interrupt_states
[i
].is_asserted
= false;
1198 s
->interrupt_states
[i
].is_pending
= false;
1199 s
->interrupt_states
[i
].is_masked
= true;
1203 static void vmxnet3_reset_mac(VMXNET3State
*s
)
1205 memcpy(&s
->conf
.macaddr
.a
, &s
->perm_mac
.a
, sizeof(s
->perm_mac
.a
));
1206 VMW_CFPRN("MAC address set to: " VMXNET_MF
, VMXNET_MA(s
->conf
.macaddr
.a
));
1209 static void vmxnet3_deactivate_device(VMXNET3State
*s
)
1211 if (s
->device_active
) {
1212 VMW_CBPRN("Deactivating vmxnet3...");
1213 vmxnet_tx_pkt_reset(s
->tx_pkt
);
1214 vmxnet_tx_pkt_uninit(s
->tx_pkt
);
1215 vmxnet_rx_pkt_uninit(s
->rx_pkt
);
1216 s
->device_active
= false;
1220 static void vmxnet3_reset(VMXNET3State
*s
)
1222 VMW_CBPRN("Resetting vmxnet3...");
1224 vmxnet3_deactivate_device(s
);
1225 vmxnet3_reset_interrupt_states(s
);
1228 s
->skip_current_tx_pkt
= false;
1231 static void vmxnet3_update_rx_mode(VMXNET3State
*s
)
1233 s
->rx_mode
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
,
1234 devRead
.rxFilterConf
.rxMode
);
1235 VMW_CFPRN("RX mode: 0x%08X", s
->rx_mode
);
1238 static void vmxnet3_update_vlan_filters(VMXNET3State
*s
)
1242 /* Copy configuration from shared memory */
1243 VMXNET3_READ_DRV_SHARED(s
->drv_shmem
,
1244 devRead
.rxFilterConf
.vfTable
,
1246 sizeof(s
->vlan_table
));
1248 /* Invert byte order when needed */
1249 for (i
= 0; i
< ARRAY_SIZE(s
->vlan_table
); i
++) {
1250 s
->vlan_table
[i
] = le32_to_cpu(s
->vlan_table
[i
]);
1253 /* Dump configuration for debugging purposes */
1254 VMW_CFPRN("Configured VLANs:");
1255 for (i
= 0; i
< sizeof(s
->vlan_table
) * 8; i
++) {
1256 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s
->vlan_table
, i
)) {
1257 VMW_CFPRN("\tVLAN %d is present", i
);
1262 static void vmxnet3_update_mcast_filters(VMXNET3State
*s
)
1264 uint16_t list_bytes
=
1265 VMXNET3_READ_DRV_SHARED16(s
->drv_shmem
,
1266 devRead
.rxFilterConf
.mfTableLen
);
1268 s
->mcast_list_len
= list_bytes
/ sizeof(s
->mcast_list
[0]);
1270 s
->mcast_list
= g_realloc(s
->mcast_list
, list_bytes
);
1271 if (!s
->mcast_list
) {
1272 if (s
->mcast_list_len
== 0) {
1273 VMW_CFPRN("Current multicast list is empty");
1275 VMW_ERPRN("Failed to allocate multicast list of %d elements",
1278 s
->mcast_list_len
= 0;
1281 hwaddr mcast_list_pa
=
1282 VMXNET3_READ_DRV_SHARED64(s
->drv_shmem
,
1283 devRead
.rxFilterConf
.mfTablePA
);
1285 cpu_physical_memory_read(mcast_list_pa
, s
->mcast_list
, list_bytes
);
1286 VMW_CFPRN("Current multicast list len is %d:", s
->mcast_list_len
);
1287 for (i
= 0; i
< s
->mcast_list_len
; i
++) {
1288 VMW_CFPRN("\t" VMXNET_MF
, VMXNET_MA(s
->mcast_list
[i
].a
));
1293 static void vmxnet3_setup_rx_filtering(VMXNET3State
*s
)
1295 vmxnet3_update_rx_mode(s
);
1296 vmxnet3_update_vlan_filters(s
);
1297 vmxnet3_update_mcast_filters(s
);
1300 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State
*s
)
1302 uint32_t interrupt_mode
= VMXNET3_IT_AUTO
| (VMXNET3_IMM_AUTO
<< 2);
1303 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode
);
1304 return interrupt_mode
;
1307 static void vmxnet3_fill_stats(VMXNET3State
*s
)
1311 if (!s
->device_active
)
1314 for (i
= 0; i
< s
->txq_num
; i
++) {
1315 cpu_physical_memory_write(s
->txq_descr
[i
].tx_stats_pa
,
1316 &s
->txq_descr
[i
].txq_stats
,
1317 sizeof(s
->txq_descr
[i
].txq_stats
));
1320 for (i
= 0; i
< s
->rxq_num
; i
++) {
1321 cpu_physical_memory_write(s
->rxq_descr
[i
].rx_stats_pa
,
1322 &s
->rxq_descr
[i
].rxq_stats
,
1323 sizeof(s
->rxq_descr
[i
].rxq_stats
));
1327 static void vmxnet3_adjust_by_guest_type(VMXNET3State
*s
)
1329 struct Vmxnet3_GOSInfo gos
;
1331 VMXNET3_READ_DRV_SHARED(s
->drv_shmem
, devRead
.misc
.driverInfo
.gos
,
1333 s
->rx_packets_compound
=
1334 (gos
.gosType
== VMXNET3_GOS_TYPE_WIN
) ? false : true;
1336 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s
->rx_packets_compound
);
1340 vmxnet3_dump_conf_descr(const char *name
,
1341 struct Vmxnet3_VariableLenConfDesc
*pm_descr
)
1343 VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
1344 name
, pm_descr
->confVer
, pm_descr
->confLen
);
1348 static void vmxnet3_update_pm_state(VMXNET3State
*s
)
1350 struct Vmxnet3_VariableLenConfDesc pm_descr
;
1353 VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, devRead
.pmConfDesc
.confLen
);
1355 VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, devRead
.pmConfDesc
.confVer
);
1357 VMXNET3_READ_DRV_SHARED64(s
->drv_shmem
, devRead
.pmConfDesc
.confPA
);
1359 vmxnet3_dump_conf_descr("PM State", &pm_descr
);
1362 static void vmxnet3_update_features(VMXNET3State
*s
)
1364 uint32_t guest_features
;
1365 int rxcso_supported
;
1367 guest_features
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
,
1368 devRead
.misc
.uptFeatures
);
1370 rxcso_supported
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_RXCSUM
);
1371 s
->rx_vlan_stripping
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_RXVLAN
);
1372 s
->lro_supported
= VMXNET_FLAG_IS_SET(guest_features
, UPT1_F_LRO
);
1374 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
1375 s
->lro_supported
, rxcso_supported
,
1376 s
->rx_vlan_stripping
);
1377 if (s
->peer_has_vhdr
) {
1378 qemu_set_offload(qemu_get_queue(s
->nic
)->peer
,
1387 static bool vmxnet3_verify_intx(VMXNET3State
*s
, int intx
)
1389 return s
->msix_used
|| s
->msi_used
|| (intx
==
1390 (pci_get_byte(s
->parent_obj
.config
+ PCI_INTERRUPT_PIN
) - 1));
1393 static void vmxnet3_validate_interrupt_idx(bool is_msix
, int idx
)
1395 int max_ints
= is_msix
? VMXNET3_MAX_INTRS
: VMXNET3_MAX_NMSIX_INTRS
;
1396 if (idx
>= max_ints
) {
1397 hw_error("Bad interrupt index: %d\n", idx
);
1401 static void vmxnet3_validate_interrupts(VMXNET3State
*s
)
1405 VMW_CFPRN("Verifying event interrupt index (%d)", s
->event_int_idx
);
1406 vmxnet3_validate_interrupt_idx(s
->msix_used
, s
->event_int_idx
);
1408 for (i
= 0; i
< s
->txq_num
; i
++) {
1409 int idx
= s
->txq_descr
[i
].intr_idx
;
1410 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i
, idx
);
1411 vmxnet3_validate_interrupt_idx(s
->msix_used
, idx
);
1414 for (i
= 0; i
< s
->rxq_num
; i
++) {
1415 int idx
= s
->rxq_descr
[i
].intr_idx
;
1416 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i
, idx
);
1417 vmxnet3_validate_interrupt_idx(s
->msix_used
, idx
);
1421 static void vmxnet3_validate_queues(VMXNET3State
*s
)
1424 * txq_num and rxq_num are total number of queues
1425 * configured by guest. These numbers must not
1426 * exceed corresponding maximal values.
1429 if (s
->txq_num
> VMXNET3_DEVICE_MAX_TX_QUEUES
) {
1430 hw_error("Bad TX queues number: %d\n", s
->txq_num
);
1433 if (s
->rxq_num
> VMXNET3_DEVICE_MAX_RX_QUEUES
) {
1434 hw_error("Bad RX queues number: %d\n", s
->rxq_num
);
1438 static void vmxnet3_activate_device(VMXNET3State
*s
)
1441 static const uint32_t VMXNET3_DEF_TX_THRESHOLD
= 1;
1442 hwaddr qdescr_table_pa
;
1446 /* Verify configuration consistency */
1447 if (!vmxnet3_verify_driver_magic(s
->drv_shmem
)) {
1448 VMW_ERPRN("Device configuration received from driver is invalid");
1452 /* Verify if device is active */
1453 if (s
->device_active
) {
1454 VMW_CFPRN("Vmxnet3 device is active");
1458 vmxnet3_adjust_by_guest_type(s
);
1459 vmxnet3_update_features(s
);
1460 vmxnet3_update_pm_state(s
);
1461 vmxnet3_setup_rx_filtering(s
);
1462 /* Cache fields from shared memory */
1463 s
->mtu
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, devRead
.misc
.mtu
);
1464 VMW_CFPRN("MTU is %u", s
->mtu
);
1467 VMXNET3_READ_DRV_SHARED16(s
->drv_shmem
, devRead
.misc
.maxNumRxSG
);
1469 if (s
->max_rx_frags
== 0) {
1470 s
->max_rx_frags
= 1;
1473 VMW_CFPRN("Max RX fragments is %u", s
->max_rx_frags
);
1476 VMXNET3_READ_DRV_SHARED8(s
->drv_shmem
, devRead
.intrConf
.eventIntrIdx
);
1477 assert(vmxnet3_verify_intx(s
, s
->event_int_idx
));
1478 VMW_CFPRN("Events interrupt line is %u", s
->event_int_idx
);
1480 s
->auto_int_masking
=
1481 VMXNET3_READ_DRV_SHARED8(s
->drv_shmem
, devRead
.intrConf
.autoMask
);
1482 VMW_CFPRN("Automatic interrupt masking is %d", (int)s
->auto_int_masking
);
1485 VMXNET3_READ_DRV_SHARED8(s
->drv_shmem
, devRead
.misc
.numTxQueues
);
1487 VMXNET3_READ_DRV_SHARED8(s
->drv_shmem
, devRead
.misc
.numRxQueues
);
1489 VMW_CFPRN("Number of TX/RX queues %u/%u", s
->txq_num
, s
->rxq_num
);
1490 vmxnet3_validate_queues(s
);
1493 VMXNET3_READ_DRV_SHARED64(s
->drv_shmem
, devRead
.misc
.queueDescPA
);
1494 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64
, qdescr_table_pa
);
1497 * Worst-case scenario is a packet that holds all TX rings space so
1498 * we calculate total size of all TX rings for max TX fragments number
1500 s
->max_tx_frags
= 0;
1503 for (i
= 0; i
< s
->txq_num
; i
++) {
1505 qdescr_table_pa
+ i
* sizeof(struct Vmxnet3_TxQueueDesc
);
1507 /* Read interrupt number for this TX queue */
1508 s
->txq_descr
[i
].intr_idx
=
1509 VMXNET3_READ_TX_QUEUE_DESCR8(qdescr_pa
, conf
.intrIdx
);
1510 assert(vmxnet3_verify_intx(s
, s
->txq_descr
[i
].intr_idx
));
1512 VMW_CFPRN("TX Queue %d interrupt: %d", i
, s
->txq_descr
[i
].intr_idx
);
1514 /* Read rings memory locations for TX queues */
1515 pa
= VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa
, conf
.txRingBasePA
);
1516 size
= VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa
, conf
.txRingSize
);
1518 vmxnet3_ring_init(&s
->txq_descr
[i
].tx_ring
, pa
, size
,
1519 sizeof(struct Vmxnet3_TxDesc
), false);
1520 VMXNET3_RING_DUMP(VMW_CFPRN
, "TX", i
, &s
->txq_descr
[i
].tx_ring
);
1522 s
->max_tx_frags
+= size
;
1525 pa
= VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa
, conf
.compRingBasePA
);
1526 size
= VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa
, conf
.compRingSize
);
1527 vmxnet3_ring_init(&s
->txq_descr
[i
].comp_ring
, pa
, size
,
1528 sizeof(struct Vmxnet3_TxCompDesc
), true);
1529 VMXNET3_RING_DUMP(VMW_CFPRN
, "TXC", i
, &s
->txq_descr
[i
].comp_ring
);
1531 s
->txq_descr
[i
].tx_stats_pa
=
1532 qdescr_pa
+ offsetof(struct Vmxnet3_TxQueueDesc
, stats
);
1534 memset(&s
->txq_descr
[i
].txq_stats
, 0,
1535 sizeof(s
->txq_descr
[i
].txq_stats
));
1537 /* Fill device-managed parameters for queues */
1538 VMXNET3_WRITE_TX_QUEUE_DESCR32(qdescr_pa
,
1540 VMXNET3_DEF_TX_THRESHOLD
);
1543 /* Preallocate TX packet wrapper */
1544 VMW_CFPRN("Max TX fragments is %u", s
->max_tx_frags
);
1545 vmxnet_tx_pkt_init(&s
->tx_pkt
, s
->max_tx_frags
, s
->peer_has_vhdr
);
1546 vmxnet_rx_pkt_init(&s
->rx_pkt
, s
->peer_has_vhdr
);
1548 /* Read rings memory locations for RX queues */
1549 for (i
= 0; i
< s
->rxq_num
; i
++) {
1552 qdescr_table_pa
+ s
->txq_num
* sizeof(struct Vmxnet3_TxQueueDesc
) +
1553 i
* sizeof(struct Vmxnet3_RxQueueDesc
);
1555 /* Read interrupt number for this RX queue */
1556 s
->rxq_descr
[i
].intr_idx
=
1557 VMXNET3_READ_TX_QUEUE_DESCR8(qd_pa
, conf
.intrIdx
);
1558 assert(vmxnet3_verify_intx(s
, s
->rxq_descr
[i
].intr_idx
));
1560 VMW_CFPRN("RX Queue %d interrupt: %d", i
, s
->rxq_descr
[i
].intr_idx
);
1562 /* Read rings memory locations */
1563 for (j
= 0; j
< VMXNET3_RX_RINGS_PER_QUEUE
; j
++) {
1565 pa
= VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa
, conf
.rxRingBasePA
[j
]);
1566 size
= VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa
, conf
.rxRingSize
[j
]);
1567 vmxnet3_ring_init(&s
->rxq_descr
[i
].rx_ring
[j
], pa
, size
,
1568 sizeof(struct Vmxnet3_RxDesc
), false);
1569 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64
", Size: %d",
1574 pa
= VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa
, conf
.compRingBasePA
);
1575 size
= VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa
, conf
.compRingSize
);
1576 vmxnet3_ring_init(&s
->rxq_descr
[i
].comp_ring
, pa
, size
,
1577 sizeof(struct Vmxnet3_RxCompDesc
), true);
1578 VMW_CFPRN("RXC queue %d: Base: %" PRIx64
", Size: %d", i
, pa
, size
);
1580 s
->rxq_descr
[i
].rx_stats_pa
=
1581 qd_pa
+ offsetof(struct Vmxnet3_RxQueueDesc
, stats
);
1582 memset(&s
->rxq_descr
[i
].rxq_stats
, 0,
1583 sizeof(s
->rxq_descr
[i
].rxq_stats
));
1586 vmxnet3_validate_interrupts(s
);
1588 /* Make sure everything is in place before device activation */
1591 vmxnet3_reset_mac(s
);
1593 s
->device_active
= true;
1596 static void vmxnet3_handle_command(VMXNET3State
*s
, uint64_t cmd
)
1598 s
->last_command
= cmd
;
1601 case VMXNET3_CMD_GET_PERM_MAC_HI
:
1602 VMW_CBPRN("Set: Get upper part of permanent MAC");
1605 case VMXNET3_CMD_GET_PERM_MAC_LO
:
1606 VMW_CBPRN("Set: Get lower part of permanent MAC");
1609 case VMXNET3_CMD_GET_STATS
:
1610 VMW_CBPRN("Set: Get device statistics");
1611 vmxnet3_fill_stats(s
);
1614 case VMXNET3_CMD_ACTIVATE_DEV
:
1615 VMW_CBPRN("Set: Activating vmxnet3 device");
1616 vmxnet3_activate_device(s
);
1619 case VMXNET3_CMD_UPDATE_RX_MODE
:
1620 VMW_CBPRN("Set: Update rx mode");
1621 vmxnet3_update_rx_mode(s
);
1624 case VMXNET3_CMD_UPDATE_VLAN_FILTERS
:
1625 VMW_CBPRN("Set: Update VLAN filters");
1626 vmxnet3_update_vlan_filters(s
);
1629 case VMXNET3_CMD_UPDATE_MAC_FILTERS
:
1630 VMW_CBPRN("Set: Update MAC filters");
1631 vmxnet3_update_mcast_filters(s
);
1634 case VMXNET3_CMD_UPDATE_FEATURE
:
1635 VMW_CBPRN("Set: Update features");
1636 vmxnet3_update_features(s
);
1639 case VMXNET3_CMD_UPDATE_PMCFG
:
1640 VMW_CBPRN("Set: Update power management config");
1641 vmxnet3_update_pm_state(s
);
1644 case VMXNET3_CMD_GET_LINK
:
1645 VMW_CBPRN("Set: Get link");
1648 case VMXNET3_CMD_RESET_DEV
:
1649 VMW_CBPRN("Set: Reset device");
1653 case VMXNET3_CMD_QUIESCE_DEV
:
1654 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device");
1655 vmxnet3_deactivate_device(s
);
1658 case VMXNET3_CMD_GET_CONF_INTR
:
1659 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
1662 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO
:
1663 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - "
1664 "adaptive ring info flags");
1667 case VMXNET3_CMD_GET_DID_LO
:
1668 VMW_CBPRN("Set: Get lower part of device ID");
1671 case VMXNET3_CMD_GET_DID_HI
:
1672 VMW_CBPRN("Set: Get upper part of device ID");
1675 case VMXNET3_CMD_GET_DEV_EXTRA_INFO
:
1676 VMW_CBPRN("Set: Get device extra info");
1680 VMW_CBPRN("Received unknown command: %" PRIx64
, cmd
);
1685 static uint64_t vmxnet3_get_command_status(VMXNET3State
*s
)
1689 switch (s
->last_command
) {
1690 case VMXNET3_CMD_ACTIVATE_DEV
:
1691 ret
= (s
->device_active
) ? 0 : 1;
1692 VMW_CFPRN("Device active: %" PRIx64
, ret
);
1695 case VMXNET3_CMD_RESET_DEV
:
1696 case VMXNET3_CMD_QUIESCE_DEV
:
1697 case VMXNET3_CMD_GET_QUEUE_STATUS
:
1698 case VMXNET3_CMD_GET_DEV_EXTRA_INFO
:
1702 case VMXNET3_CMD_GET_LINK
:
1703 ret
= s
->link_status_and_speed
;
1704 VMW_CFPRN("Link and speed: %" PRIx64
, ret
);
1707 case VMXNET3_CMD_GET_PERM_MAC_LO
:
1708 ret
= vmxnet3_get_mac_low(&s
->perm_mac
);
1711 case VMXNET3_CMD_GET_PERM_MAC_HI
:
1712 ret
= vmxnet3_get_mac_high(&s
->perm_mac
);
1715 case VMXNET3_CMD_GET_CONF_INTR
:
1716 ret
= vmxnet3_get_interrupt_config(s
);
1719 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO
:
1720 ret
= VMXNET3_DISABLE_ADAPTIVE_RING
;
1723 case VMXNET3_CMD_GET_DID_LO
:
1724 ret
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
1727 case VMXNET3_CMD_GET_DID_HI
:
1728 ret
= VMXNET3_DEVICE_REVISION
;
1732 VMW_WRPRN("Received request for unknown command: %x", s
->last_command
);
1740 static void vmxnet3_set_events(VMXNET3State
*s
, uint32_t val
)
1744 VMW_CBPRN("Setting events: 0x%x", val
);
1745 events
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, ecr
) | val
;
1746 VMXNET3_WRITE_DRV_SHARED32(s
->drv_shmem
, ecr
, events
);
1749 static void vmxnet3_ack_events(VMXNET3State
*s
, uint32_t val
)
1753 VMW_CBPRN("Clearing events: 0x%x", val
);
1754 events
= VMXNET3_READ_DRV_SHARED32(s
->drv_shmem
, ecr
) & ~val
;
1755 VMXNET3_WRITE_DRV_SHARED32(s
->drv_shmem
, ecr
, events
);
1759 vmxnet3_io_bar1_write(void *opaque
,
1764 VMXNET3State
*s
= opaque
;
1767 /* Vmxnet3 Revision Report Selection */
1768 case VMXNET3_REG_VRRS
:
1769 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64
", size %d",
1773 /* UPT Version Report Selection */
1774 case VMXNET3_REG_UVRS
:
1775 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64
", size %d",
1779 /* Driver Shared Address Low */
1780 case VMXNET3_REG_DSAL
:
1781 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64
", size %d",
1784 * Guest driver will first write the low part of the shared
1785 * memory address. We save it to temp variable and set the
1786 * shared address only after we get the high part
1789 vmxnet3_deactivate_device(s
);
1791 s
->temp_shared_guest_driver_memory
= val
;
1795 /* Driver Shared Address High */
1796 case VMXNET3_REG_DSAH
:
1797 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64
", size %d",
1800 * Set the shared memory between guest driver and device.
1801 * We already should have low address part.
1803 s
->drv_shmem
= s
->temp_shared_guest_driver_memory
| (val
<< 32);
1807 case VMXNET3_REG_CMD
:
1808 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64
", size %d",
1810 vmxnet3_handle_command(s
, val
);
1813 /* MAC Address Low */
1814 case VMXNET3_REG_MACL
:
1815 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64
", size %d",
1820 /* MAC Address High */
1821 case VMXNET3_REG_MACH
:
1822 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64
", size %d",
1824 vmxnet3_set_variable_mac(s
, val
, s
->temp_mac
);
1827 /* Interrupt Cause Register */
1828 case VMXNET3_REG_ICR
:
1829 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64
", size %d",
1831 g_assert_not_reached();
1834 /* Event Cause Register */
1835 case VMXNET3_REG_ECR
:
1836 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64
", size %d",
1838 vmxnet3_ack_events(s
, val
);
1842 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64
"] = %" PRIx64
", size %d",
1849 vmxnet3_io_bar1_read(void *opaque
, hwaddr addr
, unsigned size
)
1851 VMXNET3State
*s
= opaque
;
1855 /* Vmxnet3 Revision Report Selection */
1856 case VMXNET3_REG_VRRS
:
1857 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size
);
1858 ret
= VMXNET3_DEVICE_REVISION
;
1861 /* UPT Version Report Selection */
1862 case VMXNET3_REG_UVRS
:
1863 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size
);
1864 ret
= VMXNET3_UPT_REVISION
;
1868 case VMXNET3_REG_CMD
:
1869 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size
);
1870 ret
= vmxnet3_get_command_status(s
);
1873 /* MAC Address Low */
1874 case VMXNET3_REG_MACL
:
1875 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size
);
1876 ret
= vmxnet3_get_mac_low(&s
->conf
.macaddr
);
1879 /* MAC Address High */
1880 case VMXNET3_REG_MACH
:
1881 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size
);
1882 ret
= vmxnet3_get_mac_high(&s
->conf
.macaddr
);
1886 * Interrupt Cause Register
1887 * Used for legacy interrupts only so interrupt index always 0
1889 case VMXNET3_REG_ICR
:
1890 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size
);
1891 if (vmxnet3_interrupt_asserted(s
, 0)) {
1892 vmxnet3_clear_interrupt(s
, 0);
1900 VMW_CBPRN("Unknow read BAR1[%" PRIx64
"], %d bytes", addr
, size
);
1908 vmxnet3_can_receive(NetClientState
*nc
)
1910 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
1911 return s
->device_active
&&
1912 VMXNET_FLAG_IS_SET(s
->link_status_and_speed
, VMXNET3_LINK_STATUS_UP
);
1916 vmxnet3_is_registered_vlan(VMXNET3State
*s
, const void *data
)
1918 uint16_t vlan_tag
= eth_get_pkt_tci(data
) & VLAN_VID_MASK
;
1919 if (IS_SPECIAL_VLAN_ID(vlan_tag
)) {
1923 return VMXNET3_VFTABLE_ENTRY_IS_SET(s
->vlan_table
, vlan_tag
);
1927 vmxnet3_is_allowed_mcast_group(VMXNET3State
*s
, const uint8_t *group_mac
)
1930 for (i
= 0; i
< s
->mcast_list_len
; i
++) {
1931 if (!memcmp(group_mac
, s
->mcast_list
[i
].a
, sizeof(s
->mcast_list
[i
]))) {
1939 vmxnet3_rx_filter_may_indicate(VMXNET3State
*s
, const void *data
,
1942 struct eth_header
*ehdr
= PKT_GET_ETH_HDR(data
);
1944 if (VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_PROMISC
)) {
1948 if (!vmxnet3_is_registered_vlan(s
, data
)) {
1952 switch (vmxnet_rx_pkt_get_packet_type(s
->rx_pkt
)) {
1954 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_UCAST
)) {
1957 if (memcmp(s
->conf
.macaddr
.a
, ehdr
->h_dest
, ETH_ALEN
)) {
1963 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_BCAST
)) {
1969 if (VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_ALL_MULTI
)) {
1972 if (!VMXNET_FLAG_IS_SET(s
->rx_mode
, VMXNET3_RXM_MCAST
)) {
1975 if (!vmxnet3_is_allowed_mcast_group(s
, ehdr
->h_dest
)) {
1981 g_assert_not_reached();
1988 vmxnet3_receive(NetClientState
*nc
, const uint8_t *buf
, size_t size
)
1990 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
1991 size_t bytes_indicated
;
1992 uint8_t min_buf
[MIN_BUF_SIZE
];
1994 if (!vmxnet3_can_receive(nc
)) {
1995 VMW_PKPRN("Cannot receive now");
1999 if (s
->peer_has_vhdr
) {
2000 vmxnet_rx_pkt_set_vhdr(s
->rx_pkt
, (struct virtio_net_hdr
*)buf
);
2001 buf
+= sizeof(struct virtio_net_hdr
);
2002 size
-= sizeof(struct virtio_net_hdr
);
2005 /* Pad to minimum Ethernet frame length */
2006 if (size
< sizeof(min_buf
)) {
2007 memcpy(min_buf
, buf
, size
);
2008 memset(&min_buf
[size
], 0, sizeof(min_buf
) - size
);
2010 size
= sizeof(min_buf
);
2013 vmxnet_rx_pkt_set_packet_type(s
->rx_pkt
,
2014 get_eth_packet_type(PKT_GET_ETH_HDR(buf
)));
2016 if (vmxnet3_rx_filter_may_indicate(s
, buf
, size
)) {
2017 vmxnet_rx_pkt_set_protocols(s
->rx_pkt
, buf
, size
);
2018 vmxnet3_rx_need_csum_calculate(s
->rx_pkt
, buf
, size
);
2019 vmxnet_rx_pkt_attach_data(s
->rx_pkt
, buf
, size
, s
->rx_vlan_stripping
);
2020 bytes_indicated
= vmxnet3_indicate_packet(s
) ? size
: -1;
2021 if (bytes_indicated
< size
) {
2022 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated
, size
);
2025 VMW_PKPRN("Packet dropped by RX filter");
2026 bytes_indicated
= size
;
2030 assert(bytes_indicated
!= 0);
2031 return bytes_indicated
;
2034 static void vmxnet3_set_link_status(NetClientState
*nc
)
2036 VMXNET3State
*s
= qemu_get_nic_opaque(nc
);
2038 if (nc
->link_down
) {
2039 s
->link_status_and_speed
&= ~VMXNET3_LINK_STATUS_UP
;
2041 s
->link_status_and_speed
|= VMXNET3_LINK_STATUS_UP
;
2044 vmxnet3_set_events(s
, VMXNET3_ECR_LINK
);
2045 vmxnet3_trigger_interrupt(s
, s
->event_int_idx
);
2048 static NetClientInfo net_vmxnet3_info
= {
2049 .type
= NET_CLIENT_OPTIONS_KIND_NIC
,
2050 .size
= sizeof(NICState
),
2051 .receive
= vmxnet3_receive
,
2052 .link_status_changed
= vmxnet3_set_link_status
,
2055 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State
*s
)
2057 NetClientState
*nc
= qemu_get_queue(s
->nic
);
2059 if (qemu_has_vnet_hdr(nc
->peer
)) {
2066 static void vmxnet3_net_uninit(VMXNET3State
*s
)
2068 g_free(s
->mcast_list
);
2069 vmxnet3_deactivate_device(s
);
2070 qemu_del_nic(s
->nic
);
2073 static void vmxnet3_net_init(VMXNET3State
*s
)
2075 DeviceState
*d
= DEVICE(s
);
2077 VMW_CBPRN("vmxnet3_net_init called...");
2079 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
2081 /* Windows guest will query the address that was set on init */
2082 memcpy(&s
->perm_mac
.a
, &s
->conf
.macaddr
.a
, sizeof(s
->perm_mac
.a
));
2084 s
->mcast_list
= NULL
;
2085 s
->mcast_list_len
= 0;
2087 s
->link_status_and_speed
= VMXNET3_LINK_SPEED
| VMXNET3_LINK_STATUS_UP
;
2089 VMW_CFPRN("Permanent MAC: " VMXNET_MF
, VMXNET_MA(s
->perm_mac
.a
));
2091 s
->nic
= qemu_new_nic(&net_vmxnet3_info
, &s
->conf
,
2092 object_get_typename(OBJECT(s
)),
2095 s
->peer_has_vhdr
= vmxnet3_peer_has_vnet_hdr(s
);
2097 s
->skip_current_tx_pkt
= false;
2100 s
->rx_vlan_stripping
= false;
2101 s
->lro_supported
= false;
2103 if (s
->peer_has_vhdr
) {
2104 qemu_set_vnet_hdr_len(qemu_get_queue(s
->nic
)->peer
,
2105 sizeof(struct virtio_net_hdr
));
2107 qemu_using_vnet_hdr(qemu_get_queue(s
->nic
)->peer
, 1);
2110 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
2114 vmxnet3_unuse_msix_vectors(VMXNET3State
*s
, int num_vectors
)
2116 PCIDevice
*d
= PCI_DEVICE(s
);
2118 for (i
= 0; i
< num_vectors
; i
++) {
2119 msix_vector_unuse(d
, i
);
2124 vmxnet3_use_msix_vectors(VMXNET3State
*s
, int num_vectors
)
2126 PCIDevice
*d
= PCI_DEVICE(s
);
2128 for (i
= 0; i
< num_vectors
; i
++) {
2129 int res
= msix_vector_use(d
, i
);
2131 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i
, res
);
2132 vmxnet3_unuse_msix_vectors(s
, i
);
2140 vmxnet3_init_msix(VMXNET3State
*s
)
2142 PCIDevice
*d
= PCI_DEVICE(s
);
2143 int res
= msix_init(d
, VMXNET3_MAX_INTRS
,
2145 VMXNET3_MSIX_BAR_IDX
, VMXNET3_OFF_MSIX_TABLE
,
2147 VMXNET3_MSIX_BAR_IDX
, VMXNET3_OFF_MSIX_PBA(s
),
2148 VMXNET3_MSIX_OFFSET(s
));
2151 VMW_WRPRN("Failed to initialize MSI-X, error %d", res
);
2152 s
->msix_used
= false;
2154 if (!vmxnet3_use_msix_vectors(s
, VMXNET3_MAX_INTRS
)) {
2155 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res
);
2156 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
2157 s
->msix_used
= false;
2159 s
->msix_used
= true;
2162 return s
->msix_used
;
2166 vmxnet3_cleanup_msix(VMXNET3State
*s
)
2168 PCIDevice
*d
= PCI_DEVICE(s
);
2171 vmxnet3_unuse_msix_vectors(s
, VMXNET3_MAX_INTRS
);
2172 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
2176 #define VMXNET3_USE_64BIT (true)
2177 #define VMXNET3_PER_VECTOR_MASK (false)
2180 vmxnet3_init_msi(VMXNET3State
*s
)
2182 PCIDevice
*d
= PCI_DEVICE(s
);
2185 res
= msi_init(d
, VMXNET3_MSI_OFFSET(s
), VMXNET3_MAX_NMSIX_INTRS
,
2186 VMXNET3_USE_64BIT
, VMXNET3_PER_VECTOR_MASK
);
2188 VMW_WRPRN("Failed to initialize MSI, error %d", res
);
2189 s
->msi_used
= false;
2198 vmxnet3_cleanup_msi(VMXNET3State
*s
)
2200 PCIDevice
*d
= PCI_DEVICE(s
);
2208 vmxnet3_msix_save(QEMUFile
*f
, void *opaque
)
2210 PCIDevice
*d
= PCI_DEVICE(opaque
);
2215 vmxnet3_msix_load(QEMUFile
*f
, void *opaque
, int version_id
)
2217 PCIDevice
*d
= PCI_DEVICE(opaque
);
2222 static const MemoryRegionOps b0_ops
= {
2223 .read
= vmxnet3_io_bar0_read
,
2224 .write
= vmxnet3_io_bar0_write
,
2225 .endianness
= DEVICE_LITTLE_ENDIAN
,
2227 .min_access_size
= 4,
2228 .max_access_size
= 4,
2232 static const MemoryRegionOps b1_ops
= {
2233 .read
= vmxnet3_io_bar1_read
,
2234 .write
= vmxnet3_io_bar1_write
,
2235 .endianness
= DEVICE_LITTLE_ENDIAN
,
2237 .min_access_size
= 4,
2238 .max_access_size
= 4,
2242 static void vmxnet3_pci_realize(PCIDevice
*pci_dev
, Error
**errp
)
2244 DeviceState
*dev
= DEVICE(pci_dev
);
2245 VMXNET3State
*s
= VMXNET3(pci_dev
);
2247 VMW_CBPRN("Starting init...");
2249 memory_region_init_io(&s
->bar0
, OBJECT(s
), &b0_ops
, s
,
2250 "vmxnet3-b0", VMXNET3_PT_REG_SIZE
);
2251 pci_register_bar(pci_dev
, VMXNET3_BAR0_IDX
,
2252 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar0
);
2254 memory_region_init_io(&s
->bar1
, OBJECT(s
), &b1_ops
, s
,
2255 "vmxnet3-b1", VMXNET3_VD_REG_SIZE
);
2256 pci_register_bar(pci_dev
, VMXNET3_BAR1_IDX
,
2257 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar1
);
2259 memory_region_init(&s
->msix_bar
, OBJECT(s
), "vmxnet3-msix-bar",
2260 VMXNET3_MSIX_BAR_SIZE
);
2261 pci_register_bar(pci_dev
, VMXNET3_MSIX_BAR_IDX
,
2262 PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->msix_bar
);
2264 vmxnet3_reset_interrupt_states(s
);
2266 /* Interrupt pin A */
2267 pci_dev
->config
[PCI_INTERRUPT_PIN
] = 0x01;
2269 if (!vmxnet3_init_msix(s
)) {
2270 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
2273 if (!vmxnet3_init_msi(s
)) {
2274 VMW_WRPRN("Failed to initialize MSI, configuration is inconsistent.");
2277 vmxnet3_net_init(s
);
2279 register_savevm(dev
, "vmxnet3-msix", -1, 1,
2280 vmxnet3_msix_save
, vmxnet3_msix_load
, s
);
2283 static void vmxnet3_instance_init(Object
*obj
)
2285 VMXNET3State
*s
= VMXNET3(obj
);
2286 device_add_bootindex_property(obj
, &s
->conf
.bootindex
,
2287 "bootindex", "/ethernet-phy@0",
2291 static void vmxnet3_pci_uninit(PCIDevice
*pci_dev
)
2293 DeviceState
*dev
= DEVICE(pci_dev
);
2294 VMXNET3State
*s
= VMXNET3(pci_dev
);
2296 VMW_CBPRN("Starting uninit...");
2298 unregister_savevm(dev
, "vmxnet3-msix", s
);
2300 vmxnet3_net_uninit(s
);
2302 vmxnet3_cleanup_msix(s
);
2304 vmxnet3_cleanup_msi(s
);
2307 static void vmxnet3_qdev_reset(DeviceState
*dev
)
2309 PCIDevice
*d
= PCI_DEVICE(dev
);
2310 VMXNET3State
*s
= VMXNET3(d
);
2312 VMW_CBPRN("Starting QDEV reset...");
2316 static bool vmxnet3_mc_list_needed(void *opaque
)
2321 static int vmxnet3_mcast_list_pre_load(void *opaque
)
2323 VMXNET3State
*s
= opaque
;
2325 s
->mcast_list
= g_malloc(s
->mcast_list_buff_size
);
2331 static void vmxnet3_pre_save(void *opaque
)
2333 VMXNET3State
*s
= opaque
;
2335 s
->mcast_list_buff_size
= s
->mcast_list_len
* sizeof(MACAddr
);
2338 static const VMStateDescription vmxstate_vmxnet3_mcast_list
= {
2339 .name
= "vmxnet3/mcast_list",
2341 .minimum_version_id
= 1,
2342 .pre_load
= vmxnet3_mcast_list_pre_load
,
2343 .needed
= vmxnet3_mc_list_needed
,
2344 .fields
= (VMStateField
[]) {
2345 VMSTATE_VBUFFER_UINT32(mcast_list
, VMXNET3State
, 0, NULL
, 0,
2346 mcast_list_buff_size
),
2347 VMSTATE_END_OF_LIST()
2351 static void vmxnet3_get_ring_from_file(QEMUFile
*f
, Vmxnet3Ring
*r
)
2353 r
->pa
= qemu_get_be64(f
);
2354 r
->size
= qemu_get_be32(f
);
2355 r
->cell_size
= qemu_get_be32(f
);
2356 r
->next
= qemu_get_be32(f
);
2357 r
->gen
= qemu_get_byte(f
);
2360 static void vmxnet3_put_ring_to_file(QEMUFile
*f
, Vmxnet3Ring
*r
)
2362 qemu_put_be64(f
, r
->pa
);
2363 qemu_put_be32(f
, r
->size
);
2364 qemu_put_be32(f
, r
->cell_size
);
2365 qemu_put_be32(f
, r
->next
);
2366 qemu_put_byte(f
, r
->gen
);
2369 static void vmxnet3_get_tx_stats_from_file(QEMUFile
*f
,
2370 struct UPT1_TxStats
*tx_stat
)
2372 tx_stat
->TSOPktsTxOK
= qemu_get_be64(f
);
2373 tx_stat
->TSOBytesTxOK
= qemu_get_be64(f
);
2374 tx_stat
->ucastPktsTxOK
= qemu_get_be64(f
);
2375 tx_stat
->ucastBytesTxOK
= qemu_get_be64(f
);
2376 tx_stat
->mcastPktsTxOK
= qemu_get_be64(f
);
2377 tx_stat
->mcastBytesTxOK
= qemu_get_be64(f
);
2378 tx_stat
->bcastPktsTxOK
= qemu_get_be64(f
);
2379 tx_stat
->bcastBytesTxOK
= qemu_get_be64(f
);
2380 tx_stat
->pktsTxError
= qemu_get_be64(f
);
2381 tx_stat
->pktsTxDiscard
= qemu_get_be64(f
);
2384 static void vmxnet3_put_tx_stats_to_file(QEMUFile
*f
,
2385 struct UPT1_TxStats
*tx_stat
)
2387 qemu_put_be64(f
, tx_stat
->TSOPktsTxOK
);
2388 qemu_put_be64(f
, tx_stat
->TSOBytesTxOK
);
2389 qemu_put_be64(f
, tx_stat
->ucastPktsTxOK
);
2390 qemu_put_be64(f
, tx_stat
->ucastBytesTxOK
);
2391 qemu_put_be64(f
, tx_stat
->mcastPktsTxOK
);
2392 qemu_put_be64(f
, tx_stat
->mcastBytesTxOK
);
2393 qemu_put_be64(f
, tx_stat
->bcastPktsTxOK
);
2394 qemu_put_be64(f
, tx_stat
->bcastBytesTxOK
);
2395 qemu_put_be64(f
, tx_stat
->pktsTxError
);
2396 qemu_put_be64(f
, tx_stat
->pktsTxDiscard
);
2399 static int vmxnet3_get_txq_descr(QEMUFile
*f
, void *pv
, size_t size
)
2401 Vmxnet3TxqDescr
*r
= pv
;
2403 vmxnet3_get_ring_from_file(f
, &r
->tx_ring
);
2404 vmxnet3_get_ring_from_file(f
, &r
->comp_ring
);
2405 r
->intr_idx
= qemu_get_byte(f
);
2406 r
->tx_stats_pa
= qemu_get_be64(f
);
2408 vmxnet3_get_tx_stats_from_file(f
, &r
->txq_stats
);
2413 static void vmxnet3_put_txq_descr(QEMUFile
*f
, void *pv
, size_t size
)
2415 Vmxnet3TxqDescr
*r
= pv
;
2417 vmxnet3_put_ring_to_file(f
, &r
->tx_ring
);
2418 vmxnet3_put_ring_to_file(f
, &r
->comp_ring
);
2419 qemu_put_byte(f
, r
->intr_idx
);
2420 qemu_put_be64(f
, r
->tx_stats_pa
);
2421 vmxnet3_put_tx_stats_to_file(f
, &r
->txq_stats
);
2424 static const VMStateInfo txq_descr_info
= {
2425 .name
= "txq_descr",
2426 .get
= vmxnet3_get_txq_descr
,
2427 .put
= vmxnet3_put_txq_descr
2430 static void vmxnet3_get_rx_stats_from_file(QEMUFile
*f
,
2431 struct UPT1_RxStats
*rx_stat
)
2433 rx_stat
->LROPktsRxOK
= qemu_get_be64(f
);
2434 rx_stat
->LROBytesRxOK
= qemu_get_be64(f
);
2435 rx_stat
->ucastPktsRxOK
= qemu_get_be64(f
);
2436 rx_stat
->ucastBytesRxOK
= qemu_get_be64(f
);
2437 rx_stat
->mcastPktsRxOK
= qemu_get_be64(f
);
2438 rx_stat
->mcastBytesRxOK
= qemu_get_be64(f
);
2439 rx_stat
->bcastPktsRxOK
= qemu_get_be64(f
);
2440 rx_stat
->bcastBytesRxOK
= qemu_get_be64(f
);
2441 rx_stat
->pktsRxOutOfBuf
= qemu_get_be64(f
);
2442 rx_stat
->pktsRxError
= qemu_get_be64(f
);
2445 static void vmxnet3_put_rx_stats_to_file(QEMUFile
*f
,
2446 struct UPT1_RxStats
*rx_stat
)
2448 qemu_put_be64(f
, rx_stat
->LROPktsRxOK
);
2449 qemu_put_be64(f
, rx_stat
->LROBytesRxOK
);
2450 qemu_put_be64(f
, rx_stat
->ucastPktsRxOK
);
2451 qemu_put_be64(f
, rx_stat
->ucastBytesRxOK
);
2452 qemu_put_be64(f
, rx_stat
->mcastPktsRxOK
);
2453 qemu_put_be64(f
, rx_stat
->mcastBytesRxOK
);
2454 qemu_put_be64(f
, rx_stat
->bcastPktsRxOK
);
2455 qemu_put_be64(f
, rx_stat
->bcastBytesRxOK
);
2456 qemu_put_be64(f
, rx_stat
->pktsRxOutOfBuf
);
2457 qemu_put_be64(f
, rx_stat
->pktsRxError
);
2460 static int vmxnet3_get_rxq_descr(QEMUFile
*f
, void *pv
, size_t size
)
2462 Vmxnet3RxqDescr
*r
= pv
;
2465 for (i
= 0; i
< VMXNET3_RX_RINGS_PER_QUEUE
; i
++) {
2466 vmxnet3_get_ring_from_file(f
, &r
->rx_ring
[i
]);
2469 vmxnet3_get_ring_from_file(f
, &r
->comp_ring
);
2470 r
->intr_idx
= qemu_get_byte(f
);
2471 r
->rx_stats_pa
= qemu_get_be64(f
);
2473 vmxnet3_get_rx_stats_from_file(f
, &r
->rxq_stats
);
2478 static void vmxnet3_put_rxq_descr(QEMUFile
*f
, void *pv
, size_t size
)
2480 Vmxnet3RxqDescr
*r
= pv
;
2483 for (i
= 0; i
< VMXNET3_RX_RINGS_PER_QUEUE
; i
++) {
2484 vmxnet3_put_ring_to_file(f
, &r
->rx_ring
[i
]);
2487 vmxnet3_put_ring_to_file(f
, &r
->comp_ring
);
2488 qemu_put_byte(f
, r
->intr_idx
);
2489 qemu_put_be64(f
, r
->rx_stats_pa
);
2490 vmxnet3_put_rx_stats_to_file(f
, &r
->rxq_stats
);
2493 static int vmxnet3_post_load(void *opaque
, int version_id
)
2495 VMXNET3State
*s
= opaque
;
2496 PCIDevice
*d
= PCI_DEVICE(s
);
2498 vmxnet_tx_pkt_init(&s
->tx_pkt
, s
->max_tx_frags
, s
->peer_has_vhdr
);
2499 vmxnet_rx_pkt_init(&s
->rx_pkt
, s
->peer_has_vhdr
);
2502 if (!vmxnet3_use_msix_vectors(s
, VMXNET3_MAX_INTRS
)) {
2503 VMW_WRPRN("Failed to re-use MSI-X vectors");
2504 msix_uninit(d
, &s
->msix_bar
, &s
->msix_bar
);
2505 s
->msix_used
= false;
2510 vmxnet3_validate_queues(s
);
2511 vmxnet3_validate_interrupts(s
);
2516 static const VMStateInfo rxq_descr_info
= {
2517 .name
= "rxq_descr",
2518 .get
= vmxnet3_get_rxq_descr
,
2519 .put
= vmxnet3_put_rxq_descr
2522 static int vmxnet3_get_int_state(QEMUFile
*f
, void *pv
, size_t size
)
2524 Vmxnet3IntState
*r
= pv
;
2526 r
->is_masked
= qemu_get_byte(f
);
2527 r
->is_pending
= qemu_get_byte(f
);
2528 r
->is_asserted
= qemu_get_byte(f
);
2533 static void vmxnet3_put_int_state(QEMUFile
*f
, void *pv
, size_t size
)
2535 Vmxnet3IntState
*r
= pv
;
2537 qemu_put_byte(f
, r
->is_masked
);
2538 qemu_put_byte(f
, r
->is_pending
);
2539 qemu_put_byte(f
, r
->is_asserted
);
2542 static const VMStateInfo int_state_info
= {
2543 .name
= "int_state",
2544 .get
= vmxnet3_get_int_state
,
2545 .put
= vmxnet3_put_int_state
2548 static const VMStateDescription vmstate_vmxnet3
= {
2551 .minimum_version_id
= 1,
2552 .pre_save
= vmxnet3_pre_save
,
2553 .post_load
= vmxnet3_post_load
,
2554 .fields
= (VMStateField
[]) {
2555 VMSTATE_PCI_DEVICE(parent_obj
, VMXNET3State
),
2556 VMSTATE_BOOL(rx_packets_compound
, VMXNET3State
),
2557 VMSTATE_BOOL(rx_vlan_stripping
, VMXNET3State
),
2558 VMSTATE_BOOL(lro_supported
, VMXNET3State
),
2559 VMSTATE_UINT32(rx_mode
, VMXNET3State
),
2560 VMSTATE_UINT32(mcast_list_len
, VMXNET3State
),
2561 VMSTATE_UINT32(mcast_list_buff_size
, VMXNET3State
),
2562 VMSTATE_UINT32_ARRAY(vlan_table
, VMXNET3State
, VMXNET3_VFT_SIZE
),
2563 VMSTATE_UINT32(mtu
, VMXNET3State
),
2564 VMSTATE_UINT16(max_rx_frags
, VMXNET3State
),
2565 VMSTATE_UINT32(max_tx_frags
, VMXNET3State
),
2566 VMSTATE_UINT8(event_int_idx
, VMXNET3State
),
2567 VMSTATE_BOOL(auto_int_masking
, VMXNET3State
),
2568 VMSTATE_UINT8(txq_num
, VMXNET3State
),
2569 VMSTATE_UINT8(rxq_num
, VMXNET3State
),
2570 VMSTATE_UINT32(device_active
, VMXNET3State
),
2571 VMSTATE_UINT32(last_command
, VMXNET3State
),
2572 VMSTATE_UINT32(link_status_and_speed
, VMXNET3State
),
2573 VMSTATE_UINT32(temp_mac
, VMXNET3State
),
2574 VMSTATE_UINT64(drv_shmem
, VMXNET3State
),
2575 VMSTATE_UINT64(temp_shared_guest_driver_memory
, VMXNET3State
),
2577 VMSTATE_ARRAY(txq_descr
, VMXNET3State
,
2578 VMXNET3_DEVICE_MAX_TX_QUEUES
, 0, txq_descr_info
,
2580 VMSTATE_ARRAY(rxq_descr
, VMXNET3State
,
2581 VMXNET3_DEVICE_MAX_RX_QUEUES
, 0, rxq_descr_info
,
2583 VMSTATE_ARRAY(interrupt_states
, VMXNET3State
, VMXNET3_MAX_INTRS
,
2584 0, int_state_info
, Vmxnet3IntState
),
2586 VMSTATE_END_OF_LIST()
2588 .subsections
= (const VMStateDescription
*[]) {
2589 &vmxstate_vmxnet3_mcast_list
,
2594 static Property vmxnet3_properties
[] = {
2595 DEFINE_NIC_PROPERTIES(VMXNET3State
, conf
),
2596 DEFINE_PROP_END_OF_LIST(),
2599 static void vmxnet3_class_init(ObjectClass
*class, void *data
)
2601 DeviceClass
*dc
= DEVICE_CLASS(class);
2602 PCIDeviceClass
*c
= PCI_DEVICE_CLASS(class);
2604 c
->realize
= vmxnet3_pci_realize
;
2605 c
->exit
= vmxnet3_pci_uninit
;
2606 c
->vendor_id
= PCI_VENDOR_ID_VMWARE
;
2607 c
->device_id
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
2608 c
->revision
= PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION
;
2609 c
->class_id
= PCI_CLASS_NETWORK_ETHERNET
;
2610 c
->subsystem_vendor_id
= PCI_VENDOR_ID_VMWARE
;
2611 c
->subsystem_id
= PCI_DEVICE_ID_VMWARE_VMXNET3
;
2612 dc
->desc
= "VMWare Paravirtualized Ethernet v3";
2613 dc
->reset
= vmxnet3_qdev_reset
;
2614 dc
->vmsd
= &vmstate_vmxnet3
;
2615 dc
->props
= vmxnet3_properties
;
2616 set_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
);
2619 static const TypeInfo vmxnet3_info
= {
2620 .name
= TYPE_VMXNET3
,
2621 .parent
= TYPE_PCI_DEVICE
,
2622 .instance_size
= sizeof(VMXNET3State
),
2623 .class_init
= vmxnet3_class_init
,
2624 .instance_init
= vmxnet3_instance_init
,
2627 static void vmxnet3_register_types(void)
2629 VMW_CBPRN("vmxnet3_register_types called...");
2630 type_register_static(&vmxnet3_info
);
2633 type_init(vmxnet3_register_types
)