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pc-dimm: error out if memory hotplug is not enabled
[qemu.git] / target-ppc / translate.c
blobb23933f7bd4707b96aec598331c1ea86ccf19107
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25 #include "exec/cpu_ldst.h"
26
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 + 10*4 + 22*5 /* SPE GPRh */
50 + 10*4 + 22*5 /* FPR */
51 + 2*(10*6 + 22*7) /* AVRh, AVRl */
52 + 10*5 + 22*6 /* VSR */
53 + 8*5 /* CRF */];
54 static TCGv cpu_gpr[32];
55 static TCGv cpu_gprh[32];
56 static TCGv_i64 cpu_fpr[32];
57 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
58 static TCGv_i64 cpu_vsr[32];
59 static TCGv_i32 cpu_crf[8];
60 static TCGv cpu_nip;
61 static TCGv cpu_msr;
62 static TCGv cpu_ctr;
63 static TCGv cpu_lr;
64 #if defined(TARGET_PPC64)
65 static TCGv cpu_cfar;
66 #endif
67 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
68 static TCGv cpu_reserve;
69 static TCGv cpu_fpscr;
70 static TCGv_i32 cpu_access_type;
71
72 #include "exec/gen-icount.h"
73
74 void ppc_translate_init(void)
75 {
76 int i;
77 char* p;
78 size_t cpu_reg_names_size;
79 static int done_init = 0;
80
81 if (done_init)
82 return;
83
84 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
85
86 p = cpu_reg_names;
87 cpu_reg_names_size = sizeof(cpu_reg_names);
88
89 for (i = 0; i < 8; i++) {
90 snprintf(p, cpu_reg_names_size, "crf%d", i);
91 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
92 offsetof(CPUPPCState, crf[i]), p);
93 p += 5;
94 cpu_reg_names_size -= 5;
95 }
96
97 for (i = 0; i < 32; i++) {
98 snprintf(p, cpu_reg_names_size, "r%d", i);
99 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
100 offsetof(CPUPPCState, gpr[i]), p);
101 p += (i < 10) ? 3 : 4;
102 cpu_reg_names_size -= (i < 10) ? 3 : 4;
103 snprintf(p, cpu_reg_names_size, "r%dH", i);
104 cpu_gprh[i] = tcg_global_mem_new(TCG_AREG0,
105 offsetof(CPUPPCState, gprh[i]), p);
106 p += (i < 10) ? 4 : 5;
107 cpu_reg_names_size -= (i < 10) ? 4 : 5;
108
109 snprintf(p, cpu_reg_names_size, "fp%d", i);
110 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
111 offsetof(CPUPPCState, fpr[i]), p);
112 p += (i < 10) ? 4 : 5;
113 cpu_reg_names_size -= (i < 10) ? 4 : 5;
114
115 snprintf(p, cpu_reg_names_size, "avr%dH", i);
116 #ifdef HOST_WORDS_BIGENDIAN
117 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
118 offsetof(CPUPPCState, avr[i].u64[0]), p);
119 #else
120 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
121 offsetof(CPUPPCState, avr[i].u64[1]), p);
122 #endif
123 p += (i < 10) ? 6 : 7;
124 cpu_reg_names_size -= (i < 10) ? 6 : 7;
125
126 snprintf(p, cpu_reg_names_size, "avr%dL", i);
127 #ifdef HOST_WORDS_BIGENDIAN
128 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
129 offsetof(CPUPPCState, avr[i].u64[1]), p);
130 #else
131 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
132 offsetof(CPUPPCState, avr[i].u64[0]), p);
133 #endif
134 p += (i < 10) ? 6 : 7;
135 cpu_reg_names_size -= (i < 10) ? 6 : 7;
136 snprintf(p, cpu_reg_names_size, "vsr%d", i);
137 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
138 offsetof(CPUPPCState, vsr[i]), p);
139 p += (i < 10) ? 5 : 6;
140 cpu_reg_names_size -= (i < 10) ? 5 : 6;
141 }
142
143 cpu_nip = tcg_global_mem_new(TCG_AREG0,
144 offsetof(CPUPPCState, nip), "nip");
145
146 cpu_msr = tcg_global_mem_new(TCG_AREG0,
147 offsetof(CPUPPCState, msr), "msr");
148
149 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUPPCState, ctr), "ctr");
151
152 cpu_lr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUPPCState, lr), "lr");
154
155 #if defined(TARGET_PPC64)
156 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
157 offsetof(CPUPPCState, cfar), "cfar");
158 #endif
159
160 cpu_xer = tcg_global_mem_new(TCG_AREG0,
161 offsetof(CPUPPCState, xer), "xer");
162 cpu_so = tcg_global_mem_new(TCG_AREG0,
163 offsetof(CPUPPCState, so), "SO");
164 cpu_ov = tcg_global_mem_new(TCG_AREG0,
165 offsetof(CPUPPCState, ov), "OV");
166 cpu_ca = tcg_global_mem_new(TCG_AREG0,
167 offsetof(CPUPPCState, ca), "CA");
168
169 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
170 offsetof(CPUPPCState, reserve_addr),
171 "reserve_addr");
172
173 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
174 offsetof(CPUPPCState, fpscr), "fpscr");
175
176 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
177 offsetof(CPUPPCState, access_type), "access_type");
178
179 done_init = 1;
180 }
181
182 /* internal defines */
183 typedef struct DisasContext {
184 struct TranslationBlock *tb;
185 target_ulong nip;
186 uint32_t opcode;
187 uint32_t exception;
188 /* Routine used to access memory */
189 int mem_idx;
190 int access_type;
191 /* Translation flags */
192 int le_mode;
193 TCGMemOp default_tcg_memop_mask;
194 #if defined(TARGET_PPC64)
195 int sf_mode;
196 int has_cfar;
197 #endif
198 int fpu_enabled;
199 int altivec_enabled;
200 int vsx_enabled;
201 int spe_enabled;
202 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
203 int singlestep_enabled;
204 uint64_t insns_flags;
205 uint64_t insns_flags2;
206 } DisasContext;
207
208 /* Return true iff byteswap is needed in a scalar memop */
209 static inline bool need_byteswap(const DisasContext *ctx)
210 {
211 #if defined(TARGET_WORDS_BIGENDIAN)
212 return ctx->le_mode;
213 #else
214 return !ctx->le_mode;
215 #endif
216 }
217
218 /* True when active word size < size of target_long. */
219 #ifdef TARGET_PPC64
220 # define NARROW_MODE(C) (!(C)->sf_mode)
221 #else
222 # define NARROW_MODE(C) 0
223 #endif
224
225 struct opc_handler_t {
226 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
227 uint32_t inval1;
228 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
229 uint32_t inval2;
230 /* instruction type */
231 uint64_t type;
232 /* extended instruction type */
233 uint64_t type2;
234 /* handler */
235 void (*handler)(DisasContext *ctx);
236 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
237 const char *oname;
238 #endif
239 #if defined(DO_PPC_STATISTICS)
240 uint64_t count;
241 #endif
242 };
243
244 static inline void gen_reset_fpstatus(void)
245 {
246 gen_helper_reset_fpstatus(cpu_env);
247 }
248
249 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
250 {
251 TCGv_i32 t0 = tcg_temp_new_i32();
252
253 if (set_fprf != 0) {
254 /* This case might be optimized later */
255 tcg_gen_movi_i32(t0, 1);
256 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
257 if (unlikely(set_rc)) {
258 tcg_gen_mov_i32(cpu_crf[1], t0);
259 }
260 gen_helper_float_check_status(cpu_env);
261 } else if (unlikely(set_rc)) {
262 /* We always need to compute fpcc */
263 tcg_gen_movi_i32(t0, 0);
264 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
265 tcg_gen_mov_i32(cpu_crf[1], t0);
266 }
267
268 tcg_temp_free_i32(t0);
269 }
270
271 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
272 {
273 if (ctx->access_type != access_type) {
274 tcg_gen_movi_i32(cpu_access_type, access_type);
275 ctx->access_type = access_type;
276 }
277 }
278
279 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
280 {
281 if (NARROW_MODE(ctx)) {
282 nip = (uint32_t)nip;
283 }
284 tcg_gen_movi_tl(cpu_nip, nip);
285 }
286
287 void gen_update_current_nip(void *opaque)
288 {
289 DisasContext *ctx = opaque;
290
291 tcg_gen_movi_tl(cpu_nip, ctx->nip);
292 }
293
294 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
295 {
296 TCGv_i32 t0, t1;
297 if (ctx->exception == POWERPC_EXCP_NONE) {
298 gen_update_nip(ctx, ctx->nip);
299 }
300 t0 = tcg_const_i32(excp);
301 t1 = tcg_const_i32(error);
302 gen_helper_raise_exception_err(cpu_env, t0, t1);
303 tcg_temp_free_i32(t0);
304 tcg_temp_free_i32(t1);
305 ctx->exception = (excp);
306 }
307
308 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
309 {
310 TCGv_i32 t0;
311 if (ctx->exception == POWERPC_EXCP_NONE) {
312 gen_update_nip(ctx, ctx->nip);
313 }
314 t0 = tcg_const_i32(excp);
315 gen_helper_raise_exception(cpu_env, t0);
316 tcg_temp_free_i32(t0);
317 ctx->exception = (excp);
318 }
319
320 static inline void gen_debug_exception(DisasContext *ctx)
321 {
322 TCGv_i32 t0;
323
324 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
325 (ctx->exception != POWERPC_EXCP_SYNC)) {
326 gen_update_nip(ctx, ctx->nip);
327 }
328 t0 = tcg_const_i32(EXCP_DEBUG);
329 gen_helper_raise_exception(cpu_env, t0);
330 tcg_temp_free_i32(t0);
331 }
332
333 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
334 {
335 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
336 }
337
338 /* Stop translation */
339 static inline void gen_stop_exception(DisasContext *ctx)
340 {
341 gen_update_nip(ctx, ctx->nip);
342 ctx->exception = POWERPC_EXCP_STOP;
343 }
344
345 /* No need to update nip here, as execution flow will change */
346 static inline void gen_sync_exception(DisasContext *ctx)
347 {
348 ctx->exception = POWERPC_EXCP_SYNC;
349 }
350
351 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
352 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
353
354 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
355 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
356
357 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
358 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
359
360 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
361 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
362
363 typedef struct opcode_t {
364 unsigned char opc1, opc2, opc3;
365 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
366 unsigned char pad[5];
367 #else
368 unsigned char pad[1];
369 #endif
370 opc_handler_t handler;
371 const char *oname;
372 } opcode_t;
373
374 /*****************************************************************************/
375 /*** Instruction decoding ***/
376 #define EXTRACT_HELPER(name, shift, nb) \
377 static inline uint32_t name(uint32_t opcode) \
378 { \
379 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
380 }
381
382 #define EXTRACT_SHELPER(name, shift, nb) \
383 static inline int32_t name(uint32_t opcode) \
384 { \
385 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
386 }
387
388 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
389 static inline uint32_t name(uint32_t opcode) \
390 { \
391 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
392 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
393 }
394 /* Opcode part 1 */
395 EXTRACT_HELPER(opc1, 26, 6);
396 /* Opcode part 2 */
397 EXTRACT_HELPER(opc2, 1, 5);
398 /* Opcode part 3 */
399 EXTRACT_HELPER(opc3, 6, 5);
400 /* Update Cr0 flags */
401 EXTRACT_HELPER(Rc, 0, 1);
402 /* Update Cr6 flags (Altivec) */
403 EXTRACT_HELPER(Rc21, 10, 1);
404 /* Destination */
405 EXTRACT_HELPER(rD, 21, 5);
406 /* Source */
407 EXTRACT_HELPER(rS, 21, 5);
408 /* First operand */
409 EXTRACT_HELPER(rA, 16, 5);
410 /* Second operand */
411 EXTRACT_HELPER(rB, 11, 5);
412 /* Third operand */
413 EXTRACT_HELPER(rC, 6, 5);
414 /*** Get CRn ***/
415 EXTRACT_HELPER(crfD, 23, 3);
416 EXTRACT_HELPER(crfS, 18, 3);
417 EXTRACT_HELPER(crbD, 21, 5);
418 EXTRACT_HELPER(crbA, 16, 5);
419 EXTRACT_HELPER(crbB, 11, 5);
420 /* SPR / TBL */
421 EXTRACT_HELPER(_SPR, 11, 10);
422 static inline uint32_t SPR(uint32_t opcode)
423 {
424 uint32_t sprn = _SPR(opcode);
425
426 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
427 }
428 /*** Get constants ***/
429 /* 16 bits signed immediate value */
430 EXTRACT_SHELPER(SIMM, 0, 16);
431 /* 16 bits unsigned immediate value */
432 EXTRACT_HELPER(UIMM, 0, 16);
433 /* 5 bits signed immediate value */
434 EXTRACT_HELPER(SIMM5, 16, 5);
435 /* 5 bits signed immediate value */
436 EXTRACT_HELPER(UIMM5, 16, 5);
437 /* Bit count */
438 EXTRACT_HELPER(NB, 11, 5);
439 /* Shift count */
440 EXTRACT_HELPER(SH, 11, 5);
441 /* Vector shift count */
442 EXTRACT_HELPER(VSH, 6, 4);
443 /* Mask start */
444 EXTRACT_HELPER(MB, 6, 5);
445 /* Mask end */
446 EXTRACT_HELPER(ME, 1, 5);
447 /* Trap operand */
448 EXTRACT_HELPER(TO, 21, 5);
449
450 EXTRACT_HELPER(CRM, 12, 8);
451 EXTRACT_HELPER(SR, 16, 4);
452
453 /* mtfsf/mtfsfi */
454 EXTRACT_HELPER(FPBF, 23, 3);
455 EXTRACT_HELPER(FPIMM, 12, 4);
456 EXTRACT_HELPER(FPL, 25, 1);
457 EXTRACT_HELPER(FPFLM, 17, 8);
458 EXTRACT_HELPER(FPW, 16, 1);
459
460 /*** Jump target decoding ***/
461 /* Immediate address */
462 static inline target_ulong LI(uint32_t opcode)
463 {
464 return (opcode >> 0) & 0x03FFFFFC;
465 }
466
467 static inline uint32_t BD(uint32_t opcode)
468 {
469 return (opcode >> 0) & 0xFFFC;
470 }
471
472 EXTRACT_HELPER(BO, 21, 5);
473 EXTRACT_HELPER(BI, 16, 5);
474 /* Absolute/relative address */
475 EXTRACT_HELPER(AA, 1, 1);
476 /* Link */
477 EXTRACT_HELPER(LK, 0, 1);
478
479 /* DFP Z22-form */
480 EXTRACT_HELPER(DCM, 10, 6)
481
482 /* DFP Z23-form */
483 EXTRACT_HELPER(RMC, 9, 2)
484
485 /* Create a mask between <start> and <end> bits */
486 static inline target_ulong MASK(uint32_t start, uint32_t end)
487 {
488 target_ulong ret;
489
490 #if defined(TARGET_PPC64)
491 if (likely(start == 0)) {
492 ret = UINT64_MAX << (63 - end);
493 } else if (likely(end == 63)) {
494 ret = UINT64_MAX >> start;
495 }
496 #else
497 if (likely(start == 0)) {
498 ret = UINT32_MAX << (31 - end);
499 } else if (likely(end == 31)) {
500 ret = UINT32_MAX >> start;
501 }
502 #endif
503 else {
504 ret = (((target_ulong)(-1ULL)) >> (start)) ^
505 (((target_ulong)(-1ULL) >> (end)) >> 1);
506 if (unlikely(start > end))
507 return ~ret;
508 }
509
510 return ret;
511 }
512
513 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
514 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
515 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
516 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
517 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
518 EXTRACT_HELPER(DM, 8, 2);
519 EXTRACT_HELPER(UIM, 16, 2);
520 EXTRACT_HELPER(SHW, 8, 2);
521 EXTRACT_HELPER(SP, 19, 2);
522 /*****************************************************************************/
523 /* PowerPC instructions table */
524
525 #if defined(DO_PPC_STATISTICS)
526 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
527 { \
528 .opc1 = op1, \
529 .opc2 = op2, \
530 .opc3 = op3, \
531 .pad = { 0, }, \
532 .handler = { \
533 .inval1 = invl, \
534 .type = _typ, \
535 .type2 = _typ2, \
536 .handler = &gen_##name, \
537 .oname = stringify(name), \
538 }, \
539 .oname = stringify(name), \
540 }
541 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
542 { \
543 .opc1 = op1, \
544 .opc2 = op2, \
545 .opc3 = op3, \
546 .pad = { 0, }, \
547 .handler = { \
548 .inval1 = invl1, \
549 .inval2 = invl2, \
550 .type = _typ, \
551 .type2 = _typ2, \
552 .handler = &gen_##name, \
553 .oname = stringify(name), \
554 }, \
555 .oname = stringify(name), \
556 }
557 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
558 { \
559 .opc1 = op1, \
560 .opc2 = op2, \
561 .opc3 = op3, \
562 .pad = { 0, }, \
563 .handler = { \
564 .inval1 = invl, \
565 .type = _typ, \
566 .type2 = _typ2, \
567 .handler = &gen_##name, \
568 .oname = onam, \
569 }, \
570 .oname = onam, \
571 }
572 #else
573 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
574 { \
575 .opc1 = op1, \
576 .opc2 = op2, \
577 .opc3 = op3, \
578 .pad = { 0, }, \
579 .handler = { \
580 .inval1 = invl, \
581 .type = _typ, \
582 .type2 = _typ2, \
583 .handler = &gen_##name, \
584 }, \
585 .oname = stringify(name), \
586 }
587 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
588 { \
589 .opc1 = op1, \
590 .opc2 = op2, \
591 .opc3 = op3, \
592 .pad = { 0, }, \
593 .handler = { \
594 .inval1 = invl1, \
595 .inval2 = invl2, \
596 .type = _typ, \
597 .type2 = _typ2, \
598 .handler = &gen_##name, \
599 }, \
600 .oname = stringify(name), \
601 }
602 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
603 { \
604 .opc1 = op1, \
605 .opc2 = op2, \
606 .opc3 = op3, \
607 .pad = { 0, }, \
608 .handler = { \
609 .inval1 = invl, \
610 .type = _typ, \
611 .type2 = _typ2, \
612 .handler = &gen_##name, \
613 }, \
614 .oname = onam, \
615 }
616 #endif
617
618 /* SPR load/store helpers */
619 static inline void gen_load_spr(TCGv t, int reg)
620 {
621 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
622 }
623
624 static inline void gen_store_spr(int reg, TCGv t)
625 {
626 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
627 }
628
629 /* Invalid instruction */
630 static void gen_invalid(DisasContext *ctx)
631 {
632 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
633 }
634
635 static opc_handler_t invalid_handler = {
636 .inval1 = 0xFFFFFFFF,
637 .inval2 = 0xFFFFFFFF,
638 .type = PPC_NONE,
639 .type2 = PPC_NONE,
640 .handler = gen_invalid,
641 };
642
643 #if defined(TARGET_PPC64)
644 /* NOTE: as this time, the only use of is_user_mode() is in 64 bit code. And */
645 /* so the function is wrapped in the standard 64-bit ifdef in order to */
646 /* avoid compiler warnings in 32-bit implementations. */
647 static bool is_user_mode(DisasContext *ctx)
648 {
649 #if defined(CONFIG_USER_ONLY)
650 return true;
651 #else
652 return ctx->mem_idx == 0;
653 #endif
654 }
655 #endif
656
657 /*** Integer comparison ***/
658
659 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
660 {
661 TCGv t0 = tcg_temp_new();
662 TCGv_i32 t1 = tcg_temp_new_i32();
663
664 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
665
666 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
667 tcg_gen_trunc_tl_i32(t1, t0);
668 tcg_gen_shli_i32(t1, t1, CRF_LT);
669 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
670
671 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
672 tcg_gen_trunc_tl_i32(t1, t0);
673 tcg_gen_shli_i32(t1, t1, CRF_GT);
674 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
675
676 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
677 tcg_gen_trunc_tl_i32(t1, t0);
678 tcg_gen_shli_i32(t1, t1, CRF_EQ);
679 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
680
681 tcg_temp_free(t0);
682 tcg_temp_free_i32(t1);
683 }
684
685 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
686 {
687 TCGv t0 = tcg_const_tl(arg1);
688 gen_op_cmp(arg0, t0, s, crf);
689 tcg_temp_free(t0);
690 }
691
692 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
693 {
694 TCGv t0, t1;
695 t0 = tcg_temp_new();
696 t1 = tcg_temp_new();
697 if (s) {
698 tcg_gen_ext32s_tl(t0, arg0);
699 tcg_gen_ext32s_tl(t1, arg1);
700 } else {
701 tcg_gen_ext32u_tl(t0, arg0);
702 tcg_gen_ext32u_tl(t1, arg1);
703 }
704 gen_op_cmp(t0, t1, s, crf);
705 tcg_temp_free(t1);
706 tcg_temp_free(t0);
707 }
708
709 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
710 {
711 TCGv t0 = tcg_const_tl(arg1);
712 gen_op_cmp32(arg0, t0, s, crf);
713 tcg_temp_free(t0);
714 }
715
716 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
717 {
718 if (NARROW_MODE(ctx)) {
719 gen_op_cmpi32(reg, 0, 1, 0);
720 } else {
721 gen_op_cmpi(reg, 0, 1, 0);
722 }
723 }
724
725 /* cmp */
726 static void gen_cmp(DisasContext *ctx)
727 {
728 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
729 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
730 1, crfD(ctx->opcode));
731 } else {
732 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
733 1, crfD(ctx->opcode));
734 }
735 }
736
737 /* cmpi */
738 static void gen_cmpi(DisasContext *ctx)
739 {
740 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
741 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
742 1, crfD(ctx->opcode));
743 } else {
744 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
745 1, crfD(ctx->opcode));
746 }
747 }
748
749 /* cmpl */
750 static void gen_cmpl(DisasContext *ctx)
751 {
752 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
753 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
754 0, crfD(ctx->opcode));
755 } else {
756 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
757 0, crfD(ctx->opcode));
758 }
759 }
760
761 /* cmpli */
762 static void gen_cmpli(DisasContext *ctx)
763 {
764 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
765 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
766 0, crfD(ctx->opcode));
767 } else {
768 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
769 0, crfD(ctx->opcode));
770 }
771 }
772
773 /* isel (PowerPC 2.03 specification) */
774 static void gen_isel(DisasContext *ctx)
775 {
776 int l1, l2;
777 uint32_t bi = rC(ctx->opcode);
778 uint32_t mask;
779 TCGv_i32 t0;
780
781 l1 = gen_new_label();
782 l2 = gen_new_label();
783
784 mask = 1 << (3 - (bi & 0x03));
785 t0 = tcg_temp_new_i32();
786 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
787 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
788 if (rA(ctx->opcode) == 0)
789 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
790 else
791 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
792 tcg_gen_br(l2);
793 gen_set_label(l1);
794 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
795 gen_set_label(l2);
796 tcg_temp_free_i32(t0);
797 }
798
799 /* cmpb: PowerPC 2.05 specification */
800 static void gen_cmpb(DisasContext *ctx)
801 {
802 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
803 cpu_gpr[rB(ctx->opcode)]);
804 }
805
806 /*** Integer arithmetic ***/
807
808 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
809 TCGv arg1, TCGv arg2, int sub)
810 {
811 TCGv t0 = tcg_temp_new();
812
813 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
814 tcg_gen_xor_tl(t0, arg1, arg2);
815 if (sub) {
816 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
817 } else {
818 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
819 }
820 tcg_temp_free(t0);
821 if (NARROW_MODE(ctx)) {
822 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
823 }
824 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
825 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
826 }
827
828 /* Common add function */
829 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
830 TCGv arg2, bool add_ca, bool compute_ca,
831 bool compute_ov, bool compute_rc0)
832 {
833 TCGv t0 = ret;
834
835 if (compute_ca || compute_ov) {
836 t0 = tcg_temp_new();
837 }
838
839 if (compute_ca) {
840 if (NARROW_MODE(ctx)) {
841 /* Caution: a non-obvious corner case of the spec is that we
842 must produce the *entire* 64-bit addition, but produce the
843 carry into bit 32. */
844 TCGv t1 = tcg_temp_new();
845 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
846 tcg_gen_add_tl(t0, arg1, arg2);
847 if (add_ca) {
848 tcg_gen_add_tl(t0, t0, cpu_ca);
849 }
850 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
851 tcg_temp_free(t1);
852 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
853 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
854 } else {
855 TCGv zero = tcg_const_tl(0);
856 if (add_ca) {
857 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
858 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
859 } else {
860 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
861 }
862 tcg_temp_free(zero);
863 }
864 } else {
865 tcg_gen_add_tl(t0, arg1, arg2);
866 if (add_ca) {
867 tcg_gen_add_tl(t0, t0, cpu_ca);
868 }
869 }
870
871 if (compute_ov) {
872 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
873 }
874 if (unlikely(compute_rc0)) {
875 gen_set_Rc0(ctx, t0);
876 }
877
878 if (!TCGV_EQUAL(t0, ret)) {
879 tcg_gen_mov_tl(ret, t0);
880 tcg_temp_free(t0);
881 }
882 }
883 /* Add functions with two operands */
884 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
885 static void glue(gen_, name)(DisasContext *ctx) \
886 { \
887 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
888 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
889 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
890 }
891 /* Add functions with one operand and one immediate */
892 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
893 add_ca, compute_ca, compute_ov) \
894 static void glue(gen_, name)(DisasContext *ctx) \
895 { \
896 TCGv t0 = tcg_const_tl(const_val); \
897 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
898 cpu_gpr[rA(ctx->opcode)], t0, \
899 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
900 tcg_temp_free(t0); \
901 }
902
903 /* add add. addo addo. */
904 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
905 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
906 /* addc addc. addco addco. */
907 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
908 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
909 /* adde adde. addeo addeo. */
910 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
911 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
912 /* addme addme. addmeo addmeo. */
913 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
914 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
915 /* addze addze. addzeo addzeo.*/
916 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
917 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
918 /* addi */
919 static void gen_addi(DisasContext *ctx)
920 {
921 target_long simm = SIMM(ctx->opcode);
922
923 if (rA(ctx->opcode) == 0) {
924 /* li case */
925 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
926 } else {
927 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
928 cpu_gpr[rA(ctx->opcode)], simm);
929 }
930 }
931 /* addic addic.*/
932 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
933 {
934 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
935 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
936 c, 0, 1, 0, compute_rc0);
937 tcg_temp_free(c);
938 }
939
940 static void gen_addic(DisasContext *ctx)
941 {
942 gen_op_addic(ctx, 0);
943 }
944
945 static void gen_addic_(DisasContext *ctx)
946 {
947 gen_op_addic(ctx, 1);
948 }
949
950 /* addis */
951 static void gen_addis(DisasContext *ctx)
952 {
953 target_long simm = SIMM(ctx->opcode);
954
955 if (rA(ctx->opcode) == 0) {
956 /* lis case */
957 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
958 } else {
959 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
960 cpu_gpr[rA(ctx->opcode)], simm << 16);
961 }
962 }
963
964 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
965 TCGv arg2, int sign, int compute_ov)
966 {
967 int l1 = gen_new_label();
968 int l2 = gen_new_label();
969 TCGv_i32 t0 = tcg_temp_local_new_i32();
970 TCGv_i32 t1 = tcg_temp_local_new_i32();
971
972 tcg_gen_trunc_tl_i32(t0, arg1);
973 tcg_gen_trunc_tl_i32(t1, arg2);
974 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
975 if (sign) {
976 int l3 = gen_new_label();
977 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
978 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
979 gen_set_label(l3);
980 tcg_gen_div_i32(t0, t0, t1);
981 } else {
982 tcg_gen_divu_i32(t0, t0, t1);
983 }
984 if (compute_ov) {
985 tcg_gen_movi_tl(cpu_ov, 0);
986 }
987 tcg_gen_br(l2);
988 gen_set_label(l1);
989 if (sign) {
990 tcg_gen_sari_i32(t0, t0, 31);
991 } else {
992 tcg_gen_movi_i32(t0, 0);
993 }
994 if (compute_ov) {
995 tcg_gen_movi_tl(cpu_ov, 1);
996 tcg_gen_movi_tl(cpu_so, 1);
997 }
998 gen_set_label(l2);
999 tcg_gen_extu_i32_tl(ret, t0);
1000 tcg_temp_free_i32(t0);
1001 tcg_temp_free_i32(t1);
1002 if (unlikely(Rc(ctx->opcode) != 0))
1003 gen_set_Rc0(ctx, ret);
1004 }
1005 /* Div functions */
1006 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1007 static void glue(gen_, name)(DisasContext *ctx) \
1008 { \
1009 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1010 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1011 sign, compute_ov); \
1012 }
1013 /* divwu divwu. divwuo divwuo. */
1014 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1015 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1016 /* divw divw. divwo divwo. */
1017 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1018 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1019
1020 /* div[wd]eu[o][.] */
1021 #define GEN_DIVE(name, hlpr, compute_ov) \
1022 static void gen_##name(DisasContext *ctx) \
1023 { \
1024 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1025 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1026 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1027 tcg_temp_free_i32(t0); \
1028 if (unlikely(Rc(ctx->opcode) != 0)) { \
1029 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1030 } \
1031 }
1032
1033 GEN_DIVE(divweu, divweu, 0);
1034 GEN_DIVE(divweuo, divweu, 1);
1035 GEN_DIVE(divwe, divwe, 0);
1036 GEN_DIVE(divweo, divwe, 1);
1037
1038 #if defined(TARGET_PPC64)
1039 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1040 TCGv arg2, int sign, int compute_ov)
1041 {
1042 int l1 = gen_new_label();
1043 int l2 = gen_new_label();
1044
1045 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1046 if (sign) {
1047 int l3 = gen_new_label();
1048 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1049 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1050 gen_set_label(l3);
1051 tcg_gen_div_i64(ret, arg1, arg2);
1052 } else {
1053 tcg_gen_divu_i64(ret, arg1, arg2);
1054 }
1055 if (compute_ov) {
1056 tcg_gen_movi_tl(cpu_ov, 0);
1057 }
1058 tcg_gen_br(l2);
1059 gen_set_label(l1);
1060 if (sign) {
1061 tcg_gen_sari_i64(ret, arg1, 63);
1062 } else {
1063 tcg_gen_movi_i64(ret, 0);
1064 }
1065 if (compute_ov) {
1066 tcg_gen_movi_tl(cpu_ov, 1);
1067 tcg_gen_movi_tl(cpu_so, 1);
1068 }
1069 gen_set_label(l2);
1070 if (unlikely(Rc(ctx->opcode) != 0))
1071 gen_set_Rc0(ctx, ret);
1072 }
1073 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1074 static void glue(gen_, name)(DisasContext *ctx) \
1075 { \
1076 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1077 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1078 sign, compute_ov); \
1079 }
1080 /* divwu divwu. divwuo divwuo. */
1081 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1082 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1083 /* divw divw. divwo divwo. */
1084 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1085 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1086
1087 GEN_DIVE(divdeu, divdeu, 0);
1088 GEN_DIVE(divdeuo, divdeu, 1);
1089 GEN_DIVE(divde, divde, 0);
1090 GEN_DIVE(divdeo, divde, 1);
1091 #endif
1092
1093 /* mulhw mulhw. */
1094 static void gen_mulhw(DisasContext *ctx)
1095 {
1096 TCGv_i32 t0 = tcg_temp_new_i32();
1097 TCGv_i32 t1 = tcg_temp_new_i32();
1098
1099 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1100 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1101 tcg_gen_muls2_i32(t0, t1, t0, t1);
1102 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1103 tcg_temp_free_i32(t0);
1104 tcg_temp_free_i32(t1);
1105 if (unlikely(Rc(ctx->opcode) != 0))
1106 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1107 }
1108
1109 /* mulhwu mulhwu. */
1110 static void gen_mulhwu(DisasContext *ctx)
1111 {
1112 TCGv_i32 t0 = tcg_temp_new_i32();
1113 TCGv_i32 t1 = tcg_temp_new_i32();
1114
1115 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1116 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1117 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1118 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1119 tcg_temp_free_i32(t0);
1120 tcg_temp_free_i32(t1);
1121 if (unlikely(Rc(ctx->opcode) != 0))
1122 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1123 }
1124
1125 /* mullw mullw. */
1126 static void gen_mullw(DisasContext *ctx)
1127 {
1128 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1129 cpu_gpr[rB(ctx->opcode)]);
1130 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1131 if (unlikely(Rc(ctx->opcode) != 0))
1132 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1133 }
1134
1135 /* mullwo mullwo. */
1136 static void gen_mullwo(DisasContext *ctx)
1137 {
1138 TCGv_i32 t0 = tcg_temp_new_i32();
1139 TCGv_i32 t1 = tcg_temp_new_i32();
1140
1141 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1142 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1143 tcg_gen_muls2_i32(t0, t1, t0, t1);
1144 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1145
1146 tcg_gen_sari_i32(t0, t0, 31);
1147 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1148 tcg_gen_extu_i32_tl(cpu_ov, t0);
1149 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1150
1151 tcg_temp_free_i32(t0);
1152 tcg_temp_free_i32(t1);
1153 if (unlikely(Rc(ctx->opcode) != 0))
1154 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1155 }
1156
1157 /* mulli */
1158 static void gen_mulli(DisasContext *ctx)
1159 {
1160 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1161 SIMM(ctx->opcode));
1162 }
1163
1164 #if defined(TARGET_PPC64)
1165 /* mulhd mulhd. */
1166 static void gen_mulhd(DisasContext *ctx)
1167 {
1168 TCGv lo = tcg_temp_new();
1169 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1170 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1171 tcg_temp_free(lo);
1172 if (unlikely(Rc(ctx->opcode) != 0)) {
1173 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1174 }
1175 }
1176
1177 /* mulhdu mulhdu. */
1178 static void gen_mulhdu(DisasContext *ctx)
1179 {
1180 TCGv lo = tcg_temp_new();
1181 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1182 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1183 tcg_temp_free(lo);
1184 if (unlikely(Rc(ctx->opcode) != 0)) {
1185 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1186 }
1187 }
1188
1189 /* mulld mulld. */
1190 static void gen_mulld(DisasContext *ctx)
1191 {
1192 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1193 cpu_gpr[rB(ctx->opcode)]);
1194 if (unlikely(Rc(ctx->opcode) != 0))
1195 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1196 }
1197
1198 /* mulldo mulldo. */
1199 static void gen_mulldo(DisasContext *ctx)
1200 {
1201 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1202 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1203 if (unlikely(Rc(ctx->opcode) != 0)) {
1204 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1205 }
1206 }
1207 #endif
1208
1209 /* Common subf function */
1210 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1211 TCGv arg2, bool add_ca, bool compute_ca,
1212 bool compute_ov, bool compute_rc0)
1213 {
1214 TCGv t0 = ret;
1215
1216 if (compute_ca || compute_ov) {
1217 t0 = tcg_temp_new();
1218 }
1219
1220 if (compute_ca) {
1221 /* dest = ~arg1 + arg2 [+ ca]. */
1222 if (NARROW_MODE(ctx)) {
1223 /* Caution: a non-obvious corner case of the spec is that we
1224 must produce the *entire* 64-bit addition, but produce the
1225 carry into bit 32. */
1226 TCGv inv1 = tcg_temp_new();
1227 TCGv t1 = tcg_temp_new();
1228 tcg_gen_not_tl(inv1, arg1);
1229 if (add_ca) {
1230 tcg_gen_add_tl(t0, arg2, cpu_ca);
1231 } else {
1232 tcg_gen_addi_tl(t0, arg2, 1);
1233 }
1234 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1235 tcg_gen_add_tl(t0, t0, inv1);
1236 tcg_temp_free(inv1);
1237 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1238 tcg_temp_free(t1);
1239 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1240 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1241 } else if (add_ca) {
1242 TCGv zero, inv1 = tcg_temp_new();
1243 tcg_gen_not_tl(inv1, arg1);
1244 zero = tcg_const_tl(0);
1245 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1246 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1247 tcg_temp_free(zero);
1248 tcg_temp_free(inv1);
1249 } else {
1250 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1251 tcg_gen_sub_tl(t0, arg2, arg1);
1252 }
1253 } else if (add_ca) {
1254 /* Since we're ignoring carry-out, we can simplify the
1255 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1256 tcg_gen_sub_tl(t0, arg2, arg1);
1257 tcg_gen_add_tl(t0, t0, cpu_ca);
1258 tcg_gen_subi_tl(t0, t0, 1);
1259 } else {
1260 tcg_gen_sub_tl(t0, arg2, arg1);
1261 }
1262
1263 if (compute_ov) {
1264 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1265 }
1266 if (unlikely(compute_rc0)) {
1267 gen_set_Rc0(ctx, t0);
1268 }
1269
1270 if (!TCGV_EQUAL(t0, ret)) {
1271 tcg_gen_mov_tl(ret, t0);
1272 tcg_temp_free(t0);
1273 }
1274 }
1275 /* Sub functions with Two operands functions */
1276 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1277 static void glue(gen_, name)(DisasContext *ctx) \
1278 { \
1279 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1280 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1281 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1282 }
1283 /* Sub functions with one operand and one immediate */
1284 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1285 add_ca, compute_ca, compute_ov) \
1286 static void glue(gen_, name)(DisasContext *ctx) \
1287 { \
1288 TCGv t0 = tcg_const_tl(const_val); \
1289 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1290 cpu_gpr[rA(ctx->opcode)], t0, \
1291 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1292 tcg_temp_free(t0); \
1293 }
1294 /* subf subf. subfo subfo. */
1295 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1296 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1297 /* subfc subfc. subfco subfco. */
1298 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1299 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1300 /* subfe subfe. subfeo subfo. */
1301 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1302 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1303 /* subfme subfme. subfmeo subfmeo. */
1304 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1305 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1306 /* subfze subfze. subfzeo subfzeo.*/
1307 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1308 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1309
1310 /* subfic */
1311 static void gen_subfic(DisasContext *ctx)
1312 {
1313 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1314 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1315 c, 0, 1, 0, 0);
1316 tcg_temp_free(c);
1317 }
1318
1319 /* neg neg. nego nego. */
1320 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1321 {
1322 TCGv zero = tcg_const_tl(0);
1323 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1324 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1325 tcg_temp_free(zero);
1326 }
1327
1328 static void gen_neg(DisasContext *ctx)
1329 {
1330 gen_op_arith_neg(ctx, 0);
1331 }
1332
1333 static void gen_nego(DisasContext *ctx)
1334 {
1335 gen_op_arith_neg(ctx, 1);
1336 }
1337
1338 /*** Integer logical ***/
1339 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1340 static void glue(gen_, name)(DisasContext *ctx) \
1341 { \
1342 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1343 cpu_gpr[rB(ctx->opcode)]); \
1344 if (unlikely(Rc(ctx->opcode) != 0)) \
1345 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1346 }
1347
1348 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1349 static void glue(gen_, name)(DisasContext *ctx) \
1350 { \
1351 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1352 if (unlikely(Rc(ctx->opcode) != 0)) \
1353 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1354 }
1355
1356 /* and & and. */
1357 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1358 /* andc & andc. */
1359 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1360
1361 /* andi. */
1362 static void gen_andi_(DisasContext *ctx)
1363 {
1364 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1365 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1366 }
1367
1368 /* andis. */
1369 static void gen_andis_(DisasContext *ctx)
1370 {
1371 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1372 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1373 }
1374
1375 /* cntlzw */
1376 static void gen_cntlzw(DisasContext *ctx)
1377 {
1378 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1379 if (unlikely(Rc(ctx->opcode) != 0))
1380 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1381 }
1382 /* eqv & eqv. */
1383 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1384 /* extsb & extsb. */
1385 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1386 /* extsh & extsh. */
1387 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1388 /* nand & nand. */
1389 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1390 /* nor & nor. */
1391 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1392
1393 /* or & or. */
1394 static void gen_or(DisasContext *ctx)
1395 {
1396 int rs, ra, rb;
1397
1398 rs = rS(ctx->opcode);
1399 ra = rA(ctx->opcode);
1400 rb = rB(ctx->opcode);
1401 /* Optimisation for mr. ri case */
1402 if (rs != ra || rs != rb) {
1403 if (rs != rb)
1404 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1405 else
1406 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1407 if (unlikely(Rc(ctx->opcode) != 0))
1408 gen_set_Rc0(ctx, cpu_gpr[ra]);
1409 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1410 gen_set_Rc0(ctx, cpu_gpr[rs]);
1411 #if defined(TARGET_PPC64)
1412 } else {
1413 int prio = 0;
1414
1415 switch (rs) {
1416 case 1:
1417 /* Set process priority to low */
1418 prio = 2;
1419 break;
1420 case 6:
1421 /* Set process priority to medium-low */
1422 prio = 3;
1423 break;
1424 case 2:
1425 /* Set process priority to normal */
1426 prio = 4;
1427 break;
1428 #if !defined(CONFIG_USER_ONLY)
1429 case 31:
1430 if (ctx->mem_idx > 0) {
1431 /* Set process priority to very low */
1432 prio = 1;
1433 }
1434 break;
1435 case 5:
1436 if (ctx->mem_idx > 0) {
1437 /* Set process priority to medium-hight */
1438 prio = 5;
1439 }
1440 break;
1441 case 3:
1442 if (ctx->mem_idx > 0) {
1443 /* Set process priority to high */
1444 prio = 6;
1445 }
1446 break;
1447 case 7:
1448 if (ctx->mem_idx > 1) {
1449 /* Set process priority to very high */
1450 prio = 7;
1451 }
1452 break;
1453 #endif
1454 default:
1455 /* nop */
1456 break;
1457 }
1458 if (prio) {
1459 TCGv t0 = tcg_temp_new();
1460 gen_load_spr(t0, SPR_PPR);
1461 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1462 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1463 gen_store_spr(SPR_PPR, t0);
1464 tcg_temp_free(t0);
1465 }
1466 #endif
1467 }
1468 }
1469 /* orc & orc. */
1470 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1471
1472 /* xor & xor. */
1473 static void gen_xor(DisasContext *ctx)
1474 {
1475 /* Optimisation for "set to zero" case */
1476 if (rS(ctx->opcode) != rB(ctx->opcode))
1477 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1478 else
1479 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1480 if (unlikely(Rc(ctx->opcode) != 0))
1481 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1482 }
1483
1484 /* ori */
1485 static void gen_ori(DisasContext *ctx)
1486 {
1487 target_ulong uimm = UIMM(ctx->opcode);
1488
1489 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1490 /* NOP */
1491 /* XXX: should handle special NOPs for POWER series */
1492 return;
1493 }
1494 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1495 }
1496
1497 /* oris */
1498 static void gen_oris(DisasContext *ctx)
1499 {
1500 target_ulong uimm = UIMM(ctx->opcode);
1501
1502 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1503 /* NOP */
1504 return;
1505 }
1506 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1507 }
1508
1509 /* xori */
1510 static void gen_xori(DisasContext *ctx)
1511 {
1512 target_ulong uimm = UIMM(ctx->opcode);
1513
1514 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1515 /* NOP */
1516 return;
1517 }
1518 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1519 }
1520
1521 /* xoris */
1522 static void gen_xoris(DisasContext *ctx)
1523 {
1524 target_ulong uimm = UIMM(ctx->opcode);
1525
1526 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1527 /* NOP */
1528 return;
1529 }
1530 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1531 }
1532
1533 /* popcntb : PowerPC 2.03 specification */
1534 static void gen_popcntb(DisasContext *ctx)
1535 {
1536 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1537 }
1538
1539 static void gen_popcntw(DisasContext *ctx)
1540 {
1541 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1542 }
1543
1544 #if defined(TARGET_PPC64)
1545 /* popcntd: PowerPC 2.06 specification */
1546 static void gen_popcntd(DisasContext *ctx)
1547 {
1548 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1549 }
1550 #endif
1551
1552 /* prtyw: PowerPC 2.05 specification */
1553 static void gen_prtyw(DisasContext *ctx)
1554 {
1555 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1556 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1557 TCGv t0 = tcg_temp_new();
1558 tcg_gen_shri_tl(t0, rs, 16);
1559 tcg_gen_xor_tl(ra, rs, t0);
1560 tcg_gen_shri_tl(t0, ra, 8);
1561 tcg_gen_xor_tl(ra, ra, t0);
1562 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1563 tcg_temp_free(t0);
1564 }
1565
1566 #if defined(TARGET_PPC64)
1567 /* prtyd: PowerPC 2.05 specification */
1568 static void gen_prtyd(DisasContext *ctx)
1569 {
1570 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1571 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1572 TCGv t0 = tcg_temp_new();
1573 tcg_gen_shri_tl(t0, rs, 32);
1574 tcg_gen_xor_tl(ra, rs, t0);
1575 tcg_gen_shri_tl(t0, ra, 16);
1576 tcg_gen_xor_tl(ra, ra, t0);
1577 tcg_gen_shri_tl(t0, ra, 8);
1578 tcg_gen_xor_tl(ra, ra, t0);
1579 tcg_gen_andi_tl(ra, ra, 1);
1580 tcg_temp_free(t0);
1581 }
1582 #endif
1583
1584 #if defined(TARGET_PPC64)
1585 /* bpermd */
1586 static void gen_bpermd(DisasContext *ctx)
1587 {
1588 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1589 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1590 }
1591 #endif
1592
1593 #if defined(TARGET_PPC64)
1594 /* extsw & extsw. */
1595 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1596
1597 /* cntlzd */
1598 static void gen_cntlzd(DisasContext *ctx)
1599 {
1600 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1601 if (unlikely(Rc(ctx->opcode) != 0))
1602 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1603 }
1604 #endif
1605
1606 /*** Integer rotate ***/
1607
1608 /* rlwimi & rlwimi. */
1609 static void gen_rlwimi(DisasContext *ctx)
1610 {
1611 uint32_t mb, me, sh;
1612
1613 mb = MB(ctx->opcode);
1614 me = ME(ctx->opcode);
1615 sh = SH(ctx->opcode);
1616 if (likely(sh == 0 && mb == 0 && me == 31)) {
1617 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1618 } else {
1619 target_ulong mask;
1620 TCGv t1;
1621 TCGv t0 = tcg_temp_new();
1622 #if defined(TARGET_PPC64)
1623 TCGv_i32 t2 = tcg_temp_new_i32();
1624 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1625 tcg_gen_rotli_i32(t2, t2, sh);
1626 tcg_gen_extu_i32_i64(t0, t2);
1627 tcg_temp_free_i32(t2);
1628 #else
1629 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1630 #endif
1631 #if defined(TARGET_PPC64)
1632 mb += 32;
1633 me += 32;
1634 #endif
1635 mask = MASK(mb, me);
1636 t1 = tcg_temp_new();
1637 tcg_gen_andi_tl(t0, t0, mask);
1638 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1639 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1640 tcg_temp_free(t0);
1641 tcg_temp_free(t1);
1642 }
1643 if (unlikely(Rc(ctx->opcode) != 0))
1644 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1645 }
1646
1647 /* rlwinm & rlwinm. */
1648 static void gen_rlwinm(DisasContext *ctx)
1649 {
1650 uint32_t mb, me, sh;
1651
1652 sh = SH(ctx->opcode);
1653 mb = MB(ctx->opcode);
1654 me = ME(ctx->opcode);
1655
1656 if (likely(mb == 0 && me == (31 - sh))) {
1657 if (likely(sh == 0)) {
1658 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1659 } else {
1660 TCGv t0 = tcg_temp_new();
1661 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1662 tcg_gen_shli_tl(t0, t0, sh);
1663 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1664 tcg_temp_free(t0);
1665 }
1666 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1667 TCGv t0 = tcg_temp_new();
1668 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1669 tcg_gen_shri_tl(t0, t0, mb);
1670 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1671 tcg_temp_free(t0);
1672 } else {
1673 TCGv t0 = tcg_temp_new();
1674 #if defined(TARGET_PPC64)
1675 TCGv_i32 t1 = tcg_temp_new_i32();
1676 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1677 tcg_gen_rotli_i32(t1, t1, sh);
1678 tcg_gen_extu_i32_i64(t0, t1);
1679 tcg_temp_free_i32(t1);
1680 #else
1681 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1682 #endif
1683 #if defined(TARGET_PPC64)
1684 mb += 32;
1685 me += 32;
1686 #endif
1687 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1688 tcg_temp_free(t0);
1689 }
1690 if (unlikely(Rc(ctx->opcode) != 0))
1691 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1692 }
1693
1694 /* rlwnm & rlwnm. */
1695 static void gen_rlwnm(DisasContext *ctx)
1696 {
1697 uint32_t mb, me;
1698 TCGv t0;
1699 #if defined(TARGET_PPC64)
1700 TCGv_i32 t1, t2;
1701 #endif
1702
1703 mb = MB(ctx->opcode);
1704 me = ME(ctx->opcode);
1705 t0 = tcg_temp_new();
1706 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1707 #if defined(TARGET_PPC64)
1708 t1 = tcg_temp_new_i32();
1709 t2 = tcg_temp_new_i32();
1710 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1711 tcg_gen_trunc_i64_i32(t2, t0);
1712 tcg_gen_rotl_i32(t1, t1, t2);
1713 tcg_gen_extu_i32_i64(t0, t1);
1714 tcg_temp_free_i32(t1);
1715 tcg_temp_free_i32(t2);
1716 #else
1717 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1718 #endif
1719 if (unlikely(mb != 0 || me != 31)) {
1720 #if defined(TARGET_PPC64)
1721 mb += 32;
1722 me += 32;
1723 #endif
1724 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1725 } else {
1726 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1727 }
1728 tcg_temp_free(t0);
1729 if (unlikely(Rc(ctx->opcode) != 0))
1730 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1731 }
1732
1733 #if defined(TARGET_PPC64)
1734 #define GEN_PPC64_R2(name, opc1, opc2) \
1735 static void glue(gen_, name##0)(DisasContext *ctx) \
1736 { \
1737 gen_##name(ctx, 0); \
1738 } \
1739 \
1740 static void glue(gen_, name##1)(DisasContext *ctx) \
1741 { \
1742 gen_##name(ctx, 1); \
1743 }
1744 #define GEN_PPC64_R4(name, opc1, opc2) \
1745 static void glue(gen_, name##0)(DisasContext *ctx) \
1746 { \
1747 gen_##name(ctx, 0, 0); \
1748 } \
1749 \
1750 static void glue(gen_, name##1)(DisasContext *ctx) \
1751 { \
1752 gen_##name(ctx, 0, 1); \
1753 } \
1754 \
1755 static void glue(gen_, name##2)(DisasContext *ctx) \
1756 { \
1757 gen_##name(ctx, 1, 0); \
1758 } \
1759 \
1760 static void glue(gen_, name##3)(DisasContext *ctx) \
1761 { \
1762 gen_##name(ctx, 1, 1); \
1763 }
1764
1765 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1766 uint32_t sh)
1767 {
1768 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1769 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1770 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1771 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1772 } else {
1773 TCGv t0 = tcg_temp_new();
1774 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1775 if (likely(mb == 0 && me == 63)) {
1776 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1777 } else {
1778 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1779 }
1780 tcg_temp_free(t0);
1781 }
1782 if (unlikely(Rc(ctx->opcode) != 0))
1783 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1784 }
1785 /* rldicl - rldicl. */
1786 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1787 {
1788 uint32_t sh, mb;
1789
1790 sh = SH(ctx->opcode) | (shn << 5);
1791 mb = MB(ctx->opcode) | (mbn << 5);
1792 gen_rldinm(ctx, mb, 63, sh);
1793 }
1794 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1795 /* rldicr - rldicr. */
1796 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1797 {
1798 uint32_t sh, me;
1799
1800 sh = SH(ctx->opcode) | (shn << 5);
1801 me = MB(ctx->opcode) | (men << 5);
1802 gen_rldinm(ctx, 0, me, sh);
1803 }
1804 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1805 /* rldic - rldic. */
1806 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1807 {
1808 uint32_t sh, mb;
1809
1810 sh = SH(ctx->opcode) | (shn << 5);
1811 mb = MB(ctx->opcode) | (mbn << 5);
1812 gen_rldinm(ctx, mb, 63 - sh, sh);
1813 }
1814 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1815
1816 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1817 {
1818 TCGv t0;
1819
1820 t0 = tcg_temp_new();
1821 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1822 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1823 if (unlikely(mb != 0 || me != 63)) {
1824 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1825 } else {
1826 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1827 }
1828 tcg_temp_free(t0);
1829 if (unlikely(Rc(ctx->opcode) != 0))
1830 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1831 }
1832
1833 /* rldcl - rldcl. */
1834 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1835 {
1836 uint32_t mb;
1837
1838 mb = MB(ctx->opcode) | (mbn << 5);
1839 gen_rldnm(ctx, mb, 63);
1840 }
1841 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1842 /* rldcr - rldcr. */
1843 static inline void gen_rldcr(DisasContext *ctx, int men)
1844 {
1845 uint32_t me;
1846
1847 me = MB(ctx->opcode) | (men << 5);
1848 gen_rldnm(ctx, 0, me);
1849 }
1850 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1851 /* rldimi - rldimi. */
1852 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1853 {
1854 uint32_t sh, mb, me;
1855
1856 sh = SH(ctx->opcode) | (shn << 5);
1857 mb = MB(ctx->opcode) | (mbn << 5);
1858 me = 63 - sh;
1859 if (unlikely(sh == 0 && mb == 0)) {
1860 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1861 } else {
1862 TCGv t0, t1;
1863 target_ulong mask;
1864
1865 t0 = tcg_temp_new();
1866 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1867 t1 = tcg_temp_new();
1868 mask = MASK(mb, me);
1869 tcg_gen_andi_tl(t0, t0, mask);
1870 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1871 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1872 tcg_temp_free(t0);
1873 tcg_temp_free(t1);
1874 }
1875 if (unlikely(Rc(ctx->opcode) != 0))
1876 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1877 }
1878 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1879 #endif
1880
1881 /*** Integer shift ***/
1882
1883 /* slw & slw. */
1884 static void gen_slw(DisasContext *ctx)
1885 {
1886 TCGv t0, t1;
1887
1888 t0 = tcg_temp_new();
1889 /* AND rS with a mask that is 0 when rB >= 0x20 */
1890 #if defined(TARGET_PPC64)
1891 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1892 tcg_gen_sari_tl(t0, t0, 0x3f);
1893 #else
1894 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1895 tcg_gen_sari_tl(t0, t0, 0x1f);
1896 #endif
1897 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1898 t1 = tcg_temp_new();
1899 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1900 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1901 tcg_temp_free(t1);
1902 tcg_temp_free(t0);
1903 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1904 if (unlikely(Rc(ctx->opcode) != 0))
1905 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1906 }
1907
1908 /* sraw & sraw. */
1909 static void gen_sraw(DisasContext *ctx)
1910 {
1911 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1912 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1913 if (unlikely(Rc(ctx->opcode) != 0))
1914 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1915 }
1916
1917 /* srawi & srawi. */
1918 static void gen_srawi(DisasContext *ctx)
1919 {
1920 int sh = SH(ctx->opcode);
1921 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1922 TCGv src = cpu_gpr[rS(ctx->opcode)];
1923 if (sh == 0) {
1924 tcg_gen_mov_tl(dst, src);
1925 tcg_gen_movi_tl(cpu_ca, 0);
1926 } else {
1927 TCGv t0;
1928 tcg_gen_ext32s_tl(dst, src);
1929 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1930 t0 = tcg_temp_new();
1931 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1932 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1933 tcg_temp_free(t0);
1934 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1935 tcg_gen_sari_tl(dst, dst, sh);
1936 }
1937 if (unlikely(Rc(ctx->opcode) != 0)) {
1938 gen_set_Rc0(ctx, dst);
1939 }
1940 }
1941
1942 /* srw & srw. */
1943 static void gen_srw(DisasContext *ctx)
1944 {
1945 TCGv t0, t1;
1946
1947 t0 = tcg_temp_new();
1948 /* AND rS with a mask that is 0 when rB >= 0x20 */
1949 #if defined(TARGET_PPC64)
1950 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1951 tcg_gen_sari_tl(t0, t0, 0x3f);
1952 #else
1953 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1954 tcg_gen_sari_tl(t0, t0, 0x1f);
1955 #endif
1956 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1957 tcg_gen_ext32u_tl(t0, t0);
1958 t1 = tcg_temp_new();
1959 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1960 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1961 tcg_temp_free(t1);
1962 tcg_temp_free(t0);
1963 if (unlikely(Rc(ctx->opcode) != 0))
1964 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1965 }
1966
1967 #if defined(TARGET_PPC64)
1968 /* sld & sld. */
1969 static void gen_sld(DisasContext *ctx)
1970 {
1971 TCGv t0, t1;
1972
1973 t0 = tcg_temp_new();
1974 /* AND rS with a mask that is 0 when rB >= 0x40 */
1975 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1976 tcg_gen_sari_tl(t0, t0, 0x3f);
1977 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1978 t1 = tcg_temp_new();
1979 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1980 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1981 tcg_temp_free(t1);
1982 tcg_temp_free(t0);
1983 if (unlikely(Rc(ctx->opcode) != 0))
1984 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1985 }
1986
1987 /* srad & srad. */
1988 static void gen_srad(DisasContext *ctx)
1989 {
1990 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1991 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1992 if (unlikely(Rc(ctx->opcode) != 0))
1993 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1994 }
1995 /* sradi & sradi. */
1996 static inline void gen_sradi(DisasContext *ctx, int n)
1997 {
1998 int sh = SH(ctx->opcode) + (n << 5);
1999 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2000 TCGv src = cpu_gpr[rS(ctx->opcode)];
2001 if (sh == 0) {
2002 tcg_gen_mov_tl(dst, src);
2003 tcg_gen_movi_tl(cpu_ca, 0);
2004 } else {
2005 TCGv t0;
2006 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2007 t0 = tcg_temp_new();
2008 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2009 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2010 tcg_temp_free(t0);
2011 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2012 tcg_gen_sari_tl(dst, src, sh);
2013 }
2014 if (unlikely(Rc(ctx->opcode) != 0)) {
2015 gen_set_Rc0(ctx, dst);
2016 }
2017 }
2018
2019 static void gen_sradi0(DisasContext *ctx)
2020 {
2021 gen_sradi(ctx, 0);
2022 }
2023
2024 static void gen_sradi1(DisasContext *ctx)
2025 {
2026 gen_sradi(ctx, 1);
2027 }
2028
2029 /* srd & srd. */
2030 static void gen_srd(DisasContext *ctx)
2031 {
2032 TCGv t0, t1;
2033
2034 t0 = tcg_temp_new();
2035 /* AND rS with a mask that is 0 when rB >= 0x40 */
2036 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2037 tcg_gen_sari_tl(t0, t0, 0x3f);
2038 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2039 t1 = tcg_temp_new();
2040 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2041 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2042 tcg_temp_free(t1);
2043 tcg_temp_free(t0);
2044 if (unlikely(Rc(ctx->opcode) != 0))
2045 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2046 }
2047 #endif
2048
2049 /*** Floating-Point arithmetic ***/
2050 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2051 static void gen_f##name(DisasContext *ctx) \
2052 { \
2053 if (unlikely(!ctx->fpu_enabled)) { \
2054 gen_exception(ctx, POWERPC_EXCP_FPU); \
2055 return; \
2056 } \
2057 /* NIP cannot be restored if the memory exception comes from an helper */ \
2058 gen_update_nip(ctx, ctx->nip - 4); \
2059 gen_reset_fpstatus(); \
2060 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2061 cpu_fpr[rA(ctx->opcode)], \
2062 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2063 if (isfloat) { \
2064 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2065 cpu_fpr[rD(ctx->opcode)]); \
2066 } \
2067 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2068 Rc(ctx->opcode) != 0); \
2069 }
2070
2071 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2072 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2073 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2074
2075 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2076 static void gen_f##name(DisasContext *ctx) \
2077 { \
2078 if (unlikely(!ctx->fpu_enabled)) { \
2079 gen_exception(ctx, POWERPC_EXCP_FPU); \
2080 return; \
2081 } \
2082 /* NIP cannot be restored if the memory exception comes from an helper */ \
2083 gen_update_nip(ctx, ctx->nip - 4); \
2084 gen_reset_fpstatus(); \
2085 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2086 cpu_fpr[rA(ctx->opcode)], \
2087 cpu_fpr[rB(ctx->opcode)]); \
2088 if (isfloat) { \
2089 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2090 cpu_fpr[rD(ctx->opcode)]); \
2091 } \
2092 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2093 set_fprf, Rc(ctx->opcode) != 0); \
2094 }
2095 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2096 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2097 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2098
2099 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2100 static void gen_f##name(DisasContext *ctx) \
2101 { \
2102 if (unlikely(!ctx->fpu_enabled)) { \
2103 gen_exception(ctx, POWERPC_EXCP_FPU); \
2104 return; \
2105 } \
2106 /* NIP cannot be restored if the memory exception comes from an helper */ \
2107 gen_update_nip(ctx, ctx->nip - 4); \
2108 gen_reset_fpstatus(); \
2109 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2110 cpu_fpr[rA(ctx->opcode)], \
2111 cpu_fpr[rC(ctx->opcode)]); \
2112 if (isfloat) { \
2113 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2114 cpu_fpr[rD(ctx->opcode)]); \
2115 } \
2116 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2117 set_fprf, Rc(ctx->opcode) != 0); \
2118 }
2119 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2120 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2121 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2122
2123 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2124 static void gen_f##name(DisasContext *ctx) \
2125 { \
2126 if (unlikely(!ctx->fpu_enabled)) { \
2127 gen_exception(ctx, POWERPC_EXCP_FPU); \
2128 return; \
2129 } \
2130 /* NIP cannot be restored if the memory exception comes from an helper */ \
2131 gen_update_nip(ctx, ctx->nip - 4); \
2132 gen_reset_fpstatus(); \
2133 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2134 cpu_fpr[rB(ctx->opcode)]); \
2135 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2136 set_fprf, Rc(ctx->opcode) != 0); \
2137 }
2138
2139 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2140 static void gen_f##name(DisasContext *ctx) \
2141 { \
2142 if (unlikely(!ctx->fpu_enabled)) { \
2143 gen_exception(ctx, POWERPC_EXCP_FPU); \
2144 return; \
2145 } \
2146 /* NIP cannot be restored if the memory exception comes from an helper */ \
2147 gen_update_nip(ctx, ctx->nip - 4); \
2148 gen_reset_fpstatus(); \
2149 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2150 cpu_fpr[rB(ctx->opcode)]); \
2151 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2152 set_fprf, Rc(ctx->opcode) != 0); \
2153 }
2154
2155 /* fadd - fadds */
2156 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2157 /* fdiv - fdivs */
2158 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2159 /* fmul - fmuls */
2160 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2161
2162 /* fre */
2163 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2164
2165 /* fres */
2166 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2167
2168 /* frsqrte */
2169 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2170
2171 /* frsqrtes */
2172 static void gen_frsqrtes(DisasContext *ctx)
2173 {
2174 if (unlikely(!ctx->fpu_enabled)) {
2175 gen_exception(ctx, POWERPC_EXCP_FPU);
2176 return;
2177 }
2178 /* NIP cannot be restored if the memory exception comes from an helper */
2179 gen_update_nip(ctx, ctx->nip - 4);
2180 gen_reset_fpstatus();
2181 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2182 cpu_fpr[rB(ctx->opcode)]);
2183 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2184 cpu_fpr[rD(ctx->opcode)]);
2185 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2186 }
2187
2188 /* fsel */
2189 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2190 /* fsub - fsubs */
2191 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2192 /* Optional: */
2193
2194 /* fsqrt */
2195 static void gen_fsqrt(DisasContext *ctx)
2196 {
2197 if (unlikely(!ctx->fpu_enabled)) {
2198 gen_exception(ctx, POWERPC_EXCP_FPU);
2199 return;
2200 }
2201 /* NIP cannot be restored if the memory exception comes from an helper */
2202 gen_update_nip(ctx, ctx->nip - 4);
2203 gen_reset_fpstatus();
2204 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2205 cpu_fpr[rB(ctx->opcode)]);
2206 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2207 }
2208
2209 static void gen_fsqrts(DisasContext *ctx)
2210 {
2211 if (unlikely(!ctx->fpu_enabled)) {
2212 gen_exception(ctx, POWERPC_EXCP_FPU);
2213 return;
2214 }
2215 /* NIP cannot be restored if the memory exception comes from an helper */
2216 gen_update_nip(ctx, ctx->nip - 4);
2217 gen_reset_fpstatus();
2218 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2219 cpu_fpr[rB(ctx->opcode)]);
2220 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2221 cpu_fpr[rD(ctx->opcode)]);
2222 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2223 }
2224
2225 /*** Floating-Point multiply-and-add ***/
2226 /* fmadd - fmadds */
2227 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2228 /* fmsub - fmsubs */
2229 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2230 /* fnmadd - fnmadds */
2231 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2232 /* fnmsub - fnmsubs */
2233 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2234
2235 /*** Floating-Point round & convert ***/
2236 /* fctiw */
2237 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2238 /* fctiwu */
2239 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2240 /* fctiwz */
2241 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2242 /* fctiwuz */
2243 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2244 /* frsp */
2245 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2246 #if defined(TARGET_PPC64)
2247 /* fcfid */
2248 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2249 /* fcfids */
2250 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2251 /* fcfidu */
2252 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2253 /* fcfidus */
2254 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2255 /* fctid */
2256 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2257 /* fctidu */
2258 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2259 /* fctidz */
2260 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2261 /* fctidu */
2262 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2263 #endif
2264
2265 /* frin */
2266 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2267 /* friz */
2268 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2269 /* frip */
2270 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2271 /* frim */
2272 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2273
2274 static void gen_ftdiv(DisasContext *ctx)
2275 {
2276 if (unlikely(!ctx->fpu_enabled)) {
2277 gen_exception(ctx, POWERPC_EXCP_FPU);
2278 return;
2279 }
2280 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2281 cpu_fpr[rB(ctx->opcode)]);
2282 }
2283
2284 static void gen_ftsqrt(DisasContext *ctx)
2285 {
2286 if (unlikely(!ctx->fpu_enabled)) {
2287 gen_exception(ctx, POWERPC_EXCP_FPU);
2288 return;
2289 }
2290 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2291 }
2292
2293
2294
2295 /*** Floating-Point compare ***/
2296
2297 /* fcmpo */
2298 static void gen_fcmpo(DisasContext *ctx)
2299 {
2300 TCGv_i32 crf;
2301 if (unlikely(!ctx->fpu_enabled)) {
2302 gen_exception(ctx, POWERPC_EXCP_FPU);
2303 return;
2304 }
2305 /* NIP cannot be restored if the memory exception comes from an helper */
2306 gen_update_nip(ctx, ctx->nip - 4);
2307 gen_reset_fpstatus();
2308 crf = tcg_const_i32(crfD(ctx->opcode));
2309 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2310 cpu_fpr[rB(ctx->opcode)], crf);
2311 tcg_temp_free_i32(crf);
2312 gen_helper_float_check_status(cpu_env);
2313 }
2314
2315 /* fcmpu */
2316 static void gen_fcmpu(DisasContext *ctx)
2317 {
2318 TCGv_i32 crf;
2319 if (unlikely(!ctx->fpu_enabled)) {
2320 gen_exception(ctx, POWERPC_EXCP_FPU);
2321 return;
2322 }
2323 /* NIP cannot be restored if the memory exception comes from an helper */
2324 gen_update_nip(ctx, ctx->nip - 4);
2325 gen_reset_fpstatus();
2326 crf = tcg_const_i32(crfD(ctx->opcode));
2327 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2328 cpu_fpr[rB(ctx->opcode)], crf);
2329 tcg_temp_free_i32(crf);
2330 gen_helper_float_check_status(cpu_env);
2331 }
2332
2333 /*** Floating-point move ***/
2334 /* fabs */
2335 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2336 static void gen_fabs(DisasContext *ctx)
2337 {
2338 if (unlikely(!ctx->fpu_enabled)) {
2339 gen_exception(ctx, POWERPC_EXCP_FPU);
2340 return;
2341 }
2342 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2343 ~(1ULL << 63));
2344 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2345 }
2346
2347 /* fmr - fmr. */
2348 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2349 static void gen_fmr(DisasContext *ctx)
2350 {
2351 if (unlikely(!ctx->fpu_enabled)) {
2352 gen_exception(ctx, POWERPC_EXCP_FPU);
2353 return;
2354 }
2355 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2356 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2357 }
2358
2359 /* fnabs */
2360 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2361 static void gen_fnabs(DisasContext *ctx)
2362 {
2363 if (unlikely(!ctx->fpu_enabled)) {
2364 gen_exception(ctx, POWERPC_EXCP_FPU);
2365 return;
2366 }
2367 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2368 1ULL << 63);
2369 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2370 }
2371
2372 /* fneg */
2373 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2374 static void gen_fneg(DisasContext *ctx)
2375 {
2376 if (unlikely(!ctx->fpu_enabled)) {
2377 gen_exception(ctx, POWERPC_EXCP_FPU);
2378 return;
2379 }
2380 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2381 1ULL << 63);
2382 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2383 }
2384
2385 /* fcpsgn: PowerPC 2.05 specification */
2386 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2387 static void gen_fcpsgn(DisasContext *ctx)
2388 {
2389 if (unlikely(!ctx->fpu_enabled)) {
2390 gen_exception(ctx, POWERPC_EXCP_FPU);
2391 return;
2392 }
2393 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2394 cpu_fpr[rB(ctx->opcode)], 0, 63);
2395 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2396 }
2397
2398 static void gen_fmrgew(DisasContext *ctx)
2399 {
2400 TCGv_i64 b0;
2401 if (unlikely(!ctx->fpu_enabled)) {
2402 gen_exception(ctx, POWERPC_EXCP_FPU);
2403 return;
2404 }
2405 b0 = tcg_temp_new_i64();
2406 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2407 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2408 b0, 0, 32);
2409 tcg_temp_free_i64(b0);
2410 }
2411
2412 static void gen_fmrgow(DisasContext *ctx)
2413 {
2414 if (unlikely(!ctx->fpu_enabled)) {
2415 gen_exception(ctx, POWERPC_EXCP_FPU);
2416 return;
2417 }
2418 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2419 cpu_fpr[rB(ctx->opcode)],
2420 cpu_fpr[rA(ctx->opcode)],
2421 32, 32);
2422 }
2423
2424 /*** Floating-Point status & ctrl register ***/
2425
2426 /* mcrfs */
2427 static void gen_mcrfs(DisasContext *ctx)
2428 {
2429 TCGv tmp = tcg_temp_new();
2430 int bfa;
2431
2432 if (unlikely(!ctx->fpu_enabled)) {
2433 gen_exception(ctx, POWERPC_EXCP_FPU);
2434 return;
2435 }
2436 bfa = 4 * (7 - crfS(ctx->opcode));
2437 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2438 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2439 tcg_temp_free(tmp);
2440 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2441 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2442 }
2443
2444 /* mffs */
2445 static void gen_mffs(DisasContext *ctx)
2446 {
2447 if (unlikely(!ctx->fpu_enabled)) {
2448 gen_exception(ctx, POWERPC_EXCP_FPU);
2449 return;
2450 }
2451 gen_reset_fpstatus();
2452 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2453 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2454 }
2455
2456 /* mtfsb0 */
2457 static void gen_mtfsb0(DisasContext *ctx)
2458 {
2459 uint8_t crb;
2460
2461 if (unlikely(!ctx->fpu_enabled)) {
2462 gen_exception(ctx, POWERPC_EXCP_FPU);
2463 return;
2464 }
2465 crb = 31 - crbD(ctx->opcode);
2466 gen_reset_fpstatus();
2467 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2468 TCGv_i32 t0;
2469 /* NIP cannot be restored if the memory exception comes from an helper */
2470 gen_update_nip(ctx, ctx->nip - 4);
2471 t0 = tcg_const_i32(crb);
2472 gen_helper_fpscr_clrbit(cpu_env, t0);
2473 tcg_temp_free_i32(t0);
2474 }
2475 if (unlikely(Rc(ctx->opcode) != 0)) {
2476 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2477 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2478 }
2479 }
2480
2481 /* mtfsb1 */
2482 static void gen_mtfsb1(DisasContext *ctx)
2483 {
2484 uint8_t crb;
2485
2486 if (unlikely(!ctx->fpu_enabled)) {
2487 gen_exception(ctx, POWERPC_EXCP_FPU);
2488 return;
2489 }
2490 crb = 31 - crbD(ctx->opcode);
2491 gen_reset_fpstatus();
2492 /* XXX: we pretend we can only do IEEE floating-point computations */
2493 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2494 TCGv_i32 t0;
2495 /* NIP cannot be restored if the memory exception comes from an helper */
2496 gen_update_nip(ctx, ctx->nip - 4);
2497 t0 = tcg_const_i32(crb);
2498 gen_helper_fpscr_setbit(cpu_env, t0);
2499 tcg_temp_free_i32(t0);
2500 }
2501 if (unlikely(Rc(ctx->opcode) != 0)) {
2502 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2503 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2504 }
2505 /* We can raise a differed exception */
2506 gen_helper_float_check_status(cpu_env);
2507 }
2508
2509 /* mtfsf */
2510 static void gen_mtfsf(DisasContext *ctx)
2511 {
2512 TCGv_i32 t0;
2513 int flm, l, w;
2514
2515 if (unlikely(!ctx->fpu_enabled)) {
2516 gen_exception(ctx, POWERPC_EXCP_FPU);
2517 return;
2518 }
2519 flm = FPFLM(ctx->opcode);
2520 l = FPL(ctx->opcode);
2521 w = FPW(ctx->opcode);
2522 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2523 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2524 return;
2525 }
2526 /* NIP cannot be restored if the memory exception comes from an helper */
2527 gen_update_nip(ctx, ctx->nip - 4);
2528 gen_reset_fpstatus();
2529 if (l) {
2530 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2531 } else {
2532 t0 = tcg_const_i32(flm << (w * 8));
2533 }
2534 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2535 tcg_temp_free_i32(t0);
2536 if (unlikely(Rc(ctx->opcode) != 0)) {
2537 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2538 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2539 }
2540 /* We can raise a differed exception */
2541 gen_helper_float_check_status(cpu_env);
2542 }
2543
2544 /* mtfsfi */
2545 static void gen_mtfsfi(DisasContext *ctx)
2546 {
2547 int bf, sh, w;
2548 TCGv_i64 t0;
2549 TCGv_i32 t1;
2550
2551 if (unlikely(!ctx->fpu_enabled)) {
2552 gen_exception(ctx, POWERPC_EXCP_FPU);
2553 return;
2554 }
2555 w = FPW(ctx->opcode);
2556 bf = FPBF(ctx->opcode);
2557 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2558 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2559 return;
2560 }
2561 sh = (8 * w) + 7 - bf;
2562 /* NIP cannot be restored if the memory exception comes from an helper */
2563 gen_update_nip(ctx, ctx->nip - 4);
2564 gen_reset_fpstatus();
2565 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2566 t1 = tcg_const_i32(1 << sh);
2567 gen_helper_store_fpscr(cpu_env, t0, t1);
2568 tcg_temp_free_i64(t0);
2569 tcg_temp_free_i32(t1);
2570 if (unlikely(Rc(ctx->opcode) != 0)) {
2571 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2572 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2573 }
2574 /* We can raise a differed exception */
2575 gen_helper_float_check_status(cpu_env);
2576 }
2577
2578 /*** Addressing modes ***/
2579 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2580 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2581 target_long maskl)
2582 {
2583 target_long simm = SIMM(ctx->opcode);
2584
2585 simm &= ~maskl;
2586 if (rA(ctx->opcode) == 0) {
2587 if (NARROW_MODE(ctx)) {
2588 simm = (uint32_t)simm;
2589 }
2590 tcg_gen_movi_tl(EA, simm);
2591 } else if (likely(simm != 0)) {
2592 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2593 if (NARROW_MODE(ctx)) {
2594 tcg_gen_ext32u_tl(EA, EA);
2595 }
2596 } else {
2597 if (NARROW_MODE(ctx)) {
2598 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2599 } else {
2600 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2601 }
2602 }
2603 }
2604
2605 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2606 {
2607 if (rA(ctx->opcode) == 0) {
2608 if (NARROW_MODE(ctx)) {
2609 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2610 } else {
2611 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2612 }
2613 } else {
2614 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2615 if (NARROW_MODE(ctx)) {
2616 tcg_gen_ext32u_tl(EA, EA);
2617 }
2618 }
2619 }
2620
2621 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2622 {
2623 if (rA(ctx->opcode) == 0) {
2624 tcg_gen_movi_tl(EA, 0);
2625 } else if (NARROW_MODE(ctx)) {
2626 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2627 } else {
2628 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2629 }
2630 }
2631
2632 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2633 target_long val)
2634 {
2635 tcg_gen_addi_tl(ret, arg1, val);
2636 if (NARROW_MODE(ctx)) {
2637 tcg_gen_ext32u_tl(ret, ret);
2638 }
2639 }
2640
2641 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2642 {
2643 int l1 = gen_new_label();
2644 TCGv t0 = tcg_temp_new();
2645 TCGv_i32 t1, t2;
2646 /* NIP cannot be restored if the memory exception comes from an helper */
2647 gen_update_nip(ctx, ctx->nip - 4);
2648 tcg_gen_andi_tl(t0, EA, mask);
2649 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2650 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2651 t2 = tcg_const_i32(0);
2652 gen_helper_raise_exception_err(cpu_env, t1, t2);
2653 tcg_temp_free_i32(t1);
2654 tcg_temp_free_i32(t2);
2655 gen_set_label(l1);
2656 tcg_temp_free(t0);
2657 }
2658
2659 /*** Integer load ***/
2660 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2661 {
2662 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2663 }
2664
2665 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2666 {
2667 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2668 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2669 }
2670
2671 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2672 {
2673 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2674 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2675 }
2676
2677 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2678 {
2679 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2680 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2681 }
2682
2683 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2684 {
2685 TCGv tmp = tcg_temp_new();
2686 gen_qemu_ld32u(ctx, tmp, addr);
2687 tcg_gen_extu_tl_i64(val, tmp);
2688 tcg_temp_free(tmp);
2689 }
2690
2691 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2692 {
2693 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2694 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2695 }
2696
2697 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2698 {
2699 TCGv tmp = tcg_temp_new();
2700 gen_qemu_ld32s(ctx, tmp, addr);
2701 tcg_gen_ext_tl_i64(val, tmp);
2702 tcg_temp_free(tmp);
2703 }
2704
2705 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2706 {
2707 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2708 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2709 }
2710
2711 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2712 {
2713 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2714 }
2715
2716 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2717 {
2718 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2719 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2720 }
2721
2722 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2723 {
2724 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2725 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2726 }
2727
2728 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2729 {
2730 TCGv tmp = tcg_temp_new();
2731 tcg_gen_trunc_i64_tl(tmp, val);
2732 gen_qemu_st32(ctx, tmp, addr);
2733 tcg_temp_free(tmp);
2734 }
2735
2736 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2737 {
2738 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2739 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2740 }
2741
2742 #define GEN_LD(name, ldop, opc, type) \
2743 static void glue(gen_, name)(DisasContext *ctx) \
2744 { \
2745 TCGv EA; \
2746 gen_set_access_type(ctx, ACCESS_INT); \
2747 EA = tcg_temp_new(); \
2748 gen_addr_imm_index(ctx, EA, 0); \
2749 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2750 tcg_temp_free(EA); \
2751 }
2752
2753 #define GEN_LDU(name, ldop, opc, type) \
2754 static void glue(gen_, name##u)(DisasContext *ctx) \
2755 { \
2756 TCGv EA; \
2757 if (unlikely(rA(ctx->opcode) == 0 || \
2758 rA(ctx->opcode) == rD(ctx->opcode))) { \
2759 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2760 return; \
2761 } \
2762 gen_set_access_type(ctx, ACCESS_INT); \
2763 EA = tcg_temp_new(); \
2764 if (type == PPC_64B) \
2765 gen_addr_imm_index(ctx, EA, 0x03); \
2766 else \
2767 gen_addr_imm_index(ctx, EA, 0); \
2768 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2769 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2770 tcg_temp_free(EA); \
2771 }
2772
2773 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2774 static void glue(gen_, name##ux)(DisasContext *ctx) \
2775 { \
2776 TCGv EA; \
2777 if (unlikely(rA(ctx->opcode) == 0 || \
2778 rA(ctx->opcode) == rD(ctx->opcode))) { \
2779 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2780 return; \
2781 } \
2782 gen_set_access_type(ctx, ACCESS_INT); \
2783 EA = tcg_temp_new(); \
2784 gen_addr_reg_index(ctx, EA); \
2785 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2786 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2787 tcg_temp_free(EA); \
2788 }
2789
2790 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2791 static void glue(gen_, name##x)(DisasContext *ctx) \
2792 { \
2793 TCGv EA; \
2794 gen_set_access_type(ctx, ACCESS_INT); \
2795 EA = tcg_temp_new(); \
2796 gen_addr_reg_index(ctx, EA); \
2797 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2798 tcg_temp_free(EA); \
2799 }
2800 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2801 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2802
2803 #define GEN_LDS(name, ldop, op, type) \
2804 GEN_LD(name, ldop, op | 0x20, type); \
2805 GEN_LDU(name, ldop, op | 0x21, type); \
2806 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2807 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2808
2809 /* lbz lbzu lbzux lbzx */
2810 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2811 /* lha lhau lhaux lhax */
2812 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2813 /* lhz lhzu lhzux lhzx */
2814 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2815 /* lwz lwzu lwzux lwzx */
2816 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2817 #if defined(TARGET_PPC64)
2818 /* lwaux */
2819 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2820 /* lwax */
2821 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2822 /* ldux */
2823 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2824 /* ldx */
2825 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2826
2827 static void gen_ld(DisasContext *ctx)
2828 {
2829 TCGv EA;
2830 if (Rc(ctx->opcode)) {
2831 if (unlikely(rA(ctx->opcode) == 0 ||
2832 rA(ctx->opcode) == rD(ctx->opcode))) {
2833 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2834 return;
2835 }
2836 }
2837 gen_set_access_type(ctx, ACCESS_INT);
2838 EA = tcg_temp_new();
2839 gen_addr_imm_index(ctx, EA, 0x03);
2840 if (ctx->opcode & 0x02) {
2841 /* lwa (lwau is undefined) */
2842 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2843 } else {
2844 /* ld - ldu */
2845 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2846 }
2847 if (Rc(ctx->opcode))
2848 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2849 tcg_temp_free(EA);
2850 }
2851
2852 /* lq */
2853 static void gen_lq(DisasContext *ctx)
2854 {
2855 int ra, rd;
2856 TCGv EA;
2857
2858 /* lq is a legal user mode instruction starting in ISA 2.07 */
2859 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2860 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2861
2862 if (!legal_in_user_mode && is_user_mode(ctx)) {
2863 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2864 return;
2865 }
2866
2867 if (!le_is_supported && ctx->le_mode) {
2868 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2869 return;
2870 }
2871
2872 ra = rA(ctx->opcode);
2873 rd = rD(ctx->opcode);
2874 if (unlikely((rd & 1) || rd == ra)) {
2875 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2876 return;
2877 }
2878
2879 gen_set_access_type(ctx, ACCESS_INT);
2880 EA = tcg_temp_new();
2881 gen_addr_imm_index(ctx, EA, 0x0F);
2882
2883 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2884 64-bit byteswap already. */
2885 if (unlikely(ctx->le_mode)) {
2886 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2887 gen_addr_add(ctx, EA, EA, 8);
2888 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2889 } else {
2890 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2891 gen_addr_add(ctx, EA, EA, 8);
2892 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2893 }
2894 tcg_temp_free(EA);
2895 }
2896 #endif
2897
2898 /*** Integer store ***/
2899 #define GEN_ST(name, stop, opc, type) \
2900 static void glue(gen_, name)(DisasContext *ctx) \
2901 { \
2902 TCGv EA; \
2903 gen_set_access_type(ctx, ACCESS_INT); \
2904 EA = tcg_temp_new(); \
2905 gen_addr_imm_index(ctx, EA, 0); \
2906 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2907 tcg_temp_free(EA); \
2908 }
2909
2910 #define GEN_STU(name, stop, opc, type) \
2911 static void glue(gen_, stop##u)(DisasContext *ctx) \
2912 { \
2913 TCGv EA; \
2914 if (unlikely(rA(ctx->opcode) == 0)) { \
2915 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2916 return; \
2917 } \
2918 gen_set_access_type(ctx, ACCESS_INT); \
2919 EA = tcg_temp_new(); \
2920 if (type == PPC_64B) \
2921 gen_addr_imm_index(ctx, EA, 0x03); \
2922 else \
2923 gen_addr_imm_index(ctx, EA, 0); \
2924 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2925 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2926 tcg_temp_free(EA); \
2927 }
2928
2929 #define GEN_STUX(name, stop, opc2, opc3, type) \
2930 static void glue(gen_, name##ux)(DisasContext *ctx) \
2931 { \
2932 TCGv EA; \
2933 if (unlikely(rA(ctx->opcode) == 0)) { \
2934 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2935 return; \
2936 } \
2937 gen_set_access_type(ctx, ACCESS_INT); \
2938 EA = tcg_temp_new(); \
2939 gen_addr_reg_index(ctx, EA); \
2940 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2941 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2942 tcg_temp_free(EA); \
2943 }
2944
2945 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2946 static void glue(gen_, name##x)(DisasContext *ctx) \
2947 { \
2948 TCGv EA; \
2949 gen_set_access_type(ctx, ACCESS_INT); \
2950 EA = tcg_temp_new(); \
2951 gen_addr_reg_index(ctx, EA); \
2952 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2953 tcg_temp_free(EA); \
2954 }
2955 #define GEN_STX(name, stop, opc2, opc3, type) \
2956 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2957
2958 #define GEN_STS(name, stop, op, type) \
2959 GEN_ST(name, stop, op | 0x20, type); \
2960 GEN_STU(name, stop, op | 0x21, type); \
2961 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2962 GEN_STX(name, stop, 0x17, op | 0x00, type)
2963
2964 /* stb stbu stbux stbx */
2965 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2966 /* sth sthu sthux sthx */
2967 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2968 /* stw stwu stwux stwx */
2969 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2970 #if defined(TARGET_PPC64)
2971 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2972 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2973
2974 static void gen_std(DisasContext *ctx)
2975 {
2976 int rs;
2977 TCGv EA;
2978
2979 rs = rS(ctx->opcode);
2980 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2981
2982 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2983 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2984
2985 if (!legal_in_user_mode && is_user_mode(ctx)) {
2986 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2987 return;
2988 }
2989
2990 if (!le_is_supported && ctx->le_mode) {
2991 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2992 return;
2993 }
2994
2995 if (unlikely(rs & 1)) {
2996 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2997 return;
2998 }
2999 gen_set_access_type(ctx, ACCESS_INT);
3000 EA = tcg_temp_new();
3001 gen_addr_imm_index(ctx, EA, 0x03);
3002
3003 /* We only need to swap high and low halves. gen_qemu_st64 does
3004 necessary 64-bit byteswap already. */
3005 if (unlikely(ctx->le_mode)) {
3006 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3007 gen_addr_add(ctx, EA, EA, 8);
3008 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3009 } else {
3010 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3011 gen_addr_add(ctx, EA, EA, 8);
3012 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3013 }
3014 tcg_temp_free(EA);
3015 } else {
3016 /* std / stdu*/
3017 if (Rc(ctx->opcode)) {
3018 if (unlikely(rA(ctx->opcode) == 0)) {
3019 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3020 return;
3021 }
3022 }
3023 gen_set_access_type(ctx, ACCESS_INT);
3024 EA = tcg_temp_new();
3025 gen_addr_imm_index(ctx, EA, 0x03);
3026 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3027 if (Rc(ctx->opcode))
3028 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3029 tcg_temp_free(EA);
3030 }
3031 }
3032 #endif
3033 /*** Integer load and store with byte reverse ***/
3034
3035 /* lhbrx */
3036 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3037 {
3038 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3039 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3040 }
3041 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3042
3043 /* lwbrx */
3044 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3045 {
3046 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3047 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3048 }
3049 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3050
3051 #if defined(TARGET_PPC64)
3052 /* ldbrx */
3053 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3054 {
3055 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3056 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3057 }
3058 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3059 #endif /* TARGET_PPC64 */
3060
3061 /* sthbrx */
3062 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3063 {
3064 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3065 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3066 }
3067 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3068
3069 /* stwbrx */
3070 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3071 {
3072 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3073 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3074 }
3075 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3076
3077 #if defined(TARGET_PPC64)
3078 /* stdbrx */
3079 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3080 {
3081 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3082 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3083 }
3084 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3085 #endif /* TARGET_PPC64 */
3086
3087 /*** Integer load and store multiple ***/
3088
3089 /* lmw */
3090 static void gen_lmw(DisasContext *ctx)
3091 {
3092 TCGv t0;
3093 TCGv_i32 t1;
3094 gen_set_access_type(ctx, ACCESS_INT);
3095 /* NIP cannot be restored if the memory exception comes from an helper */
3096 gen_update_nip(ctx, ctx->nip - 4);
3097 t0 = tcg_temp_new();
3098 t1 = tcg_const_i32(rD(ctx->opcode));
3099 gen_addr_imm_index(ctx, t0, 0);
3100 gen_helper_lmw(cpu_env, t0, t1);
3101 tcg_temp_free(t0);
3102 tcg_temp_free_i32(t1);
3103 }
3104
3105 /* stmw */
3106 static void gen_stmw(DisasContext *ctx)
3107 {
3108 TCGv t0;
3109 TCGv_i32 t1;
3110 gen_set_access_type(ctx, ACCESS_INT);
3111 /* NIP cannot be restored if the memory exception comes from an helper */
3112 gen_update_nip(ctx, ctx->nip - 4);
3113 t0 = tcg_temp_new();
3114 t1 = tcg_const_i32(rS(ctx->opcode));
3115 gen_addr_imm_index(ctx, t0, 0);
3116 gen_helper_stmw(cpu_env, t0, t1);
3117 tcg_temp_free(t0);
3118 tcg_temp_free_i32(t1);
3119 }
3120
3121 /*** Integer load and store strings ***/
3122
3123 /* lswi */
3124 /* PowerPC32 specification says we must generate an exception if
3125 * rA is in the range of registers to be loaded.
3126 * In an other hand, IBM says this is valid, but rA won't be loaded.
3127 * For now, I'll follow the spec...
3128 */
3129 static void gen_lswi(DisasContext *ctx)
3130 {
3131 TCGv t0;
3132 TCGv_i32 t1, t2;
3133 int nb = NB(ctx->opcode);
3134 int start = rD(ctx->opcode);
3135 int ra = rA(ctx->opcode);
3136 int nr;
3137
3138 if (nb == 0)
3139 nb = 32;
3140 nr = nb / 4;
3141 if (unlikely(((start + nr) > 32 &&
3142 start <= ra && (start + nr - 32) > ra) ||
3143 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3144 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3145 return;
3146 }
3147 gen_set_access_type(ctx, ACCESS_INT);
3148 /* NIP cannot be restored if the memory exception comes from an helper */
3149 gen_update_nip(ctx, ctx->nip - 4);
3150 t0 = tcg_temp_new();
3151 gen_addr_register(ctx, t0);
3152 t1 = tcg_const_i32(nb);
3153 t2 = tcg_const_i32(start);
3154 gen_helper_lsw(cpu_env, t0, t1, t2);
3155 tcg_temp_free(t0);
3156 tcg_temp_free_i32(t1);
3157 tcg_temp_free_i32(t2);
3158 }
3159
3160 /* lswx */
3161 static void gen_lswx(DisasContext *ctx)
3162 {
3163 TCGv t0;
3164 TCGv_i32 t1, t2, t3;
3165 gen_set_access_type(ctx, ACCESS_INT);
3166 /* NIP cannot be restored if the memory exception comes from an helper */
3167 gen_update_nip(ctx, ctx->nip - 4);
3168 t0 = tcg_temp_new();
3169 gen_addr_reg_index(ctx, t0);
3170 t1 = tcg_const_i32(rD(ctx->opcode));
3171 t2 = tcg_const_i32(rA(ctx->opcode));
3172 t3 = tcg_const_i32(rB(ctx->opcode));
3173 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3174 tcg_temp_free(t0);
3175 tcg_temp_free_i32(t1);
3176 tcg_temp_free_i32(t2);
3177 tcg_temp_free_i32(t3);
3178 }
3179
3180 /* stswi */
3181 static void gen_stswi(DisasContext *ctx)
3182 {
3183 TCGv t0;
3184 TCGv_i32 t1, t2;
3185 int nb = NB(ctx->opcode);
3186 gen_set_access_type(ctx, ACCESS_INT);
3187 /* NIP cannot be restored if the memory exception comes from an helper */
3188 gen_update_nip(ctx, ctx->nip - 4);
3189 t0 = tcg_temp_new();
3190 gen_addr_register(ctx, t0);
3191 if (nb == 0)
3192 nb = 32;
3193 t1 = tcg_const_i32(nb);
3194 t2 = tcg_const_i32(rS(ctx->opcode));
3195 gen_helper_stsw(cpu_env, t0, t1, t2);
3196 tcg_temp_free(t0);
3197 tcg_temp_free_i32(t1);
3198 tcg_temp_free_i32(t2);
3199 }
3200
3201 /* stswx */
3202 static void gen_stswx(DisasContext *ctx)
3203 {
3204 TCGv t0;
3205 TCGv_i32 t1, t2;
3206 gen_set_access_type(ctx, ACCESS_INT);
3207 /* NIP cannot be restored if the memory exception comes from an helper */
3208 gen_update_nip(ctx, ctx->nip - 4);
3209 t0 = tcg_temp_new();
3210 gen_addr_reg_index(ctx, t0);
3211 t1 = tcg_temp_new_i32();
3212 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3213 tcg_gen_andi_i32(t1, t1, 0x7F);
3214 t2 = tcg_const_i32(rS(ctx->opcode));
3215 gen_helper_stsw(cpu_env, t0, t1, t2);
3216 tcg_temp_free(t0);
3217 tcg_temp_free_i32(t1);
3218 tcg_temp_free_i32(t2);
3219 }
3220
3221 /*** Memory synchronisation ***/
3222 /* eieio */
3223 static void gen_eieio(DisasContext *ctx)
3224 {
3225 }
3226
3227 /* isync */
3228 static void gen_isync(DisasContext *ctx)
3229 {
3230 gen_stop_exception(ctx);
3231 }
3232
3233 #define LARX(name, len, loadop) \
3234 static void gen_##name(DisasContext *ctx) \
3235 { \
3236 TCGv t0; \
3237 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3238 gen_set_access_type(ctx, ACCESS_RES); \
3239 t0 = tcg_temp_local_new(); \
3240 gen_addr_reg_index(ctx, t0); \
3241 if ((len) > 1) { \
3242 gen_check_align(ctx, t0, (len)-1); \
3243 } \
3244 gen_qemu_##loadop(ctx, gpr, t0); \
3245 tcg_gen_mov_tl(cpu_reserve, t0); \
3246 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3247 tcg_temp_free(t0); \
3248 }
3249
3250 /* lwarx */
3251 LARX(lbarx, 1, ld8u);
3252 LARX(lharx, 2, ld16u);
3253 LARX(lwarx, 4, ld32u);
3254
3255
3256 #if defined(CONFIG_USER_ONLY)
3257 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3258 int reg, int size)
3259 {
3260 TCGv t0 = tcg_temp_new();
3261 uint32_t save_exception = ctx->exception;
3262
3263 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3264 tcg_gen_movi_tl(t0, (size << 5) | reg);
3265 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3266 tcg_temp_free(t0);
3267 gen_update_nip(ctx, ctx->nip-4);
3268 ctx->exception = POWERPC_EXCP_BRANCH;
3269 gen_exception(ctx, POWERPC_EXCP_STCX);
3270 ctx->exception = save_exception;
3271 }
3272 #else
3273 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3274 int reg, int size)
3275 {
3276 int l1;
3277
3278 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3279 l1 = gen_new_label();
3280 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3281 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3282 #if defined(TARGET_PPC64)
3283 if (size == 8) {
3284 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3285 } else
3286 #endif
3287 if (size == 4) {
3288 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3289 } else if (size == 2) {
3290 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3291 #if defined(TARGET_PPC64)
3292 } else if (size == 16) {
3293 TCGv gpr1, gpr2 , EA8;
3294 if (unlikely(ctx->le_mode)) {
3295 gpr1 = cpu_gpr[reg+1];
3296 gpr2 = cpu_gpr[reg];
3297 } else {
3298 gpr1 = cpu_gpr[reg];
3299 gpr2 = cpu_gpr[reg+1];
3300 }
3301 gen_qemu_st64(ctx, gpr1, EA);
3302 EA8 = tcg_temp_local_new();
3303 gen_addr_add(ctx, EA8, EA, 8);
3304 gen_qemu_st64(ctx, gpr2, EA8);
3305 tcg_temp_free(EA8);
3306 #endif
3307 } else {
3308 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3309 }
3310 gen_set_label(l1);
3311 tcg_gen_movi_tl(cpu_reserve, -1);
3312 }
3313 #endif
3314
3315 #define STCX(name, len) \
3316 static void gen_##name(DisasContext *ctx) \
3317 { \
3318 TCGv t0; \
3319 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3320 gen_inval_exception(ctx, \
3321 POWERPC_EXCP_INVAL_INVAL); \
3322 return; \
3323 } \
3324 gen_set_access_type(ctx, ACCESS_RES); \
3325 t0 = tcg_temp_local_new(); \
3326 gen_addr_reg_index(ctx, t0); \
3327 if (len > 1) { \
3328 gen_check_align(ctx, t0, (len)-1); \
3329 } \
3330 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3331 tcg_temp_free(t0); \
3332 }
3333
3334 STCX(stbcx_, 1);
3335 STCX(sthcx_, 2);
3336 STCX(stwcx_, 4);
3337
3338 #if defined(TARGET_PPC64)
3339 /* ldarx */
3340 LARX(ldarx, 8, ld64);
3341
3342 /* lqarx */
3343 static void gen_lqarx(DisasContext *ctx)
3344 {
3345 TCGv EA;
3346 int rd = rD(ctx->opcode);
3347 TCGv gpr1, gpr2;
3348
3349 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3350 (rd == rB(ctx->opcode)))) {
3351 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3352 return;
3353 }
3354
3355 gen_set_access_type(ctx, ACCESS_RES);
3356 EA = tcg_temp_local_new();
3357 gen_addr_reg_index(ctx, EA);
3358 gen_check_align(ctx, EA, 15);
3359 if (unlikely(ctx->le_mode)) {
3360 gpr1 = cpu_gpr[rd+1];
3361 gpr2 = cpu_gpr[rd];
3362 } else {
3363 gpr1 = cpu_gpr[rd];
3364 gpr2 = cpu_gpr[rd+1];
3365 }
3366 gen_qemu_ld64(ctx, gpr1, EA);
3367 tcg_gen_mov_tl(cpu_reserve, EA);
3368
3369 gen_addr_add(ctx, EA, EA, 8);
3370 gen_qemu_ld64(ctx, gpr2, EA);
3371
3372 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3373 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3374
3375 tcg_temp_free(EA);
3376 }
3377
3378 /* stdcx. */
3379 STCX(stdcx_, 8);
3380 STCX(stqcx_, 16);
3381 #endif /* defined(TARGET_PPC64) */
3382
3383 /* sync */
3384 static void gen_sync(DisasContext *ctx)
3385 {
3386 }
3387
3388 /* wait */
3389 static void gen_wait(DisasContext *ctx)
3390 {
3391 TCGv_i32 t0 = tcg_temp_new_i32();
3392 tcg_gen_st_i32(t0, cpu_env,
3393 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3394 tcg_temp_free_i32(t0);
3395 /* Stop translation, as the CPU is supposed to sleep from now */
3396 gen_exception_err(ctx, EXCP_HLT, 1);
3397 }
3398
3399 /*** Floating-point load ***/
3400 #define GEN_LDF(name, ldop, opc, type) \
3401 static void glue(gen_, name)(DisasContext *ctx) \
3402 { \
3403 TCGv EA; \
3404 if (unlikely(!ctx->fpu_enabled)) { \
3405 gen_exception(ctx, POWERPC_EXCP_FPU); \
3406 return; \
3407 } \
3408 gen_set_access_type(ctx, ACCESS_FLOAT); \
3409 EA = tcg_temp_new(); \
3410 gen_addr_imm_index(ctx, EA, 0); \
3411 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3412 tcg_temp_free(EA); \
3413 }
3414
3415 #define GEN_LDUF(name, ldop, opc, type) \
3416 static void glue(gen_, name##u)(DisasContext *ctx) \
3417 { \
3418 TCGv EA; \
3419 if (unlikely(!ctx->fpu_enabled)) { \
3420 gen_exception(ctx, POWERPC_EXCP_FPU); \
3421 return; \
3422 } \
3423 if (unlikely(rA(ctx->opcode) == 0)) { \
3424 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3425 return; \
3426 } \
3427 gen_set_access_type(ctx, ACCESS_FLOAT); \
3428 EA = tcg_temp_new(); \
3429 gen_addr_imm_index(ctx, EA, 0); \
3430 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3431 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3432 tcg_temp_free(EA); \
3433 }
3434
3435 #define GEN_LDUXF(name, ldop, opc, type) \
3436 static void glue(gen_, name##ux)(DisasContext *ctx) \
3437 { \
3438 TCGv EA; \
3439 if (unlikely(!ctx->fpu_enabled)) { \
3440 gen_exception(ctx, POWERPC_EXCP_FPU); \
3441 return; \
3442 } \
3443 if (unlikely(rA(ctx->opcode) == 0)) { \
3444 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3445 return; \
3446 } \
3447 gen_set_access_type(ctx, ACCESS_FLOAT); \
3448 EA = tcg_temp_new(); \
3449 gen_addr_reg_index(ctx, EA); \
3450 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3451 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3452 tcg_temp_free(EA); \
3453 }
3454
3455 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3456 static void glue(gen_, name##x)(DisasContext *ctx) \
3457 { \
3458 TCGv EA; \
3459 if (unlikely(!ctx->fpu_enabled)) { \
3460 gen_exception(ctx, POWERPC_EXCP_FPU); \
3461 return; \
3462 } \
3463 gen_set_access_type(ctx, ACCESS_FLOAT); \
3464 EA = tcg_temp_new(); \
3465 gen_addr_reg_index(ctx, EA); \
3466 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3467 tcg_temp_free(EA); \
3468 }
3469
3470 #define GEN_LDFS(name, ldop, op, type) \
3471 GEN_LDF(name, ldop, op | 0x20, type); \
3472 GEN_LDUF(name, ldop, op | 0x21, type); \
3473 GEN_LDUXF(name, ldop, op | 0x01, type); \
3474 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3475
3476 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3477 {
3478 TCGv t0 = tcg_temp_new();
3479 TCGv_i32 t1 = tcg_temp_new_i32();
3480 gen_qemu_ld32u(ctx, t0, arg2);
3481 tcg_gen_trunc_tl_i32(t1, t0);
3482 tcg_temp_free(t0);
3483 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3484 tcg_temp_free_i32(t1);
3485 }
3486
3487 /* lfd lfdu lfdux lfdx */
3488 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3489 /* lfs lfsu lfsux lfsx */
3490 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3491
3492 /* lfdp */
3493 static void gen_lfdp(DisasContext *ctx)
3494 {
3495 TCGv EA;
3496 if (unlikely(!ctx->fpu_enabled)) {
3497 gen_exception(ctx, POWERPC_EXCP_FPU);
3498 return;
3499 }
3500 gen_set_access_type(ctx, ACCESS_FLOAT);
3501 EA = tcg_temp_new();
3502 gen_addr_imm_index(ctx, EA, 0);
3503 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3504 64-bit byteswap already. */
3505 if (unlikely(ctx->le_mode)) {
3506 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3507 tcg_gen_addi_tl(EA, EA, 8);
3508 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3509 } else {
3510 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3511 tcg_gen_addi_tl(EA, EA, 8);
3512 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3513 }
3514 tcg_temp_free(EA);
3515 }
3516
3517 /* lfdpx */
3518 static void gen_lfdpx(DisasContext *ctx)
3519 {
3520 TCGv EA;
3521 if (unlikely(!ctx->fpu_enabled)) {
3522 gen_exception(ctx, POWERPC_EXCP_FPU);
3523 return;
3524 }
3525 gen_set_access_type(ctx, ACCESS_FLOAT);
3526 EA = tcg_temp_new();
3527 gen_addr_reg_index(ctx, EA);
3528 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3529 64-bit byteswap already. */
3530 if (unlikely(ctx->le_mode)) {
3531 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3532 tcg_gen_addi_tl(EA, EA, 8);
3533 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3534 } else {
3535 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3536 tcg_gen_addi_tl(EA, EA, 8);
3537 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3538 }
3539 tcg_temp_free(EA);
3540 }
3541
3542 /* lfiwax */
3543 static void gen_lfiwax(DisasContext *ctx)
3544 {
3545 TCGv EA;
3546 TCGv t0;
3547 if (unlikely(!ctx->fpu_enabled)) {
3548 gen_exception(ctx, POWERPC_EXCP_FPU);
3549 return;
3550 }
3551 gen_set_access_type(ctx, ACCESS_FLOAT);
3552 EA = tcg_temp_new();
3553 t0 = tcg_temp_new();
3554 gen_addr_reg_index(ctx, EA);
3555 gen_qemu_ld32s(ctx, t0, EA);
3556 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3557 tcg_temp_free(EA);
3558 tcg_temp_free(t0);
3559 }
3560
3561 /* lfiwzx */
3562 static void gen_lfiwzx(DisasContext *ctx)
3563 {
3564 TCGv EA;
3565 if (unlikely(!ctx->fpu_enabled)) {
3566 gen_exception(ctx, POWERPC_EXCP_FPU);
3567 return;
3568 }
3569 gen_set_access_type(ctx, ACCESS_FLOAT);
3570 EA = tcg_temp_new();
3571 gen_addr_reg_index(ctx, EA);
3572 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3573 tcg_temp_free(EA);
3574 }
3575 /*** Floating-point store ***/
3576 #define GEN_STF(name, stop, opc, type) \
3577 static void glue(gen_, name)(DisasContext *ctx) \
3578 { \
3579 TCGv EA; \
3580 if (unlikely(!ctx->fpu_enabled)) { \
3581 gen_exception(ctx, POWERPC_EXCP_FPU); \
3582 return; \
3583 } \
3584 gen_set_access_type(ctx, ACCESS_FLOAT); \
3585 EA = tcg_temp_new(); \
3586 gen_addr_imm_index(ctx, EA, 0); \
3587 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3588 tcg_temp_free(EA); \
3589 }
3590
3591 #define GEN_STUF(name, stop, opc, type) \
3592 static void glue(gen_, name##u)(DisasContext *ctx) \
3593 { \
3594 TCGv EA; \
3595 if (unlikely(!ctx->fpu_enabled)) { \
3596 gen_exception(ctx, POWERPC_EXCP_FPU); \
3597 return; \
3598 } \
3599 if (unlikely(rA(ctx->opcode) == 0)) { \
3600 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3601 return; \
3602 } \
3603 gen_set_access_type(ctx, ACCESS_FLOAT); \
3604 EA = tcg_temp_new(); \
3605 gen_addr_imm_index(ctx, EA, 0); \
3606 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3607 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3608 tcg_temp_free(EA); \
3609 }
3610
3611 #define GEN_STUXF(name, stop, opc, type) \
3612 static void glue(gen_, name##ux)(DisasContext *ctx) \
3613 { \
3614 TCGv EA; \
3615 if (unlikely(!ctx->fpu_enabled)) { \
3616 gen_exception(ctx, POWERPC_EXCP_FPU); \
3617 return; \
3618 } \
3619 if (unlikely(rA(ctx->opcode) == 0)) { \
3620 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3621 return; \
3622 } \
3623 gen_set_access_type(ctx, ACCESS_FLOAT); \
3624 EA = tcg_temp_new(); \
3625 gen_addr_reg_index(ctx, EA); \
3626 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3627 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3628 tcg_temp_free(EA); \
3629 }
3630
3631 #define GEN_STXF(name, stop, opc2, opc3, type) \
3632 static void glue(gen_, name##x)(DisasContext *ctx) \
3633 { \
3634 TCGv EA; \
3635 if (unlikely(!ctx->fpu_enabled)) { \
3636 gen_exception(ctx, POWERPC_EXCP_FPU); \
3637 return; \
3638 } \
3639 gen_set_access_type(ctx, ACCESS_FLOAT); \
3640 EA = tcg_temp_new(); \
3641 gen_addr_reg_index(ctx, EA); \
3642 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3643 tcg_temp_free(EA); \
3644 }
3645
3646 #define GEN_STFS(name, stop, op, type) \
3647 GEN_STF(name, stop, op | 0x20, type); \
3648 GEN_STUF(name, stop, op | 0x21, type); \
3649 GEN_STUXF(name, stop, op | 0x01, type); \
3650 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3651
3652 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3653 {
3654 TCGv_i32 t0 = tcg_temp_new_i32();
3655 TCGv t1 = tcg_temp_new();
3656 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3657 tcg_gen_extu_i32_tl(t1, t0);
3658 tcg_temp_free_i32(t0);
3659 gen_qemu_st32(ctx, t1, arg2);
3660 tcg_temp_free(t1);
3661 }
3662
3663 /* stfd stfdu stfdux stfdx */
3664 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3665 /* stfs stfsu stfsux stfsx */
3666 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3667
3668 /* stfdp */
3669 static void gen_stfdp(DisasContext *ctx)
3670 {
3671 TCGv EA;
3672 if (unlikely(!ctx->fpu_enabled)) {
3673 gen_exception(ctx, POWERPC_EXCP_FPU);
3674 return;
3675 }
3676 gen_set_access_type(ctx, ACCESS_FLOAT);
3677 EA = tcg_temp_new();
3678 gen_addr_imm_index(ctx, EA, 0);
3679 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3680 64-bit byteswap already. */
3681 if (unlikely(ctx->le_mode)) {
3682 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3683 tcg_gen_addi_tl(EA, EA, 8);
3684 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3685 } else {
3686 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3687 tcg_gen_addi_tl(EA, EA, 8);
3688 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3689 }
3690 tcg_temp_free(EA);
3691 }
3692
3693 /* stfdpx */
3694 static void gen_stfdpx(DisasContext *ctx)
3695 {
3696 TCGv EA;
3697 if (unlikely(!ctx->fpu_enabled)) {
3698 gen_exception(ctx, POWERPC_EXCP_FPU);
3699 return;
3700 }
3701 gen_set_access_type(ctx, ACCESS_FLOAT);
3702 EA = tcg_temp_new();
3703 gen_addr_reg_index(ctx, EA);
3704 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3705 64-bit byteswap already. */
3706 if (unlikely(ctx->le_mode)) {
3707 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3708 tcg_gen_addi_tl(EA, EA, 8);
3709 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3710 } else {
3711 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3712 tcg_gen_addi_tl(EA, EA, 8);
3713 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3714 }
3715 tcg_temp_free(EA);
3716 }
3717
3718 /* Optional: */
3719 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3720 {
3721 TCGv t0 = tcg_temp_new();
3722 tcg_gen_trunc_i64_tl(t0, arg1),
3723 gen_qemu_st32(ctx, t0, arg2);
3724 tcg_temp_free(t0);
3725 }
3726 /* stfiwx */
3727 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3728
3729 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3730 {
3731 #if defined(TARGET_PPC64)
3732 if (ctx->has_cfar)
3733 tcg_gen_movi_tl(cpu_cfar, nip);
3734 #endif
3735 }
3736
3737 /*** Branch ***/
3738 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3739 {
3740 TranslationBlock *tb;
3741 tb = ctx->tb;
3742 if (NARROW_MODE(ctx)) {
3743 dest = (uint32_t) dest;
3744 }
3745 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3746 likely(!ctx->singlestep_enabled)) {
3747 tcg_gen_goto_tb(n);
3748 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3749 tcg_gen_exit_tb((uintptr_t)tb + n);
3750 } else {
3751 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3752 if (unlikely(ctx->singlestep_enabled)) {
3753 if ((ctx->singlestep_enabled &
3754 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3755 (ctx->exception == POWERPC_EXCP_BRANCH ||
3756 ctx->exception == POWERPC_EXCP_TRACE)) {
3757 target_ulong tmp = ctx->nip;
3758 ctx->nip = dest;
3759 gen_exception(ctx, POWERPC_EXCP_TRACE);
3760 ctx->nip = tmp;
3761 }
3762 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3763 gen_debug_exception(ctx);
3764 }
3765 }
3766 tcg_gen_exit_tb(0);
3767 }
3768 }
3769
3770 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3771 {
3772 if (NARROW_MODE(ctx)) {
3773 nip = (uint32_t)nip;
3774 }
3775 tcg_gen_movi_tl(cpu_lr, nip);
3776 }
3777
3778 /* b ba bl bla */
3779 static void gen_b(DisasContext *ctx)
3780 {
3781 target_ulong li, target;
3782
3783 ctx->exception = POWERPC_EXCP_BRANCH;
3784 /* sign extend LI */
3785 li = LI(ctx->opcode);
3786 li = (li ^ 0x02000000) - 0x02000000;
3787 if (likely(AA(ctx->opcode) == 0)) {
3788 target = ctx->nip + li - 4;
3789 } else {
3790 target = li;
3791 }
3792 if (LK(ctx->opcode)) {
3793 gen_setlr(ctx, ctx->nip);
3794 }
3795 gen_update_cfar(ctx, ctx->nip);
3796 gen_goto_tb(ctx, 0, target);
3797 }
3798
3799 #define BCOND_IM 0
3800 #define BCOND_LR 1
3801 #define BCOND_CTR 2
3802 #define BCOND_TAR 3
3803
3804 static inline void gen_bcond(DisasContext *ctx, int type)
3805 {
3806 uint32_t bo = BO(ctx->opcode);
3807 int l1;
3808 TCGv target;
3809
3810 ctx->exception = POWERPC_EXCP_BRANCH;
3811 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3812 target = tcg_temp_local_new();
3813 if (type == BCOND_CTR)
3814 tcg_gen_mov_tl(target, cpu_ctr);
3815 else if (type == BCOND_TAR)
3816 gen_load_spr(target, SPR_TAR);
3817 else
3818 tcg_gen_mov_tl(target, cpu_lr);
3819 } else {
3820 TCGV_UNUSED(target);
3821 }
3822 if (LK(ctx->opcode))
3823 gen_setlr(ctx, ctx->nip);
3824 l1 = gen_new_label();
3825 if ((bo & 0x4) == 0) {
3826 /* Decrement and test CTR */
3827 TCGv temp = tcg_temp_new();
3828 if (unlikely(type == BCOND_CTR)) {
3829 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3830 return;
3831 }
3832 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3833 if (NARROW_MODE(ctx)) {
3834 tcg_gen_ext32u_tl(temp, cpu_ctr);
3835 } else {
3836 tcg_gen_mov_tl(temp, cpu_ctr);
3837 }
3838 if (bo & 0x2) {
3839 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3840 } else {
3841 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3842 }
3843 tcg_temp_free(temp);
3844 }
3845 if ((bo & 0x10) == 0) {
3846 /* Test CR */
3847 uint32_t bi = BI(ctx->opcode);
3848 uint32_t mask = 1 << (3 - (bi & 0x03));
3849 TCGv_i32 temp = tcg_temp_new_i32();
3850
3851 if (bo & 0x8) {
3852 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3853 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3854 } else {
3855 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3856 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3857 }
3858 tcg_temp_free_i32(temp);
3859 }
3860 gen_update_cfar(ctx, ctx->nip);
3861 if (type == BCOND_IM) {
3862 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3863 if (likely(AA(ctx->opcode) == 0)) {
3864 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3865 } else {
3866 gen_goto_tb(ctx, 0, li);
3867 }
3868 gen_set_label(l1);
3869 gen_goto_tb(ctx, 1, ctx->nip);
3870 } else {
3871 if (NARROW_MODE(ctx)) {
3872 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3873 } else {
3874 tcg_gen_andi_tl(cpu_nip, target, ~3);
3875 }
3876 tcg_gen_exit_tb(0);
3877 gen_set_label(l1);
3878 gen_update_nip(ctx, ctx->nip);
3879 tcg_gen_exit_tb(0);
3880 }
3881 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3882 tcg_temp_free(target);
3883 }
3884 }
3885
3886 static void gen_bc(DisasContext *ctx)
3887 {
3888 gen_bcond(ctx, BCOND_IM);
3889 }
3890
3891 static void gen_bcctr(DisasContext *ctx)
3892 {
3893 gen_bcond(ctx, BCOND_CTR);
3894 }
3895
3896 static void gen_bclr(DisasContext *ctx)
3897 {
3898 gen_bcond(ctx, BCOND_LR);
3899 }
3900
3901 static void gen_bctar(DisasContext *ctx)
3902 {
3903 gen_bcond(ctx, BCOND_TAR);
3904 }
3905
3906 /*** Condition register logical ***/
3907 #define GEN_CRLOGIC(name, tcg_op, opc) \
3908 static void glue(gen_, name)(DisasContext *ctx) \
3909 { \
3910 uint8_t bitmask; \
3911 int sh; \
3912 TCGv_i32 t0, t1; \
3913 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3914 t0 = tcg_temp_new_i32(); \
3915 if (sh > 0) \
3916 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3917 else if (sh < 0) \
3918 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3919 else \
3920 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3921 t1 = tcg_temp_new_i32(); \
3922 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3923 if (sh > 0) \
3924 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3925 else if (sh < 0) \
3926 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3927 else \
3928 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3929 tcg_op(t0, t0, t1); \
3930 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3931 tcg_gen_andi_i32(t0, t0, bitmask); \
3932 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3933 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3934 tcg_temp_free_i32(t0); \
3935 tcg_temp_free_i32(t1); \
3936 }
3937
3938 /* crand */
3939 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3940 /* crandc */
3941 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3942 /* creqv */
3943 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3944 /* crnand */
3945 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3946 /* crnor */
3947 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3948 /* cror */
3949 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3950 /* crorc */
3951 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3952 /* crxor */
3953 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3954
3955 /* mcrf */
3956 static void gen_mcrf(DisasContext *ctx)
3957 {
3958 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3959 }
3960
3961 /*** System linkage ***/
3962
3963 /* rfi (mem_idx only) */
3964 static void gen_rfi(DisasContext *ctx)
3965 {
3966 #if defined(CONFIG_USER_ONLY)
3967 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3968 #else
3969 /* Restore CPU state */
3970 if (unlikely(!ctx->mem_idx)) {
3971 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3972 return;
3973 }
3974 gen_update_cfar(ctx, ctx->nip);
3975 gen_helper_rfi(cpu_env);
3976 gen_sync_exception(ctx);
3977 #endif
3978 }
3979
3980 #if defined(TARGET_PPC64)
3981 static void gen_rfid(DisasContext *ctx)
3982 {
3983 #if defined(CONFIG_USER_ONLY)
3984 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3985 #else
3986 /* Restore CPU state */
3987 if (unlikely(!ctx->mem_idx)) {
3988 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3989 return;
3990 }
3991 gen_update_cfar(ctx, ctx->nip);
3992 gen_helper_rfid(cpu_env);
3993 gen_sync_exception(ctx);
3994 #endif
3995 }
3996
3997 static void gen_hrfid(DisasContext *ctx)
3998 {
3999 #if defined(CONFIG_USER_ONLY)
4000 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4001 #else
4002 /* Restore CPU state */
4003 if (unlikely(ctx->mem_idx <= 1)) {
4004 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4005 return;
4006 }
4007 gen_helper_hrfid(cpu_env);
4008 gen_sync_exception(ctx);
4009 #endif
4010 }
4011 #endif
4012
4013 /* sc */
4014 #if defined(CONFIG_USER_ONLY)
4015 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4016 #else
4017 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4018 #endif
4019 static void gen_sc(DisasContext *ctx)
4020 {
4021 uint32_t lev;
4022
4023 lev = (ctx->opcode >> 5) & 0x7F;
4024 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4025 }
4026
4027 /*** Trap ***/
4028
4029 /* tw */
4030 static void gen_tw(DisasContext *ctx)
4031 {
4032 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4033 /* Update the nip since this might generate a trap exception */
4034 gen_update_nip(ctx, ctx->nip);
4035 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4036 t0);
4037 tcg_temp_free_i32(t0);
4038 }
4039
4040 /* twi */
4041 static void gen_twi(DisasContext *ctx)
4042 {
4043 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4044 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4045 /* Update the nip since this might generate a trap exception */
4046 gen_update_nip(ctx, ctx->nip);
4047 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4048 tcg_temp_free(t0);
4049 tcg_temp_free_i32(t1);
4050 }
4051
4052 #if defined(TARGET_PPC64)
4053 /* td */
4054 static void gen_td(DisasContext *ctx)
4055 {
4056 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4057 /* Update the nip since this might generate a trap exception */
4058 gen_update_nip(ctx, ctx->nip);
4059 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4060 t0);
4061 tcg_temp_free_i32(t0);
4062 }
4063
4064 /* tdi */
4065 static void gen_tdi(DisasContext *ctx)
4066 {
4067 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4068 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4069 /* Update the nip since this might generate a trap exception */
4070 gen_update_nip(ctx, ctx->nip);
4071 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4072 tcg_temp_free(t0);
4073 tcg_temp_free_i32(t1);
4074 }
4075 #endif
4076
4077 /*** Processor control ***/
4078
4079 static void gen_read_xer(TCGv dst)
4080 {
4081 TCGv t0 = tcg_temp_new();
4082 TCGv t1 = tcg_temp_new();
4083 TCGv t2 = tcg_temp_new();
4084 tcg_gen_mov_tl(dst, cpu_xer);
4085 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4086 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4087 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4088 tcg_gen_or_tl(t0, t0, t1);
4089 tcg_gen_or_tl(dst, dst, t2);
4090 tcg_gen_or_tl(dst, dst, t0);
4091 tcg_temp_free(t0);
4092 tcg_temp_free(t1);
4093 tcg_temp_free(t2);
4094 }
4095
4096 static void gen_write_xer(TCGv src)
4097 {
4098 tcg_gen_andi_tl(cpu_xer, src,
4099 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4100 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4101 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4102 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4103 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4104 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4105 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4106 }
4107
4108 /* mcrxr */
4109 static void gen_mcrxr(DisasContext *ctx)
4110 {
4111 TCGv_i32 t0 = tcg_temp_new_i32();
4112 TCGv_i32 t1 = tcg_temp_new_i32();
4113 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4114
4115 tcg_gen_trunc_tl_i32(t0, cpu_so);
4116 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4117 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4118 tcg_gen_shli_i32(t0, t0, 3);
4119 tcg_gen_shli_i32(t1, t1, 2);
4120 tcg_gen_shli_i32(dst, dst, 1);
4121 tcg_gen_or_i32(dst, dst, t0);
4122 tcg_gen_or_i32(dst, dst, t1);
4123 tcg_temp_free_i32(t0);
4124 tcg_temp_free_i32(t1);
4125
4126 tcg_gen_movi_tl(cpu_so, 0);
4127 tcg_gen_movi_tl(cpu_ov, 0);
4128 tcg_gen_movi_tl(cpu_ca, 0);
4129 }
4130
4131 /* mfcr mfocrf */
4132 static void gen_mfcr(DisasContext *ctx)
4133 {
4134 uint32_t crm, crn;
4135
4136 if (likely(ctx->opcode & 0x00100000)) {
4137 crm = CRM(ctx->opcode);
4138 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4139 crn = ctz32 (crm);
4140 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4141 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4142 cpu_gpr[rD(ctx->opcode)], crn * 4);
4143 }
4144 } else {
4145 TCGv_i32 t0 = tcg_temp_new_i32();
4146 tcg_gen_mov_i32(t0, cpu_crf[0]);
4147 tcg_gen_shli_i32(t0, t0, 4);
4148 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4149 tcg_gen_shli_i32(t0, t0, 4);
4150 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4151 tcg_gen_shli_i32(t0, t0, 4);
4152 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4153 tcg_gen_shli_i32(t0, t0, 4);
4154 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4155 tcg_gen_shli_i32(t0, t0, 4);
4156 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4157 tcg_gen_shli_i32(t0, t0, 4);
4158 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4159 tcg_gen_shli_i32(t0, t0, 4);
4160 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4161 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4162 tcg_temp_free_i32(t0);
4163 }
4164 }
4165
4166 /* mfmsr */
4167 static void gen_mfmsr(DisasContext *ctx)
4168 {
4169 #if defined(CONFIG_USER_ONLY)
4170 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4171 #else
4172 if (unlikely(!ctx->mem_idx)) {
4173 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4174 return;
4175 }
4176 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4177 #endif
4178 }
4179
4180 static void spr_noaccess(void *opaque, int gprn, int sprn)
4181 {
4182 #if 0
4183 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4184 printf("ERROR: try to access SPR %d !\n", sprn);
4185 #endif
4186 }
4187 #define SPR_NOACCESS (&spr_noaccess)
4188
4189 /* mfspr */
4190 static inline void gen_op_mfspr(DisasContext *ctx)
4191 {
4192 void (*read_cb)(void *opaque, int gprn, int sprn);
4193 uint32_t sprn = SPR(ctx->opcode);
4194
4195 #if !defined(CONFIG_USER_ONLY)
4196 if (ctx->mem_idx == 2)
4197 read_cb = ctx->spr_cb[sprn].hea_read;
4198 else if (ctx->mem_idx)
4199 read_cb = ctx->spr_cb[sprn].oea_read;
4200 else
4201 #endif
4202 read_cb = ctx->spr_cb[sprn].uea_read;
4203 if (likely(read_cb != NULL)) {
4204 if (likely(read_cb != SPR_NOACCESS)) {
4205 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4206 } else {
4207 /* Privilege exception */
4208 /* This is a hack to avoid warnings when running Linux:
4209 * this OS breaks the PowerPC virtualisation model,
4210 * allowing userland application to read the PVR
4211 */
4212 if (sprn != SPR_PVR) {
4213 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4214 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4215 printf("Trying to read privileged spr %d (0x%03x) at "
4216 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4217 }
4218 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4219 }
4220 } else {
4221 /* Not defined */
4222 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4223 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4224 printf("Trying to read invalid spr %d (0x%03x) at "
4225 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4226 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4227 }
4228 }
4229
4230 static void gen_mfspr(DisasContext *ctx)
4231 {
4232 gen_op_mfspr(ctx);
4233 }
4234
4235 /* mftb */
4236 static void gen_mftb(DisasContext *ctx)
4237 {
4238 gen_op_mfspr(ctx);
4239 }
4240
4241 /* mtcrf mtocrf*/
4242 static void gen_mtcrf(DisasContext *ctx)
4243 {
4244 uint32_t crm, crn;
4245
4246 crm = CRM(ctx->opcode);
4247 if (likely((ctx->opcode & 0x00100000))) {
4248 if (crm && ((crm & (crm - 1)) == 0)) {
4249 TCGv_i32 temp = tcg_temp_new_i32();
4250 crn = ctz32 (crm);
4251 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4252 tcg_gen_shri_i32(temp, temp, crn * 4);
4253 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4254 tcg_temp_free_i32(temp);
4255 }
4256 } else {
4257 TCGv_i32 temp = tcg_temp_new_i32();
4258 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4259 for (crn = 0 ; crn < 8 ; crn++) {
4260 if (crm & (1 << crn)) {
4261 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4262 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4263 }
4264 }
4265 tcg_temp_free_i32(temp);
4266 }
4267 }
4268
4269 /* mtmsr */
4270 #if defined(TARGET_PPC64)
4271 static void gen_mtmsrd(DisasContext *ctx)
4272 {
4273 #if defined(CONFIG_USER_ONLY)
4274 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4275 #else
4276 if (unlikely(!ctx->mem_idx)) {
4277 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4278 return;
4279 }
4280 if (ctx->opcode & 0x00010000) {
4281 /* Special form that does not need any synchronisation */
4282 TCGv t0 = tcg_temp_new();
4283 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4284 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4285 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4286 tcg_temp_free(t0);
4287 } else {
4288 /* XXX: we need to update nip before the store
4289 * if we enter power saving mode, we will exit the loop
4290 * directly from ppc_store_msr
4291 */
4292 gen_update_nip(ctx, ctx->nip);
4293 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4294 /* Must stop the translation as machine state (may have) changed */
4295 /* Note that mtmsr is not always defined as context-synchronizing */
4296 gen_stop_exception(ctx);
4297 }
4298 #endif
4299 }
4300 #endif
4301
4302 static void gen_mtmsr(DisasContext *ctx)
4303 {
4304 #if defined(CONFIG_USER_ONLY)
4305 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4306 #else
4307 if (unlikely(!ctx->mem_idx)) {
4308 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4309 return;
4310 }
4311 if (ctx->opcode & 0x00010000) {
4312 /* Special form that does not need any synchronisation */
4313 TCGv t0 = tcg_temp_new();
4314 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4315 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4316 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4317 tcg_temp_free(t0);
4318 } else {
4319 TCGv msr = tcg_temp_new();
4320
4321 /* XXX: we need to update nip before the store
4322 * if we enter power saving mode, we will exit the loop
4323 * directly from ppc_store_msr
4324 */
4325 gen_update_nip(ctx, ctx->nip);
4326 #if defined(TARGET_PPC64)
4327 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4328 #else
4329 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4330 #endif
4331 gen_helper_store_msr(cpu_env, msr);
4332 tcg_temp_free(msr);
4333 /* Must stop the translation as machine state (may have) changed */
4334 /* Note that mtmsr is not always defined as context-synchronizing */
4335 gen_stop_exception(ctx);
4336 }
4337 #endif
4338 }
4339
4340 /* mtspr */
4341 static void gen_mtspr(DisasContext *ctx)
4342 {
4343 void (*write_cb)(void *opaque, int sprn, int gprn);
4344 uint32_t sprn = SPR(ctx->opcode);
4345
4346 #if !defined(CONFIG_USER_ONLY)
4347 if (ctx->mem_idx == 2)
4348 write_cb = ctx->spr_cb[sprn].hea_write;
4349 else if (ctx->mem_idx)
4350 write_cb = ctx->spr_cb[sprn].oea_write;
4351 else
4352 #endif
4353 write_cb = ctx->spr_cb[sprn].uea_write;
4354 if (likely(write_cb != NULL)) {
4355 if (likely(write_cb != SPR_NOACCESS)) {
4356 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4357 } else {
4358 /* Privilege exception */
4359 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4360 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4361 printf("Trying to write privileged spr %d (0x%03x) at "
4362 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4363 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4364 }
4365 } else {
4366 /* Not defined */
4367 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4368 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4369 printf("Trying to write invalid spr %d (0x%03x) at "
4370 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4371 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4372 }
4373 }
4374
4375 /*** Cache management ***/
4376
4377 /* dcbf */
4378 static void gen_dcbf(DisasContext *ctx)
4379 {
4380 /* XXX: specification says this is treated as a load by the MMU */
4381 TCGv t0;
4382 gen_set_access_type(ctx, ACCESS_CACHE);
4383 t0 = tcg_temp_new();
4384 gen_addr_reg_index(ctx, t0);
4385 gen_qemu_ld8u(ctx, t0, t0);
4386 tcg_temp_free(t0);
4387 }
4388
4389 /* dcbi (Supervisor only) */
4390 static void gen_dcbi(DisasContext *ctx)
4391 {
4392 #if defined(CONFIG_USER_ONLY)
4393 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4394 #else
4395 TCGv EA, val;
4396 if (unlikely(!ctx->mem_idx)) {
4397 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4398 return;
4399 }
4400 EA = tcg_temp_new();
4401 gen_set_access_type(ctx, ACCESS_CACHE);
4402 gen_addr_reg_index(ctx, EA);
4403 val = tcg_temp_new();
4404 /* XXX: specification says this should be treated as a store by the MMU */
4405 gen_qemu_ld8u(ctx, val, EA);
4406 gen_qemu_st8(ctx, val, EA);
4407 tcg_temp_free(val);
4408 tcg_temp_free(EA);
4409 #endif
4410 }
4411
4412 /* dcdst */
4413 static void gen_dcbst(DisasContext *ctx)
4414 {
4415 /* XXX: specification say this is treated as a load by the MMU */
4416 TCGv t0;
4417 gen_set_access_type(ctx, ACCESS_CACHE);
4418 t0 = tcg_temp_new();
4419 gen_addr_reg_index(ctx, t0);
4420 gen_qemu_ld8u(ctx, t0, t0);
4421 tcg_temp_free(t0);
4422 }
4423
4424 /* dcbt */
4425 static void gen_dcbt(DisasContext *ctx)
4426 {
4427 /* interpreted as no-op */
4428 /* XXX: specification say this is treated as a load by the MMU
4429 * but does not generate any exception
4430 */
4431 }
4432
4433 /* dcbtst */
4434 static void gen_dcbtst(DisasContext *ctx)
4435 {
4436 /* interpreted as no-op */
4437 /* XXX: specification say this is treated as a load by the MMU
4438 * but does not generate any exception
4439 */
4440 }
4441
4442 /* dcbtls */
4443 static void gen_dcbtls(DisasContext *ctx)
4444 {
4445 /* Always fails locking the cache */
4446 TCGv t0 = tcg_temp_new();
4447 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4448 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4449 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4450 tcg_temp_free(t0);
4451 }
4452
4453 /* dcbz */
4454 static void gen_dcbz(DisasContext *ctx)
4455 {
4456 TCGv tcgv_addr;
4457 TCGv_i32 tcgv_is_dcbzl;
4458 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4459
4460 gen_set_access_type(ctx, ACCESS_CACHE);
4461 /* NIP cannot be restored if the memory exception comes from an helper */
4462 gen_update_nip(ctx, ctx->nip - 4);
4463 tcgv_addr = tcg_temp_new();
4464 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4465
4466 gen_addr_reg_index(ctx, tcgv_addr);
4467 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4468
4469 tcg_temp_free(tcgv_addr);
4470 tcg_temp_free_i32(tcgv_is_dcbzl);
4471 }
4472
4473 /* dst / dstt */
4474 static void gen_dst(DisasContext *ctx)
4475 {
4476 if (rA(ctx->opcode) == 0) {
4477 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4478 } else {
4479 /* interpreted as no-op */
4480 }
4481 }
4482
4483 /* dstst /dststt */
4484 static void gen_dstst(DisasContext *ctx)
4485 {
4486 if (rA(ctx->opcode) == 0) {
4487 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4488 } else {
4489 /* interpreted as no-op */
4490 }
4491
4492 }
4493
4494 /* dss / dssall */
4495 static void gen_dss(DisasContext *ctx)
4496 {
4497 /* interpreted as no-op */
4498 }
4499
4500 /* icbi */
4501 static void gen_icbi(DisasContext *ctx)
4502 {
4503 TCGv t0;
4504 gen_set_access_type(ctx, ACCESS_CACHE);
4505 /* NIP cannot be restored if the memory exception comes from an helper */
4506 gen_update_nip(ctx, ctx->nip - 4);
4507 t0 = tcg_temp_new();
4508 gen_addr_reg_index(ctx, t0);
4509 gen_helper_icbi(cpu_env, t0);
4510 tcg_temp_free(t0);
4511 }
4512
4513 /* Optional: */
4514 /* dcba */
4515 static void gen_dcba(DisasContext *ctx)
4516 {
4517 /* interpreted as no-op */
4518 /* XXX: specification say this is treated as a store by the MMU
4519 * but does not generate any exception
4520 */
4521 }
4522
4523 /*** Segment register manipulation ***/
4524 /* Supervisor only: */
4525
4526 /* mfsr */
4527 static void gen_mfsr(DisasContext *ctx)
4528 {
4529 #if defined(CONFIG_USER_ONLY)
4530 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4531 #else
4532 TCGv t0;
4533 if (unlikely(!ctx->mem_idx)) {
4534 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4535 return;
4536 }
4537 t0 = tcg_const_tl(SR(ctx->opcode));
4538 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4539 tcg_temp_free(t0);
4540 #endif
4541 }
4542
4543 /* mfsrin */
4544 static void gen_mfsrin(DisasContext *ctx)
4545 {
4546 #if defined(CONFIG_USER_ONLY)
4547 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4548 #else
4549 TCGv t0;
4550 if (unlikely(!ctx->mem_idx)) {
4551 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4552 return;
4553 }
4554 t0 = tcg_temp_new();
4555 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4556 tcg_gen_andi_tl(t0, t0, 0xF);
4557 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4558 tcg_temp_free(t0);
4559 #endif
4560 }
4561
4562 /* mtsr */
4563 static void gen_mtsr(DisasContext *ctx)
4564 {
4565 #if defined(CONFIG_USER_ONLY)
4566 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4567 #else
4568 TCGv t0;
4569 if (unlikely(!ctx->mem_idx)) {
4570 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4571 return;
4572 }
4573 t0 = tcg_const_tl(SR(ctx->opcode));
4574 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4575 tcg_temp_free(t0);
4576 #endif
4577 }
4578
4579 /* mtsrin */
4580 static void gen_mtsrin(DisasContext *ctx)
4581 {
4582 #if defined(CONFIG_USER_ONLY)
4583 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4584 #else
4585 TCGv t0;
4586 if (unlikely(!ctx->mem_idx)) {
4587 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4588 return;
4589 }
4590 t0 = tcg_temp_new();
4591 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4592 tcg_gen_andi_tl(t0, t0, 0xF);
4593 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4594 tcg_temp_free(t0);
4595 #endif
4596 }
4597
4598 #if defined(TARGET_PPC64)
4599 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4600
4601 /* mfsr */
4602 static void gen_mfsr_64b(DisasContext *ctx)
4603 {
4604 #if defined(CONFIG_USER_ONLY)
4605 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4606 #else
4607 TCGv t0;
4608 if (unlikely(!ctx->mem_idx)) {
4609 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4610 return;
4611 }
4612 t0 = tcg_const_tl(SR(ctx->opcode));
4613 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4614 tcg_temp_free(t0);
4615 #endif
4616 }
4617
4618 /* mfsrin */
4619 static void gen_mfsrin_64b(DisasContext *ctx)
4620 {
4621 #if defined(CONFIG_USER_ONLY)
4622 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4623 #else
4624 TCGv t0;
4625 if (unlikely(!ctx->mem_idx)) {
4626 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4627 return;
4628 }
4629 t0 = tcg_temp_new();
4630 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4631 tcg_gen_andi_tl(t0, t0, 0xF);
4632 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4633 tcg_temp_free(t0);
4634 #endif
4635 }
4636
4637 /* mtsr */
4638 static void gen_mtsr_64b(DisasContext *ctx)
4639 {
4640 #if defined(CONFIG_USER_ONLY)
4641 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4642 #else
4643 TCGv t0;
4644 if (unlikely(!ctx->mem_idx)) {
4645 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4646 return;
4647 }
4648 t0 = tcg_const_tl(SR(ctx->opcode));
4649 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4650 tcg_temp_free(t0);
4651 #endif
4652 }
4653
4654 /* mtsrin */
4655 static void gen_mtsrin_64b(DisasContext *ctx)
4656 {
4657 #if defined(CONFIG_USER_ONLY)
4658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4659 #else
4660 TCGv t0;
4661 if (unlikely(!ctx->mem_idx)) {
4662 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4663 return;
4664 }
4665 t0 = tcg_temp_new();
4666 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4667 tcg_gen_andi_tl(t0, t0, 0xF);
4668 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4669 tcg_temp_free(t0);
4670 #endif
4671 }
4672
4673 /* slbmte */
4674 static void gen_slbmte(DisasContext *ctx)
4675 {
4676 #if defined(CONFIG_USER_ONLY)
4677 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4678 #else
4679 if (unlikely(!ctx->mem_idx)) {
4680 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4681 return;
4682 }
4683 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4684 cpu_gpr[rS(ctx->opcode)]);
4685 #endif
4686 }
4687
4688 static void gen_slbmfee(DisasContext *ctx)
4689 {
4690 #if defined(CONFIG_USER_ONLY)
4691 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4692 #else
4693 if (unlikely(!ctx->mem_idx)) {
4694 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4695 return;
4696 }
4697 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4698 cpu_gpr[rB(ctx->opcode)]);
4699 #endif
4700 }
4701
4702 static void gen_slbmfev(DisasContext *ctx)
4703 {
4704 #if defined(CONFIG_USER_ONLY)
4705 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4706 #else
4707 if (unlikely(!ctx->mem_idx)) {
4708 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4709 return;
4710 }
4711 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4712 cpu_gpr[rB(ctx->opcode)]);
4713 #endif
4714 }
4715 #endif /* defined(TARGET_PPC64) */
4716
4717 /*** Lookaside buffer management ***/
4718 /* Optional & mem_idx only: */
4719
4720 /* tlbia */
4721 static void gen_tlbia(DisasContext *ctx)
4722 {
4723 #if defined(CONFIG_USER_ONLY)
4724 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4725 #else
4726 if (unlikely(!ctx->mem_idx)) {
4727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4728 return;
4729 }
4730 gen_helper_tlbia(cpu_env);
4731 #endif
4732 }
4733
4734 /* tlbiel */
4735 static void gen_tlbiel(DisasContext *ctx)
4736 {
4737 #if defined(CONFIG_USER_ONLY)
4738 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4739 #else
4740 if (unlikely(!ctx->mem_idx)) {
4741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4742 return;
4743 }
4744 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4745 #endif
4746 }
4747
4748 /* tlbie */
4749 static void gen_tlbie(DisasContext *ctx)
4750 {
4751 #if defined(CONFIG_USER_ONLY)
4752 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4753 #else
4754 if (unlikely(!ctx->mem_idx)) {
4755 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4756 return;
4757 }
4758 if (NARROW_MODE(ctx)) {
4759 TCGv t0 = tcg_temp_new();
4760 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4761 gen_helper_tlbie(cpu_env, t0);
4762 tcg_temp_free(t0);
4763 } else {
4764 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4765 }
4766 #endif
4767 }
4768
4769 /* tlbsync */
4770 static void gen_tlbsync(DisasContext *ctx)
4771 {
4772 #if defined(CONFIG_USER_ONLY)
4773 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4774 #else
4775 if (unlikely(!ctx->mem_idx)) {
4776 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4777 return;
4778 }
4779 /* This has no effect: it should ensure that all previous
4780 * tlbie have completed
4781 */
4782 gen_stop_exception(ctx);
4783 #endif
4784 }
4785
4786 #if defined(TARGET_PPC64)
4787 /* slbia */
4788 static void gen_slbia(DisasContext *ctx)
4789 {
4790 #if defined(CONFIG_USER_ONLY)
4791 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4792 #else
4793 if (unlikely(!ctx->mem_idx)) {
4794 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4795 return;
4796 }
4797 gen_helper_slbia(cpu_env);
4798 #endif
4799 }
4800
4801 /* slbie */
4802 static void gen_slbie(DisasContext *ctx)
4803 {
4804 #if defined(CONFIG_USER_ONLY)
4805 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4806 #else
4807 if (unlikely(!ctx->mem_idx)) {
4808 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4809 return;
4810 }
4811 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4812 #endif
4813 }
4814 #endif
4815
4816 /*** External control ***/
4817 /* Optional: */
4818
4819 /* eciwx */
4820 static void gen_eciwx(DisasContext *ctx)
4821 {
4822 TCGv t0;
4823 /* Should check EAR[E] ! */
4824 gen_set_access_type(ctx, ACCESS_EXT);
4825 t0 = tcg_temp_new();
4826 gen_addr_reg_index(ctx, t0);
4827 gen_check_align(ctx, t0, 0x03);
4828 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4829 tcg_temp_free(t0);
4830 }
4831
4832 /* ecowx */
4833 static void gen_ecowx(DisasContext *ctx)
4834 {
4835 TCGv t0;
4836 /* Should check EAR[E] ! */
4837 gen_set_access_type(ctx, ACCESS_EXT);
4838 t0 = tcg_temp_new();
4839 gen_addr_reg_index(ctx, t0);
4840 gen_check_align(ctx, t0, 0x03);
4841 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4842 tcg_temp_free(t0);
4843 }
4844
4845 /* PowerPC 601 specific instructions */
4846
4847 /* abs - abs. */
4848 static void gen_abs(DisasContext *ctx)
4849 {
4850 int l1 = gen_new_label();
4851 int l2 = gen_new_label();
4852 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4853 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4854 tcg_gen_br(l2);
4855 gen_set_label(l1);
4856 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4857 gen_set_label(l2);
4858 if (unlikely(Rc(ctx->opcode) != 0))
4859 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4860 }
4861
4862 /* abso - abso. */
4863 static void gen_abso(DisasContext *ctx)
4864 {
4865 int l1 = gen_new_label();
4866 int l2 = gen_new_label();
4867 int l3 = gen_new_label();
4868 /* Start with XER OV disabled, the most likely case */
4869 tcg_gen_movi_tl(cpu_ov, 0);
4870 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4871 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4872 tcg_gen_movi_tl(cpu_ov, 1);
4873 tcg_gen_movi_tl(cpu_so, 1);
4874 tcg_gen_br(l2);
4875 gen_set_label(l1);
4876 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4877 tcg_gen_br(l3);
4878 gen_set_label(l2);
4879 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4880 gen_set_label(l3);
4881 if (unlikely(Rc(ctx->opcode) != 0))
4882 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4883 }
4884
4885 /* clcs */
4886 static void gen_clcs(DisasContext *ctx)
4887 {
4888 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4889 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4890 tcg_temp_free_i32(t0);
4891 /* Rc=1 sets CR0 to an undefined state */
4892 }
4893
4894 /* div - div. */
4895 static void gen_div(DisasContext *ctx)
4896 {
4897 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4898 cpu_gpr[rB(ctx->opcode)]);
4899 if (unlikely(Rc(ctx->opcode) != 0))
4900 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4901 }
4902
4903 /* divo - divo. */
4904 static void gen_divo(DisasContext *ctx)
4905 {
4906 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4907 cpu_gpr[rB(ctx->opcode)]);
4908 if (unlikely(Rc(ctx->opcode) != 0))
4909 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4910 }
4911
4912 /* divs - divs. */
4913 static void gen_divs(DisasContext *ctx)
4914 {
4915 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4916 cpu_gpr[rB(ctx->opcode)]);
4917 if (unlikely(Rc(ctx->opcode) != 0))
4918 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4919 }
4920
4921 /* divso - divso. */
4922 static void gen_divso(DisasContext *ctx)
4923 {
4924 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4925 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4926 if (unlikely(Rc(ctx->opcode) != 0))
4927 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4928 }
4929
4930 /* doz - doz. */
4931 static void gen_doz(DisasContext *ctx)
4932 {
4933 int l1 = gen_new_label();
4934 int l2 = gen_new_label();
4935 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4936 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4937 tcg_gen_br(l2);
4938 gen_set_label(l1);
4939 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4940 gen_set_label(l2);
4941 if (unlikely(Rc(ctx->opcode) != 0))
4942 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4943 }
4944
4945 /* dozo - dozo. */
4946 static void gen_dozo(DisasContext *ctx)
4947 {
4948 int l1 = gen_new_label();
4949 int l2 = gen_new_label();
4950 TCGv t0 = tcg_temp_new();
4951 TCGv t1 = tcg_temp_new();
4952 TCGv t2 = tcg_temp_new();
4953 /* Start with XER OV disabled, the most likely case */
4954 tcg_gen_movi_tl(cpu_ov, 0);
4955 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4956 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4957 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4958 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4959 tcg_gen_andc_tl(t1, t1, t2);
4960 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4961 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4962 tcg_gen_movi_tl(cpu_ov, 1);
4963 tcg_gen_movi_tl(cpu_so, 1);
4964 tcg_gen_br(l2);
4965 gen_set_label(l1);
4966 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4967 gen_set_label(l2);
4968 tcg_temp_free(t0);
4969 tcg_temp_free(t1);
4970 tcg_temp_free(t2);
4971 if (unlikely(Rc(ctx->opcode) != 0))
4972 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4973 }
4974
4975 /* dozi */
4976 static void gen_dozi(DisasContext *ctx)
4977 {
4978 target_long simm = SIMM(ctx->opcode);
4979 int l1 = gen_new_label();
4980 int l2 = gen_new_label();
4981 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4982 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4983 tcg_gen_br(l2);
4984 gen_set_label(l1);
4985 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4986 gen_set_label(l2);
4987 if (unlikely(Rc(ctx->opcode) != 0))
4988 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4989 }
4990
4991 /* lscbx - lscbx. */
4992 static void gen_lscbx(DisasContext *ctx)
4993 {
4994 TCGv t0 = tcg_temp_new();
4995 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4996 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4997 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4998
4999 gen_addr_reg_index(ctx, t0);
5000 /* NIP cannot be restored if the memory exception comes from an helper */
5001 gen_update_nip(ctx, ctx->nip - 4);
5002 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5003 tcg_temp_free_i32(t1);
5004 tcg_temp_free_i32(t2);
5005 tcg_temp_free_i32(t3);
5006 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5007 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5008 if (unlikely(Rc(ctx->opcode) != 0))
5009 gen_set_Rc0(ctx, t0);
5010 tcg_temp_free(t0);
5011 }
5012
5013 /* maskg - maskg. */
5014 static void gen_maskg(DisasContext *ctx)
5015 {
5016 int l1 = gen_new_label();
5017 TCGv t0 = tcg_temp_new();
5018 TCGv t1 = tcg_temp_new();
5019 TCGv t2 = tcg_temp_new();
5020 TCGv t3 = tcg_temp_new();
5021 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5022 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5023 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5024 tcg_gen_addi_tl(t2, t0, 1);
5025 tcg_gen_shr_tl(t2, t3, t2);
5026 tcg_gen_shr_tl(t3, t3, t1);
5027 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5028 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5029 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5030 gen_set_label(l1);
5031 tcg_temp_free(t0);
5032 tcg_temp_free(t1);
5033 tcg_temp_free(t2);
5034 tcg_temp_free(t3);
5035 if (unlikely(Rc(ctx->opcode) != 0))
5036 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5037 }
5038
5039 /* maskir - maskir. */
5040 static void gen_maskir(DisasContext *ctx)
5041 {
5042 TCGv t0 = tcg_temp_new();
5043 TCGv t1 = tcg_temp_new();
5044 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5045 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5046 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5047 tcg_temp_free(t0);
5048 tcg_temp_free(t1);
5049 if (unlikely(Rc(ctx->opcode) != 0))
5050 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5051 }
5052
5053 /* mul - mul. */
5054 static void gen_mul(DisasContext *ctx)
5055 {
5056 TCGv_i64 t0 = tcg_temp_new_i64();
5057 TCGv_i64 t1 = tcg_temp_new_i64();
5058 TCGv t2 = tcg_temp_new();
5059 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5060 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5061 tcg_gen_mul_i64(t0, t0, t1);
5062 tcg_gen_trunc_i64_tl(t2, t0);
5063 gen_store_spr(SPR_MQ, t2);
5064 tcg_gen_shri_i64(t1, t0, 32);
5065 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5066 tcg_temp_free_i64(t0);
5067 tcg_temp_free_i64(t1);
5068 tcg_temp_free(t2);
5069 if (unlikely(Rc(ctx->opcode) != 0))
5070 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5071 }
5072
5073 /* mulo - mulo. */
5074 static void gen_mulo(DisasContext *ctx)
5075 {
5076 int l1 = gen_new_label();
5077 TCGv_i64 t0 = tcg_temp_new_i64();
5078 TCGv_i64 t1 = tcg_temp_new_i64();
5079 TCGv t2 = tcg_temp_new();
5080 /* Start with XER OV disabled, the most likely case */
5081 tcg_gen_movi_tl(cpu_ov, 0);
5082 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5083 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5084 tcg_gen_mul_i64(t0, t0, t1);
5085 tcg_gen_trunc_i64_tl(t2, t0);
5086 gen_store_spr(SPR_MQ, t2);
5087 tcg_gen_shri_i64(t1, t0, 32);
5088 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5089 tcg_gen_ext32s_i64(t1, t0);
5090 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5091 tcg_gen_movi_tl(cpu_ov, 1);
5092 tcg_gen_movi_tl(cpu_so, 1);
5093 gen_set_label(l1);
5094 tcg_temp_free_i64(t0);
5095 tcg_temp_free_i64(t1);
5096 tcg_temp_free(t2);
5097 if (unlikely(Rc(ctx->opcode) != 0))
5098 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5099 }
5100
5101 /* nabs - nabs. */
5102 static void gen_nabs(DisasContext *ctx)
5103 {
5104 int l1 = gen_new_label();
5105 int l2 = gen_new_label();
5106 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5107 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5108 tcg_gen_br(l2);
5109 gen_set_label(l1);
5110 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5111 gen_set_label(l2);
5112 if (unlikely(Rc(ctx->opcode) != 0))
5113 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5114 }
5115
5116 /* nabso - nabso. */
5117 static void gen_nabso(DisasContext *ctx)
5118 {
5119 int l1 = gen_new_label();
5120 int l2 = gen_new_label();
5121 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5122 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5123 tcg_gen_br(l2);
5124 gen_set_label(l1);
5125 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5126 gen_set_label(l2);
5127 /* nabs never overflows */
5128 tcg_gen_movi_tl(cpu_ov, 0);
5129 if (unlikely(Rc(ctx->opcode) != 0))
5130 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5131 }
5132
5133 /* rlmi - rlmi. */
5134 static void gen_rlmi(DisasContext *ctx)
5135 {
5136 uint32_t mb = MB(ctx->opcode);
5137 uint32_t me = ME(ctx->opcode);
5138 TCGv t0 = tcg_temp_new();
5139 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5140 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5141 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5142 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5143 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5144 tcg_temp_free(t0);
5145 if (unlikely(Rc(ctx->opcode) != 0))
5146 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5147 }
5148
5149 /* rrib - rrib. */
5150 static void gen_rrib(DisasContext *ctx)
5151 {
5152 TCGv t0 = tcg_temp_new();
5153 TCGv t1 = tcg_temp_new();
5154 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5155 tcg_gen_movi_tl(t1, 0x80000000);
5156 tcg_gen_shr_tl(t1, t1, t0);
5157 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5158 tcg_gen_and_tl(t0, t0, t1);
5159 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5160 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5161 tcg_temp_free(t0);
5162 tcg_temp_free(t1);
5163 if (unlikely(Rc(ctx->opcode) != 0))
5164 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5165 }
5166
5167 /* sle - sle. */
5168 static void gen_sle(DisasContext *ctx)
5169 {
5170 TCGv t0 = tcg_temp_new();
5171 TCGv t1 = tcg_temp_new();
5172 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5173 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5174 tcg_gen_subfi_tl(t1, 32, t1);
5175 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5176 tcg_gen_or_tl(t1, t0, t1);
5177 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5178 gen_store_spr(SPR_MQ, t1);
5179 tcg_temp_free(t0);
5180 tcg_temp_free(t1);
5181 if (unlikely(Rc(ctx->opcode) != 0))
5182 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5183 }
5184
5185 /* sleq - sleq. */
5186 static void gen_sleq(DisasContext *ctx)
5187 {
5188 TCGv t0 = tcg_temp_new();
5189 TCGv t1 = tcg_temp_new();
5190 TCGv t2 = tcg_temp_new();
5191 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5192 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5193 tcg_gen_shl_tl(t2, t2, t0);
5194 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5195 gen_load_spr(t1, SPR_MQ);
5196 gen_store_spr(SPR_MQ, t0);
5197 tcg_gen_and_tl(t0, t0, t2);
5198 tcg_gen_andc_tl(t1, t1, t2);
5199 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5200 tcg_temp_free(t0);
5201 tcg_temp_free(t1);
5202 tcg_temp_free(t2);
5203 if (unlikely(Rc(ctx->opcode) != 0))
5204 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5205 }
5206
5207 /* sliq - sliq. */
5208 static void gen_sliq(DisasContext *ctx)
5209 {
5210 int sh = SH(ctx->opcode);
5211 TCGv t0 = tcg_temp_new();
5212 TCGv t1 = tcg_temp_new();
5213 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5214 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5215 tcg_gen_or_tl(t1, t0, t1);
5216 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5217 gen_store_spr(SPR_MQ, t1);
5218 tcg_temp_free(t0);
5219 tcg_temp_free(t1);
5220 if (unlikely(Rc(ctx->opcode) != 0))
5221 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5222 }
5223
5224 /* slliq - slliq. */
5225 static void gen_slliq(DisasContext *ctx)
5226 {
5227 int sh = SH(ctx->opcode);
5228 TCGv t0 = tcg_temp_new();
5229 TCGv t1 = tcg_temp_new();
5230 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5231 gen_load_spr(t1, SPR_MQ);
5232 gen_store_spr(SPR_MQ, t0);
5233 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5234 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5235 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5236 tcg_temp_free(t0);
5237 tcg_temp_free(t1);
5238 if (unlikely(Rc(ctx->opcode) != 0))
5239 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5240 }
5241
5242 /* sllq - sllq. */
5243 static void gen_sllq(DisasContext *ctx)
5244 {
5245 int l1 = gen_new_label();
5246 int l2 = gen_new_label();
5247 TCGv t0 = tcg_temp_local_new();
5248 TCGv t1 = tcg_temp_local_new();
5249 TCGv t2 = tcg_temp_local_new();
5250 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5251 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5252 tcg_gen_shl_tl(t1, t1, t2);
5253 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5254 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5255 gen_load_spr(t0, SPR_MQ);
5256 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5257 tcg_gen_br(l2);
5258 gen_set_label(l1);
5259 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5260 gen_load_spr(t2, SPR_MQ);
5261 tcg_gen_andc_tl(t1, t2, t1);
5262 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5263 gen_set_label(l2);
5264 tcg_temp_free(t0);
5265 tcg_temp_free(t1);
5266 tcg_temp_free(t2);
5267 if (unlikely(Rc(ctx->opcode) != 0))
5268 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5269 }
5270
5271 /* slq - slq. */
5272 static void gen_slq(DisasContext *ctx)
5273 {
5274 int l1 = gen_new_label();
5275 TCGv t0 = tcg_temp_new();
5276 TCGv t1 = tcg_temp_new();
5277 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5278 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5279 tcg_gen_subfi_tl(t1, 32, t1);
5280 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5281 tcg_gen_or_tl(t1, t0, t1);
5282 gen_store_spr(SPR_MQ, t1);
5283 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5284 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5285 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5286 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5287 gen_set_label(l1);
5288 tcg_temp_free(t0);
5289 tcg_temp_free(t1);
5290 if (unlikely(Rc(ctx->opcode) != 0))
5291 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5292 }
5293
5294 /* sraiq - sraiq. */
5295 static void gen_sraiq(DisasContext *ctx)
5296 {
5297 int sh = SH(ctx->opcode);
5298 int l1 = gen_new_label();
5299 TCGv t0 = tcg_temp_new();
5300 TCGv t1 = tcg_temp_new();
5301 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5302 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5303 tcg_gen_or_tl(t0, t0, t1);
5304 gen_store_spr(SPR_MQ, t0);
5305 tcg_gen_movi_tl(cpu_ca, 0);
5306 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5307 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5308 tcg_gen_movi_tl(cpu_ca, 1);
5309 gen_set_label(l1);
5310 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5311 tcg_temp_free(t0);
5312 tcg_temp_free(t1);
5313 if (unlikely(Rc(ctx->opcode) != 0))
5314 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5315 }
5316
5317 /* sraq - sraq. */
5318 static void gen_sraq(DisasContext *ctx)
5319 {
5320 int l1 = gen_new_label();
5321 int l2 = gen_new_label();
5322 TCGv t0 = tcg_temp_new();
5323 TCGv t1 = tcg_temp_local_new();
5324 TCGv t2 = tcg_temp_local_new();
5325 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5326 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5327 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5328 tcg_gen_subfi_tl(t2, 32, t2);
5329 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5330 tcg_gen_or_tl(t0, t0, t2);
5331 gen_store_spr(SPR_MQ, t0);
5332 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5333 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5334 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5335 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5336 gen_set_label(l1);
5337 tcg_temp_free(t0);
5338 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5339 tcg_gen_movi_tl(cpu_ca, 0);
5340 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5341 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5342 tcg_gen_movi_tl(cpu_ca, 1);
5343 gen_set_label(l2);
5344 tcg_temp_free(t1);
5345 tcg_temp_free(t2);
5346 if (unlikely(Rc(ctx->opcode) != 0))
5347 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5348 }
5349
5350 /* sre - sre. */
5351 static void gen_sre(DisasContext *ctx)
5352 {
5353 TCGv t0 = tcg_temp_new();
5354 TCGv t1 = tcg_temp_new();
5355 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5356 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5357 tcg_gen_subfi_tl(t1, 32, t1);
5358 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5359 tcg_gen_or_tl(t1, t0, t1);
5360 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5361 gen_store_spr(SPR_MQ, t1);
5362 tcg_temp_free(t0);
5363 tcg_temp_free(t1);
5364 if (unlikely(Rc(ctx->opcode) != 0))
5365 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5366 }
5367
5368 /* srea - srea. */
5369 static void gen_srea(DisasContext *ctx)
5370 {
5371 TCGv t0 = tcg_temp_new();
5372 TCGv t1 = tcg_temp_new();
5373 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5374 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5375 gen_store_spr(SPR_MQ, t0);
5376 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5377 tcg_temp_free(t0);
5378 tcg_temp_free(t1);
5379 if (unlikely(Rc(ctx->opcode) != 0))
5380 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5381 }
5382
5383 /* sreq */
5384 static void gen_sreq(DisasContext *ctx)
5385 {
5386 TCGv t0 = tcg_temp_new();
5387 TCGv t1 = tcg_temp_new();
5388 TCGv t2 = tcg_temp_new();
5389 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5390 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5391 tcg_gen_shr_tl(t1, t1, t0);
5392 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5393 gen_load_spr(t2, SPR_MQ);
5394 gen_store_spr(SPR_MQ, t0);
5395 tcg_gen_and_tl(t0, t0, t1);
5396 tcg_gen_andc_tl(t2, t2, t1);
5397 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5398 tcg_temp_free(t0);
5399 tcg_temp_free(t1);
5400 tcg_temp_free(t2);
5401 if (unlikely(Rc(ctx->opcode) != 0))
5402 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5403 }
5404
5405 /* sriq */
5406 static void gen_sriq(DisasContext *ctx)
5407 {
5408 int sh = SH(ctx->opcode);
5409 TCGv t0 = tcg_temp_new();
5410 TCGv t1 = tcg_temp_new();
5411 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5412 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5413 tcg_gen_or_tl(t1, t0, t1);
5414 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5415 gen_store_spr(SPR_MQ, t1);
5416 tcg_temp_free(t0);
5417 tcg_temp_free(t1);
5418 if (unlikely(Rc(ctx->opcode) != 0))
5419 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5420 }
5421
5422 /* srliq */
5423 static void gen_srliq(DisasContext *ctx)
5424 {
5425 int sh = SH(ctx->opcode);
5426 TCGv t0 = tcg_temp_new();
5427 TCGv t1 = tcg_temp_new();
5428 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5429 gen_load_spr(t1, SPR_MQ);
5430 gen_store_spr(SPR_MQ, t0);
5431 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5432 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5433 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5434 tcg_temp_free(t0);
5435 tcg_temp_free(t1);
5436 if (unlikely(Rc(ctx->opcode) != 0))
5437 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5438 }
5439
5440 /* srlq */
5441 static void gen_srlq(DisasContext *ctx)
5442 {
5443 int l1 = gen_new_label();
5444 int l2 = gen_new_label();
5445 TCGv t0 = tcg_temp_local_new();
5446 TCGv t1 = tcg_temp_local_new();
5447 TCGv t2 = tcg_temp_local_new();
5448 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5449 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5450 tcg_gen_shr_tl(t2, t1, t2);
5451 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5452 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5453 gen_load_spr(t0, SPR_MQ);
5454 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5455 tcg_gen_br(l2);
5456 gen_set_label(l1);
5457 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5458 tcg_gen_and_tl(t0, t0, t2);
5459 gen_load_spr(t1, SPR_MQ);
5460 tcg_gen_andc_tl(t1, t1, t2);
5461 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5462 gen_set_label(l2);
5463 tcg_temp_free(t0);
5464 tcg_temp_free(t1);
5465 tcg_temp_free(t2);
5466 if (unlikely(Rc(ctx->opcode) != 0))
5467 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5468 }
5469
5470 /* srq */
5471 static void gen_srq(DisasContext *ctx)
5472 {
5473 int l1 = gen_new_label();
5474 TCGv t0 = tcg_temp_new();
5475 TCGv t1 = tcg_temp_new();
5476 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5477 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5478 tcg_gen_subfi_tl(t1, 32, t1);
5479 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5480 tcg_gen_or_tl(t1, t0, t1);
5481 gen_store_spr(SPR_MQ, t1);
5482 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5483 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5484 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5485 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5486 gen_set_label(l1);
5487 tcg_temp_free(t0);
5488 tcg_temp_free(t1);
5489 if (unlikely(Rc(ctx->opcode) != 0))
5490 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5491 }
5492
5493 /* PowerPC 602 specific instructions */
5494
5495 /* dsa */
5496 static void gen_dsa(DisasContext *ctx)
5497 {
5498 /* XXX: TODO */
5499 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5500 }
5501
5502 /* esa */
5503 static void gen_esa(DisasContext *ctx)
5504 {
5505 /* XXX: TODO */
5506 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5507 }
5508
5509 /* mfrom */
5510 static void gen_mfrom(DisasContext *ctx)
5511 {
5512 #if defined(CONFIG_USER_ONLY)
5513 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5514 #else
5515 if (unlikely(!ctx->mem_idx)) {
5516 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5517 return;
5518 }
5519 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5520 #endif
5521 }
5522
5523 /* 602 - 603 - G2 TLB management */
5524
5525 /* tlbld */
5526 static void gen_tlbld_6xx(DisasContext *ctx)
5527 {
5528 #if defined(CONFIG_USER_ONLY)
5529 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5530 #else
5531 if (unlikely(!ctx->mem_idx)) {
5532 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5533 return;
5534 }
5535 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5536 #endif
5537 }
5538
5539 /* tlbli */
5540 static void gen_tlbli_6xx(DisasContext *ctx)
5541 {
5542 #if defined(CONFIG_USER_ONLY)
5543 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5544 #else
5545 if (unlikely(!ctx->mem_idx)) {
5546 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5547 return;
5548 }
5549 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5550 #endif
5551 }
5552
5553 /* 74xx TLB management */
5554
5555 /* tlbld */
5556 static void gen_tlbld_74xx(DisasContext *ctx)
5557 {
5558 #if defined(CONFIG_USER_ONLY)
5559 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5560 #else
5561 if (unlikely(!ctx->mem_idx)) {
5562 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5563 return;
5564 }
5565 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5566 #endif
5567 }
5568
5569 /* tlbli */
5570 static void gen_tlbli_74xx(DisasContext *ctx)
5571 {
5572 #if defined(CONFIG_USER_ONLY)
5573 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5574 #else
5575 if (unlikely(!ctx->mem_idx)) {
5576 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5577 return;
5578 }
5579 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5580 #endif
5581 }
5582
5583 /* POWER instructions not in PowerPC 601 */
5584
5585 /* clf */
5586 static void gen_clf(DisasContext *ctx)
5587 {
5588 /* Cache line flush: implemented as no-op */
5589 }
5590
5591 /* cli */
5592 static void gen_cli(DisasContext *ctx)
5593 {
5594 /* Cache line invalidate: privileged and treated as no-op */
5595 #if defined(CONFIG_USER_ONLY)
5596 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5597 #else
5598 if (unlikely(!ctx->mem_idx)) {
5599 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5600 return;
5601 }
5602 #endif
5603 }
5604
5605 /* dclst */
5606 static void gen_dclst(DisasContext *ctx)
5607 {
5608 /* Data cache line store: treated as no-op */
5609 }
5610
5611 static void gen_mfsri(DisasContext *ctx)
5612 {
5613 #if defined(CONFIG_USER_ONLY)
5614 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5615 #else
5616 int ra = rA(ctx->opcode);
5617 int rd = rD(ctx->opcode);
5618 TCGv t0;
5619 if (unlikely(!ctx->mem_idx)) {
5620 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5621 return;
5622 }
5623 t0 = tcg_temp_new();
5624 gen_addr_reg_index(ctx, t0);
5625 tcg_gen_shri_tl(t0, t0, 28);
5626 tcg_gen_andi_tl(t0, t0, 0xF);
5627 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5628 tcg_temp_free(t0);
5629 if (ra != 0 && ra != rd)
5630 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5631 #endif
5632 }
5633
5634 static void gen_rac(DisasContext *ctx)
5635 {
5636 #if defined(CONFIG_USER_ONLY)
5637 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5638 #else
5639 TCGv t0;
5640 if (unlikely(!ctx->mem_idx)) {
5641 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5642 return;
5643 }
5644 t0 = tcg_temp_new();
5645 gen_addr_reg_index(ctx, t0);
5646 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5647 tcg_temp_free(t0);
5648 #endif
5649 }
5650
5651 static void gen_rfsvc(DisasContext *ctx)
5652 {
5653 #if defined(CONFIG_USER_ONLY)
5654 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5655 #else
5656 if (unlikely(!ctx->mem_idx)) {
5657 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5658 return;
5659 }
5660 gen_helper_rfsvc(cpu_env);
5661 gen_sync_exception(ctx);
5662 #endif
5663 }
5664
5665 /* svc is not implemented for now */
5666
5667 /* POWER2 specific instructions */
5668 /* Quad manipulation (load/store two floats at a time) */
5669
5670 /* lfq */
5671 static void gen_lfq(DisasContext *ctx)
5672 {
5673 int rd = rD(ctx->opcode);
5674 TCGv t0;
5675 gen_set_access_type(ctx, ACCESS_FLOAT);
5676 t0 = tcg_temp_new();
5677 gen_addr_imm_index(ctx, t0, 0);
5678 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5679 gen_addr_add(ctx, t0, t0, 8);
5680 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5681 tcg_temp_free(t0);
5682 }
5683
5684 /* lfqu */
5685 static void gen_lfqu(DisasContext *ctx)
5686 {
5687 int ra = rA(ctx->opcode);
5688 int rd = rD(ctx->opcode);
5689 TCGv t0, t1;
5690 gen_set_access_type(ctx, ACCESS_FLOAT);
5691 t0 = tcg_temp_new();
5692 t1 = tcg_temp_new();
5693 gen_addr_imm_index(ctx, t0, 0);
5694 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5695 gen_addr_add(ctx, t1, t0, 8);
5696 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5697 if (ra != 0)
5698 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5699 tcg_temp_free(t0);
5700 tcg_temp_free(t1);
5701 }
5702
5703 /* lfqux */
5704 static void gen_lfqux(DisasContext *ctx)
5705 {
5706 int ra = rA(ctx->opcode);
5707 int rd = rD(ctx->opcode);
5708 gen_set_access_type(ctx, ACCESS_FLOAT);
5709 TCGv t0, t1;
5710 t0 = tcg_temp_new();
5711 gen_addr_reg_index(ctx, t0);
5712 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5713 t1 = tcg_temp_new();
5714 gen_addr_add(ctx, t1, t0, 8);
5715 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5716 tcg_temp_free(t1);
5717 if (ra != 0)
5718 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5719 tcg_temp_free(t0);
5720 }
5721
5722 /* lfqx */
5723 static void gen_lfqx(DisasContext *ctx)
5724 {
5725 int rd = rD(ctx->opcode);
5726 TCGv t0;
5727 gen_set_access_type(ctx, ACCESS_FLOAT);
5728 t0 = tcg_temp_new();
5729 gen_addr_reg_index(ctx, t0);
5730 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5731 gen_addr_add(ctx, t0, t0, 8);
5732 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5733 tcg_temp_free(t0);
5734 }
5735
5736 /* stfq */
5737 static void gen_stfq(DisasContext *ctx)
5738 {
5739 int rd = rD(ctx->opcode);
5740 TCGv t0;
5741 gen_set_access_type(ctx, ACCESS_FLOAT);
5742 t0 = tcg_temp_new();
5743 gen_addr_imm_index(ctx, t0, 0);
5744 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5745 gen_addr_add(ctx, t0, t0, 8);
5746 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5747 tcg_temp_free(t0);
5748 }
5749
5750 /* stfqu */
5751 static void gen_stfqu(DisasContext *ctx)
5752 {
5753 int ra = rA(ctx->opcode);
5754 int rd = rD(ctx->opcode);
5755 TCGv t0, t1;
5756 gen_set_access_type(ctx, ACCESS_FLOAT);
5757 t0 = tcg_temp_new();
5758 gen_addr_imm_index(ctx, t0, 0);
5759 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5760 t1 = tcg_temp_new();
5761 gen_addr_add(ctx, t1, t0, 8);
5762 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5763 tcg_temp_free(t1);
5764 if (ra != 0)
5765 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5766 tcg_temp_free(t0);
5767 }
5768
5769 /* stfqux */
5770 static void gen_stfqux(DisasContext *ctx)
5771 {
5772 int ra = rA(ctx->opcode);
5773 int rd = rD(ctx->opcode);
5774 TCGv t0, t1;
5775 gen_set_access_type(ctx, ACCESS_FLOAT);
5776 t0 = tcg_temp_new();
5777 gen_addr_reg_index(ctx, t0);
5778 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5779 t1 = tcg_temp_new();
5780 gen_addr_add(ctx, t1, t0, 8);
5781 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5782 tcg_temp_free(t1);
5783 if (ra != 0)
5784 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5785 tcg_temp_free(t0);
5786 }
5787
5788 /* stfqx */
5789 static void gen_stfqx(DisasContext *ctx)
5790 {
5791 int rd = rD(ctx->opcode);
5792 TCGv t0;
5793 gen_set_access_type(ctx, ACCESS_FLOAT);
5794 t0 = tcg_temp_new();
5795 gen_addr_reg_index(ctx, t0);
5796 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5797 gen_addr_add(ctx, t0, t0, 8);
5798 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5799 tcg_temp_free(t0);
5800 }
5801
5802 /* BookE specific instructions */
5803
5804 /* XXX: not implemented on 440 ? */
5805 static void gen_mfapidi(DisasContext *ctx)
5806 {
5807 /* XXX: TODO */
5808 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5809 }
5810
5811 /* XXX: not implemented on 440 ? */
5812 static void gen_tlbiva(DisasContext *ctx)
5813 {
5814 #if defined(CONFIG_USER_ONLY)
5815 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5816 #else
5817 TCGv t0;
5818 if (unlikely(!ctx->mem_idx)) {
5819 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5820 return;
5821 }
5822 t0 = tcg_temp_new();
5823 gen_addr_reg_index(ctx, t0);
5824 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5825 tcg_temp_free(t0);
5826 #endif
5827 }
5828
5829 /* All 405 MAC instructions are translated here */
5830 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5831 int ra, int rb, int rt, int Rc)
5832 {
5833 TCGv t0, t1;
5834
5835 t0 = tcg_temp_local_new();
5836 t1 = tcg_temp_local_new();
5837
5838 switch (opc3 & 0x0D) {
5839 case 0x05:
5840 /* macchw - macchw. - macchwo - macchwo. */
5841 /* macchws - macchws. - macchwso - macchwso. */
5842 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5843 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5844 /* mulchw - mulchw. */
5845 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5846 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5847 tcg_gen_ext16s_tl(t1, t1);
5848 break;
5849 case 0x04:
5850 /* macchwu - macchwu. - macchwuo - macchwuo. */
5851 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5852 /* mulchwu - mulchwu. */
5853 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5854 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5855 tcg_gen_ext16u_tl(t1, t1);
5856 break;
5857 case 0x01:
5858 /* machhw - machhw. - machhwo - machhwo. */
5859 /* machhws - machhws. - machhwso - machhwso. */
5860 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5861 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5862 /* mulhhw - mulhhw. */
5863 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5864 tcg_gen_ext16s_tl(t0, t0);
5865 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5866 tcg_gen_ext16s_tl(t1, t1);
5867 break;
5868 case 0x00:
5869 /* machhwu - machhwu. - machhwuo - machhwuo. */
5870 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5871 /* mulhhwu - mulhhwu. */
5872 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5873 tcg_gen_ext16u_tl(t0, t0);
5874 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5875 tcg_gen_ext16u_tl(t1, t1);
5876 break;
5877 case 0x0D:
5878 /* maclhw - maclhw. - maclhwo - maclhwo. */
5879 /* maclhws - maclhws. - maclhwso - maclhwso. */
5880 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5881 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5882 /* mullhw - mullhw. */
5883 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5884 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5885 break;
5886 case 0x0C:
5887 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5888 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5889 /* mullhwu - mullhwu. */
5890 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5891 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5892 break;
5893 }
5894 if (opc2 & 0x04) {
5895 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5896 tcg_gen_mul_tl(t1, t0, t1);
5897 if (opc2 & 0x02) {
5898 /* nmultiply-and-accumulate (0x0E) */
5899 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5900 } else {
5901 /* multiply-and-accumulate (0x0C) */
5902 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5903 }
5904
5905 if (opc3 & 0x12) {
5906 /* Check overflow and/or saturate */
5907 int l1 = gen_new_label();
5908
5909 if (opc3 & 0x10) {
5910 /* Start with XER OV disabled, the most likely case */
5911 tcg_gen_movi_tl(cpu_ov, 0);
5912 }
5913 if (opc3 & 0x01) {
5914 /* Signed */
5915 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5916 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5917 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5918 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5919 if (opc3 & 0x02) {
5920 /* Saturate */
5921 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5922 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5923 }
5924 } else {
5925 /* Unsigned */
5926 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5927 if (opc3 & 0x02) {
5928 /* Saturate */
5929 tcg_gen_movi_tl(t0, UINT32_MAX);
5930 }
5931 }
5932 if (opc3 & 0x10) {
5933 /* Check overflow */
5934 tcg_gen_movi_tl(cpu_ov, 1);
5935 tcg_gen_movi_tl(cpu_so, 1);
5936 }
5937 gen_set_label(l1);
5938 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5939 }
5940 } else {
5941 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5942 }
5943 tcg_temp_free(t0);
5944 tcg_temp_free(t1);
5945 if (unlikely(Rc) != 0) {
5946 /* Update Rc0 */
5947 gen_set_Rc0(ctx, cpu_gpr[rt]);
5948 }
5949 }
5950
5951 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5952 static void glue(gen_, name)(DisasContext *ctx) \
5953 { \
5954 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5955 rD(ctx->opcode), Rc(ctx->opcode)); \
5956 }
5957
5958 /* macchw - macchw. */
5959 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5960 /* macchwo - macchwo. */
5961 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5962 /* macchws - macchws. */
5963 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5964 /* macchwso - macchwso. */
5965 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5966 /* macchwsu - macchwsu. */
5967 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5968 /* macchwsuo - macchwsuo. */
5969 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5970 /* macchwu - macchwu. */
5971 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5972 /* macchwuo - macchwuo. */
5973 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5974 /* machhw - machhw. */
5975 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5976 /* machhwo - machhwo. */
5977 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5978 /* machhws - machhws. */
5979 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5980 /* machhwso - machhwso. */
5981 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5982 /* machhwsu - machhwsu. */
5983 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5984 /* machhwsuo - machhwsuo. */
5985 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5986 /* machhwu - machhwu. */
5987 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5988 /* machhwuo - machhwuo. */
5989 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5990 /* maclhw - maclhw. */
5991 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5992 /* maclhwo - maclhwo. */
5993 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5994 /* maclhws - maclhws. */
5995 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5996 /* maclhwso - maclhwso. */
5997 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5998 /* maclhwu - maclhwu. */
5999 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6000 /* maclhwuo - maclhwuo. */
6001 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6002 /* maclhwsu - maclhwsu. */
6003 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6004 /* maclhwsuo - maclhwsuo. */
6005 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6006 /* nmacchw - nmacchw. */
6007 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6008 /* nmacchwo - nmacchwo. */
6009 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6010 /* nmacchws - nmacchws. */
6011 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6012 /* nmacchwso - nmacchwso. */
6013 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6014 /* nmachhw - nmachhw. */
6015 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6016 /* nmachhwo - nmachhwo. */
6017 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6018 /* nmachhws - nmachhws. */
6019 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6020 /* nmachhwso - nmachhwso. */
6021 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6022 /* nmaclhw - nmaclhw. */
6023 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6024 /* nmaclhwo - nmaclhwo. */
6025 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6026 /* nmaclhws - nmaclhws. */
6027 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6028 /* nmaclhwso - nmaclhwso. */
6029 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6030
6031 /* mulchw - mulchw. */
6032 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6033 /* mulchwu - mulchwu. */
6034 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6035 /* mulhhw - mulhhw. */
6036 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6037 /* mulhhwu - mulhhwu. */
6038 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6039 /* mullhw - mullhw. */
6040 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6041 /* mullhwu - mullhwu. */
6042 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6043
6044 /* mfdcr */
6045 static void gen_mfdcr(DisasContext *ctx)
6046 {
6047 #if defined(CONFIG_USER_ONLY)
6048 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6049 #else
6050 TCGv dcrn;
6051 if (unlikely(!ctx->mem_idx)) {
6052 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6053 return;
6054 }
6055 /* NIP cannot be restored if the memory exception comes from an helper */
6056 gen_update_nip(ctx, ctx->nip - 4);
6057 dcrn = tcg_const_tl(SPR(ctx->opcode));
6058 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6059 tcg_temp_free(dcrn);
6060 #endif
6061 }
6062
6063 /* mtdcr */
6064 static void gen_mtdcr(DisasContext *ctx)
6065 {
6066 #if defined(CONFIG_USER_ONLY)
6067 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6068 #else
6069 TCGv dcrn;
6070 if (unlikely(!ctx->mem_idx)) {
6071 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6072 return;
6073 }
6074 /* NIP cannot be restored if the memory exception comes from an helper */
6075 gen_update_nip(ctx, ctx->nip - 4);
6076 dcrn = tcg_const_tl(SPR(ctx->opcode));
6077 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6078 tcg_temp_free(dcrn);
6079 #endif
6080 }
6081
6082 /* mfdcrx */
6083 /* XXX: not implemented on 440 ? */
6084 static void gen_mfdcrx(DisasContext *ctx)
6085 {
6086 #if defined(CONFIG_USER_ONLY)
6087 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6088 #else
6089 if (unlikely(!ctx->mem_idx)) {
6090 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6091 return;
6092 }
6093 /* NIP cannot be restored if the memory exception comes from an helper */
6094 gen_update_nip(ctx, ctx->nip - 4);
6095 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6096 cpu_gpr[rA(ctx->opcode)]);
6097 /* Note: Rc update flag set leads to undefined state of Rc0 */
6098 #endif
6099 }
6100
6101 /* mtdcrx */
6102 /* XXX: not implemented on 440 ? */
6103 static void gen_mtdcrx(DisasContext *ctx)
6104 {
6105 #if defined(CONFIG_USER_ONLY)
6106 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6107 #else
6108 if (unlikely(!ctx->mem_idx)) {
6109 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6110 return;
6111 }
6112 /* NIP cannot be restored if the memory exception comes from an helper */
6113 gen_update_nip(ctx, ctx->nip - 4);
6114 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6115 cpu_gpr[rS(ctx->opcode)]);
6116 /* Note: Rc update flag set leads to undefined state of Rc0 */
6117 #endif
6118 }
6119
6120 /* mfdcrux (PPC 460) : user-mode access to DCR */
6121 static void gen_mfdcrux(DisasContext *ctx)
6122 {
6123 /* NIP cannot be restored if the memory exception comes from an helper */
6124 gen_update_nip(ctx, ctx->nip - 4);
6125 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6126 cpu_gpr[rA(ctx->opcode)]);
6127 /* Note: Rc update flag set leads to undefined state of Rc0 */
6128 }
6129
6130 /* mtdcrux (PPC 460) : user-mode access to DCR */
6131 static void gen_mtdcrux(DisasContext *ctx)
6132 {
6133 /* NIP cannot be restored if the memory exception comes from an helper */
6134 gen_update_nip(ctx, ctx->nip - 4);
6135 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6136 cpu_gpr[rS(ctx->opcode)]);
6137 /* Note: Rc update flag set leads to undefined state of Rc0 */
6138 }
6139
6140 /* dccci */
6141 static void gen_dccci(DisasContext *ctx)
6142 {
6143 #if defined(CONFIG_USER_ONLY)
6144 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6145 #else
6146 if (unlikely(!ctx->mem_idx)) {
6147 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6148 return;
6149 }
6150 /* interpreted as no-op */
6151 #endif
6152 }
6153
6154 /* dcread */
6155 static void gen_dcread(DisasContext *ctx)
6156 {
6157 #if defined(CONFIG_USER_ONLY)
6158 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6159 #else
6160 TCGv EA, val;
6161 if (unlikely(!ctx->mem_idx)) {
6162 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6163 return;
6164 }
6165 gen_set_access_type(ctx, ACCESS_CACHE);
6166 EA = tcg_temp_new();
6167 gen_addr_reg_index(ctx, EA);
6168 val = tcg_temp_new();
6169 gen_qemu_ld32u(ctx, val, EA);
6170 tcg_temp_free(val);
6171 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6172 tcg_temp_free(EA);
6173 #endif
6174 }
6175
6176 /* icbt */
6177 static void gen_icbt_40x(DisasContext *ctx)
6178 {
6179 /* interpreted as no-op */
6180 /* XXX: specification say this is treated as a load by the MMU
6181 * but does not generate any exception
6182 */
6183 }
6184
6185 /* iccci */
6186 static void gen_iccci(DisasContext *ctx)
6187 {
6188 #if defined(CONFIG_USER_ONLY)
6189 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6190 #else
6191 if (unlikely(!ctx->mem_idx)) {
6192 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6193 return;
6194 }
6195 /* interpreted as no-op */
6196 #endif
6197 }
6198
6199 /* icread */
6200 static void gen_icread(DisasContext *ctx)
6201 {
6202 #if defined(CONFIG_USER_ONLY)
6203 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6204 #else
6205 if (unlikely(!ctx->mem_idx)) {
6206 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6207 return;
6208 }
6209 /* interpreted as no-op */
6210 #endif
6211 }
6212
6213 /* rfci (mem_idx only) */
6214 static void gen_rfci_40x(DisasContext *ctx)
6215 {
6216 #if defined(CONFIG_USER_ONLY)
6217 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6218 #else
6219 if (unlikely(!ctx->mem_idx)) {
6220 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6221 return;
6222 }
6223 /* Restore CPU state */
6224 gen_helper_40x_rfci(cpu_env);
6225 gen_sync_exception(ctx);
6226 #endif
6227 }
6228
6229 static void gen_rfci(DisasContext *ctx)
6230 {
6231 #if defined(CONFIG_USER_ONLY)
6232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6233 #else
6234 if (unlikely(!ctx->mem_idx)) {
6235 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6236 return;
6237 }
6238 /* Restore CPU state */
6239 gen_helper_rfci(cpu_env);
6240 gen_sync_exception(ctx);
6241 #endif
6242 }
6243
6244 /* BookE specific */
6245
6246 /* XXX: not implemented on 440 ? */
6247 static void gen_rfdi(DisasContext *ctx)
6248 {
6249 #if defined(CONFIG_USER_ONLY)
6250 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6251 #else
6252 if (unlikely(!ctx->mem_idx)) {
6253 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6254 return;
6255 }
6256 /* Restore CPU state */
6257 gen_helper_rfdi(cpu_env);
6258 gen_sync_exception(ctx);
6259 #endif
6260 }
6261
6262 /* XXX: not implemented on 440 ? */
6263 static void gen_rfmci(DisasContext *ctx)
6264 {
6265 #if defined(CONFIG_USER_ONLY)
6266 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6267 #else
6268 if (unlikely(!ctx->mem_idx)) {
6269 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6270 return;
6271 }
6272 /* Restore CPU state */
6273 gen_helper_rfmci(cpu_env);
6274 gen_sync_exception(ctx);
6275 #endif
6276 }
6277
6278 /* TLB management - PowerPC 405 implementation */
6279
6280 /* tlbre */
6281 static void gen_tlbre_40x(DisasContext *ctx)
6282 {
6283 #if defined(CONFIG_USER_ONLY)
6284 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6285 #else
6286 if (unlikely(!ctx->mem_idx)) {
6287 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6288 return;
6289 }
6290 switch (rB(ctx->opcode)) {
6291 case 0:
6292 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6293 cpu_gpr[rA(ctx->opcode)]);
6294 break;
6295 case 1:
6296 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6297 cpu_gpr[rA(ctx->opcode)]);
6298 break;
6299 default:
6300 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6301 break;
6302 }
6303 #endif
6304 }
6305
6306 /* tlbsx - tlbsx. */
6307 static void gen_tlbsx_40x(DisasContext *ctx)
6308 {
6309 #if defined(CONFIG_USER_ONLY)
6310 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6311 #else
6312 TCGv t0;
6313 if (unlikely(!ctx->mem_idx)) {
6314 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6315 return;
6316 }
6317 t0 = tcg_temp_new();
6318 gen_addr_reg_index(ctx, t0);
6319 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6320 tcg_temp_free(t0);
6321 if (Rc(ctx->opcode)) {
6322 int l1 = gen_new_label();
6323 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6324 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6325 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6326 gen_set_label(l1);
6327 }
6328 #endif
6329 }
6330
6331 /* tlbwe */
6332 static void gen_tlbwe_40x(DisasContext *ctx)
6333 {
6334 #if defined(CONFIG_USER_ONLY)
6335 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6336 #else
6337 if (unlikely(!ctx->mem_idx)) {
6338 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6339 return;
6340 }
6341 switch (rB(ctx->opcode)) {
6342 case 0:
6343 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6344 cpu_gpr[rS(ctx->opcode)]);
6345 break;
6346 case 1:
6347 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6348 cpu_gpr[rS(ctx->opcode)]);
6349 break;
6350 default:
6351 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6352 break;
6353 }
6354 #endif
6355 }
6356
6357 /* TLB management - PowerPC 440 implementation */
6358
6359 /* tlbre */
6360 static void gen_tlbre_440(DisasContext *ctx)
6361 {
6362 #if defined(CONFIG_USER_ONLY)
6363 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6364 #else
6365 if (unlikely(!ctx->mem_idx)) {
6366 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6367 return;
6368 }
6369 switch (rB(ctx->opcode)) {
6370 case 0:
6371 case 1:
6372 case 2:
6373 {
6374 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6375 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6376 t0, cpu_gpr[rA(ctx->opcode)]);
6377 tcg_temp_free_i32(t0);
6378 }
6379 break;
6380 default:
6381 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6382 break;
6383 }
6384 #endif
6385 }
6386
6387 /* tlbsx - tlbsx. */
6388 static void gen_tlbsx_440(DisasContext *ctx)
6389 {
6390 #if defined(CONFIG_USER_ONLY)
6391 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6392 #else
6393 TCGv t0;
6394 if (unlikely(!ctx->mem_idx)) {
6395 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6396 return;
6397 }
6398 t0 = tcg_temp_new();
6399 gen_addr_reg_index(ctx, t0);
6400 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6401 tcg_temp_free(t0);
6402 if (Rc(ctx->opcode)) {
6403 int l1 = gen_new_label();
6404 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6405 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6406 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6407 gen_set_label(l1);
6408 }
6409 #endif
6410 }
6411
6412 /* tlbwe */
6413 static void gen_tlbwe_440(DisasContext *ctx)
6414 {
6415 #if defined(CONFIG_USER_ONLY)
6416 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6417 #else
6418 if (unlikely(!ctx->mem_idx)) {
6419 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6420 return;
6421 }
6422 switch (rB(ctx->opcode)) {
6423 case 0:
6424 case 1:
6425 case 2:
6426 {
6427 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6428 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6429 cpu_gpr[rS(ctx->opcode)]);
6430 tcg_temp_free_i32(t0);
6431 }
6432 break;
6433 default:
6434 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6435 break;
6436 }
6437 #endif
6438 }
6439
6440 /* TLB management - PowerPC BookE 2.06 implementation */
6441
6442 /* tlbre */
6443 static void gen_tlbre_booke206(DisasContext *ctx)
6444 {
6445 #if defined(CONFIG_USER_ONLY)
6446 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6447 #else
6448 if (unlikely(!ctx->mem_idx)) {
6449 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6450 return;
6451 }
6452
6453 gen_helper_booke206_tlbre(cpu_env);
6454 #endif
6455 }
6456
6457 /* tlbsx - tlbsx. */
6458 static void gen_tlbsx_booke206(DisasContext *ctx)
6459 {
6460 #if defined(CONFIG_USER_ONLY)
6461 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6462 #else
6463 TCGv t0;
6464 if (unlikely(!ctx->mem_idx)) {
6465 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6466 return;
6467 }
6468
6469 if (rA(ctx->opcode)) {
6470 t0 = tcg_temp_new();
6471 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6472 } else {
6473 t0 = tcg_const_tl(0);
6474 }
6475
6476 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6477 gen_helper_booke206_tlbsx(cpu_env, t0);
6478 tcg_temp_free(t0);
6479 #endif
6480 }
6481
6482 /* tlbwe */
6483 static void gen_tlbwe_booke206(DisasContext *ctx)
6484 {
6485 #if defined(CONFIG_USER_ONLY)
6486 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6487 #else
6488 if (unlikely(!ctx->mem_idx)) {
6489 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6490 return;
6491 }
6492 gen_update_nip(ctx, ctx->nip - 4);
6493 gen_helper_booke206_tlbwe(cpu_env);
6494 #endif
6495 }
6496
6497 static void gen_tlbivax_booke206(DisasContext *ctx)
6498 {
6499 #if defined(CONFIG_USER_ONLY)
6500 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6501 #else
6502 TCGv t0;
6503 if (unlikely(!ctx->mem_idx)) {
6504 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6505 return;
6506 }
6507
6508 t0 = tcg_temp_new();
6509 gen_addr_reg_index(ctx, t0);
6510
6511 gen_helper_booke206_tlbivax(cpu_env, t0);
6512 tcg_temp_free(t0);
6513 #endif
6514 }
6515
6516 static void gen_tlbilx_booke206(DisasContext *ctx)
6517 {
6518 #if defined(CONFIG_USER_ONLY)
6519 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6520 #else
6521 TCGv t0;
6522 if (unlikely(!ctx->mem_idx)) {
6523 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6524 return;
6525 }
6526
6527 t0 = tcg_temp_new();
6528 gen_addr_reg_index(ctx, t0);
6529
6530 switch((ctx->opcode >> 21) & 0x3) {
6531 case 0:
6532 gen_helper_booke206_tlbilx0(cpu_env, t0);
6533 break;
6534 case 1:
6535 gen_helper_booke206_tlbilx1(cpu_env, t0);
6536 break;
6537 case 3:
6538 gen_helper_booke206_tlbilx3(cpu_env, t0);
6539 break;
6540 default:
6541 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6542 break;
6543 }
6544
6545 tcg_temp_free(t0);
6546 #endif
6547 }
6548
6549
6550 /* wrtee */
6551 static void gen_wrtee(DisasContext *ctx)
6552 {
6553 #if defined(CONFIG_USER_ONLY)
6554 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6555 #else
6556 TCGv t0;
6557 if (unlikely(!ctx->mem_idx)) {
6558 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6559 return;
6560 }
6561 t0 = tcg_temp_new();
6562 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6563 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6564 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6565 tcg_temp_free(t0);
6566 /* Stop translation to have a chance to raise an exception
6567 * if we just set msr_ee to 1
6568 */
6569 gen_stop_exception(ctx);
6570 #endif
6571 }
6572
6573 /* wrteei */
6574 static void gen_wrteei(DisasContext *ctx)
6575 {
6576 #if defined(CONFIG_USER_ONLY)
6577 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6578 #else
6579 if (unlikely(!ctx->mem_idx)) {
6580 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6581 return;
6582 }
6583 if (ctx->opcode & 0x00008000) {
6584 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6585 /* Stop translation to have a chance to raise an exception */
6586 gen_stop_exception(ctx);
6587 } else {
6588 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6589 }
6590 #endif
6591 }
6592
6593 /* PowerPC 440 specific instructions */
6594
6595 /* dlmzb */
6596 static void gen_dlmzb(DisasContext *ctx)
6597 {
6598 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6599 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6600 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6601 tcg_temp_free_i32(t0);
6602 }
6603
6604 /* mbar replaces eieio on 440 */
6605 static void gen_mbar(DisasContext *ctx)
6606 {
6607 /* interpreted as no-op */
6608 }
6609
6610 /* msync replaces sync on 440 */
6611 static void gen_msync_4xx(DisasContext *ctx)
6612 {
6613 /* interpreted as no-op */
6614 }
6615
6616 /* icbt */
6617 static void gen_icbt_440(DisasContext *ctx)
6618 {
6619 /* interpreted as no-op */
6620 /* XXX: specification say this is treated as a load by the MMU
6621 * but does not generate any exception
6622 */
6623 }
6624
6625 /* Embedded.Processor Control */
6626
6627 static void gen_msgclr(DisasContext *ctx)
6628 {
6629 #if defined(CONFIG_USER_ONLY)
6630 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6631 #else
6632 if (unlikely(ctx->mem_idx == 0)) {
6633 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6634 return;
6635 }
6636
6637 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6638 #endif
6639 }
6640
6641 static void gen_msgsnd(DisasContext *ctx)
6642 {
6643 #if defined(CONFIG_USER_ONLY)
6644 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6645 #else
6646 if (unlikely(ctx->mem_idx == 0)) {
6647 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6648 return;
6649 }
6650
6651 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6652 #endif
6653 }
6654
6655 /*** Altivec vector extension ***/
6656 /* Altivec registers moves */
6657
6658 static inline TCGv_ptr gen_avr_ptr(int reg)
6659 {
6660 TCGv_ptr r = tcg_temp_new_ptr();
6661 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6662 return r;
6663 }
6664
6665 #define GEN_VR_LDX(name, opc2, opc3) \
6666 static void glue(gen_, name)(DisasContext *ctx) \
6667 { \
6668 TCGv EA; \
6669 if (unlikely(!ctx->altivec_enabled)) { \
6670 gen_exception(ctx, POWERPC_EXCP_VPU); \
6671 return; \
6672 } \
6673 gen_set_access_type(ctx, ACCESS_INT); \
6674 EA = tcg_temp_new(); \
6675 gen_addr_reg_index(ctx, EA); \
6676 tcg_gen_andi_tl(EA, EA, ~0xf); \
6677 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6678 64-bit byteswap already. */ \
6679 if (ctx->le_mode) { \
6680 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6681 tcg_gen_addi_tl(EA, EA, 8); \
6682 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6683 } else { \
6684 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6685 tcg_gen_addi_tl(EA, EA, 8); \
6686 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6687 } \
6688 tcg_temp_free(EA); \
6689 }
6690
6691 #define GEN_VR_STX(name, opc2, opc3) \
6692 static void gen_st##name(DisasContext *ctx) \
6693 { \
6694 TCGv EA; \
6695 if (unlikely(!ctx->altivec_enabled)) { \
6696 gen_exception(ctx, POWERPC_EXCP_VPU); \
6697 return; \
6698 } \
6699 gen_set_access_type(ctx, ACCESS_INT); \
6700 EA = tcg_temp_new(); \
6701 gen_addr_reg_index(ctx, EA); \
6702 tcg_gen_andi_tl(EA, EA, ~0xf); \
6703 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6704 64-bit byteswap already. */ \
6705 if (ctx->le_mode) { \
6706 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6707 tcg_gen_addi_tl(EA, EA, 8); \
6708 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6709 } else { \
6710 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6711 tcg_gen_addi_tl(EA, EA, 8); \
6712 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6713 } \
6714 tcg_temp_free(EA); \
6715 }
6716
6717 #define GEN_VR_LVE(name, opc2, opc3) \
6718 static void gen_lve##name(DisasContext *ctx) \
6719 { \
6720 TCGv EA; \
6721 TCGv_ptr rs; \
6722 if (unlikely(!ctx->altivec_enabled)) { \
6723 gen_exception(ctx, POWERPC_EXCP_VPU); \
6724 return; \
6725 } \
6726 gen_set_access_type(ctx, ACCESS_INT); \
6727 EA = tcg_temp_new(); \
6728 gen_addr_reg_index(ctx, EA); \
6729 rs = gen_avr_ptr(rS(ctx->opcode)); \
6730 gen_helper_lve##name(cpu_env, rs, EA); \
6731 tcg_temp_free(EA); \
6732 tcg_temp_free_ptr(rs); \
6733 }
6734
6735 #define GEN_VR_STVE(name, opc2, opc3) \
6736 static void gen_stve##name(DisasContext *ctx) \
6737 { \
6738 TCGv EA; \
6739 TCGv_ptr rs; \
6740 if (unlikely(!ctx->altivec_enabled)) { \
6741 gen_exception(ctx, POWERPC_EXCP_VPU); \
6742 return; \
6743 } \
6744 gen_set_access_type(ctx, ACCESS_INT); \
6745 EA = tcg_temp_new(); \
6746 gen_addr_reg_index(ctx, EA); \
6747 rs = gen_avr_ptr(rS(ctx->opcode)); \
6748 gen_helper_stve##name(cpu_env, rs, EA); \
6749 tcg_temp_free(EA); \
6750 tcg_temp_free_ptr(rs); \
6751 }
6752
6753 GEN_VR_LDX(lvx, 0x07, 0x03);
6754 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6755 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6756
6757 GEN_VR_LVE(bx, 0x07, 0x00);
6758 GEN_VR_LVE(hx, 0x07, 0x01);
6759 GEN_VR_LVE(wx, 0x07, 0x02);
6760
6761 GEN_VR_STX(svx, 0x07, 0x07);
6762 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6763 GEN_VR_STX(svxl, 0x07, 0x0F);
6764
6765 GEN_VR_STVE(bx, 0x07, 0x04);
6766 GEN_VR_STVE(hx, 0x07, 0x05);
6767 GEN_VR_STVE(wx, 0x07, 0x06);
6768
6769 static void gen_lvsl(DisasContext *ctx)
6770 {
6771 TCGv_ptr rd;
6772 TCGv EA;
6773 if (unlikely(!ctx->altivec_enabled)) {
6774 gen_exception(ctx, POWERPC_EXCP_VPU);
6775 return;
6776 }
6777 EA = tcg_temp_new();
6778 gen_addr_reg_index(ctx, EA);
6779 rd = gen_avr_ptr(rD(ctx->opcode));
6780 gen_helper_lvsl(rd, EA);
6781 tcg_temp_free(EA);
6782 tcg_temp_free_ptr(rd);
6783 }
6784
6785 static void gen_lvsr(DisasContext *ctx)
6786 {
6787 TCGv_ptr rd;
6788 TCGv EA;
6789 if (unlikely(!ctx->altivec_enabled)) {
6790 gen_exception(ctx, POWERPC_EXCP_VPU);
6791 return;
6792 }
6793 EA = tcg_temp_new();
6794 gen_addr_reg_index(ctx, EA);
6795 rd = gen_avr_ptr(rD(ctx->opcode));
6796 gen_helper_lvsr(rd, EA);
6797 tcg_temp_free(EA);
6798 tcg_temp_free_ptr(rd);
6799 }
6800
6801 static void gen_mfvscr(DisasContext *ctx)
6802 {
6803 TCGv_i32 t;
6804 if (unlikely(!ctx->altivec_enabled)) {
6805 gen_exception(ctx, POWERPC_EXCP_VPU);
6806 return;
6807 }
6808 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6809 t = tcg_temp_new_i32();
6810 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6811 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6812 tcg_temp_free_i32(t);
6813 }
6814
6815 static void gen_mtvscr(DisasContext *ctx)
6816 {
6817 TCGv_ptr p;
6818 if (unlikely(!ctx->altivec_enabled)) {
6819 gen_exception(ctx, POWERPC_EXCP_VPU);
6820 return;
6821 }
6822 p = gen_avr_ptr(rD(ctx->opcode));
6823 gen_helper_mtvscr(cpu_env, p);
6824 tcg_temp_free_ptr(p);
6825 }
6826
6827 /* Logical operations */
6828 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6829 static void glue(gen_, name)(DisasContext *ctx) \
6830 { \
6831 if (unlikely(!ctx->altivec_enabled)) { \
6832 gen_exception(ctx, POWERPC_EXCP_VPU); \
6833 return; \
6834 } \
6835 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6836 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6837 }
6838
6839 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6840 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6841 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6842 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6843 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6844 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6845 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6846 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6847
6848 #define GEN_VXFORM(name, opc2, opc3) \
6849 static void glue(gen_, name)(DisasContext *ctx) \
6850 { \
6851 TCGv_ptr ra, rb, rd; \
6852 if (unlikely(!ctx->altivec_enabled)) { \
6853 gen_exception(ctx, POWERPC_EXCP_VPU); \
6854 return; \
6855 } \
6856 ra = gen_avr_ptr(rA(ctx->opcode)); \
6857 rb = gen_avr_ptr(rB(ctx->opcode)); \
6858 rd = gen_avr_ptr(rD(ctx->opcode)); \
6859 gen_helper_##name (rd, ra, rb); \
6860 tcg_temp_free_ptr(ra); \
6861 tcg_temp_free_ptr(rb); \
6862 tcg_temp_free_ptr(rd); \
6863 }
6864
6865 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6866 static void glue(gen_, name)(DisasContext *ctx) \
6867 { \
6868 TCGv_ptr ra, rb, rd; \
6869 if (unlikely(!ctx->altivec_enabled)) { \
6870 gen_exception(ctx, POWERPC_EXCP_VPU); \
6871 return; \
6872 } \
6873 ra = gen_avr_ptr(rA(ctx->opcode)); \
6874 rb = gen_avr_ptr(rB(ctx->opcode)); \
6875 rd = gen_avr_ptr(rD(ctx->opcode)); \
6876 gen_helper_##name(cpu_env, rd, ra, rb); \
6877 tcg_temp_free_ptr(ra); \
6878 tcg_temp_free_ptr(rb); \
6879 tcg_temp_free_ptr(rd); \
6880 }
6881
6882 #define GEN_VXFORM3(name, opc2, opc3) \
6883 static void glue(gen_, name)(DisasContext *ctx) \
6884 { \
6885 TCGv_ptr ra, rb, rc, rd; \
6886 if (unlikely(!ctx->altivec_enabled)) { \
6887 gen_exception(ctx, POWERPC_EXCP_VPU); \
6888 return; \
6889 } \
6890 ra = gen_avr_ptr(rA(ctx->opcode)); \
6891 rb = gen_avr_ptr(rB(ctx->opcode)); \
6892 rc = gen_avr_ptr(rC(ctx->opcode)); \
6893 rd = gen_avr_ptr(rD(ctx->opcode)); \
6894 gen_helper_##name(rd, ra, rb, rc); \
6895 tcg_temp_free_ptr(ra); \
6896 tcg_temp_free_ptr(rb); \
6897 tcg_temp_free_ptr(rc); \
6898 tcg_temp_free_ptr(rd); \
6899 }
6900
6901 /*
6902 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6903 * an opcode bit. In general, these pairs come from different
6904 * versions of the ISA, so we must also support a pair of flags for
6905 * each instruction.
6906 */
6907 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6908 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6909 { \
6910 if ((Rc(ctx->opcode) == 0) && \
6911 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6912 gen_##name0(ctx); \
6913 } else if ((Rc(ctx->opcode) == 1) && \
6914 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6915 gen_##name1(ctx); \
6916 } else { \
6917 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
6918 } \
6919 }
6920
6921 GEN_VXFORM(vaddubm, 0, 0);
6922 GEN_VXFORM(vadduhm, 0, 1);
6923 GEN_VXFORM(vadduwm, 0, 2);
6924 GEN_VXFORM(vaddudm, 0, 3);
6925 GEN_VXFORM(vsububm, 0, 16);
6926 GEN_VXFORM(vsubuhm, 0, 17);
6927 GEN_VXFORM(vsubuwm, 0, 18);
6928 GEN_VXFORM(vsubudm, 0, 19);
6929 GEN_VXFORM(vmaxub, 1, 0);
6930 GEN_VXFORM(vmaxuh, 1, 1);
6931 GEN_VXFORM(vmaxuw, 1, 2);
6932 GEN_VXFORM(vmaxud, 1, 3);
6933 GEN_VXFORM(vmaxsb, 1, 4);
6934 GEN_VXFORM(vmaxsh, 1, 5);
6935 GEN_VXFORM(vmaxsw, 1, 6);
6936 GEN_VXFORM(vmaxsd, 1, 7);
6937 GEN_VXFORM(vminub, 1, 8);
6938 GEN_VXFORM(vminuh, 1, 9);
6939 GEN_VXFORM(vminuw, 1, 10);
6940 GEN_VXFORM(vminud, 1, 11);
6941 GEN_VXFORM(vminsb, 1, 12);
6942 GEN_VXFORM(vminsh, 1, 13);
6943 GEN_VXFORM(vminsw, 1, 14);
6944 GEN_VXFORM(vminsd, 1, 15);
6945 GEN_VXFORM(vavgub, 1, 16);
6946 GEN_VXFORM(vavguh, 1, 17);
6947 GEN_VXFORM(vavguw, 1, 18);
6948 GEN_VXFORM(vavgsb, 1, 20);
6949 GEN_VXFORM(vavgsh, 1, 21);
6950 GEN_VXFORM(vavgsw, 1, 22);
6951 GEN_VXFORM(vmrghb, 6, 0);
6952 GEN_VXFORM(vmrghh, 6, 1);
6953 GEN_VXFORM(vmrghw, 6, 2);
6954 GEN_VXFORM(vmrglb, 6, 4);
6955 GEN_VXFORM(vmrglh, 6, 5);
6956 GEN_VXFORM(vmrglw, 6, 6);
6957
6958 static void gen_vmrgew(DisasContext *ctx)
6959 {
6960 TCGv_i64 tmp;
6961 int VT, VA, VB;
6962 if (unlikely(!ctx->altivec_enabled)) {
6963 gen_exception(ctx, POWERPC_EXCP_VPU);
6964 return;
6965 }
6966 VT = rD(ctx->opcode);
6967 VA = rA(ctx->opcode);
6968 VB = rB(ctx->opcode);
6969 tmp = tcg_temp_new_i64();
6970 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
6971 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
6972 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
6973 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
6974 tcg_temp_free_i64(tmp);
6975 }
6976
6977 static void gen_vmrgow(DisasContext *ctx)
6978 {
6979 int VT, VA, VB;
6980 if (unlikely(!ctx->altivec_enabled)) {
6981 gen_exception(ctx, POWERPC_EXCP_VPU);
6982 return;
6983 }
6984 VT = rD(ctx->opcode);
6985 VA = rA(ctx->opcode);
6986 VB = rB(ctx->opcode);
6987
6988 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
6989 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
6990 }
6991
6992 GEN_VXFORM(vmuloub, 4, 0);
6993 GEN_VXFORM(vmulouh, 4, 1);
6994 GEN_VXFORM(vmulouw, 4, 2);
6995 GEN_VXFORM(vmuluwm, 4, 2);
6996 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
6997 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
6998 GEN_VXFORM(vmulosb, 4, 4);
6999 GEN_VXFORM(vmulosh, 4, 5);
7000 GEN_VXFORM(vmulosw, 4, 6);
7001 GEN_VXFORM(vmuleub, 4, 8);
7002 GEN_VXFORM(vmuleuh, 4, 9);
7003 GEN_VXFORM(vmuleuw, 4, 10);
7004 GEN_VXFORM(vmulesb, 4, 12);
7005 GEN_VXFORM(vmulesh, 4, 13);
7006 GEN_VXFORM(vmulesw, 4, 14);
7007 GEN_VXFORM(vslb, 2, 4);
7008 GEN_VXFORM(vslh, 2, 5);
7009 GEN_VXFORM(vslw, 2, 6);
7010 GEN_VXFORM(vsld, 2, 23);
7011 GEN_VXFORM(vsrb, 2, 8);
7012 GEN_VXFORM(vsrh, 2, 9);
7013 GEN_VXFORM(vsrw, 2, 10);
7014 GEN_VXFORM(vsrd, 2, 27);
7015 GEN_VXFORM(vsrab, 2, 12);
7016 GEN_VXFORM(vsrah, 2, 13);
7017 GEN_VXFORM(vsraw, 2, 14);
7018 GEN_VXFORM(vsrad, 2, 15);
7019 GEN_VXFORM(vslo, 6, 16);
7020 GEN_VXFORM(vsro, 6, 17);
7021 GEN_VXFORM(vaddcuw, 0, 6);
7022 GEN_VXFORM(vsubcuw, 0, 22);
7023 GEN_VXFORM_ENV(vaddubs, 0, 8);
7024 GEN_VXFORM_ENV(vadduhs, 0, 9);
7025 GEN_VXFORM_ENV(vadduws, 0, 10);
7026 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7027 GEN_VXFORM_ENV(vaddshs, 0, 13);
7028 GEN_VXFORM_ENV(vaddsws, 0, 14);
7029 GEN_VXFORM_ENV(vsububs, 0, 24);
7030 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7031 GEN_VXFORM_ENV(vsubuws, 0, 26);
7032 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7033 GEN_VXFORM_ENV(vsubshs, 0, 29);
7034 GEN_VXFORM_ENV(vsubsws, 0, 30);
7035 GEN_VXFORM(vadduqm, 0, 4);
7036 GEN_VXFORM(vaddcuq, 0, 5);
7037 GEN_VXFORM3(vaddeuqm, 30, 0);
7038 GEN_VXFORM3(vaddecuq, 30, 0);
7039 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7040 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7041 GEN_VXFORM(vsubuqm, 0, 20);
7042 GEN_VXFORM(vsubcuq, 0, 21);
7043 GEN_VXFORM3(vsubeuqm, 31, 0);
7044 GEN_VXFORM3(vsubecuq, 31, 0);
7045 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7046 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7047 GEN_VXFORM(vrlb, 2, 0);
7048 GEN_VXFORM(vrlh, 2, 1);
7049 GEN_VXFORM(vrlw, 2, 2);
7050 GEN_VXFORM(vrld, 2, 3);
7051 GEN_VXFORM(vsl, 2, 7);
7052 GEN_VXFORM(vsr, 2, 11);
7053 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7054 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7055 GEN_VXFORM_ENV(vpkudum, 7, 17);
7056 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7057 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7058 GEN_VXFORM_ENV(vpkudus, 7, 19);
7059 GEN_VXFORM_ENV(vpkshus, 7, 4);
7060 GEN_VXFORM_ENV(vpkswus, 7, 5);
7061 GEN_VXFORM_ENV(vpksdus, 7, 21);
7062 GEN_VXFORM_ENV(vpkshss, 7, 6);
7063 GEN_VXFORM_ENV(vpkswss, 7, 7);
7064 GEN_VXFORM_ENV(vpksdss, 7, 23);
7065 GEN_VXFORM(vpkpx, 7, 12);
7066 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7067 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7068 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7069 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7070 GEN_VXFORM_ENV(vsumsws, 4, 30);
7071 GEN_VXFORM_ENV(vaddfp, 5, 0);
7072 GEN_VXFORM_ENV(vsubfp, 5, 1);
7073 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7074 GEN_VXFORM_ENV(vminfp, 5, 17);
7075
7076 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7077 static void glue(gen_, name)(DisasContext *ctx) \
7078 { \
7079 TCGv_ptr ra, rb, rd; \
7080 if (unlikely(!ctx->altivec_enabled)) { \
7081 gen_exception(ctx, POWERPC_EXCP_VPU); \
7082 return; \
7083 } \
7084 ra = gen_avr_ptr(rA(ctx->opcode)); \
7085 rb = gen_avr_ptr(rB(ctx->opcode)); \
7086 rd = gen_avr_ptr(rD(ctx->opcode)); \
7087 gen_helper_##opname(cpu_env, rd, ra, rb); \
7088 tcg_temp_free_ptr(ra); \
7089 tcg_temp_free_ptr(rb); \
7090 tcg_temp_free_ptr(rd); \
7091 }
7092
7093 #define GEN_VXRFORM(name, opc2, opc3) \
7094 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7095 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7096
7097 /*
7098 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7099 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7100 * come from different versions of the ISA, so we must also support a
7101 * pair of flags for each instruction.
7102 */
7103 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7104 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7105 { \
7106 if ((Rc(ctx->opcode) == 0) && \
7107 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7108 if (Rc21(ctx->opcode) == 0) { \
7109 gen_##name0(ctx); \
7110 } else { \
7111 gen_##name0##_(ctx); \
7112 } \
7113 } else if ((Rc(ctx->opcode) == 1) && \
7114 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7115 if (Rc21(ctx->opcode) == 0) { \
7116 gen_##name1(ctx); \
7117 } else { \
7118 gen_##name1##_(ctx); \
7119 } \
7120 } else { \
7121 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7122 } \
7123 }
7124
7125 GEN_VXRFORM(vcmpequb, 3, 0)
7126 GEN_VXRFORM(vcmpequh, 3, 1)
7127 GEN_VXRFORM(vcmpequw, 3, 2)
7128 GEN_VXRFORM(vcmpequd, 3, 3)
7129 GEN_VXRFORM(vcmpgtsb, 3, 12)
7130 GEN_VXRFORM(vcmpgtsh, 3, 13)
7131 GEN_VXRFORM(vcmpgtsw, 3, 14)
7132 GEN_VXRFORM(vcmpgtsd, 3, 15)
7133 GEN_VXRFORM(vcmpgtub, 3, 8)
7134 GEN_VXRFORM(vcmpgtuh, 3, 9)
7135 GEN_VXRFORM(vcmpgtuw, 3, 10)
7136 GEN_VXRFORM(vcmpgtud, 3, 11)
7137 GEN_VXRFORM(vcmpeqfp, 3, 3)
7138 GEN_VXRFORM(vcmpgefp, 3, 7)
7139 GEN_VXRFORM(vcmpgtfp, 3, 11)
7140 GEN_VXRFORM(vcmpbfp, 3, 15)
7141
7142 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7143 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7144 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7145 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7146 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7147 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7148
7149 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7150 static void glue(gen_, name)(DisasContext *ctx) \
7151 { \
7152 TCGv_ptr rd; \
7153 TCGv_i32 simm; \
7154 if (unlikely(!ctx->altivec_enabled)) { \
7155 gen_exception(ctx, POWERPC_EXCP_VPU); \
7156 return; \
7157 } \
7158 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7159 rd = gen_avr_ptr(rD(ctx->opcode)); \
7160 gen_helper_##name (rd, simm); \
7161 tcg_temp_free_i32(simm); \
7162 tcg_temp_free_ptr(rd); \
7163 }
7164
7165 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7166 GEN_VXFORM_SIMM(vspltish, 6, 13);
7167 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7168
7169 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7170 static void glue(gen_, name)(DisasContext *ctx) \
7171 { \
7172 TCGv_ptr rb, rd; \
7173 if (unlikely(!ctx->altivec_enabled)) { \
7174 gen_exception(ctx, POWERPC_EXCP_VPU); \
7175 return; \
7176 } \
7177 rb = gen_avr_ptr(rB(ctx->opcode)); \
7178 rd = gen_avr_ptr(rD(ctx->opcode)); \
7179 gen_helper_##name (rd, rb); \
7180 tcg_temp_free_ptr(rb); \
7181 tcg_temp_free_ptr(rd); \
7182 }
7183
7184 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7185 static void glue(gen_, name)(DisasContext *ctx) \
7186 { \
7187 TCGv_ptr rb, rd; \
7188 \
7189 if (unlikely(!ctx->altivec_enabled)) { \
7190 gen_exception(ctx, POWERPC_EXCP_VPU); \
7191 return; \
7192 } \
7193 rb = gen_avr_ptr(rB(ctx->opcode)); \
7194 rd = gen_avr_ptr(rD(ctx->opcode)); \
7195 gen_helper_##name(cpu_env, rd, rb); \
7196 tcg_temp_free_ptr(rb); \
7197 tcg_temp_free_ptr(rd); \
7198 }
7199
7200 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7201 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7202 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7203 GEN_VXFORM_NOA(vupklsb, 7, 10);
7204 GEN_VXFORM_NOA(vupklsh, 7, 11);
7205 GEN_VXFORM_NOA(vupklsw, 7, 27);
7206 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7207 GEN_VXFORM_NOA(vupklpx, 7, 15);
7208 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7209 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7210 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7211 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7212 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
7213 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
7214 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7215 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
7216
7217 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7218 static void glue(gen_, name)(DisasContext *ctx) \
7219 { \
7220 TCGv_ptr rd; \
7221 TCGv_i32 simm; \
7222 if (unlikely(!ctx->altivec_enabled)) { \
7223 gen_exception(ctx, POWERPC_EXCP_VPU); \
7224 return; \
7225 } \
7226 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7227 rd = gen_avr_ptr(rD(ctx->opcode)); \
7228 gen_helper_##name (rd, simm); \
7229 tcg_temp_free_i32(simm); \
7230 tcg_temp_free_ptr(rd); \
7231 }
7232
7233 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7234 static void glue(gen_, name)(DisasContext *ctx) \
7235 { \
7236 TCGv_ptr rb, rd; \
7237 TCGv_i32 uimm; \
7238 if (unlikely(!ctx->altivec_enabled)) { \
7239 gen_exception(ctx, POWERPC_EXCP_VPU); \
7240 return; \
7241 } \
7242 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7243 rb = gen_avr_ptr(rB(ctx->opcode)); \
7244 rd = gen_avr_ptr(rD(ctx->opcode)); \
7245 gen_helper_##name (rd, rb, uimm); \
7246 tcg_temp_free_i32(uimm); \
7247 tcg_temp_free_ptr(rb); \
7248 tcg_temp_free_ptr(rd); \
7249 }
7250
7251 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7252 static void glue(gen_, name)(DisasContext *ctx) \
7253 { \
7254 TCGv_ptr rb, rd; \
7255 TCGv_i32 uimm; \
7256 \
7257 if (unlikely(!ctx->altivec_enabled)) { \
7258 gen_exception(ctx, POWERPC_EXCP_VPU); \
7259 return; \
7260 } \
7261 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7262 rb = gen_avr_ptr(rB(ctx->opcode)); \
7263 rd = gen_avr_ptr(rD(ctx->opcode)); \
7264 gen_helper_##name(cpu_env, rd, rb, uimm); \
7265 tcg_temp_free_i32(uimm); \
7266 tcg_temp_free_ptr(rb); \
7267 tcg_temp_free_ptr(rd); \
7268 }
7269
7270 GEN_VXFORM_UIMM(vspltb, 6, 8);
7271 GEN_VXFORM_UIMM(vsplth, 6, 9);
7272 GEN_VXFORM_UIMM(vspltw, 6, 10);
7273 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7274 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7275 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7276 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7277
7278 static void gen_vsldoi(DisasContext *ctx)
7279 {
7280 TCGv_ptr ra, rb, rd;
7281 TCGv_i32 sh;
7282 if (unlikely(!ctx->altivec_enabled)) {
7283 gen_exception(ctx, POWERPC_EXCP_VPU);
7284 return;
7285 }
7286 ra = gen_avr_ptr(rA(ctx->opcode));
7287 rb = gen_avr_ptr(rB(ctx->opcode));
7288 rd = gen_avr_ptr(rD(ctx->opcode));
7289 sh = tcg_const_i32(VSH(ctx->opcode));
7290 gen_helper_vsldoi (rd, ra, rb, sh);
7291 tcg_temp_free_ptr(ra);
7292 tcg_temp_free_ptr(rb);
7293 tcg_temp_free_ptr(rd);
7294 tcg_temp_free_i32(sh);
7295 }
7296
7297 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7298 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7299 { \
7300 TCGv_ptr ra, rb, rc, rd; \
7301 if (unlikely(!ctx->altivec_enabled)) { \
7302 gen_exception(ctx, POWERPC_EXCP_VPU); \
7303 return; \
7304 } \
7305 ra = gen_avr_ptr(rA(ctx->opcode)); \
7306 rb = gen_avr_ptr(rB(ctx->opcode)); \
7307 rc = gen_avr_ptr(rC(ctx->opcode)); \
7308 rd = gen_avr_ptr(rD(ctx->opcode)); \
7309 if (Rc(ctx->opcode)) { \
7310 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7311 } else { \
7312 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7313 } \
7314 tcg_temp_free_ptr(ra); \
7315 tcg_temp_free_ptr(rb); \
7316 tcg_temp_free_ptr(rc); \
7317 tcg_temp_free_ptr(rd); \
7318 }
7319
7320 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7321
7322 static void gen_vmladduhm(DisasContext *ctx)
7323 {
7324 TCGv_ptr ra, rb, rc, rd;
7325 if (unlikely(!ctx->altivec_enabled)) {
7326 gen_exception(ctx, POWERPC_EXCP_VPU);
7327 return;
7328 }
7329 ra = gen_avr_ptr(rA(ctx->opcode));
7330 rb = gen_avr_ptr(rB(ctx->opcode));
7331 rc = gen_avr_ptr(rC(ctx->opcode));
7332 rd = gen_avr_ptr(rD(ctx->opcode));
7333 gen_helper_vmladduhm(rd, ra, rb, rc);
7334 tcg_temp_free_ptr(ra);
7335 tcg_temp_free_ptr(rb);
7336 tcg_temp_free_ptr(rc);
7337 tcg_temp_free_ptr(rd);
7338 }
7339
7340 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7341 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7342 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7343 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7344 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7345
7346 GEN_VXFORM_NOA(vclzb, 1, 28)
7347 GEN_VXFORM_NOA(vclzh, 1, 29)
7348 GEN_VXFORM_NOA(vclzw, 1, 30)
7349 GEN_VXFORM_NOA(vclzd, 1, 31)
7350 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7351 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7352 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7353 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7354 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7355 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7356 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7357 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7358 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7359 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7360 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7361 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7362 GEN_VXFORM(vbpermq, 6, 21);
7363 GEN_VXFORM_NOA(vgbbd, 6, 20);
7364 GEN_VXFORM(vpmsumb, 4, 16)
7365 GEN_VXFORM(vpmsumh, 4, 17)
7366 GEN_VXFORM(vpmsumw, 4, 18)
7367 GEN_VXFORM(vpmsumd, 4, 19)
7368
7369 #define GEN_BCD(op) \
7370 static void gen_##op(DisasContext *ctx) \
7371 { \
7372 TCGv_ptr ra, rb, rd; \
7373 TCGv_i32 ps; \
7374 \
7375 if (unlikely(!ctx->altivec_enabled)) { \
7376 gen_exception(ctx, POWERPC_EXCP_VPU); \
7377 return; \
7378 } \
7379 \
7380 ra = gen_avr_ptr(rA(ctx->opcode)); \
7381 rb = gen_avr_ptr(rB(ctx->opcode)); \
7382 rd = gen_avr_ptr(rD(ctx->opcode)); \
7383 \
7384 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7385 \
7386 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7387 \
7388 tcg_temp_free_ptr(ra); \
7389 tcg_temp_free_ptr(rb); \
7390 tcg_temp_free_ptr(rd); \
7391 tcg_temp_free_i32(ps); \
7392 }
7393
7394 GEN_BCD(bcdadd)
7395 GEN_BCD(bcdsub)
7396
7397 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7398 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7399 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7400 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7401 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7402 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7403 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7404 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7405
7406 static void gen_vsbox(DisasContext *ctx)
7407 {
7408 TCGv_ptr ra, rd;
7409 if (unlikely(!ctx->altivec_enabled)) {
7410 gen_exception(ctx, POWERPC_EXCP_VPU);
7411 return;
7412 }
7413 ra = gen_avr_ptr(rA(ctx->opcode));
7414 rd = gen_avr_ptr(rD(ctx->opcode));
7415 gen_helper_vsbox(rd, ra);
7416 tcg_temp_free_ptr(ra);
7417 tcg_temp_free_ptr(rd);
7418 }
7419
7420 GEN_VXFORM(vcipher, 4, 20)
7421 GEN_VXFORM(vcipherlast, 4, 20)
7422 GEN_VXFORM(vncipher, 4, 21)
7423 GEN_VXFORM(vncipherlast, 4, 21)
7424
7425 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7426 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7427 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7428 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7429
7430 #define VSHASIGMA(op) \
7431 static void gen_##op(DisasContext *ctx) \
7432 { \
7433 TCGv_ptr ra, rd; \
7434 TCGv_i32 st_six; \
7435 if (unlikely(!ctx->altivec_enabled)) { \
7436 gen_exception(ctx, POWERPC_EXCP_VPU); \
7437 return; \
7438 } \
7439 ra = gen_avr_ptr(rA(ctx->opcode)); \
7440 rd = gen_avr_ptr(rD(ctx->opcode)); \
7441 st_six = tcg_const_i32(rB(ctx->opcode)); \
7442 gen_helper_##op(rd, ra, st_six); \
7443 tcg_temp_free_ptr(ra); \
7444 tcg_temp_free_ptr(rd); \
7445 tcg_temp_free_i32(st_six); \
7446 }
7447
7448 VSHASIGMA(vshasigmaw)
7449 VSHASIGMA(vshasigmad)
7450
7451 GEN_VXFORM3(vpermxor, 22, 0xFF)
7452 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7453 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7454
7455 /*** VSX extension ***/
7456
7457 static inline TCGv_i64 cpu_vsrh(int n)
7458 {
7459 if (n < 32) {
7460 return cpu_fpr[n];
7461 } else {
7462 return cpu_avrh[n-32];
7463 }
7464 }
7465
7466 static inline TCGv_i64 cpu_vsrl(int n)
7467 {
7468 if (n < 32) {
7469 return cpu_vsr[n];
7470 } else {
7471 return cpu_avrl[n-32];
7472 }
7473 }
7474
7475 #define VSX_LOAD_SCALAR(name, operation) \
7476 static void gen_##name(DisasContext *ctx) \
7477 { \
7478 TCGv EA; \
7479 if (unlikely(!ctx->vsx_enabled)) { \
7480 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7481 return; \
7482 } \
7483 gen_set_access_type(ctx, ACCESS_INT); \
7484 EA = tcg_temp_new(); \
7485 gen_addr_reg_index(ctx, EA); \
7486 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7487 /* NOTE: cpu_vsrl is undefined */ \
7488 tcg_temp_free(EA); \
7489 }
7490
7491 VSX_LOAD_SCALAR(lxsdx, ld64)
7492 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7493 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7494 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7495
7496 static void gen_lxvd2x(DisasContext *ctx)
7497 {
7498 TCGv EA;
7499 if (unlikely(!ctx->vsx_enabled)) {
7500 gen_exception(ctx, POWERPC_EXCP_VSXU);
7501 return;
7502 }
7503 gen_set_access_type(ctx, ACCESS_INT);
7504 EA = tcg_temp_new();
7505 gen_addr_reg_index(ctx, EA);
7506 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7507 tcg_gen_addi_tl(EA, EA, 8);
7508 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7509 tcg_temp_free(EA);
7510 }
7511
7512 static void gen_lxvdsx(DisasContext *ctx)
7513 {
7514 TCGv EA;
7515 if (unlikely(!ctx->vsx_enabled)) {
7516 gen_exception(ctx, POWERPC_EXCP_VSXU);
7517 return;
7518 }
7519 gen_set_access_type(ctx, ACCESS_INT);
7520 EA = tcg_temp_new();
7521 gen_addr_reg_index(ctx, EA);
7522 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7523 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7524 tcg_temp_free(EA);
7525 }
7526
7527 static void gen_lxvw4x(DisasContext *ctx)
7528 {
7529 TCGv EA;
7530 TCGv_i64 tmp;
7531 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7532 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7533 if (unlikely(!ctx->vsx_enabled)) {
7534 gen_exception(ctx, POWERPC_EXCP_VSXU);
7535 return;
7536 }
7537 gen_set_access_type(ctx, ACCESS_INT);
7538 EA = tcg_temp_new();
7539 tmp = tcg_temp_new_i64();
7540
7541 gen_addr_reg_index(ctx, EA);
7542 gen_qemu_ld32u_i64(ctx, tmp, EA);
7543 tcg_gen_addi_tl(EA, EA, 4);
7544 gen_qemu_ld32u_i64(ctx, xth, EA);
7545 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7546
7547 tcg_gen_addi_tl(EA, EA, 4);
7548 gen_qemu_ld32u_i64(ctx, tmp, EA);
7549 tcg_gen_addi_tl(EA, EA, 4);
7550 gen_qemu_ld32u_i64(ctx, xtl, EA);
7551 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7552
7553 tcg_temp_free(EA);
7554 tcg_temp_free_i64(tmp);
7555 }
7556
7557 #define VSX_STORE_SCALAR(name, operation) \
7558 static void gen_##name(DisasContext *ctx) \
7559 { \
7560 TCGv EA; \
7561 if (unlikely(!ctx->vsx_enabled)) { \
7562 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7563 return; \
7564 } \
7565 gen_set_access_type(ctx, ACCESS_INT); \
7566 EA = tcg_temp_new(); \
7567 gen_addr_reg_index(ctx, EA); \
7568 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7569 tcg_temp_free(EA); \
7570 }
7571
7572 VSX_STORE_SCALAR(stxsdx, st64)
7573 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7574 VSX_STORE_SCALAR(stxsspx, st32fs)
7575
7576 static void gen_stxvd2x(DisasContext *ctx)
7577 {
7578 TCGv EA;
7579 if (unlikely(!ctx->vsx_enabled)) {
7580 gen_exception(ctx, POWERPC_EXCP_VSXU);
7581 return;
7582 }
7583 gen_set_access_type(ctx, ACCESS_INT);
7584 EA = tcg_temp_new();
7585 gen_addr_reg_index(ctx, EA);
7586 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7587 tcg_gen_addi_tl(EA, EA, 8);
7588 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7589 tcg_temp_free(EA);
7590 }
7591
7592 static void gen_stxvw4x(DisasContext *ctx)
7593 {
7594 TCGv_i64 tmp;
7595 TCGv EA;
7596 if (unlikely(!ctx->vsx_enabled)) {
7597 gen_exception(ctx, POWERPC_EXCP_VSXU);
7598 return;
7599 }
7600 gen_set_access_type(ctx, ACCESS_INT);
7601 EA = tcg_temp_new();
7602 gen_addr_reg_index(ctx, EA);
7603 tmp = tcg_temp_new_i64();
7604
7605 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7606 gen_qemu_st32_i64(ctx, tmp, EA);
7607 tcg_gen_addi_tl(EA, EA, 4);
7608 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7609
7610 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7611 tcg_gen_addi_tl(EA, EA, 4);
7612 gen_qemu_st32_i64(ctx, tmp, EA);
7613 tcg_gen_addi_tl(EA, EA, 4);
7614 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7615
7616 tcg_temp_free(EA);
7617 tcg_temp_free_i64(tmp);
7618 }
7619
7620 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7621 static void gen_##name(DisasContext *ctx) \
7622 { \
7623 if (xS(ctx->opcode) < 32) { \
7624 if (unlikely(!ctx->fpu_enabled)) { \
7625 gen_exception(ctx, POWERPC_EXCP_FPU); \
7626 return; \
7627 } \
7628 } else { \
7629 if (unlikely(!ctx->altivec_enabled)) { \
7630 gen_exception(ctx, POWERPC_EXCP_VPU); \
7631 return; \
7632 } \
7633 } \
7634 TCGv_i64 tmp = tcg_temp_new_i64(); \
7635 tcg_gen_##tcgop1(tmp, source); \
7636 tcg_gen_##tcgop2(target, tmp); \
7637 tcg_temp_free_i64(tmp); \
7638 }
7639
7640
7641 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7642 cpu_vsrh(xS(ctx->opcode)))
7643 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7644 cpu_gpr[rA(ctx->opcode)])
7645 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7646 cpu_gpr[rA(ctx->opcode)])
7647
7648 #if defined(TARGET_PPC64)
7649 #define MV_VSRD(name, target, source) \
7650 static void gen_##name(DisasContext *ctx) \
7651 { \
7652 if (xS(ctx->opcode) < 32) { \
7653 if (unlikely(!ctx->fpu_enabled)) { \
7654 gen_exception(ctx, POWERPC_EXCP_FPU); \
7655 return; \
7656 } \
7657 } else { \
7658 if (unlikely(!ctx->altivec_enabled)) { \
7659 gen_exception(ctx, POWERPC_EXCP_VPU); \
7660 return; \
7661 } \
7662 } \
7663 tcg_gen_mov_i64(target, source); \
7664 }
7665
7666 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7667 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7668
7669 #endif
7670
7671 static void gen_xxpermdi(DisasContext *ctx)
7672 {
7673 if (unlikely(!ctx->vsx_enabled)) {
7674 gen_exception(ctx, POWERPC_EXCP_VSXU);
7675 return;
7676 }
7677
7678 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7679 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7680 TCGv_i64 xh, xl;
7681
7682 xh = tcg_temp_new_i64();
7683 xl = tcg_temp_new_i64();
7684
7685 if ((DM(ctx->opcode) & 2) == 0) {
7686 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7687 } else {
7688 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7689 }
7690 if ((DM(ctx->opcode) & 1) == 0) {
7691 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7692 } else {
7693 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7694 }
7695
7696 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7697 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7698
7699 tcg_temp_free_i64(xh);
7700 tcg_temp_free_i64(xl);
7701 } else {
7702 if ((DM(ctx->opcode) & 2) == 0) {
7703 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7704 } else {
7705 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7706 }
7707 if ((DM(ctx->opcode) & 1) == 0) {
7708 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7709 } else {
7710 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7711 }
7712 }
7713 }
7714
7715 #define OP_ABS 1
7716 #define OP_NABS 2
7717 #define OP_NEG 3
7718 #define OP_CPSGN 4
7719 #define SGN_MASK_DP 0x8000000000000000ull
7720 #define SGN_MASK_SP 0x8000000080000000ull
7721
7722 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7723 static void glue(gen_, name)(DisasContext * ctx) \
7724 { \
7725 TCGv_i64 xb, sgm; \
7726 if (unlikely(!ctx->vsx_enabled)) { \
7727 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7728 return; \
7729 } \
7730 xb = tcg_temp_new_i64(); \
7731 sgm = tcg_temp_new_i64(); \
7732 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7733 tcg_gen_movi_i64(sgm, sgn_mask); \
7734 switch (op) { \
7735 case OP_ABS: { \
7736 tcg_gen_andc_i64(xb, xb, sgm); \
7737 break; \
7738 } \
7739 case OP_NABS: { \
7740 tcg_gen_or_i64(xb, xb, sgm); \
7741 break; \
7742 } \
7743 case OP_NEG: { \
7744 tcg_gen_xor_i64(xb, xb, sgm); \
7745 break; \
7746 } \
7747 case OP_CPSGN: { \
7748 TCGv_i64 xa = tcg_temp_new_i64(); \
7749 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7750 tcg_gen_and_i64(xa, xa, sgm); \
7751 tcg_gen_andc_i64(xb, xb, sgm); \
7752 tcg_gen_or_i64(xb, xb, xa); \
7753 tcg_temp_free_i64(xa); \
7754 break; \
7755 } \
7756 } \
7757 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7758 tcg_temp_free_i64(xb); \
7759 tcg_temp_free_i64(sgm); \
7760 }
7761
7762 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7763 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7764 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7765 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7766
7767 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7768 static void glue(gen_, name)(DisasContext * ctx) \
7769 { \
7770 TCGv_i64 xbh, xbl, sgm; \
7771 if (unlikely(!ctx->vsx_enabled)) { \
7772 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7773 return; \
7774 } \
7775 xbh = tcg_temp_new_i64(); \
7776 xbl = tcg_temp_new_i64(); \
7777 sgm = tcg_temp_new_i64(); \
7778 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7779 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7780 tcg_gen_movi_i64(sgm, sgn_mask); \
7781 switch (op) { \
7782 case OP_ABS: { \
7783 tcg_gen_andc_i64(xbh, xbh, sgm); \
7784 tcg_gen_andc_i64(xbl, xbl, sgm); \
7785 break; \
7786 } \
7787 case OP_NABS: { \
7788 tcg_gen_or_i64(xbh, xbh, sgm); \
7789 tcg_gen_or_i64(xbl, xbl, sgm); \
7790 break; \
7791 } \
7792 case OP_NEG: { \
7793 tcg_gen_xor_i64(xbh, xbh, sgm); \
7794 tcg_gen_xor_i64(xbl, xbl, sgm); \
7795 break; \
7796 } \
7797 case OP_CPSGN: { \
7798 TCGv_i64 xah = tcg_temp_new_i64(); \
7799 TCGv_i64 xal = tcg_temp_new_i64(); \
7800 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7801 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7802 tcg_gen_and_i64(xah, xah, sgm); \
7803 tcg_gen_and_i64(xal, xal, sgm); \
7804 tcg_gen_andc_i64(xbh, xbh, sgm); \
7805 tcg_gen_andc_i64(xbl, xbl, sgm); \
7806 tcg_gen_or_i64(xbh, xbh, xah); \
7807 tcg_gen_or_i64(xbl, xbl, xal); \
7808 tcg_temp_free_i64(xah); \
7809 tcg_temp_free_i64(xal); \
7810 break; \
7811 } \
7812 } \
7813 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7814 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7815 tcg_temp_free_i64(xbh); \
7816 tcg_temp_free_i64(xbl); \
7817 tcg_temp_free_i64(sgm); \
7818 }
7819
7820 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7821 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7822 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7823 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7824 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7825 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7826 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7827 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7828
7829 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7830 static void gen_##name(DisasContext * ctx) \
7831 { \
7832 TCGv_i32 opc; \
7833 if (unlikely(!ctx->vsx_enabled)) { \
7834 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7835 return; \
7836 } \
7837 /* NIP cannot be restored if the memory exception comes from an helper */ \
7838 gen_update_nip(ctx, ctx->nip - 4); \
7839 opc = tcg_const_i32(ctx->opcode); \
7840 gen_helper_##name(cpu_env, opc); \
7841 tcg_temp_free_i32(opc); \
7842 }
7843
7844 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7845 static void gen_##name(DisasContext * ctx) \
7846 { \
7847 if (unlikely(!ctx->vsx_enabled)) { \
7848 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7849 return; \
7850 } \
7851 /* NIP cannot be restored if the exception comes */ \
7852 /* from a helper. */ \
7853 gen_update_nip(ctx, ctx->nip - 4); \
7854 \
7855 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7856 cpu_vsrh(xB(ctx->opcode))); \
7857 }
7858
7859 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7860 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7861 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7862 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7863 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7864 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7865 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7866 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7867 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7868 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7869 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7870 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7871 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7872 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7873 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7874 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7875 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7876 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7877 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7878 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7879 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7880 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7881 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7882 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7883 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7884 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7885 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7886 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7887 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7888 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7889 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7890 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7891 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7892 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7893 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7894 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7895 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7896
7897 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7898 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7899 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7900 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7901 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7902 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7903 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7904 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7905 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7906 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7907 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7908 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7909 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7910 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7911 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
7912 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7913 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
7914
7915 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7916 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7917 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7918 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
7919 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
7920 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
7921 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
7922 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
7923 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
7924 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
7925 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
7926 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
7927 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
7928 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
7929 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
7930 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
7931 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
7932 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
7933 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
7934 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
7935 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
7936 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
7937 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
7938 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
7939 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
7940 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
7941 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
7942 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
7943 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
7944 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
7945 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
7946 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
7947 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
7948 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
7949 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
7950 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
7951
7952 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
7953 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
7954 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
7955 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
7956 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
7957 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
7958 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
7959 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
7960 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
7961 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
7962 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
7963 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
7964 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
7965 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
7966 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
7967 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
7968 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
7969 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
7970 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
7971 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
7972 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
7973 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
7974 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
7975 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
7976 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
7977 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
7978 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
7979 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
7980 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
7981 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
7982 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
7983 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
7984 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
7985 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
7986 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
7987 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
7988
7989 #define VSX_LOGICAL(name, tcg_op) \
7990 static void glue(gen_, name)(DisasContext * ctx) \
7991 { \
7992 if (unlikely(!ctx->vsx_enabled)) { \
7993 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7994 return; \
7995 } \
7996 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
7997 cpu_vsrh(xB(ctx->opcode))); \
7998 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
7999 cpu_vsrl(xB(ctx->opcode))); \
8000 }
8001
8002 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8003 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8004 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8005 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8006 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8007 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8008 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8009 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8010
8011 #define VSX_XXMRG(name, high) \
8012 static void glue(gen_, name)(DisasContext * ctx) \
8013 { \
8014 TCGv_i64 a0, a1, b0, b1; \
8015 if (unlikely(!ctx->vsx_enabled)) { \
8016 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8017 return; \
8018 } \
8019 a0 = tcg_temp_new_i64(); \
8020 a1 = tcg_temp_new_i64(); \
8021 b0 = tcg_temp_new_i64(); \
8022 b1 = tcg_temp_new_i64(); \
8023 if (high) { \
8024 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8025 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8026 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8027 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8028 } else { \
8029 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8030 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8031 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8032 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8033 } \
8034 tcg_gen_shri_i64(a0, a0, 32); \
8035 tcg_gen_shri_i64(b0, b0, 32); \
8036 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8037 b0, a0, 32, 32); \
8038 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8039 b1, a1, 32, 32); \
8040 tcg_temp_free_i64(a0); \
8041 tcg_temp_free_i64(a1); \
8042 tcg_temp_free_i64(b0); \
8043 tcg_temp_free_i64(b1); \
8044 }
8045
8046 VSX_XXMRG(xxmrghw, 1)
8047 VSX_XXMRG(xxmrglw, 0)
8048
8049 static void gen_xxsel(DisasContext * ctx)
8050 {
8051 TCGv_i64 a, b, c;
8052 if (unlikely(!ctx->vsx_enabled)) {
8053 gen_exception(ctx, POWERPC_EXCP_VSXU);
8054 return;
8055 }
8056 a = tcg_temp_new_i64();
8057 b = tcg_temp_new_i64();
8058 c = tcg_temp_new_i64();
8059
8060 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8061 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8062 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8063
8064 tcg_gen_and_i64(b, b, c);
8065 tcg_gen_andc_i64(a, a, c);
8066 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8067
8068 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8069 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8070 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8071
8072 tcg_gen_and_i64(b, b, c);
8073 tcg_gen_andc_i64(a, a, c);
8074 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8075
8076 tcg_temp_free_i64(a);
8077 tcg_temp_free_i64(b);
8078 tcg_temp_free_i64(c);
8079 }
8080
8081 static void gen_xxspltw(DisasContext *ctx)
8082 {
8083 TCGv_i64 b, b2;
8084 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8085 cpu_vsrl(xB(ctx->opcode)) :
8086 cpu_vsrh(xB(ctx->opcode));
8087
8088 if (unlikely(!ctx->vsx_enabled)) {
8089 gen_exception(ctx, POWERPC_EXCP_VSXU);
8090 return;
8091 }
8092
8093 b = tcg_temp_new_i64();
8094 b2 = tcg_temp_new_i64();
8095
8096 if (UIM(ctx->opcode) & 1) {
8097 tcg_gen_ext32u_i64(b, vsr);
8098 } else {
8099 tcg_gen_shri_i64(b, vsr, 32);
8100 }
8101
8102 tcg_gen_shli_i64(b2, b, 32);
8103 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8104 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8105
8106 tcg_temp_free_i64(b);
8107 tcg_temp_free_i64(b2);
8108 }
8109
8110 static void gen_xxsldwi(DisasContext *ctx)
8111 {
8112 TCGv_i64 xth, xtl;
8113 if (unlikely(!ctx->vsx_enabled)) {
8114 gen_exception(ctx, POWERPC_EXCP_VSXU);
8115 return;
8116 }
8117 xth = tcg_temp_new_i64();
8118 xtl = tcg_temp_new_i64();
8119
8120 switch (SHW(ctx->opcode)) {
8121 case 0: {
8122 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8123 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8124 break;
8125 }
8126 case 1: {
8127 TCGv_i64 t0 = tcg_temp_new_i64();
8128 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8129 tcg_gen_shli_i64(xth, xth, 32);
8130 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8131 tcg_gen_shri_i64(t0, t0, 32);
8132 tcg_gen_or_i64(xth, xth, t0);
8133 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8134 tcg_gen_shli_i64(xtl, xtl, 32);
8135 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8136 tcg_gen_shri_i64(t0, t0, 32);
8137 tcg_gen_or_i64(xtl, xtl, t0);
8138 tcg_temp_free_i64(t0);
8139 break;
8140 }
8141 case 2: {
8142 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8143 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8144 break;
8145 }
8146 case 3: {
8147 TCGv_i64 t0 = tcg_temp_new_i64();
8148 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8149 tcg_gen_shli_i64(xth, xth, 32);
8150 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8151 tcg_gen_shri_i64(t0, t0, 32);
8152 tcg_gen_or_i64(xth, xth, t0);
8153 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8154 tcg_gen_shli_i64(xtl, xtl, 32);
8155 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8156 tcg_gen_shri_i64(t0, t0, 32);
8157 tcg_gen_or_i64(xtl, xtl, t0);
8158 tcg_temp_free_i64(t0);
8159 break;
8160 }
8161 }
8162
8163 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8164 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8165
8166 tcg_temp_free_i64(xth);
8167 tcg_temp_free_i64(xtl);
8168 }
8169
8170 /*** Decimal Floating Point ***/
8171
8172 static inline TCGv_ptr gen_fprp_ptr(int reg)
8173 {
8174 TCGv_ptr r = tcg_temp_new_ptr();
8175 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8176 return r;
8177 }
8178
8179 #if defined(TARGET_PPC64)
8180 static void gen_set_cr6_from_fpscr(DisasContext *ctx)
8181 {
8182 TCGv_i32 tmp = tcg_temp_new_i32();
8183 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
8184 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
8185 tcg_temp_free_i32(tmp);
8186 }
8187 #else
8188 static void gen_set_cr6_from_fpscr(DisasContext *ctx)
8189 {
8190 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
8191 }
8192 #endif
8193
8194 #define GEN_DFP_T_A_B_Rc(name) \
8195 static void gen_##name(DisasContext *ctx) \
8196 { \
8197 TCGv_ptr rd, ra, rb; \
8198 if (unlikely(!ctx->fpu_enabled)) { \
8199 gen_exception(ctx, POWERPC_EXCP_FPU); \
8200 return; \
8201 } \
8202 gen_update_nip(ctx, ctx->nip - 4); \
8203 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8204 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8205 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8206 gen_helper_##name(cpu_env, rd, ra, rb); \
8207 if (unlikely(Rc(ctx->opcode) != 0)) { \
8208 gen_set_cr6_from_fpscr(ctx); \
8209 } \
8210 tcg_temp_free_ptr(rd); \
8211 tcg_temp_free_ptr(ra); \
8212 tcg_temp_free_ptr(rb); \
8213 }
8214
8215 #define GEN_DFP_BF_A_B(name) \
8216 static void gen_##name(DisasContext *ctx) \
8217 { \
8218 TCGv_ptr ra, rb; \
8219 if (unlikely(!ctx->fpu_enabled)) { \
8220 gen_exception(ctx, POWERPC_EXCP_FPU); \
8221 return; \
8222 } \
8223 gen_update_nip(ctx, ctx->nip - 4); \
8224 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8225 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8226 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8227 cpu_env, ra, rb); \
8228 tcg_temp_free_ptr(ra); \
8229 tcg_temp_free_ptr(rb); \
8230 }
8231
8232 #define GEN_DFP_BF_A_DCM(name) \
8233 static void gen_##name(DisasContext *ctx) \
8234 { \
8235 TCGv_ptr ra; \
8236 TCGv_i32 dcm; \
8237 if (unlikely(!ctx->fpu_enabled)) { \
8238 gen_exception(ctx, POWERPC_EXCP_FPU); \
8239 return; \
8240 } \
8241 gen_update_nip(ctx, ctx->nip - 4); \
8242 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8243 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8244 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8245 cpu_env, ra, dcm); \
8246 tcg_temp_free_ptr(ra); \
8247 tcg_temp_free_i32(dcm); \
8248 }
8249
8250 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8251 static void gen_##name(DisasContext *ctx) \
8252 { \
8253 TCGv_ptr rt, rb; \
8254 TCGv_i32 u32_1, u32_2; \
8255 if (unlikely(!ctx->fpu_enabled)) { \
8256 gen_exception(ctx, POWERPC_EXCP_FPU); \
8257 return; \
8258 } \
8259 gen_update_nip(ctx, ctx->nip - 4); \
8260 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8261 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8262 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8263 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8264 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8265 if (unlikely(Rc(ctx->opcode) != 0)) { \
8266 gen_set_cr6_from_fpscr(ctx); \
8267 } \
8268 tcg_temp_free_ptr(rt); \
8269 tcg_temp_free_ptr(rb); \
8270 tcg_temp_free_i32(u32_1); \
8271 tcg_temp_free_i32(u32_2); \
8272 }
8273
8274 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8275 static void gen_##name(DisasContext *ctx) \
8276 { \
8277 TCGv_ptr rt, ra, rb; \
8278 TCGv_i32 i32; \
8279 if (unlikely(!ctx->fpu_enabled)) { \
8280 gen_exception(ctx, POWERPC_EXCP_FPU); \
8281 return; \
8282 } \
8283 gen_update_nip(ctx, ctx->nip - 4); \
8284 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8285 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8286 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8287 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8288 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8289 if (unlikely(Rc(ctx->opcode) != 0)) { \
8290 gen_set_cr6_from_fpscr(ctx); \
8291 } \
8292 tcg_temp_free_ptr(rt); \
8293 tcg_temp_free_ptr(rb); \
8294 tcg_temp_free_ptr(ra); \
8295 tcg_temp_free_i32(i32); \
8296 }
8297
8298 #define GEN_DFP_T_B_Rc(name) \
8299 static void gen_##name(DisasContext *ctx) \
8300 { \
8301 TCGv_ptr rt, rb; \
8302 if (unlikely(!ctx->fpu_enabled)) { \
8303 gen_exception(ctx, POWERPC_EXCP_FPU); \
8304 return; \
8305 } \
8306 gen_update_nip(ctx, ctx->nip - 4); \
8307 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8308 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8309 gen_helper_##name(cpu_env, rt, rb); \
8310 if (unlikely(Rc(ctx->opcode) != 0)) { \
8311 gen_set_cr6_from_fpscr(ctx); \
8312 } \
8313 tcg_temp_free_ptr(rt); \
8314 tcg_temp_free_ptr(rb); \
8315 }
8316
8317 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8318 static void gen_##name(DisasContext *ctx) \
8319 { \
8320 TCGv_ptr rt, rs; \
8321 TCGv_i32 i32; \
8322 if (unlikely(!ctx->fpu_enabled)) { \
8323 gen_exception(ctx, POWERPC_EXCP_FPU); \
8324 return; \
8325 } \
8326 gen_update_nip(ctx, ctx->nip - 4); \
8327 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8328 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8329 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8330 gen_helper_##name(cpu_env, rt, rs, i32); \
8331 if (unlikely(Rc(ctx->opcode) != 0)) { \
8332 gen_set_cr6_from_fpscr(ctx); \
8333 } \
8334 tcg_temp_free_ptr(rt); \
8335 tcg_temp_free_ptr(rs); \
8336 tcg_temp_free_i32(i32); \
8337 }
8338
8339 GEN_DFP_T_A_B_Rc(dadd)
8340 GEN_DFP_T_A_B_Rc(daddq)
8341 GEN_DFP_T_A_B_Rc(dsub)
8342 GEN_DFP_T_A_B_Rc(dsubq)
8343 GEN_DFP_T_A_B_Rc(dmul)
8344 GEN_DFP_T_A_B_Rc(dmulq)
8345 GEN_DFP_T_A_B_Rc(ddiv)
8346 GEN_DFP_T_A_B_Rc(ddivq)
8347 GEN_DFP_BF_A_B(dcmpu)
8348 GEN_DFP_BF_A_B(dcmpuq)
8349 GEN_DFP_BF_A_B(dcmpo)
8350 GEN_DFP_BF_A_B(dcmpoq)
8351 GEN_DFP_BF_A_DCM(dtstdc)
8352 GEN_DFP_BF_A_DCM(dtstdcq)
8353 GEN_DFP_BF_A_DCM(dtstdg)
8354 GEN_DFP_BF_A_DCM(dtstdgq)
8355 GEN_DFP_BF_A_B(dtstex)
8356 GEN_DFP_BF_A_B(dtstexq)
8357 GEN_DFP_BF_A_B(dtstsf)
8358 GEN_DFP_BF_A_B(dtstsfq)
8359 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8360 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8361 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8362 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8363 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8364 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8365 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8366 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8367 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8368 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8369 GEN_DFP_T_B_Rc(dctdp)
8370 GEN_DFP_T_B_Rc(dctqpq)
8371 GEN_DFP_T_B_Rc(drsp)
8372 GEN_DFP_T_B_Rc(drdpq)
8373 GEN_DFP_T_B_Rc(dcffix)
8374 GEN_DFP_T_B_Rc(dcffixq)
8375 GEN_DFP_T_B_Rc(dctfix)
8376 GEN_DFP_T_B_Rc(dctfixq)
8377 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8378 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8379 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8380 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8381 GEN_DFP_T_B_Rc(dxex)
8382 GEN_DFP_T_B_Rc(dxexq)
8383 GEN_DFP_T_A_B_Rc(diex)
8384 GEN_DFP_T_A_B_Rc(diexq)
8385 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8386 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8387 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8388 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8389
8390 /*** SPE extension ***/
8391 /* Register moves */
8392
8393 static inline void gen_evmra(DisasContext *ctx)
8394 {
8395
8396 if (unlikely(!ctx->spe_enabled)) {
8397 gen_exception(ctx, POWERPC_EXCP_SPEU);
8398 return;
8399 }
8400
8401 TCGv_i64 tmp = tcg_temp_new_i64();
8402
8403 /* tmp := rA_lo + rA_hi << 32 */
8404 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8405
8406 /* spe_acc := tmp */
8407 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8408 tcg_temp_free_i64(tmp);
8409
8410 /* rD := rA */
8411 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8412 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8413 }
8414
8415 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8416 {
8417 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8418 }
8419
8420 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8421 {
8422 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8423 }
8424
8425 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8426 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8427 { \
8428 if (Rc(ctx->opcode)) \
8429 gen_##name1(ctx); \
8430 else \
8431 gen_##name0(ctx); \
8432 }
8433
8434 /* Handler for undefined SPE opcodes */
8435 static inline void gen_speundef(DisasContext *ctx)
8436 {
8437 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8438 }
8439
8440 /* SPE logic */
8441 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8442 static inline void gen_##name(DisasContext *ctx) \
8443 { \
8444 if (unlikely(!ctx->spe_enabled)) { \
8445 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8446 return; \
8447 } \
8448 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8449 cpu_gpr[rB(ctx->opcode)]); \
8450 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8451 cpu_gprh[rB(ctx->opcode)]); \
8452 }
8453
8454 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8455 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8456 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8457 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8458 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8459 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8460 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8461 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8462
8463 /* SPE logic immediate */
8464 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8465 static inline void gen_##name(DisasContext *ctx) \
8466 { \
8467 TCGv_i32 t0; \
8468 if (unlikely(!ctx->spe_enabled)) { \
8469 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8470 return; \
8471 } \
8472 t0 = tcg_temp_new_i32(); \
8473 \
8474 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8475 tcg_opi(t0, t0, rB(ctx->opcode)); \
8476 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8477 \
8478 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8479 tcg_opi(t0, t0, rB(ctx->opcode)); \
8480 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8481 \
8482 tcg_temp_free_i32(t0); \
8483 }
8484 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8485 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8486 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8487 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8488
8489 /* SPE arithmetic */
8490 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8491 static inline void gen_##name(DisasContext *ctx) \
8492 { \
8493 TCGv_i32 t0; \
8494 if (unlikely(!ctx->spe_enabled)) { \
8495 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8496 return; \
8497 } \
8498 t0 = tcg_temp_new_i32(); \
8499 \
8500 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8501 tcg_op(t0, t0); \
8502 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8503 \
8504 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8505 tcg_op(t0, t0); \
8506 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8507 \
8508 tcg_temp_free_i32(t0); \
8509 }
8510
8511 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8512 {
8513 int l1 = gen_new_label();
8514 int l2 = gen_new_label();
8515
8516 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8517 tcg_gen_neg_i32(ret, arg1);
8518 tcg_gen_br(l2);
8519 gen_set_label(l1);
8520 tcg_gen_mov_i32(ret, arg1);
8521 gen_set_label(l2);
8522 }
8523 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8524 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8525 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8526 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8527 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8528 {
8529 tcg_gen_addi_i32(ret, arg1, 0x8000);
8530 tcg_gen_ext16u_i32(ret, ret);
8531 }
8532 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8533 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8534 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8535
8536 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8537 static inline void gen_##name(DisasContext *ctx) \
8538 { \
8539 TCGv_i32 t0, t1; \
8540 if (unlikely(!ctx->spe_enabled)) { \
8541 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8542 return; \
8543 } \
8544 t0 = tcg_temp_new_i32(); \
8545 t1 = tcg_temp_new_i32(); \
8546 \
8547 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8548 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8549 tcg_op(t0, t0, t1); \
8550 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8551 \
8552 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8553 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8554 tcg_op(t0, t0, t1); \
8555 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8556 \
8557 tcg_temp_free_i32(t0); \
8558 tcg_temp_free_i32(t1); \
8559 }
8560
8561 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8562 {
8563 TCGv_i32 t0;
8564 int l1, l2;
8565
8566 l1 = gen_new_label();
8567 l2 = gen_new_label();
8568 t0 = tcg_temp_local_new_i32();
8569 /* No error here: 6 bits are used */
8570 tcg_gen_andi_i32(t0, arg2, 0x3F);
8571 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8572 tcg_gen_shr_i32(ret, arg1, t0);
8573 tcg_gen_br(l2);
8574 gen_set_label(l1);
8575 tcg_gen_movi_i32(ret, 0);
8576 gen_set_label(l2);
8577 tcg_temp_free_i32(t0);
8578 }
8579 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8580 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8581 {
8582 TCGv_i32 t0;
8583 int l1, l2;
8584
8585 l1 = gen_new_label();
8586 l2 = gen_new_label();
8587 t0 = tcg_temp_local_new_i32();
8588 /* No error here: 6 bits are used */
8589 tcg_gen_andi_i32(t0, arg2, 0x3F);
8590 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8591 tcg_gen_sar_i32(ret, arg1, t0);
8592 tcg_gen_br(l2);
8593 gen_set_label(l1);
8594 tcg_gen_movi_i32(ret, 0);
8595 gen_set_label(l2);
8596 tcg_temp_free_i32(t0);
8597 }
8598 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8599 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8600 {
8601 TCGv_i32 t0;
8602 int l1, l2;
8603
8604 l1 = gen_new_label();
8605 l2 = gen_new_label();
8606 t0 = tcg_temp_local_new_i32();
8607 /* No error here: 6 bits are used */
8608 tcg_gen_andi_i32(t0, arg2, 0x3F);
8609 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8610 tcg_gen_shl_i32(ret, arg1, t0);
8611 tcg_gen_br(l2);
8612 gen_set_label(l1);
8613 tcg_gen_movi_i32(ret, 0);
8614 gen_set_label(l2);
8615 tcg_temp_free_i32(t0);
8616 }
8617 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8618 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8619 {
8620 TCGv_i32 t0 = tcg_temp_new_i32();
8621 tcg_gen_andi_i32(t0, arg2, 0x1F);
8622 tcg_gen_rotl_i32(ret, arg1, t0);
8623 tcg_temp_free_i32(t0);
8624 }
8625 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8626 static inline void gen_evmergehi(DisasContext *ctx)
8627 {
8628 if (unlikely(!ctx->spe_enabled)) {
8629 gen_exception(ctx, POWERPC_EXCP_SPEU);
8630 return;
8631 }
8632 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8633 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8634 }
8635 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8636 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8637 {
8638 tcg_gen_sub_i32(ret, arg2, arg1);
8639 }
8640 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8641
8642 /* SPE arithmetic immediate */
8643 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8644 static inline void gen_##name(DisasContext *ctx) \
8645 { \
8646 TCGv_i32 t0; \
8647 if (unlikely(!ctx->spe_enabled)) { \
8648 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8649 return; \
8650 } \
8651 t0 = tcg_temp_new_i32(); \
8652 \
8653 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8654 tcg_op(t0, t0, rA(ctx->opcode)); \
8655 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8656 \
8657 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8658 tcg_op(t0, t0, rA(ctx->opcode)); \
8659 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8660 \
8661 tcg_temp_free_i32(t0); \
8662 }
8663 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8664 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8665
8666 /* SPE comparison */
8667 #define GEN_SPEOP_COMP(name, tcg_cond) \
8668 static inline void gen_##name(DisasContext *ctx) \
8669 { \
8670 if (unlikely(!ctx->spe_enabled)) { \
8671 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8672 return; \
8673 } \
8674 int l1 = gen_new_label(); \
8675 int l2 = gen_new_label(); \
8676 int l3 = gen_new_label(); \
8677 int l4 = gen_new_label(); \
8678 \
8679 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8680 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8681 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8682 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8683 \
8684 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8685 cpu_gpr[rB(ctx->opcode)], l1); \
8686 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8687 tcg_gen_br(l2); \
8688 gen_set_label(l1); \
8689 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8690 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8691 gen_set_label(l2); \
8692 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8693 cpu_gprh[rB(ctx->opcode)], l3); \
8694 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8695 ~(CRF_CH | CRF_CH_AND_CL)); \
8696 tcg_gen_br(l4); \
8697 gen_set_label(l3); \
8698 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8699 CRF_CH | CRF_CH_OR_CL); \
8700 gen_set_label(l4); \
8701 }
8702 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8703 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8704 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8705 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8706 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8707
8708 /* SPE misc */
8709 static inline void gen_brinc(DisasContext *ctx)
8710 {
8711 /* Note: brinc is usable even if SPE is disabled */
8712 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8713 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8714 }
8715 static inline void gen_evmergelo(DisasContext *ctx)
8716 {
8717 if (unlikely(!ctx->spe_enabled)) {
8718 gen_exception(ctx, POWERPC_EXCP_SPEU);
8719 return;
8720 }
8721 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8722 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8723 }
8724 static inline void gen_evmergehilo(DisasContext *ctx)
8725 {
8726 if (unlikely(!ctx->spe_enabled)) {
8727 gen_exception(ctx, POWERPC_EXCP_SPEU);
8728 return;
8729 }
8730 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8731 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8732 }
8733 static inline void gen_evmergelohi(DisasContext *ctx)
8734 {
8735 if (unlikely(!ctx->spe_enabled)) {
8736 gen_exception(ctx, POWERPC_EXCP_SPEU);
8737 return;
8738 }
8739 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8740 TCGv tmp = tcg_temp_new();
8741 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8742 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8743 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8744 tcg_temp_free(tmp);
8745 } else {
8746 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8747 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8748 }
8749 }
8750 static inline void gen_evsplati(DisasContext *ctx)
8751 {
8752 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8753
8754 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8755 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8756 }
8757 static inline void gen_evsplatfi(DisasContext *ctx)
8758 {
8759 uint64_t imm = rA(ctx->opcode) << 27;
8760
8761 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8762 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8763 }
8764
8765 static inline void gen_evsel(DisasContext *ctx)
8766 {
8767 int l1 = gen_new_label();
8768 int l2 = gen_new_label();
8769 int l3 = gen_new_label();
8770 int l4 = gen_new_label();
8771 TCGv_i32 t0 = tcg_temp_local_new_i32();
8772 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8773 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8774 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8775 tcg_gen_br(l2);
8776 gen_set_label(l1);
8777 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8778 gen_set_label(l2);
8779 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8780 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8781 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8782 tcg_gen_br(l4);
8783 gen_set_label(l3);
8784 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8785 gen_set_label(l4);
8786 tcg_temp_free_i32(t0);
8787 }
8788
8789 static void gen_evsel0(DisasContext *ctx)
8790 {
8791 gen_evsel(ctx);
8792 }
8793
8794 static void gen_evsel1(DisasContext *ctx)
8795 {
8796 gen_evsel(ctx);
8797 }
8798
8799 static void gen_evsel2(DisasContext *ctx)
8800 {
8801 gen_evsel(ctx);
8802 }
8803
8804 static void gen_evsel3(DisasContext *ctx)
8805 {
8806 gen_evsel(ctx);
8807 }
8808
8809 /* Multiply */
8810
8811 static inline void gen_evmwumi(DisasContext *ctx)
8812 {
8813 TCGv_i64 t0, t1;
8814
8815 if (unlikely(!ctx->spe_enabled)) {
8816 gen_exception(ctx, POWERPC_EXCP_SPEU);
8817 return;
8818 }
8819
8820 t0 = tcg_temp_new_i64();
8821 t1 = tcg_temp_new_i64();
8822
8823 /* t0 := rA; t1 := rB */
8824 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8825 tcg_gen_ext32u_i64(t0, t0);
8826 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8827 tcg_gen_ext32u_i64(t1, t1);
8828
8829 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8830
8831 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8832
8833 tcg_temp_free_i64(t0);
8834 tcg_temp_free_i64(t1);
8835 }
8836
8837 static inline void gen_evmwumia(DisasContext *ctx)
8838 {
8839 TCGv_i64 tmp;
8840
8841 if (unlikely(!ctx->spe_enabled)) {
8842 gen_exception(ctx, POWERPC_EXCP_SPEU);
8843 return;
8844 }
8845
8846 gen_evmwumi(ctx); /* rD := rA * rB */
8847
8848 tmp = tcg_temp_new_i64();
8849
8850 /* acc := rD */
8851 gen_load_gpr64(tmp, rD(ctx->opcode));
8852 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8853 tcg_temp_free_i64(tmp);
8854 }
8855
8856 static inline void gen_evmwumiaa(DisasContext *ctx)
8857 {
8858 TCGv_i64 acc;
8859 TCGv_i64 tmp;
8860
8861 if (unlikely(!ctx->spe_enabled)) {
8862 gen_exception(ctx, POWERPC_EXCP_SPEU);
8863 return;
8864 }
8865
8866 gen_evmwumi(ctx); /* rD := rA * rB */
8867
8868 acc = tcg_temp_new_i64();
8869 tmp = tcg_temp_new_i64();
8870
8871 /* tmp := rD */
8872 gen_load_gpr64(tmp, rD(ctx->opcode));
8873
8874 /* Load acc */
8875 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8876
8877 /* acc := tmp + acc */
8878 tcg_gen_add_i64(acc, acc, tmp);
8879
8880 /* Store acc */
8881 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8882
8883 /* rD := acc */
8884 gen_store_gpr64(rD(ctx->opcode), acc);
8885
8886 tcg_temp_free_i64(acc);
8887 tcg_temp_free_i64(tmp);
8888 }
8889
8890 static inline void gen_evmwsmi(DisasContext *ctx)
8891 {
8892 TCGv_i64 t0, t1;
8893
8894 if (unlikely(!ctx->spe_enabled)) {
8895 gen_exception(ctx, POWERPC_EXCP_SPEU);
8896 return;
8897 }
8898
8899 t0 = tcg_temp_new_i64();
8900 t1 = tcg_temp_new_i64();
8901
8902 /* t0 := rA; t1 := rB */
8903 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8904 tcg_gen_ext32s_i64(t0, t0);
8905 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8906 tcg_gen_ext32s_i64(t1, t1);
8907
8908 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8909
8910 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8911
8912 tcg_temp_free_i64(t0);
8913 tcg_temp_free_i64(t1);
8914 }
8915
8916 static inline void gen_evmwsmia(DisasContext *ctx)
8917 {
8918 TCGv_i64 tmp;
8919
8920 gen_evmwsmi(ctx); /* rD := rA * rB */
8921
8922 tmp = tcg_temp_new_i64();
8923
8924 /* acc := rD */
8925 gen_load_gpr64(tmp, rD(ctx->opcode));
8926 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8927
8928 tcg_temp_free_i64(tmp);
8929 }
8930
8931 static inline void gen_evmwsmiaa(DisasContext *ctx)
8932 {
8933 TCGv_i64 acc = tcg_temp_new_i64();
8934 TCGv_i64 tmp = tcg_temp_new_i64();
8935
8936 gen_evmwsmi(ctx); /* rD := rA * rB */
8937
8938 acc = tcg_temp_new_i64();
8939 tmp = tcg_temp_new_i64();
8940
8941 /* tmp := rD */
8942 gen_load_gpr64(tmp, rD(ctx->opcode));
8943
8944 /* Load acc */
8945 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8946
8947 /* acc := tmp + acc */
8948 tcg_gen_add_i64(acc, acc, tmp);
8949
8950 /* Store acc */
8951 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8952
8953 /* rD := acc */
8954 gen_store_gpr64(rD(ctx->opcode), acc);
8955
8956 tcg_temp_free_i64(acc);
8957 tcg_temp_free_i64(tmp);
8958 }
8959
8960 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8961 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8962 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8963 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8964 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8965 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8966 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8967 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
8968 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
8969 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8970 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8971 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8972 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8973 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8974 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8975 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8976 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8977 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8978 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8979 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
8980 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8981 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8982 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
8983 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
8984 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8985 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8986 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8987 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8988 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
8989
8990 /* SPE load and stores */
8991 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
8992 {
8993 target_ulong uimm = rB(ctx->opcode);
8994
8995 if (rA(ctx->opcode) == 0) {
8996 tcg_gen_movi_tl(EA, uimm << sh);
8997 } else {
8998 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
8999 if (NARROW_MODE(ctx)) {
9000 tcg_gen_ext32u_tl(EA, EA);
9001 }
9002 }
9003 }
9004
9005 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9006 {
9007 TCGv_i64 t0 = tcg_temp_new_i64();
9008 gen_qemu_ld64(ctx, t0, addr);
9009 gen_store_gpr64(rD(ctx->opcode), t0);
9010 tcg_temp_free_i64(t0);
9011 }
9012
9013 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9014 {
9015 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9016 gen_addr_add(ctx, addr, addr, 4);
9017 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9018 }
9019
9020 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9021 {
9022 TCGv t0 = tcg_temp_new();
9023 gen_qemu_ld16u(ctx, t0, addr);
9024 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9025 gen_addr_add(ctx, addr, addr, 2);
9026 gen_qemu_ld16u(ctx, t0, addr);
9027 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9028 gen_addr_add(ctx, addr, addr, 2);
9029 gen_qemu_ld16u(ctx, t0, addr);
9030 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9031 gen_addr_add(ctx, addr, addr, 2);
9032 gen_qemu_ld16u(ctx, t0, addr);
9033 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9034 tcg_temp_free(t0);
9035 }
9036
9037 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9038 {
9039 TCGv t0 = tcg_temp_new();
9040 gen_qemu_ld16u(ctx, t0, addr);
9041 tcg_gen_shli_tl(t0, t0, 16);
9042 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9043 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9044 tcg_temp_free(t0);
9045 }
9046
9047 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9048 {
9049 TCGv t0 = tcg_temp_new();
9050 gen_qemu_ld16u(ctx, t0, addr);
9051 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9052 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9053 tcg_temp_free(t0);
9054 }
9055
9056 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9057 {
9058 TCGv t0 = tcg_temp_new();
9059 gen_qemu_ld16s(ctx, t0, addr);
9060 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9061 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9062 tcg_temp_free(t0);
9063 }
9064
9065 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9066 {
9067 TCGv t0 = tcg_temp_new();
9068 gen_qemu_ld16u(ctx, t0, addr);
9069 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9070 gen_addr_add(ctx, addr, addr, 2);
9071 gen_qemu_ld16u(ctx, t0, addr);
9072 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9073 tcg_temp_free(t0);
9074 }
9075
9076 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9077 {
9078 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9079 gen_addr_add(ctx, addr, addr, 2);
9080 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9081 }
9082
9083 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9084 {
9085 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9086 gen_addr_add(ctx, addr, addr, 2);
9087 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9088 }
9089
9090 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9091 {
9092 TCGv t0 = tcg_temp_new();
9093 gen_qemu_ld32u(ctx, t0, addr);
9094 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9095 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9096 tcg_temp_free(t0);
9097 }
9098
9099 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9100 {
9101 TCGv t0 = tcg_temp_new();
9102 gen_qemu_ld16u(ctx, t0, addr);
9103 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9104 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9105 gen_addr_add(ctx, addr, addr, 2);
9106 gen_qemu_ld16u(ctx, t0, addr);
9107 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9108 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9109 tcg_temp_free(t0);
9110 }
9111
9112 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9113 {
9114 TCGv_i64 t0 = tcg_temp_new_i64();
9115 gen_load_gpr64(t0, rS(ctx->opcode));
9116 gen_qemu_st64(ctx, t0, addr);
9117 tcg_temp_free_i64(t0);
9118 }
9119
9120 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9121 {
9122 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9123 gen_addr_add(ctx, addr, addr, 4);
9124 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9125 }
9126
9127 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9128 {
9129 TCGv t0 = tcg_temp_new();
9130 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9131 gen_qemu_st16(ctx, t0, addr);
9132 gen_addr_add(ctx, addr, addr, 2);
9133 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9134 gen_addr_add(ctx, addr, addr, 2);
9135 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9136 gen_qemu_st16(ctx, t0, addr);
9137 tcg_temp_free(t0);
9138 gen_addr_add(ctx, addr, addr, 2);
9139 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9140 }
9141
9142 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9143 {
9144 TCGv t0 = tcg_temp_new();
9145 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9146 gen_qemu_st16(ctx, t0, addr);
9147 gen_addr_add(ctx, addr, addr, 2);
9148 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9149 gen_qemu_st16(ctx, t0, addr);
9150 tcg_temp_free(t0);
9151 }
9152
9153 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9154 {
9155 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9156 gen_addr_add(ctx, addr, addr, 2);
9157 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9158 }
9159
9160 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9161 {
9162 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9163 }
9164
9165 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9166 {
9167 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9168 }
9169
9170 #define GEN_SPEOP_LDST(name, opc2, sh) \
9171 static void glue(gen_, name)(DisasContext *ctx) \
9172 { \
9173 TCGv t0; \
9174 if (unlikely(!ctx->spe_enabled)) { \
9175 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9176 return; \
9177 } \
9178 gen_set_access_type(ctx, ACCESS_INT); \
9179 t0 = tcg_temp_new(); \
9180 if (Rc(ctx->opcode)) { \
9181 gen_addr_spe_imm_index(ctx, t0, sh); \
9182 } else { \
9183 gen_addr_reg_index(ctx, t0); \
9184 } \
9185 gen_op_##name(ctx, t0); \
9186 tcg_temp_free(t0); \
9187 }
9188
9189 GEN_SPEOP_LDST(evldd, 0x00, 3);
9190 GEN_SPEOP_LDST(evldw, 0x01, 3);
9191 GEN_SPEOP_LDST(evldh, 0x02, 3);
9192 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9193 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9194 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9195 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9196 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9197 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9198 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9199 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9200
9201 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9202 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9203 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9204 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9205 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9206 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9207 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9208
9209 /* Multiply and add - TODO */
9210 #if 0
9211 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9212 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9213 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9214 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9215 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9216 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9217 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9218 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9219 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9220 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9221 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9222 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9223
9224 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9225 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9226 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9227 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9228 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9229 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9230 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9231 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9232 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9233 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9234 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9235 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9236
9237 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9238 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9239 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9240 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9241 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9242
9243 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9244 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9245 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9246 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9247 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9248 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9249 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9250 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9251 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9252 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9253 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9254 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9255
9256 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9257 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9258 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9259 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9260
9261 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9262 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9263 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9264 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9265 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9266 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9267 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9268 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9269 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9270 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9271 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9272 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9273
9274 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9275 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9276 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9277 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9278 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9279 #endif
9280
9281 /*** SPE floating-point extension ***/
9282 #define GEN_SPEFPUOP_CONV_32_32(name) \
9283 static inline void gen_##name(DisasContext *ctx) \
9284 { \
9285 TCGv_i32 t0 = tcg_temp_new_i32(); \
9286 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9287 gen_helper_##name(t0, cpu_env, t0); \
9288 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9289 tcg_temp_free_i32(t0); \
9290 }
9291 #define GEN_SPEFPUOP_CONV_32_64(name) \
9292 static inline void gen_##name(DisasContext *ctx) \
9293 { \
9294 TCGv_i64 t0 = tcg_temp_new_i64(); \
9295 TCGv_i32 t1 = tcg_temp_new_i32(); \
9296 gen_load_gpr64(t0, rB(ctx->opcode)); \
9297 gen_helper_##name(t1, cpu_env, t0); \
9298 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9299 tcg_temp_free_i64(t0); \
9300 tcg_temp_free_i32(t1); \
9301 }
9302 #define GEN_SPEFPUOP_CONV_64_32(name) \
9303 static inline void gen_##name(DisasContext *ctx) \
9304 { \
9305 TCGv_i64 t0 = tcg_temp_new_i64(); \
9306 TCGv_i32 t1 = tcg_temp_new_i32(); \
9307 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9308 gen_helper_##name(t0, cpu_env, t1); \
9309 gen_store_gpr64(rD(ctx->opcode), t0); \
9310 tcg_temp_free_i64(t0); \
9311 tcg_temp_free_i32(t1); \
9312 }
9313 #define GEN_SPEFPUOP_CONV_64_64(name) \
9314 static inline void gen_##name(DisasContext *ctx) \
9315 { \
9316 TCGv_i64 t0 = tcg_temp_new_i64(); \
9317 gen_load_gpr64(t0, rB(ctx->opcode)); \
9318 gen_helper_##name(t0, cpu_env, t0); \
9319 gen_store_gpr64(rD(ctx->opcode), t0); \
9320 tcg_temp_free_i64(t0); \
9321 }
9322 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9323 static inline void gen_##name(DisasContext *ctx) \
9324 { \
9325 TCGv_i32 t0, t1; \
9326 if (unlikely(!ctx->spe_enabled)) { \
9327 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9328 return; \
9329 } \
9330 t0 = tcg_temp_new_i32(); \
9331 t1 = tcg_temp_new_i32(); \
9332 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9333 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9334 gen_helper_##name(t0, cpu_env, t0, t1); \
9335 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9336 \
9337 tcg_temp_free_i32(t0); \
9338 tcg_temp_free_i32(t1); \
9339 }
9340 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9341 static inline void gen_##name(DisasContext *ctx) \
9342 { \
9343 TCGv_i64 t0, t1; \
9344 if (unlikely(!ctx->spe_enabled)) { \
9345 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9346 return; \
9347 } \
9348 t0 = tcg_temp_new_i64(); \
9349 t1 = tcg_temp_new_i64(); \
9350 gen_load_gpr64(t0, rA(ctx->opcode)); \
9351 gen_load_gpr64(t1, rB(ctx->opcode)); \
9352 gen_helper_##name(t0, cpu_env, t0, t1); \
9353 gen_store_gpr64(rD(ctx->opcode), t0); \
9354 tcg_temp_free_i64(t0); \
9355 tcg_temp_free_i64(t1); \
9356 }
9357 #define GEN_SPEFPUOP_COMP_32(name) \
9358 static inline void gen_##name(DisasContext *ctx) \
9359 { \
9360 TCGv_i32 t0, t1; \
9361 if (unlikely(!ctx->spe_enabled)) { \
9362 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9363 return; \
9364 } \
9365 t0 = tcg_temp_new_i32(); \
9366 t1 = tcg_temp_new_i32(); \
9367 \
9368 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9369 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9370 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9371 \
9372 tcg_temp_free_i32(t0); \
9373 tcg_temp_free_i32(t1); \
9374 }
9375 #define GEN_SPEFPUOP_COMP_64(name) \
9376 static inline void gen_##name(DisasContext *ctx) \
9377 { \
9378 TCGv_i64 t0, t1; \
9379 if (unlikely(!ctx->spe_enabled)) { \
9380 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9381 return; \
9382 } \
9383 t0 = tcg_temp_new_i64(); \
9384 t1 = tcg_temp_new_i64(); \
9385 gen_load_gpr64(t0, rA(ctx->opcode)); \
9386 gen_load_gpr64(t1, rB(ctx->opcode)); \
9387 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9388 tcg_temp_free_i64(t0); \
9389 tcg_temp_free_i64(t1); \
9390 }
9391
9392 /* Single precision floating-point vectors operations */
9393 /* Arithmetic */
9394 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9395 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9396 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9397 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9398 static inline void gen_evfsabs(DisasContext *ctx)
9399 {
9400 if (unlikely(!ctx->spe_enabled)) {
9401 gen_exception(ctx, POWERPC_EXCP_SPEU);
9402 return;
9403 }
9404 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9405 ~0x80000000);
9406 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9407 ~0x80000000);
9408 }
9409 static inline void gen_evfsnabs(DisasContext *ctx)
9410 {
9411 if (unlikely(!ctx->spe_enabled)) {
9412 gen_exception(ctx, POWERPC_EXCP_SPEU);
9413 return;
9414 }
9415 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9416 0x80000000);
9417 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9418 0x80000000);
9419 }
9420 static inline void gen_evfsneg(DisasContext *ctx)
9421 {
9422 if (unlikely(!ctx->spe_enabled)) {
9423 gen_exception(ctx, POWERPC_EXCP_SPEU);
9424 return;
9425 }
9426 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9427 0x80000000);
9428 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9429 0x80000000);
9430 }
9431
9432 /* Conversion */
9433 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9434 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9435 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9436 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9437 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9438 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9439 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9440 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9441 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9442 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9443
9444 /* Comparison */
9445 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9446 GEN_SPEFPUOP_COMP_64(evfscmplt);
9447 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9448 GEN_SPEFPUOP_COMP_64(evfststgt);
9449 GEN_SPEFPUOP_COMP_64(evfststlt);
9450 GEN_SPEFPUOP_COMP_64(evfststeq);
9451
9452 /* Opcodes definitions */
9453 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9454 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9455 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9456 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9457 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9458 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9459 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9460 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9461 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9462 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9463 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9464 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9465 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9466 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9467
9468 /* Single precision floating-point operations */
9469 /* Arithmetic */
9470 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9471 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9472 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9473 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9474 static inline void gen_efsabs(DisasContext *ctx)
9475 {
9476 if (unlikely(!ctx->spe_enabled)) {
9477 gen_exception(ctx, POWERPC_EXCP_SPEU);
9478 return;
9479 }
9480 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9481 }
9482 static inline void gen_efsnabs(DisasContext *ctx)
9483 {
9484 if (unlikely(!ctx->spe_enabled)) {
9485 gen_exception(ctx, POWERPC_EXCP_SPEU);
9486 return;
9487 }
9488 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9489 }
9490 static inline void gen_efsneg(DisasContext *ctx)
9491 {
9492 if (unlikely(!ctx->spe_enabled)) {
9493 gen_exception(ctx, POWERPC_EXCP_SPEU);
9494 return;
9495 }
9496 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9497 }
9498
9499 /* Conversion */
9500 GEN_SPEFPUOP_CONV_32_32(efscfui);
9501 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9502 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9503 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9504 GEN_SPEFPUOP_CONV_32_32(efsctui);
9505 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9506 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9507 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9508 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9509 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9510 GEN_SPEFPUOP_CONV_32_64(efscfd);
9511
9512 /* Comparison */
9513 GEN_SPEFPUOP_COMP_32(efscmpgt);
9514 GEN_SPEFPUOP_COMP_32(efscmplt);
9515 GEN_SPEFPUOP_COMP_32(efscmpeq);
9516 GEN_SPEFPUOP_COMP_32(efststgt);
9517 GEN_SPEFPUOP_COMP_32(efststlt);
9518 GEN_SPEFPUOP_COMP_32(efststeq);
9519
9520 /* Opcodes definitions */
9521 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9522 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9523 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9524 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9525 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9526 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9527 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9528 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9529 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9530 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9531 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9532 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9533 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9534 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9535
9536 /* Double precision floating-point operations */
9537 /* Arithmetic */
9538 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9539 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9540 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9541 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9542 static inline void gen_efdabs(DisasContext *ctx)
9543 {
9544 if (unlikely(!ctx->spe_enabled)) {
9545 gen_exception(ctx, POWERPC_EXCP_SPEU);
9546 return;
9547 }
9548 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9549 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9550 ~0x80000000);
9551 }
9552 static inline void gen_efdnabs(DisasContext *ctx)
9553 {
9554 if (unlikely(!ctx->spe_enabled)) {
9555 gen_exception(ctx, POWERPC_EXCP_SPEU);
9556 return;
9557 }
9558 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9559 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9560 0x80000000);
9561 }
9562 static inline void gen_efdneg(DisasContext *ctx)
9563 {
9564 if (unlikely(!ctx->spe_enabled)) {
9565 gen_exception(ctx, POWERPC_EXCP_SPEU);
9566 return;
9567 }
9568 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9569 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9570 0x80000000);
9571 }
9572
9573 /* Conversion */
9574 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9575 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9576 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9577 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9578 GEN_SPEFPUOP_CONV_32_64(efdctui);
9579 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9580 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9581 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9582 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9583 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9584 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9585 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9586 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9587 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9588 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9589
9590 /* Comparison */
9591 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9592 GEN_SPEFPUOP_COMP_64(efdcmplt);
9593 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9594 GEN_SPEFPUOP_COMP_64(efdtstgt);
9595 GEN_SPEFPUOP_COMP_64(efdtstlt);
9596 GEN_SPEFPUOP_COMP_64(efdtsteq);
9597
9598 /* Opcodes definitions */
9599 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9600 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9601 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9602 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9603 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9604 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9605 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9606 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9607 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9608 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9609 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9610 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9611 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9612 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9613 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9614 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9615
9616 static opcode_t opcodes[] = {
9617 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9618 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9619 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9620 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9621 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9622 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9623 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9624 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9625 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9626 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9627 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9628 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9629 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9630 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9631 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9632 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9633 #if defined(TARGET_PPC64)
9634 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9635 #endif
9636 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9637 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9638 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9639 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9640 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9641 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9642 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9643 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9644 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9645 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9646 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9647 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9648 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9649 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9650 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9651 #if defined(TARGET_PPC64)
9652 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9653 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9654 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9655 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9656 #endif
9657 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9658 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9659 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9660 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9661 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9662 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9663 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9664 #if defined(TARGET_PPC64)
9665 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9666 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9667 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9668 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9669 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9670 #endif
9671 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9672 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9673 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9674 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9675 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9676 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9677 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9678 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9679 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9680 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9681 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9682 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9683 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9684 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9685 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9686 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9687 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9688 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9689 #if defined(TARGET_PPC64)
9690 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9691 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9692 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9693 #endif
9694 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9695 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9696 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9697 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9698 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9699 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9700 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9701 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9702 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9703 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9704 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9705 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9706 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9707 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9708 #if defined(TARGET_PPC64)
9709 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9710 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9711 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9712 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9713 #endif
9714 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9715 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9716 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9717 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9718 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9719 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9720 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9721 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9722 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9723 #if defined(TARGET_PPC64)
9724 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9725 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9726 #endif
9727 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9728 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9729 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9730 #if defined(TARGET_PPC64)
9731 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9732 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9733 #endif
9734 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9735 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9736 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9737 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9738 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9739 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9740 #if defined(TARGET_PPC64)
9741 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9742 #endif
9743 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9744 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9745 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9746 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9747 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9748 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9749 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9750 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9751 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9752 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9753 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9754 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9755 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9756 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9757 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9758 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9759 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9760 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9761 #if defined(TARGET_PPC64)
9762 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9763 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9764 PPC_SEGMENT_64B),
9765 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9766 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9767 PPC_SEGMENT_64B),
9768 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9769 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9770 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9771 #endif
9772 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9773 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9774 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9775 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9776 #if defined(TARGET_PPC64)
9777 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9778 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9779 #endif
9780 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9781 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9782 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9783 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9784 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9785 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9786 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9787 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9788 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9789 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9790 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9791 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9792 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9793 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9794 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9795 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9796 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9797 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9798 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9799 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9800 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9801 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9802 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9803 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9804 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9805 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9806 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9807 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9808 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9809 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9810 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9811 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9812 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9813 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9814 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9815 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9816 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9817 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9818 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9819 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9820 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9821 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9822 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9823 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9824 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9825 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9826 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9827 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9828 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9829 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9830 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9831 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9832 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9833 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9834 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9835 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9836 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9837 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9838 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9839 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9840 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9841 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9842 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9843 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9844 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9845 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9846 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9847 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9848 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9849 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9850 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
9851 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
9852 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9853 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9854 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9855 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9856 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
9857 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
9858 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
9859 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
9860 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
9861 PPC_NONE, PPC2_BOOKE206),
9862 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
9863 PPC_NONE, PPC2_BOOKE206),
9864 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
9865 PPC_NONE, PPC2_BOOKE206),
9866 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
9867 PPC_NONE, PPC2_BOOKE206),
9868 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
9869 PPC_NONE, PPC2_BOOKE206),
9870 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
9871 PPC_NONE, PPC2_PRCNTL),
9872 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
9873 PPC_NONE, PPC2_PRCNTL),
9874 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
9875 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
9876 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
9877 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
9878 PPC_BOOKE, PPC2_BOOKE206),
9879 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
9880 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
9881 PPC_BOOKE, PPC2_BOOKE206),
9882 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
9883 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
9884 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
9885 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
9886 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
9887 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
9888 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
9889 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
9890 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
9891
9892 #undef GEN_INT_ARITH_ADD
9893 #undef GEN_INT_ARITH_ADD_CONST
9894 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
9895 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
9896 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
9897 add_ca, compute_ca, compute_ov) \
9898 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
9899 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
9900 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
9901 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
9902 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
9903 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
9904 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
9905 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
9906 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
9907 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
9908 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
9909
9910 #undef GEN_INT_ARITH_DIVW
9911 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
9912 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
9913 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
9914 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
9915 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
9916 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
9917 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9918 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9919 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9920 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9921
9922 #if defined(TARGET_PPC64)
9923 #undef GEN_INT_ARITH_DIVD
9924 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
9925 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9926 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
9927 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
9928 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
9929 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
9930
9931 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9932 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9933 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9934 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9935
9936 #undef GEN_INT_ARITH_MUL_HELPER
9937 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
9938 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9939 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
9940 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
9941 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
9942 #endif
9943
9944 #undef GEN_INT_ARITH_SUBF
9945 #undef GEN_INT_ARITH_SUBF_CONST
9946 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
9947 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
9948 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
9949 add_ca, compute_ca, compute_ov) \
9950 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
9951 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
9952 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
9953 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
9954 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
9955 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
9956 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
9957 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
9958 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
9959 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
9960 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
9961
9962 #undef GEN_LOGICAL1
9963 #undef GEN_LOGICAL2
9964 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
9965 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
9966 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
9967 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
9968 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
9969 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
9970 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
9971 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
9972 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
9973 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
9974 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
9975 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
9976 #if defined(TARGET_PPC64)
9977 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
9978 #endif
9979
9980 #if defined(TARGET_PPC64)
9981 #undef GEN_PPC64_R2
9982 #undef GEN_PPC64_R4
9983 #define GEN_PPC64_R2(name, opc1, opc2) \
9984 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9985 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9986 PPC_64B)
9987 #define GEN_PPC64_R4(name, opc1, opc2) \
9988 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9989 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
9990 PPC_64B), \
9991 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9992 PPC_64B), \
9993 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
9994 PPC_64B)
9995 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
9996 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
9997 GEN_PPC64_R4(rldic, 0x1E, 0x04),
9998 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
9999 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10000 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10001 #endif
10002
10003 #undef _GEN_FLOAT_ACB
10004 #undef GEN_FLOAT_ACB
10005 #undef _GEN_FLOAT_AB
10006 #undef GEN_FLOAT_AB
10007 #undef _GEN_FLOAT_AC
10008 #undef GEN_FLOAT_AC
10009 #undef GEN_FLOAT_B
10010 #undef GEN_FLOAT_BS
10011 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10012 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10013 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10014 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10015 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10016 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10017 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10018 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10019 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10020 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10021 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10022 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10023 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10024 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10025 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10026 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10027 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10028 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10029 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10030
10031 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10032 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10033 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10034 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10035 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10036 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10037 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10038 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10039 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10040 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10041 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10042 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10043 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10044 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10045 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10046 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10047 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10048 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10049 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10050 #if defined(TARGET_PPC64)
10051 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
10052 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10053 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10054 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10055 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
10056 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10057 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
10058 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10059 #endif
10060 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10061 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10062 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10063 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10064
10065 #undef GEN_LD
10066 #undef GEN_LDU
10067 #undef GEN_LDUX
10068 #undef GEN_LDX_E
10069 #undef GEN_LDS
10070 #define GEN_LD(name, ldop, opc, type) \
10071 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10072 #define GEN_LDU(name, ldop, opc, type) \
10073 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10074 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10075 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10076 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10077 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10078 #define GEN_LDS(name, ldop, op, type) \
10079 GEN_LD(name, ldop, op | 0x20, type) \
10080 GEN_LDU(name, ldop, op | 0x21, type) \
10081 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10082 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10083
10084 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10085 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10086 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10087 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10088 #if defined(TARGET_PPC64)
10089 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10090 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10091 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10092 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10093 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10094 #endif
10095 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10096 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10097
10098 #undef GEN_ST
10099 #undef GEN_STU
10100 #undef GEN_STUX
10101 #undef GEN_STX_E
10102 #undef GEN_STS
10103 #define GEN_ST(name, stop, opc, type) \
10104 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10105 #define GEN_STU(name, stop, opc, type) \
10106 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10107 #define GEN_STUX(name, stop, opc2, opc3, type) \
10108 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10109 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10110 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10111 #define GEN_STS(name, stop, op, type) \
10112 GEN_ST(name, stop, op | 0x20, type) \
10113 GEN_STU(name, stop, op | 0x21, type) \
10114 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10115 GEN_STX(name, stop, 0x17, op | 0x00, type)
10116
10117 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10118 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10119 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10120 #if defined(TARGET_PPC64)
10121 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10122 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10123 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10124 #endif
10125 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10126 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10127
10128 #undef GEN_LDF
10129 #undef GEN_LDUF
10130 #undef GEN_LDUXF
10131 #undef GEN_LDXF
10132 #undef GEN_LDFS
10133 #define GEN_LDF(name, ldop, opc, type) \
10134 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10135 #define GEN_LDUF(name, ldop, opc, type) \
10136 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10137 #define GEN_LDUXF(name, ldop, opc, type) \
10138 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10139 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10140 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10141 #define GEN_LDFS(name, ldop, op, type) \
10142 GEN_LDF(name, ldop, op | 0x20, type) \
10143 GEN_LDUF(name, ldop, op | 0x21, type) \
10144 GEN_LDUXF(name, ldop, op | 0x01, type) \
10145 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10146
10147 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10148 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10149 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10150 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10151 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10152 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10153
10154 #undef GEN_STF
10155 #undef GEN_STUF
10156 #undef GEN_STUXF
10157 #undef GEN_STXF
10158 #undef GEN_STFS
10159 #define GEN_STF(name, stop, opc, type) \
10160 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10161 #define GEN_STUF(name, stop, opc, type) \
10162 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10163 #define GEN_STUXF(name, stop, opc, type) \
10164 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10165 #define GEN_STXF(name, stop, opc2, opc3, type) \
10166 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10167 #define GEN_STFS(name, stop, op, type) \
10168 GEN_STF(name, stop, op | 0x20, type) \
10169 GEN_STUF(name, stop, op | 0x21, type) \
10170 GEN_STUXF(name, stop, op | 0x01, type) \
10171 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10172
10173 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10174 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10175 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10176 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10177 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10178
10179 #undef GEN_CRLOGIC
10180 #define GEN_CRLOGIC(name, tcg_op, opc) \
10181 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10182 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10183 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10184 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10185 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10186 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10187 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10188 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10189 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10190
10191 #undef GEN_MAC_HANDLER
10192 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10193 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10194 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10195 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10196 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10197 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10198 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10199 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10200 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10201 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10202 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10203 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10204 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10205 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10206 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10207 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10208 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10209 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10210 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10211 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10212 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10213 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10214 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10215 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10216 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10217 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10218 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10219 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10220 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10221 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10222 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10223 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10224 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10225 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10226 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10227 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10228 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10229 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10230 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10231 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10232 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10233 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10234 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10235 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10236
10237 #undef GEN_VR_LDX
10238 #undef GEN_VR_STX
10239 #undef GEN_VR_LVE
10240 #undef GEN_VR_STVE
10241 #define GEN_VR_LDX(name, opc2, opc3) \
10242 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10243 #define GEN_VR_STX(name, opc2, opc3) \
10244 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10245 #define GEN_VR_LVE(name, opc2, opc3) \
10246 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10247 #define GEN_VR_STVE(name, opc2, opc3) \
10248 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10249 GEN_VR_LDX(lvx, 0x07, 0x03),
10250 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10251 GEN_VR_LVE(bx, 0x07, 0x00),
10252 GEN_VR_LVE(hx, 0x07, 0x01),
10253 GEN_VR_LVE(wx, 0x07, 0x02),
10254 GEN_VR_STX(svx, 0x07, 0x07),
10255 GEN_VR_STX(svxl, 0x07, 0x0F),
10256 GEN_VR_STVE(bx, 0x07, 0x04),
10257 GEN_VR_STVE(hx, 0x07, 0x05),
10258 GEN_VR_STVE(wx, 0x07, 0x06),
10259
10260 #undef GEN_VX_LOGICAL
10261 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10262 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10263
10264 #undef GEN_VX_LOGICAL_207
10265 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10266 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10267
10268 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10269 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10270 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10271 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10272 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10273 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10274 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10275 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10276
10277 #undef GEN_VXFORM
10278 #define GEN_VXFORM(name, opc2, opc3) \
10279 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10280
10281 #undef GEN_VXFORM_207
10282 #define GEN_VXFORM_207(name, opc2, opc3) \
10283 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10284
10285 #undef GEN_VXFORM_DUAL
10286 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10287 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10288
10289 #undef GEN_VXRFORM_DUAL
10290 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10291 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10292 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10293
10294 GEN_VXFORM(vaddubm, 0, 0),
10295 GEN_VXFORM(vadduhm, 0, 1),
10296 GEN_VXFORM(vadduwm, 0, 2),
10297 GEN_VXFORM_207(vaddudm, 0, 3),
10298 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10299 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10300 GEN_VXFORM(vsubuwm, 0, 18),
10301 GEN_VXFORM_207(vsubudm, 0, 19),
10302 GEN_VXFORM(vmaxub, 1, 0),
10303 GEN_VXFORM(vmaxuh, 1, 1),
10304 GEN_VXFORM(vmaxuw, 1, 2),
10305 GEN_VXFORM_207(vmaxud, 1, 3),
10306 GEN_VXFORM(vmaxsb, 1, 4),
10307 GEN_VXFORM(vmaxsh, 1, 5),
10308 GEN_VXFORM(vmaxsw, 1, 6),
10309 GEN_VXFORM_207(vmaxsd, 1, 7),
10310 GEN_VXFORM(vminub, 1, 8),
10311 GEN_VXFORM(vminuh, 1, 9),
10312 GEN_VXFORM(vminuw, 1, 10),
10313 GEN_VXFORM_207(vminud, 1, 11),
10314 GEN_VXFORM(vminsb, 1, 12),
10315 GEN_VXFORM(vminsh, 1, 13),
10316 GEN_VXFORM(vminsw, 1, 14),
10317 GEN_VXFORM_207(vminsd, 1, 15),
10318 GEN_VXFORM(vavgub, 1, 16),
10319 GEN_VXFORM(vavguh, 1, 17),
10320 GEN_VXFORM(vavguw, 1, 18),
10321 GEN_VXFORM(vavgsb, 1, 20),
10322 GEN_VXFORM(vavgsh, 1, 21),
10323 GEN_VXFORM(vavgsw, 1, 22),
10324 GEN_VXFORM(vmrghb, 6, 0),
10325 GEN_VXFORM(vmrghh, 6, 1),
10326 GEN_VXFORM(vmrghw, 6, 2),
10327 GEN_VXFORM(vmrglb, 6, 4),
10328 GEN_VXFORM(vmrglh, 6, 5),
10329 GEN_VXFORM(vmrglw, 6, 6),
10330 GEN_VXFORM_207(vmrgew, 6, 30),
10331 GEN_VXFORM_207(vmrgow, 6, 26),
10332 GEN_VXFORM(vmuloub, 4, 0),
10333 GEN_VXFORM(vmulouh, 4, 1),
10334 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10335 GEN_VXFORM(vmulosb, 4, 4),
10336 GEN_VXFORM(vmulosh, 4, 5),
10337 GEN_VXFORM_207(vmulosw, 4, 6),
10338 GEN_VXFORM(vmuleub, 4, 8),
10339 GEN_VXFORM(vmuleuh, 4, 9),
10340 GEN_VXFORM_207(vmuleuw, 4, 10),
10341 GEN_VXFORM(vmulesb, 4, 12),
10342 GEN_VXFORM(vmulesh, 4, 13),
10343 GEN_VXFORM_207(vmulesw, 4, 14),
10344 GEN_VXFORM(vslb, 2, 4),
10345 GEN_VXFORM(vslh, 2, 5),
10346 GEN_VXFORM(vslw, 2, 6),
10347 GEN_VXFORM_207(vsld, 2, 23),
10348 GEN_VXFORM(vsrb, 2, 8),
10349 GEN_VXFORM(vsrh, 2, 9),
10350 GEN_VXFORM(vsrw, 2, 10),
10351 GEN_VXFORM_207(vsrd, 2, 27),
10352 GEN_VXFORM(vsrab, 2, 12),
10353 GEN_VXFORM(vsrah, 2, 13),
10354 GEN_VXFORM(vsraw, 2, 14),
10355 GEN_VXFORM_207(vsrad, 2, 15),
10356 GEN_VXFORM(vslo, 6, 16),
10357 GEN_VXFORM(vsro, 6, 17),
10358 GEN_VXFORM(vaddcuw, 0, 6),
10359 GEN_VXFORM(vsubcuw, 0, 22),
10360 GEN_VXFORM(vaddubs, 0, 8),
10361 GEN_VXFORM(vadduhs, 0, 9),
10362 GEN_VXFORM(vadduws, 0, 10),
10363 GEN_VXFORM(vaddsbs, 0, 12),
10364 GEN_VXFORM(vaddshs, 0, 13),
10365 GEN_VXFORM(vaddsws, 0, 14),
10366 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10367 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10368 GEN_VXFORM(vsubuws, 0, 26),
10369 GEN_VXFORM(vsubsbs, 0, 28),
10370 GEN_VXFORM(vsubshs, 0, 29),
10371 GEN_VXFORM(vsubsws, 0, 30),
10372 GEN_VXFORM_207(vadduqm, 0, 4),
10373 GEN_VXFORM_207(vaddcuq, 0, 5),
10374 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10375 GEN_VXFORM_207(vsubuqm, 0, 20),
10376 GEN_VXFORM_207(vsubcuq, 0, 21),
10377 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10378 GEN_VXFORM(vrlb, 2, 0),
10379 GEN_VXFORM(vrlh, 2, 1),
10380 GEN_VXFORM(vrlw, 2, 2),
10381 GEN_VXFORM_207(vrld, 2, 3),
10382 GEN_VXFORM(vsl, 2, 7),
10383 GEN_VXFORM(vsr, 2, 11),
10384 GEN_VXFORM(vpkuhum, 7, 0),
10385 GEN_VXFORM(vpkuwum, 7, 1),
10386 GEN_VXFORM_207(vpkudum, 7, 17),
10387 GEN_VXFORM(vpkuhus, 7, 2),
10388 GEN_VXFORM(vpkuwus, 7, 3),
10389 GEN_VXFORM_207(vpkudus, 7, 19),
10390 GEN_VXFORM(vpkshus, 7, 4),
10391 GEN_VXFORM(vpkswus, 7, 5),
10392 GEN_VXFORM_207(vpksdus, 7, 21),
10393 GEN_VXFORM(vpkshss, 7, 6),
10394 GEN_VXFORM(vpkswss, 7, 7),
10395 GEN_VXFORM_207(vpksdss, 7, 23),
10396 GEN_VXFORM(vpkpx, 7, 12),
10397 GEN_VXFORM(vsum4ubs, 4, 24),
10398 GEN_VXFORM(vsum4sbs, 4, 28),
10399 GEN_VXFORM(vsum4shs, 4, 25),
10400 GEN_VXFORM(vsum2sws, 4, 26),
10401 GEN_VXFORM(vsumsws, 4, 30),
10402 GEN_VXFORM(vaddfp, 5, 0),
10403 GEN_VXFORM(vsubfp, 5, 1),
10404 GEN_VXFORM(vmaxfp, 5, 16),
10405 GEN_VXFORM(vminfp, 5, 17),
10406
10407 #undef GEN_VXRFORM1
10408 #undef GEN_VXRFORM
10409 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10410 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10411 #define GEN_VXRFORM(name, opc2, opc3) \
10412 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10413 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10414 GEN_VXRFORM(vcmpequb, 3, 0)
10415 GEN_VXRFORM(vcmpequh, 3, 1)
10416 GEN_VXRFORM(vcmpequw, 3, 2)
10417 GEN_VXRFORM(vcmpgtsb, 3, 12)
10418 GEN_VXRFORM(vcmpgtsh, 3, 13)
10419 GEN_VXRFORM(vcmpgtsw, 3, 14)
10420 GEN_VXRFORM(vcmpgtub, 3, 8)
10421 GEN_VXRFORM(vcmpgtuh, 3, 9)
10422 GEN_VXRFORM(vcmpgtuw, 3, 10)
10423 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10424 GEN_VXRFORM(vcmpgefp, 3, 7)
10425 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10426 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10427
10428 #undef GEN_VXFORM_SIMM
10429 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10430 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10431 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10432 GEN_VXFORM_SIMM(vspltish, 6, 13),
10433 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10434
10435 #undef GEN_VXFORM_NOA
10436 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10437 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10438 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10439 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10440 GEN_VXFORM_207(vupkhsw, 7, 25),
10441 GEN_VXFORM_NOA(vupklsb, 7, 10),
10442 GEN_VXFORM_NOA(vupklsh, 7, 11),
10443 GEN_VXFORM_207(vupklsw, 7, 27),
10444 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10445 GEN_VXFORM_NOA(vupklpx, 7, 15),
10446 GEN_VXFORM_NOA(vrefp, 5, 4),
10447 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10448 GEN_VXFORM_NOA(vexptefp, 5, 6),
10449 GEN_VXFORM_NOA(vlogefp, 5, 7),
10450 GEN_VXFORM_NOA(vrfim, 5, 8),
10451 GEN_VXFORM_NOA(vrfin, 5, 9),
10452 GEN_VXFORM_NOA(vrfip, 5, 10),
10453 GEN_VXFORM_NOA(vrfiz, 5, 11),
10454
10455 #undef GEN_VXFORM_UIMM
10456 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10457 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10458 GEN_VXFORM_UIMM(vspltb, 6, 8),
10459 GEN_VXFORM_UIMM(vsplth, 6, 9),
10460 GEN_VXFORM_UIMM(vspltw, 6, 10),
10461 GEN_VXFORM_UIMM(vcfux, 5, 12),
10462 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10463 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10464 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10465
10466 #undef GEN_VAFORM_PAIRED
10467 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10468 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10469 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10470 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10471 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10472 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10473 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10474 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10475
10476 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10477 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10478 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10479 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10480
10481 GEN_VXFORM_207(vbpermq, 6, 21),
10482 GEN_VXFORM_207(vgbbd, 6, 20),
10483 GEN_VXFORM_207(vpmsumb, 4, 16),
10484 GEN_VXFORM_207(vpmsumh, 4, 17),
10485 GEN_VXFORM_207(vpmsumw, 4, 18),
10486 GEN_VXFORM_207(vpmsumd, 4, 19),
10487
10488 GEN_VXFORM_207(vsbox, 4, 23),
10489
10490 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10491 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10492
10493 GEN_VXFORM_207(vshasigmaw, 1, 26),
10494 GEN_VXFORM_207(vshasigmad, 1, 27),
10495
10496 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10497
10498 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10499 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10500 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10501 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10502 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10503 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10504 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10505
10506 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10507 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10508 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10509 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10510 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10511
10512 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10513 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10514 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10515 #if defined(TARGET_PPC64)
10516 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10517 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10518 #endif
10519
10520 #undef GEN_XX2FORM
10521 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10522 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10523 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10524
10525 #undef GEN_XX3FORM
10526 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10527 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10528 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10529 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10530 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10531
10532 #undef GEN_XX3_RC_FORM
10533 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10534 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10535 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10536 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10537 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10538 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10539 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10540 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10541 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10542
10543 #undef GEN_XX3FORM_DM
10544 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10545 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10546 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10547 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10548 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10549 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10550 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10551 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10552 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10553 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10554 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10555 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10556 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10557 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10558 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10559 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10560 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10561
10562 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10563 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10564 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10565 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10566
10567 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10568 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10569 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10570 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10571 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10572 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10573 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10574 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10575
10576 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10577 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10578 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10579 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10580 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10581 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10582 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10583 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10584 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10585 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10586 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10587 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10588 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10589 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10590 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10591 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10592 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10593 GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10594 GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10595 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10596 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10597 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10598 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10599 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10600 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10601 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10602 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10603 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10604 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10605 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10606 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10607 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10608 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10609 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10610 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10611 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10612
10613 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10614 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10615 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10616 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10617 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10618 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10619 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10620 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10621 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10622 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10623 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10624 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10625 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10626 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10627 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10628 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10629 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10630 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10631
10632 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10633 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10634 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10635 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10636 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10637 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10638 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10639 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10640 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10641 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10642 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10643 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10644 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10645 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10646 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10647 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10648 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10649 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10650 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10651 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10652 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10653 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10654 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10655 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10656 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10657 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10658 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10659 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10660 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10661 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10662 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10663 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10664 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10665 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10666 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10667 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10668
10669 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10670 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10671 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10672 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10673 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10674 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10675 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10676 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10677 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10678 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10679 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10680 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10681 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10682 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10683 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10684 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10685 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10686 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10687 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10688 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10689 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10690 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10691 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10692 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10693 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10694 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10695 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10696 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10697 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10698 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10699 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10700 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10701 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10702 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10703 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10704 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10705
10706 #undef VSX_LOGICAL
10707 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10708 GEN_XX3FORM(name, opc2, opc3, fl2)
10709
10710 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10711 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10712 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10713 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10714 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10715 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10716 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10717 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10718 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10719 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10720 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10721 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10722
10723 #define GEN_XXSEL_ROW(opc3) \
10724 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10725 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10726 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10727 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10728 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10729 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10730 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10731 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10732
10733 GEN_XXSEL_ROW(0x00)
10734 GEN_XXSEL_ROW(0x01)
10735 GEN_XXSEL_ROW(0x02)
10736 GEN_XXSEL_ROW(0x03)
10737 GEN_XXSEL_ROW(0x04)
10738 GEN_XXSEL_ROW(0x05)
10739 GEN_XXSEL_ROW(0x06)
10740 GEN_XXSEL_ROW(0x07)
10741 GEN_XXSEL_ROW(0x08)
10742 GEN_XXSEL_ROW(0x09)
10743 GEN_XXSEL_ROW(0x0A)
10744 GEN_XXSEL_ROW(0x0B)
10745 GEN_XXSEL_ROW(0x0C)
10746 GEN_XXSEL_ROW(0x0D)
10747 GEN_XXSEL_ROW(0x0E)
10748 GEN_XXSEL_ROW(0x0F)
10749 GEN_XXSEL_ROW(0x10)
10750 GEN_XXSEL_ROW(0x11)
10751 GEN_XXSEL_ROW(0x12)
10752 GEN_XXSEL_ROW(0x13)
10753 GEN_XXSEL_ROW(0x14)
10754 GEN_XXSEL_ROW(0x15)
10755 GEN_XXSEL_ROW(0x16)
10756 GEN_XXSEL_ROW(0x17)
10757 GEN_XXSEL_ROW(0x18)
10758 GEN_XXSEL_ROW(0x19)
10759 GEN_XXSEL_ROW(0x1A)
10760 GEN_XXSEL_ROW(0x1B)
10761 GEN_XXSEL_ROW(0x1C)
10762 GEN_XXSEL_ROW(0x1D)
10763 GEN_XXSEL_ROW(0x1E)
10764 GEN_XXSEL_ROW(0x1F)
10765
10766 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10767
10768 #undef GEN_DFP_T_A_B_Rc
10769 #undef GEN_DFP_BF_A_B
10770 #undef GEN_DFP_BF_A_DCM
10771 #undef GEN_DFP_T_B_U32_U32_Rc
10772 #undef GEN_DFP_T_A_B_I32_Rc
10773 #undef GEN_DFP_T_B_Rc
10774 #undef GEN_DFP_T_FPR_I32_Rc
10775
10776 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10777 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10778
10779 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10780 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10781 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10782
10783 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10784 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10785 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10786 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10787 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10788
10789 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10790 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10791
10792 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10793 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10794 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10795
10796 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10797 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10798 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10799 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10800 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10801
10802 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10803 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10804
10805 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10806 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10807
10808 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10809 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10810
10811 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10812 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10813
10814 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10815 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10816
10817 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10818 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10819
10820 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10821 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10822
10823 #define GEN_DFP_BF_A_B(name, op1, op2) \
10824 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
10825
10826 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
10827 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
10828
10829 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
10830 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
10831
10832 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
10833 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
10834
10835 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
10836 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
10837
10838 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
10839 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10840
10841 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
10842 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
10843
10844 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
10845 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
10846
10847 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
10848 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10849
10850 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
10851 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
10852
10853 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
10854 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
10855
10856 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
10857 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
10858
10859 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
10860 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
10861
10862 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
10863 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
10864
10865 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
10866 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
10867
10868 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
10869 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
10870
10871 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
10872 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
10873
10874 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
10875 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
10876
10877 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
10878 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
10879 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
10880 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
10881 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
10882 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
10883 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
10884 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
10885 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
10886 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
10887 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
10888 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
10889 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
10890 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
10891 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
10892 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
10893 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
10894 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
10895 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
10896 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
10897 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
10898 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
10899 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
10900 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
10901 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
10902 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
10903 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
10904 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
10905 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
10906 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
10907 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
10908 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
10909 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
10910 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
10911 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
10912 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
10913 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
10914 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
10915 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
10916 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
10917 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
10918 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
10919 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
10920 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
10921 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
10922 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
10923 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
10924 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
10925 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
10926 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
10927
10928 #undef GEN_SPE
10929 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
10930 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
10931 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10932 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10933 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10934 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10935 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10936 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10937 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10938 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
10939 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
10940 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10941 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10942 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10943 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10944 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10945 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10946 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
10947 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10948 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10949 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10950 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10951 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10952 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10953 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10954 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10955 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10956 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10957 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10958 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10959 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
10960
10961 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10962 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10963 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10964 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10965 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10966 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10967 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10968 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10969 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10970 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10971 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10972 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10973 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10974 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10975
10976 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10977 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10978 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10979 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10980 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10981 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
10982 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10983 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10984 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10985 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10986 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10987 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10988 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10989 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10990
10991 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10992 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10993 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
10994 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10995 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10996 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10997 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
10998 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
10999 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11000 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11001 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11002 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11003 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11004 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11005 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11006 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11007
11008 #undef GEN_SPEOP_LDST
11009 #define GEN_SPEOP_LDST(name, opc2, sh) \
11010 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11011 GEN_SPEOP_LDST(evldd, 0x00, 3),
11012 GEN_SPEOP_LDST(evldw, 0x01, 3),
11013 GEN_SPEOP_LDST(evldh, 0x02, 3),
11014 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11015 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11016 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11017 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11018 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11019 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11020 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11021 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11022
11023 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11024 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11025 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11026 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11027 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11028 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11029 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11030 };
11031
11032 #include "helper_regs.h"
11033 #include "translate_init.c"
11034
11035 /*****************************************************************************/
11036 /* Misc PowerPC helpers */
11037 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11038 int flags)
11039 {
11040 #define RGPL 4
11041 #define RFPL 4
11042
11043 PowerPCCPU *cpu = POWERPC_CPU(cs);
11044 CPUPPCState *env = &cpu->env;
11045 int i;
11046
11047 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11048 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
11049 env->nip, env->lr, env->ctr, cpu_read_xer(env));
11050 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11051 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11052 env->hflags, env->mmu_idx);
11053 #if !defined(NO_TIMER_DUMP)
11054 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11055 #if !defined(CONFIG_USER_ONLY)
11056 " DECR %08" PRIu32
11057 #endif
11058 "\n",
11059 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11060 #if !defined(CONFIG_USER_ONLY)
11061 , cpu_ppc_load_decr(env)
11062 #endif
11063 );
11064 #endif
11065 for (i = 0; i < 32; i++) {
11066 if ((i & (RGPL - 1)) == 0)
11067 cpu_fprintf(f, "GPR%02d", i);
11068 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11069 if ((i & (RGPL - 1)) == (RGPL - 1))
11070 cpu_fprintf(f, "\n");
11071 }
11072 cpu_fprintf(f, "CR ");
11073 for (i = 0; i < 8; i++)
11074 cpu_fprintf(f, "%01x", env->crf[i]);
11075 cpu_fprintf(f, " [");
11076 for (i = 0; i < 8; i++) {
11077 char a = '-';
11078 if (env->crf[i] & 0x08)
11079 a = 'L';
11080 else if (env->crf[i] & 0x04)
11081 a = 'G';
11082 else if (env->crf[i] & 0x02)
11083 a = 'E';
11084 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11085 }
11086 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11087 env->reserve_addr);
11088 for (i = 0; i < 32; i++) {
11089 if ((i & (RFPL - 1)) == 0)
11090 cpu_fprintf(f, "FPR%02d", i);
11091 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11092 if ((i & (RFPL - 1)) == (RFPL - 1))
11093 cpu_fprintf(f, "\n");
11094 }
11095 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11096 #if !defined(CONFIG_USER_ONLY)
11097 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11098 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11099 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11100 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11101
11102 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11103 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11104 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11105 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11106
11107 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11108 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11109 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11110 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11111
11112 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11113 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11114 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11115 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11116 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11117
11118 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11119 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11120 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11121 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11122
11123 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11124 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11125 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11126 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11127
11128 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11129 " EPR " TARGET_FMT_lx "\n",
11130 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11131 env->spr[SPR_BOOKE_EPR]);
11132
11133 /* FSL-specific */
11134 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11135 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11136 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11137 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11138
11139 /*
11140 * IVORs are left out as they are large and do not change often --
11141 * they can be read with "p $ivor0", "p $ivor1", etc.
11142 */
11143 }
11144
11145 #if defined(TARGET_PPC64)
11146 if (env->flags & POWERPC_FLAG_CFAR) {
11147 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11148 }
11149 #endif
11150
11151 switch (env->mmu_model) {
11152 case POWERPC_MMU_32B:
11153 case POWERPC_MMU_601:
11154 case POWERPC_MMU_SOFT_6xx:
11155 case POWERPC_MMU_SOFT_74xx:
11156 #if defined(TARGET_PPC64)
11157 case POWERPC_MMU_64B:
11158 case POWERPC_MMU_2_06:
11159 case POWERPC_MMU_2_06a:
11160 case POWERPC_MMU_2_06d:
11161 #endif
11162 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11163 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11164 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11165 break;
11166 case POWERPC_MMU_BOOKE206:
11167 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11168 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11169 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11170 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11171
11172 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11173 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11174 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11175 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11176
11177 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11178 " TLB1CFG " TARGET_FMT_lx "\n",
11179 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11180 env->spr[SPR_BOOKE_TLB1CFG]);
11181 break;
11182 default:
11183 break;
11184 }
11185 #endif
11186
11187 #undef RGPL
11188 #undef RFPL
11189 }
11190
11191 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11192 fprintf_function cpu_fprintf, int flags)
11193 {
11194 #if defined(DO_PPC_STATISTICS)
11195 PowerPCCPU *cpu = POWERPC_CPU(cs);
11196 opc_handler_t **t1, **t2, **t3, *handler;
11197 int op1, op2, op3;
11198
11199 t1 = cpu->env.opcodes;
11200 for (op1 = 0; op1 < 64; op1++) {
11201 handler = t1[op1];
11202 if (is_indirect_opcode(handler)) {
11203 t2 = ind_table(handler);
11204 for (op2 = 0; op2 < 32; op2++) {
11205 handler = t2[op2];
11206 if (is_indirect_opcode(handler)) {
11207 t3 = ind_table(handler);
11208 for (op3 = 0; op3 < 32; op3++) {
11209 handler = t3[op3];
11210 if (handler->count == 0)
11211 continue;
11212 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11213 "%016" PRIx64 " %" PRId64 "\n",
11214 op1, op2, op3, op1, (op3 << 5) | op2,
11215 handler->oname,
11216 handler->count, handler->count);
11217 }
11218 } else {
11219 if (handler->count == 0)
11220 continue;
11221 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11222 "%016" PRIx64 " %" PRId64 "\n",
11223 op1, op2, op1, op2, handler->oname,
11224 handler->count, handler->count);
11225 }
11226 }
11227 } else {
11228 if (handler->count == 0)
11229 continue;
11230 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11231 " %" PRId64 "\n",
11232 op1, op1, handler->oname,
11233 handler->count, handler->count);
11234 }
11235 }
11236 #endif
11237 }
11238
11239 /*****************************************************************************/
11240 static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
11241 TranslationBlock *tb,
11242 bool search_pc)
11243 {
11244 CPUState *cs = CPU(cpu);
11245 CPUPPCState *env = &cpu->env;
11246 DisasContext ctx, *ctxp = &ctx;
11247 opc_handler_t **table, *handler;
11248 target_ulong pc_start;
11249 uint16_t *gen_opc_end;
11250 CPUBreakpoint *bp;
11251 int j, lj = -1;
11252 int num_insns;
11253 int max_insns;
11254
11255 pc_start = tb->pc;
11256 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
11257 ctx.nip = pc_start;
11258 ctx.tb = tb;
11259 ctx.exception = POWERPC_EXCP_NONE;
11260 ctx.spr_cb = env->spr_cb;
11261 ctx.mem_idx = env->mmu_idx;
11262 ctx.insns_flags = env->insns_flags;
11263 ctx.insns_flags2 = env->insns_flags2;
11264 ctx.access_type = -1;
11265 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11266 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11267 #if defined(TARGET_PPC64)
11268 ctx.sf_mode = msr_is_64bit(env, env->msr);
11269 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11270 #endif
11271 ctx.fpu_enabled = msr_fp;
11272 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11273 ctx.spe_enabled = msr_spe;
11274 else
11275 ctx.spe_enabled = 0;
11276 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11277 ctx.altivec_enabled = msr_vr;
11278 else
11279 ctx.altivec_enabled = 0;
11280 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11281 ctx.vsx_enabled = msr_vsx;
11282 } else {
11283 ctx.vsx_enabled = 0;
11284 }
11285 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11286 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11287 else
11288 ctx.singlestep_enabled = 0;
11289 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11290 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11291 if (unlikely(cs->singlestep_enabled)) {
11292 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11293 }
11294 #if defined (DO_SINGLE_STEP) && 0
11295 /* Single step trace mode */
11296 msr_se = 1;
11297 #endif
11298 num_insns = 0;
11299 max_insns = tb->cflags & CF_COUNT_MASK;
11300 if (max_insns == 0)
11301 max_insns = CF_COUNT_MASK;
11302
11303 gen_tb_start();
11304 tcg_clear_temp_count();
11305 /* Set env in case of segfault during code fetch */
11306 while (ctx.exception == POWERPC_EXCP_NONE
11307 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
11308 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
11309 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
11310 if (bp->pc == ctx.nip) {
11311 gen_debug_exception(ctxp);
11312 break;
11313 }
11314 }
11315 }
11316 if (unlikely(search_pc)) {
11317 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11318 if (lj < j) {
11319 lj++;
11320 while (lj < j)
11321 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11322 }
11323 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
11324 tcg_ctx.gen_opc_instr_start[lj] = 1;
11325 tcg_ctx.gen_opc_icount[lj] = num_insns;
11326 }
11327 LOG_DISAS("----------------\n");
11328 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11329 ctx.nip, ctx.mem_idx, (int)msr_ir);
11330 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
11331 gen_io_start();
11332 if (unlikely(need_byteswap(&ctx))) {
11333 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11334 } else {
11335 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11336 }
11337 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11338 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11339 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11340 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
11341 tcg_gen_debug_insn_start(ctx.nip);
11342 }
11343 ctx.nip += 4;
11344 table = env->opcodes;
11345 num_insns++;
11346 handler = table[opc1(ctx.opcode)];
11347 if (is_indirect_opcode(handler)) {
11348 table = ind_table(handler);
11349 handler = table[opc2(ctx.opcode)];
11350 if (is_indirect_opcode(handler)) {
11351 table = ind_table(handler);
11352 handler = table[opc3(ctx.opcode)];
11353 }
11354 }
11355 /* Is opcode *REALLY* valid ? */
11356 if (unlikely(handler->handler == &gen_invalid)) {
11357 if (qemu_log_enabled()) {
11358 qemu_log("invalid/unsupported opcode: "
11359 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11360 opc1(ctx.opcode), opc2(ctx.opcode),
11361 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11362 }
11363 } else {
11364 uint32_t inval;
11365
11366 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11367 inval = handler->inval2;
11368 } else {
11369 inval = handler->inval1;
11370 }
11371
11372 if (unlikely((ctx.opcode & inval) != 0)) {
11373 if (qemu_log_enabled()) {
11374 qemu_log("invalid bits: %08x for opcode: "
11375 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11376 ctx.opcode & inval, opc1(ctx.opcode),
11377 opc2(ctx.opcode), opc3(ctx.opcode),
11378 ctx.opcode, ctx.nip - 4);
11379 }
11380 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11381 break;
11382 }
11383 }
11384 (*(handler->handler))(&ctx);
11385 #if defined(DO_PPC_STATISTICS)
11386 handler->count++;
11387 #endif
11388 /* Check trace mode exceptions */
11389 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11390 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11391 ctx.exception != POWERPC_SYSCALL &&
11392 ctx.exception != POWERPC_EXCP_TRAP &&
11393 ctx.exception != POWERPC_EXCP_BRANCH)) {
11394 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11395 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11396 (cs->singlestep_enabled) ||
11397 singlestep ||
11398 num_insns >= max_insns)) {
11399 /* if we reach a page boundary or are single stepping, stop
11400 * generation
11401 */
11402 break;
11403 }
11404 if (tcg_check_temp_count()) {
11405 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11406 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11407 ctx.opcode);
11408 exit(1);
11409 }
11410 }
11411 if (tb->cflags & CF_LAST_IO)
11412 gen_io_end();
11413 if (ctx.exception == POWERPC_EXCP_NONE) {
11414 gen_goto_tb(&ctx, 0, ctx.nip);
11415 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11416 if (unlikely(cs->singlestep_enabled)) {
11417 gen_debug_exception(ctxp);
11418 }
11419 /* Generate the return instruction */
11420 tcg_gen_exit_tb(0);
11421 }
11422 gen_tb_end(tb, num_insns);
11423 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
11424 if (unlikely(search_pc)) {
11425 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11426 lj++;
11427 while (lj <= j)
11428 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11429 } else {
11430 tb->size = ctx.nip - pc_start;
11431 tb->icount = num_insns;
11432 }
11433 #if defined(DEBUG_DISAS)
11434 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11435 int flags;
11436 flags = env->bfd_mach;
11437 flags |= ctx.le_mode << 16;
11438 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11439 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
11440 qemu_log("\n");
11441 }
11442 #endif
11443 }
11444
11445 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
11446 {
11447 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
11448 }
11449
11450 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
11451 {
11452 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
11453 }
11454
11455 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
11456 {
11457 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
11458 }
QEmu